sw/device/tests/smc/smc_kelvin_checksum_test.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

// Run kelvin_chechsum test from SMC

#include "hw/top_matcha/ip/ml_top/data/ml_top_regs.h"  // Generated.
#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"
#include "sw/device/tests/testdata/test_image.h"

#define ML_DMEM_INPUT_OFFSET_ADDR 0x00300000
#define ML_DMEM_OUT_OFFSET_ADDR 0x00380000

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t smc_uart;

void _ottf_main(void) {
  uint32_t mem_val;
  uint32_t intr_state;

  test_status_set(kTestStatusInTest);
  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }

  // Write DMEM with initial values
  const uint32_t *input = (const uint32_t *)hps_0;
  mmio_region_t ml_dmem_base = mmio_region_from_addr(
      TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR + ML_DMEM_INPUT_OFFSET_ADDR);
  for (uintptr_t word_idx = 0; word_idx < hps_0_len / sizeof(uint32_t);
       ++word_idx) {
    uintptr_t offset = word_idx * sizeof(uint32_t);
    mmio_region_write32(ml_dmem_base, offset, input[word_idx]);
  }

  // Set ML_TOP_Core registers
  mmio_region_t base_addr =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_CORE_BASE_ADDR);
  // Un-freeze clock and Reset of ML_TOP
  mmio_region_write32(base_addr, ML_TOP_CTRL_REG_OFFSET,
                      ML_TOP_CTRL_REG_RESVAL);
  mem_val = mmio_region_read32(base_addr, ML_TOP_CTRL_REG_OFFSET);
  CHECK(mem_val == ML_TOP_CTRL_REG_RESVAL,
        "ML_TOP_CTRL read out: expected : 0x%x | actual: 0x%x",
        ML_TOP_CTRL_REG_RESVAL, mem_val);

  // Release the Reset of ML_TOP
  mmio_region_write32(base_addr, ML_TOP_CTRL_REG_OFFSET, 0x0);

  // Wait for a interrupt
  intr_state = mmio_region_read32(base_addr, ML_TOP_INTR_STATE_REG_OFFSET);
  CHECK(intr_state == 0,
        "ML_TOP_Core offset 0 INTR_STATE - Expected: 0x0 | Actual: 0x%x",
        intr_state);

  while (intr_state == 0x0) {
    intr_state = mmio_region_read32(base_addr, ML_TOP_INTR_STATE_REG_OFFSET);
    busy_spin_micros(200);
  }

  // Received interrupts from Kelvin core, check if only FINISH asserted
  CHECK(intr_state == (1 << ML_TOP_INTR_STATE_FINISH_BIT),
        "INTR_STATE read out: expected : 0x%x | actual: 0x%x",
        (1 << ML_TOP_INTR_STATE_FINISH_BIT), intr_state);

  // Check kelvin result. The program sums to the data stored in the test
  // range 0x5A300000 to 0x5A312c00, and stored at 0x5A380000
  ml_dmem_base = mmio_region_from_addr(TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR);
  mem_val = mmio_region_read32(ml_dmem_base, ML_DMEM_OUT_OFFSET_ADDR);
  const uint32_t kExpectedSum = 0x0d42e16c;
  CHECK(mem_val == kExpectedSum,
        "Mismatch output - Expected: 0x%x | Actual: 0x%x", kExpectedSum,
        mem_val);
  test_status_set(kTestStatusPassed);
}