sw/device/tests/smc/smc_isp_wrapper_irq_test.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

// ISP TPG mode with user defined resolution: 120x64, which covers the reg
// access, two interrupts, dma to dl_mem path.

#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_isp_wrapper.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t smc_uart;
static dif_isp_wrapper_t isp_wrapper;
static dif_rv_plic_t plic_smc;

uint32_t en_result;
uint32_t mem_val;
const uint32_t mp_frame_end_mask = 0x1;

// These flags are used in the test routine to verify that a corresponding
// interrupt has elapsed, and has been serviced. These are declared as volatile
// since they are referenced in the ISR routine as well as in the main program
// flow.
static volatile bool isp_wrapper_isp_handled;
static volatile bool isp_wrapper_mi_handled;

static void handle_isp_ctrl_isr(const dif_rv_plic_irq_id_t interrupt_id) {
  // NOTE: This initialization is superfluous, since the `default` case below
  // is effectively noreturn, but the compiler is unable to prove this.
  //  dif_isp_wrapper_irq_t isp_ctrl_irq = 0;

  switch (interrupt_id) {
    case kTopMatchaPlicIrqIdIspWrapperIsp:
      CHECK(!isp_wrapper_isp_handled,
            "ISP_WRAPPER isp IRQ asserted more than once");
      uint32_t isp_mis;
      CHECK_DIF_OK(dif_isp_wrapper_read_isp_mis(&isp_wrapper, &isp_mis));
      CHECK_DIF_OK(dif_isp_wrapper_isp_irq_mask(&isp_wrapper));
      CHECK_DIF_OK(dif_isp_wrapper_write_isp_icr(&isp_wrapper, isp_mis));
      isp_wrapper_isp_handled = true;
      LOG_INFO("ISP Wrapper isp interrupt occurred!");
      break;
    case kTopMatchaPlicIrqIdIspWrapperMi:
      CHECK(!isp_wrapper_mi_handled,
            "ISP_WRAPPER mi IRQ asserted more than once");
      uint32_t mi_mis;
      CHECK_DIF_OK(dif_isp_wrapper_read_mi_mis(&isp_wrapper, &mi_mis));
      if(mi_mis & mp_frame_end_mask) {
        CHECK_DIF_OK(dif_isp_wrapper_mi_irq_mask(&isp_wrapper));
        isp_wrapper_mi_handled = true;
      }
      CHECK_DIF_OK(dif_isp_wrapper_write_mi_icr(&isp_wrapper, mi_mis));
      LOG_INFO("ISP Wrapper mi interrupt occurred!");
      break;
    default:
      LOG_FATAL("ISR is not implemented!");
  }
}

void ottf_external_isr(void) {
  // Claim the IRQ by reading the Ibex specific CC register.
  dif_rv_plic_irq_id_t interrupt_id;
  LOG_INFO("Interrupt Entered!");

  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                     &interrupt_id));

  // Check if the interrupted peripheral is ISP WRAPPER.
  top_matcha_plic_peripheral_smc_t peripheral_id =
      top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
  CHECK(peripheral_id == kTopMatchaPlicPeripheralIspWrapper,
        "ISR interrupted peripheral is ISP_WRAPPER!");
  switch (peripheral_id) {
    case kTopMatchaPlicPeripheralIspWrapper:
      handle_isp_ctrl_isr(interrupt_id);
      break;
    default:
      LOG_FATAL("Peripheral is not implemented!");
  }

  // Complete the IRQ by writing the IRQ source to the Ibex specific CC
  // register.
  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                        interrupt_id));
}

/*
 * Configures all the relevant interrupts in PLIC_SEC.
 */
static void plic_smc_configure_irqs(dif_rv_plic_t *plic) {
  // Set IRQ priorities to MAX
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      plic, kTopMatchaPlicIrqIdIspWrapperIsp, kDifRvPlicMaxPriority));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      plic, kTopMatchaPlicIrqIdIspWrapperMi, kDifRvPlicMaxPriority));

  // Set Ibex IRQ priority threshold level
  CHECK_DIF_OK(dif_rv_plic_target_set_threshold(
      plic, kTopMatchaPlicTargetIbex0Smc, kDifRvPlicMinPriority));

  // Enable IRQs in PLIC
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      plic, kTopMatchaPlicIrqIdIspWrapperIsp, kTopMatchaPlicTargetIbex0Smc,
      kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      plic, kTopMatchaPlicIrqIdIspWrapperMi, kTopMatchaPlicTargetIbex0Smc,
      kDifToggleEnabled));
}

void _ottf_main(void) {
  test_status_set(kTestStatusInTest);
  irq_global_ctrl(true);
  irq_external_ctrl(true);

  isp_wrapper_isp_handled = false;
  isp_wrapper_mi_handled = false;

  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }
  LOG_INFO("Hello from the SMC!");
  CHECK_DIF_OK(dif_isp_wrapper_init(
      mmio_region_from_addr(TOP_MATCHA_ISP_WRAPPER_BASE_ADDR), &isp_wrapper));
  CHECK_DIF_OK(dif_isp_wrapper_set_en(&isp_wrapper),
               "isp_wrapper failed to be set in TPG mode");

  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc));
  plic_smc_configure_irqs(&plic_smc);

  while (isp_wrapper_isp_handled != true) {
    asm volatile("wfi");
  }

  while (isp_wrapper_mi_handled != true) {
    asm volatile("wfi");
  }

  mmio_region_t ml_dmem_base_addr =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x200);
  CHECK(mem_val == 0xfcfcfcfc,
        "ISP Write to ML_DMEM value offset 0x200 - Expected: 0xfcfcfcfc | "
        "Actual: %x",
        mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x23C);
  CHECK(mem_val == 0x90909090,
        "ISP Write to ML_DMEM value offset 0x23C - Expected: 0x90909090 | "
        "Actual: %x",
        mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0010);
  CHECK(mem_val == 0xd8d8d8d8,
        "ISP Write to ML_DMEM value offset 0x0010 - Expected: 0xd8d8d8d8 | "
        "Actual: %x",
        mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0030);
  CHECK(mem_val == 0x90909090,
        "ISP Write to ML_DMEM value offset 0x0030 - Expected: 0x90909090 | "
        "Actual: %x",
        mem_val);

  test_status_set(kTestStatusPassed);
}