sw/device/tests/smc/smc_kelvin_checksum_test.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

// Run kelvin_chechsum test from SMC

#include "hw/ip/ml_top/data/ml_top_regs.h"  // Generated.
#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_ml_top.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"
#include "sw/device/tests/testdata/test_image.h"

#define ML_DMEM_INPUT_OFFSET_ADDR 0x00300000
#define ML_DMEM_OUT_OFFSET_ADDR 0x00380000

OTTF_DEFINE_TEST_CONFIG();

static dif_ml_top_t ml_top;
static dif_rv_plic_t plic_smc;
static dif_uart_t smc_uart;

static volatile bool ml_top_finish_done = false;

static void handle_ml_top_isr(const dif_rv_plic_irq_id_t interrupt_id) {
  switch (interrupt_id) {
    case kTopMatchaPlicIrqIdMlTopFinish:
      ml_top_finish_done = true;
      break;
    case kTopMatchaPlicIrqIdMlTopFinish | kTopMatchaPlicIrqIdMlTopFault:
      LOG_ERROR("ML core raised fault interrupt.");
      test_status_set(kTestStatusFailed);
    default:
      LOG_FATAL("ISR is not implemented!");
      test_status_set(kTestStatusFailed);
  }

  CHECK_DIF_OK(dif_ml_top_reset_ctrl_en(&ml_top));
  CHECK_DIF_OK(dif_ml_top_irq_acknowledge_all(&ml_top));
}

void ottf_external_isr(void) {
  // Claim the IRQ by reading the Ibex specific CC register.
  dif_rv_plic_irq_id_t interrupt_id;

  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                     &interrupt_id));

  // Check if the interrupted peripheral is ISP WRAPPER.
  top_matcha_plic_peripheral_smc_t peripheral_id =
      top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
  CHECK(peripheral_id == kTopMatchaPlicPeripheralMlTop,
        "Unexpected peripheral in ISR: %d", peripheral_id);
  switch (peripheral_id) {
    case kTopMatchaPlicPeripheralMlTop: {
      handle_ml_top_isr(interrupt_id);
      break;
    }
    default:
      LOG_FATAL("Peripheral is not implemented!");
  }

  // Complete the IRQ by writing the IRQ source to the Ibex specific CC
  // register.
  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                        interrupt_id));
}

// Configures all relevant interrupts in PLIC_SMC.
static void plic_smc_configure_irqs(dif_rv_plic_t *plic) {
  // Set IRQ priorities to MAX
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      plic, kTopMatchaPlicIrqIdMlTopFinish, kDifRvPlicMaxPriority));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, kTopMatchaPlicIrqIdMlTopFault,
                                            kDifRvPlicMaxPriority));

  // Set Ibex IRQ priority threshold level
  CHECK_DIF_OK(dif_rv_plic_target_set_threshold(
      plic, kTopMatchaPlicTargetIbex0Smc, kDifRvPlicMinPriority));

  // Enable ML core IRQs
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, kTopMatchaPlicIrqIdMlTopFinish,
                                           kTopMatchaPlicTargetIbex0Smc,
                                           kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, kTopMatchaPlicIrqIdMlTopFault,
                                           kTopMatchaPlicTargetIbex0Smc,
                                           kDifToggleEnabled));
}

void _ottf_main(void) {
  test_status_set(kTestStatusInTest);
  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }

  // Init IRQs
  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc));
  plic_smc_configure_irqs(&plic_smc);
  irq_global_ctrl(true);
  irq_external_ctrl(true);

  // Init ML_TOP
  CHECK_DIF_OK(dif_ml_top_init(
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_CORE_BASE_ADDR), &ml_top));
  CHECK_DIF_OK(dif_ml_top_irq_set_enabled(&ml_top, kDifMlTopIrqFinish,
                                          kDifToggleEnabled));
  CHECK_DIF_OK(dif_ml_top_irq_set_enabled(&ml_top, kDifMlTopIrqFault,
                                          kDifToggleEnabled));

  // Write DMEM with initial values
  const uint32_t *input = (const uint32_t *)hps_0;
  mmio_region_t ml_dmem_base = mmio_region_from_addr(
      TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR + ML_DMEM_INPUT_OFFSET_ADDR);
  for (uintptr_t word_idx = 0; word_idx < hps_0_len / sizeof(uint32_t);
       ++word_idx) {
    uintptr_t offset = word_idx * sizeof(uint32_t);
    mmio_region_write32(ml_dmem_base, offset, input[word_idx]);
  }

  // Set ML_TOP_Core registers
  mmio_region_t base_addr =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_CORE_BASE_ADDR);
  // Un-freeze clock and Reset of ML_TOP
  CHECK_DIF_OK(dif_ml_top_reset_ctrl_en(&ml_top));
  uint32_t mem_val = mmio_region_read32(base_addr, ML_TOP_CTRL_REG_OFFSET);
  CHECK(mem_val == ML_TOP_CTRL_REG_RESVAL,
        "ML_TOP_CTRL read out: expected : 0x%x | actual: 0x%x",
        ML_TOP_CTRL_REG_RESVAL, mem_val);

  // Release the Reset of ML_TOP
  ml_top_finish_done = false;
  CHECK_DIF_OK(dif_ml_top_release_ctrl_en(&ml_top));

  // Wait until Kelvin finishes.
  while (!ml_top_finish_done) {
    asm volatile("wfi");
  }

  // Check kelvin result. The program sums to the data stored in the test
  // range 0x5A300000 to 0x5A312c00, and stored at 0x5A380000
  ml_dmem_base = mmio_region_from_addr(TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR);
  mem_val = mmio_region_read32(ml_dmem_base, ML_DMEM_OUT_OFFSET_ADDR);
  const uint32_t kExpectedSum = 0x0d42e16c;
  CHECK(mem_val == kExpectedSum,
        "Mismatch output - Expected: 0x%x | Actual: 0x%x", kExpectedSum,
        mem_val);
  test_status_set(kTestStatusPassed);
}