hw/ip/smc_ctrl/data/smc_ctrl.hjson

// Copyright 2023 Google LLC
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "smc_ctrl",
  clocking: [{clock: "clk_i", reset: "rst_ni"}],
  bus_interfaces: [
    { protocol: "tlul", direction: "device" }
  ],

  inter_signal_list: [
    { struct:  "boot_en",
      type:    "uni",
      name:    "smc_boot_en",
      act:     "req",
      package: "lc_ctrl_pkg",
    },
  ],

  regwidth: "32",
  registers: [
    { name:  "SMC_BOOT_EN_REGWEN",
      desc:  '''
        Register write enable for software controllable boot enable.
        When the bit value is 0, the value in !!SMC_BOOT_EN_CTRL can no longer be changed.
        When the bit value is 1, the value in !!SMC_BOOT_EN_CTR can be changed.
      ''',
      swaccess: "rw0c",
      hwaccess: "hro",
      fields: [
        {
          bits: "0",
          name: "regwen",
          desc: "Register write enable for software controllable boot enable.",
          resval: "1",
        },
      ]
      tags: [// Exclude from Csr tests
             "excl:CsrAllTests:CsrExclAll"],
    }
    { name:  "SMC_BOOT_EN_CTRL",
      desc:  '''
        Software controllable boot enable.
        When a particular bit value is 0, the corresponding core boot is disabled.
        When a particular bit value is 1, the corresponding core boot is enabled.
      ''',
      swaccess: "rw",
      hwaccess: "hro",
      regwen: "SMC_BOOT_EN_REGWEN"
      fields: [
        {
          bits: "0",
          name: "en_ctrl",
          desc: "Software boot enable.",
          resval: "0",
        },
      ],
      tags: [// Exclude from Csr tests
             "excl:CsrAllTests:CsrExclAll"],
    }
  ],

}