hw/ip/dma/chisel/BUILD

# Copyright 2023 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

genrule(
    name = "fastvdma_verilog",
    srcs = [
        "//hw/ip/dma/chisel/src:DMATop.sv"
    ],
    outs = [
        "fastvdma.sv",
    ],

    cmd = """
    cat $(location //hw/ip/dma/chisel/src:DMATop.sv) >> $(location fastvdma.sv)
    """,
    visibility = ["//visibility:public"],
)

# Generate fastvdma.core from this template so it can sit at the same GenDir as
# the RTL file.
genrule(
    name = "fastvdma_core",
    srcs = [
        "fastvdma.core.in",
        "fastvdma_verilog",
    ],
    outs = [
        "fastvdma.core",
    ],
    cmd = """
    cp -f $(location fastvdma.core.in) $(location fastvdma.core)
    """,
    visibility = ["//visibility:public"],
)