[ml_top/hw] Update Kelvin with mlu decode fix - https://spacebeaker-review.git.corp.google.com/c/shodan/hw/kelvin/+/46049 Fix: 295921340 Change-Id: I4e17b78d6375d94a924b1ff000de27f6952e1bfb
diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v index 82a85c5..0078ef8 100644 --- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v +++ b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
@@ -1,4 +1,4 @@ -// SHA: 8ed7b045ef01ae8da0b95ff6d2e0e7c40aea1230 +// SHA: 7c1ccd51884a09e0a61b55b1680498f001ba2013 module Regfile( input clock, input reset, @@ -103,7 +103,6 @@ input io_writeMask_1_valid, input io_writeMask_2_valid, input io_writeMask_3_valid, - input io_writeMask_4_valid, output [31:0] io_scoreboard_regd, output [31:0] io_scoreboard_comb ); @@ -255,28 +254,27 @@ reg [31:0] readDataBits_6; // @[Regfile.scala 125:26] reg [31:0] readDataBits_7; // @[Regfile.scala 125:26] wire _valid_T_1 = io_writeData_5_valid & io_writeData_5_addr == 5'h1; // @[Regfile.scala 143:43] - wire _valid_T_4 = ~io_writeMask_4_valid; // @[Regfile.scala 145:23] - wire _valid_T_5 = io_writeData_4_valid & io_writeData_4_addr == 5'h1 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_8 = ~io_writeMask_3_valid; // @[Regfile.scala 147:23] - wire _valid_T_9 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_12 = ~io_writeMask_2_valid; // @[Regfile.scala 149:23] - wire _valid_T_13 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_16 = ~io_writeMask_1_valid; // @[Regfile.scala 151:23] - wire _valid_T_17 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_19 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 152:43] - wire [5:0] valid = {_valid_T_1,_valid_T_5,_valid_T_9,_valid_T_13,_valid_T_17,_valid_T_19}; // @[Cat.scala 31:58] + wire _valid_T_3 = io_writeData_4_valid & io_writeData_4_addr == 5'h1; // @[Regfile.scala 144:43] + wire _valid_T_6 = ~io_writeMask_3_valid; // @[Regfile.scala 146:23] + wire _valid_T_7 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_10 = ~io_writeMask_2_valid; // @[Regfile.scala 148:23] + wire _valid_T_11 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_14 = ~io_writeMask_1_valid; // @[Regfile.scala 150:23] + wire _valid_T_15 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_17 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 151:43] + wire [5:0] valid = {_valid_T_1,_valid_T_3,_valid_T_7,_valid_T_11,_valid_T_15,_valid_T_17}; // @[Cat.scala 31:58] wire [31:0] _data_T_1 = valid[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_3 = valid[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 155:55] + wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 154:55] wire [31:0] _data_T_6 = valid[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 156:55] + wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 155:55] wire [31:0] _data_T_9 = valid[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 157:55] + wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 156:55] wire [31:0] _data_T_12 = valid[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 158:55] + wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 157:55] wire [31:0] _data_T_15 = valid[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 159:55] - wire writeValid_1 = valid != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 158:55] + wire writeValid_1 = valid != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_9 = valid[1] + valid[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_41 = {{1'd0}, valid[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_11 = _GEN_41 + _T_9; // @[Bitwise.scala 48:55] @@ -284,26 +282,26 @@ wire [1:0] _GEN_42 = {{1'd0}, valid[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_15 = _GEN_42 + _T_13; // @[Bitwise.scala 48:55] wire [2:0] _T_17 = _T_11[1:0] + _T_15[1:0]; // @[Bitwise.scala 48:55] - wire _T_21 = ~reset; // @[Regfile.scala 165:11] - wire _valid_T_23 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 143:43] - wire _valid_T_27 = io_writeData_4_valid & io_writeData_4_addr == 5'h2 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_31 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_35 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_39 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_41 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 152:43] - wire [5:0] valid_1 = {_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_39,_valid_T_41}; // @[Cat.scala 31:58] + wire _T_21 = ~reset; // @[Regfile.scala 164:11] + wire _valid_T_21 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 143:43] + wire _valid_T_23 = io_writeData_4_valid & io_writeData_4_addr == 5'h2; // @[Regfile.scala 144:43] + wire _valid_T_27 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_31 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_35 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_37 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 151:43] + wire [5:0] valid_1 = {_valid_T_21,_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_37}; // @[Cat.scala 31:58] wire [31:0] _data_T_17 = valid_1[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_19 = valid_1[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 155:55] + wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 154:55] wire [31:0] _data_T_22 = valid_1[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 156:55] + wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 155:55] wire [31:0] _data_T_25 = valid_1[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 157:55] + wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 156:55] wire [31:0] _data_T_28 = valid_1[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 158:55] + wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 157:55] wire [31:0] _data_T_31 = valid_1[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 159:55] - wire writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 158:55] + wire writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_29 = valid_1[1] + valid_1[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_43 = {{1'd0}, valid_1[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_31 = _GEN_43 + _T_29; // @[Bitwise.scala 48:55] @@ -311,25 +309,25 @@ wire [1:0] _GEN_44 = {{1'd0}, valid_1[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_35 = _GEN_44 + _T_33; // @[Bitwise.scala 48:55] wire [2:0] _T_37 = _T_31[1:0] + _T_35[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_45 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 143:43] - wire _valid_T_49 = io_writeData_4_valid & io_writeData_4_addr == 5'h3 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_53 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_57 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_61 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_63 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 152:43] - wire [5:0] valid_2 = {_valid_T_45,_valid_T_49,_valid_T_53,_valid_T_57,_valid_T_61,_valid_T_63}; // @[Cat.scala 31:58] + wire _valid_T_41 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 143:43] + wire _valid_T_43 = io_writeData_4_valid & io_writeData_4_addr == 5'h3; // @[Regfile.scala 144:43] + wire _valid_T_47 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_51 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_55 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_57 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 151:43] + wire [5:0] valid_2 = {_valid_T_41,_valid_T_43,_valid_T_47,_valid_T_51,_valid_T_55,_valid_T_57}; // @[Cat.scala 31:58] wire [31:0] _data_T_33 = valid_2[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_35 = valid_2[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 155:55] + wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 154:55] wire [31:0] _data_T_38 = valid_2[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 156:55] + wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 155:55] wire [31:0] _data_T_41 = valid_2[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 157:55] + wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 156:55] wire [31:0] _data_T_44 = valid_2[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 158:55] + wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 157:55] wire [31:0] _data_T_47 = valid_2[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 159:55] - wire writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 158:55] + wire writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_49 = valid_2[1] + valid_2[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_45 = {{1'd0}, valid_2[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_51 = _GEN_45 + _T_49; // @[Bitwise.scala 48:55] @@ -337,25 +335,25 @@ wire [1:0] _GEN_46 = {{1'd0}, valid_2[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_55 = _GEN_46 + _T_53; // @[Bitwise.scala 48:55] wire [2:0] _T_57 = _T_51[1:0] + _T_55[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_67 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 143:43] - wire _valid_T_71 = io_writeData_4_valid & io_writeData_4_addr == 5'h4 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_75 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_79 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_83 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_85 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 152:43] - wire [5:0] valid_3 = {_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_79,_valid_T_83,_valid_T_85}; // @[Cat.scala 31:58] + wire _valid_T_61 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 143:43] + wire _valid_T_63 = io_writeData_4_valid & io_writeData_4_addr == 5'h4; // @[Regfile.scala 144:43] + wire _valid_T_67 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_71 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_75 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_77 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 151:43] + wire [5:0] valid_3 = {_valid_T_61,_valid_T_63,_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_77}; // @[Cat.scala 31:58] wire [31:0] _data_T_49 = valid_3[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_51 = valid_3[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 155:55] + wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 154:55] wire [31:0] _data_T_54 = valid_3[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 156:55] + wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 155:55] wire [31:0] _data_T_57 = valid_3[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 157:55] + wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 156:55] wire [31:0] _data_T_60 = valid_3[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 158:55] + wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 157:55] wire [31:0] _data_T_63 = valid_3[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 159:55] - wire writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 158:55] + wire writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_69 = valid_3[1] + valid_3[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_47 = {{1'd0}, valid_3[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_71 = _GEN_47 + _T_69; // @[Bitwise.scala 48:55] @@ -363,25 +361,25 @@ wire [1:0] _GEN_48 = {{1'd0}, valid_3[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_75 = _GEN_48 + _T_73; // @[Bitwise.scala 48:55] wire [2:0] _T_77 = _T_71[1:0] + _T_75[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_89 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 143:43] - wire _valid_T_93 = io_writeData_4_valid & io_writeData_4_addr == 5'h5 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_97 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_101 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_105 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_107 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 152:43] - wire [5:0] valid_4 = {_valid_T_89,_valid_T_93,_valid_T_97,_valid_T_101,_valid_T_105,_valid_T_107}; // @[Cat.scala 31:58] + wire _valid_T_81 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 143:43] + wire _valid_T_83 = io_writeData_4_valid & io_writeData_4_addr == 5'h5; // @[Regfile.scala 144:43] + wire _valid_T_87 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_91 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_95 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_97 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 151:43] + wire [5:0] valid_4 = {_valid_T_81,_valid_T_83,_valid_T_87,_valid_T_91,_valid_T_95,_valid_T_97}; // @[Cat.scala 31:58] wire [31:0] _data_T_65 = valid_4[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_67 = valid_4[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 155:55] + wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 154:55] wire [31:0] _data_T_70 = valid_4[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 156:55] + wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 155:55] wire [31:0] _data_T_73 = valid_4[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 157:55] + wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 156:55] wire [31:0] _data_T_76 = valid_4[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 158:55] + wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 157:55] wire [31:0] _data_T_79 = valid_4[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 159:55] - wire writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 158:55] + wire writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_89 = valid_4[1] + valid_4[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_49 = {{1'd0}, valid_4[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_91 = _GEN_49 + _T_89; // @[Bitwise.scala 48:55] @@ -389,25 +387,25 @@ wire [1:0] _GEN_50 = {{1'd0}, valid_4[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_95 = _GEN_50 + _T_93; // @[Bitwise.scala 48:55] wire [2:0] _T_97 = _T_91[1:0] + _T_95[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_111 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 143:43] - wire _valid_T_115 = io_writeData_4_valid & io_writeData_4_addr == 5'h6 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_119 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_123 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_127 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_129 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 152:43] - wire [5:0] valid_5 = {_valid_T_111,_valid_T_115,_valid_T_119,_valid_T_123,_valid_T_127,_valid_T_129}; // @[Cat.scala 31:58] + wire _valid_T_101 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 143:43] + wire _valid_T_103 = io_writeData_4_valid & io_writeData_4_addr == 5'h6; // @[Regfile.scala 144:43] + wire _valid_T_107 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_111 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_115 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_117 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 151:43] + wire [5:0] valid_5 = {_valid_T_101,_valid_T_103,_valid_T_107,_valid_T_111,_valid_T_115,_valid_T_117}; // @[Cat.scala 31:58] wire [31:0] _data_T_81 = valid_5[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_83 = valid_5[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 155:55] + wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 154:55] wire [31:0] _data_T_86 = valid_5[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 156:55] + wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 155:55] wire [31:0] _data_T_89 = valid_5[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 157:55] + wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 156:55] wire [31:0] _data_T_92 = valid_5[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 158:55] + wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 157:55] wire [31:0] _data_T_95 = valid_5[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 159:55] - wire writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 158:55] + wire writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_109 = valid_5[1] + valid_5[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_51 = {{1'd0}, valid_5[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_111 = _GEN_51 + _T_109; // @[Bitwise.scala 48:55] @@ -415,25 +413,25 @@ wire [1:0] _GEN_52 = {{1'd0}, valid_5[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_115 = _GEN_52 + _T_113; // @[Bitwise.scala 48:55] wire [2:0] _T_117 = _T_111[1:0] + _T_115[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_133 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 143:43] - wire _valid_T_137 = io_writeData_4_valid & io_writeData_4_addr == 5'h7 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_141 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_145 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_149 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_151 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 152:43] - wire [5:0] valid_6 = {_valid_T_133,_valid_T_137,_valid_T_141,_valid_T_145,_valid_T_149,_valid_T_151}; // @[Cat.scala 31:58] + wire _valid_T_121 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 143:43] + wire _valid_T_123 = io_writeData_4_valid & io_writeData_4_addr == 5'h7; // @[Regfile.scala 144:43] + wire _valid_T_127 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_131 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_135 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_137 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 151:43] + wire [5:0] valid_6 = {_valid_T_121,_valid_T_123,_valid_T_127,_valid_T_131,_valid_T_135,_valid_T_137}; // @[Cat.scala 31:58] wire [31:0] _data_T_97 = valid_6[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_99 = valid_6[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 155:55] + wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 154:55] wire [31:0] _data_T_102 = valid_6[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 156:55] + wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 155:55] wire [31:0] _data_T_105 = valid_6[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 157:55] + wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 156:55] wire [31:0] _data_T_108 = valid_6[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 158:55] + wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 157:55] wire [31:0] _data_T_111 = valid_6[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 159:55] - wire writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 158:55] + wire writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_129 = valid_6[1] + valid_6[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_53 = {{1'd0}, valid_6[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_131 = _GEN_53 + _T_129; // @[Bitwise.scala 48:55] @@ -441,25 +439,25 @@ wire [1:0] _GEN_54 = {{1'd0}, valid_6[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_135 = _GEN_54 + _T_133; // @[Bitwise.scala 48:55] wire [2:0] _T_137 = _T_131[1:0] + _T_135[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_155 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 143:43] - wire _valid_T_159 = io_writeData_4_valid & io_writeData_4_addr == 5'h8 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_163 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_167 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_171 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_173 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 152:43] - wire [5:0] valid_7 = {_valid_T_155,_valid_T_159,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_173}; // @[Cat.scala 31:58] + wire _valid_T_141 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 143:43] + wire _valid_T_143 = io_writeData_4_valid & io_writeData_4_addr == 5'h8; // @[Regfile.scala 144:43] + wire _valid_T_147 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_151 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_155 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_157 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 151:43] + wire [5:0] valid_7 = {_valid_T_141,_valid_T_143,_valid_T_147,_valid_T_151,_valid_T_155,_valid_T_157}; // @[Cat.scala 31:58] wire [31:0] _data_T_113 = valid_7[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_115 = valid_7[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 155:55] + wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 154:55] wire [31:0] _data_T_118 = valid_7[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 156:55] + wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 155:55] wire [31:0] _data_T_121 = valid_7[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 157:55] + wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 156:55] wire [31:0] _data_T_124 = valid_7[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 158:55] + wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 157:55] wire [31:0] _data_T_127 = valid_7[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 159:55] - wire writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 158:55] + wire writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_149 = valid_7[1] + valid_7[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_55 = {{1'd0}, valid_7[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_151 = _GEN_55 + _T_149; // @[Bitwise.scala 48:55] @@ -467,25 +465,25 @@ wire [1:0] _GEN_56 = {{1'd0}, valid_7[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_155 = _GEN_56 + _T_153; // @[Bitwise.scala 48:55] wire [2:0] _T_157 = _T_151[1:0] + _T_155[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_177 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 143:43] - wire _valid_T_181 = io_writeData_4_valid & io_writeData_4_addr == 5'h9 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_185 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_189 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_193 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_195 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 152:43] - wire [5:0] valid_8 = {_valid_T_177,_valid_T_181,_valid_T_185,_valid_T_189,_valid_T_193,_valid_T_195}; // @[Cat.scala 31:58] + wire _valid_T_161 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 143:43] + wire _valid_T_163 = io_writeData_4_valid & io_writeData_4_addr == 5'h9; // @[Regfile.scala 144:43] + wire _valid_T_167 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_171 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_175 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_177 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 151:43] + wire [5:0] valid_8 = {_valid_T_161,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_175,_valid_T_177}; // @[Cat.scala 31:58] wire [31:0] _data_T_129 = valid_8[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_131 = valid_8[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 155:55] + wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 154:55] wire [31:0] _data_T_134 = valid_8[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 156:55] + wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 155:55] wire [31:0] _data_T_137 = valid_8[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 157:55] + wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 156:55] wire [31:0] _data_T_140 = valid_8[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 158:55] + wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 157:55] wire [31:0] _data_T_143 = valid_8[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 159:55] - wire writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 158:55] + wire writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_169 = valid_8[1] + valid_8[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_57 = {{1'd0}, valid_8[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_171 = _GEN_57 + _T_169; // @[Bitwise.scala 48:55] @@ -493,25 +491,25 @@ wire [1:0] _GEN_58 = {{1'd0}, valid_8[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_175 = _GEN_58 + _T_173; // @[Bitwise.scala 48:55] wire [2:0] _T_177 = _T_171[1:0] + _T_175[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_199 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 143:43] - wire _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'ha & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 152:43] - wire [5:0] valid_9 = {_valid_T_199,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58] + wire _valid_T_181 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 143:43] + wire _valid_T_183 = io_writeData_4_valid & io_writeData_4_addr == 5'ha; // @[Regfile.scala 144:43] + wire _valid_T_187 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_191 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_195 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_197 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 151:43] + wire [5:0] valid_9 = {_valid_T_181,_valid_T_183,_valid_T_187,_valid_T_191,_valid_T_195,_valid_T_197}; // @[Cat.scala 31:58] wire [31:0] _data_T_145 = valid_9[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_147 = valid_9[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 155:55] + wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 154:55] wire [31:0] _data_T_150 = valid_9[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 156:55] + wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 155:55] wire [31:0] _data_T_153 = valid_9[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 157:55] + wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 156:55] wire [31:0] _data_T_156 = valid_9[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 158:55] + wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 157:55] wire [31:0] _data_T_159 = valid_9[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 159:55] - wire writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 158:55] + wire writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_189 = valid_9[1] + valid_9[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_59 = {{1'd0}, valid_9[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_191 = _GEN_59 + _T_189; // @[Bitwise.scala 48:55] @@ -519,25 +517,25 @@ wire [1:0] _GEN_60 = {{1'd0}, valid_9[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_195 = _GEN_60 + _T_193; // @[Bitwise.scala 48:55] wire [2:0] _T_197 = _T_191[1:0] + _T_195[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 143:43] - wire _valid_T_225 = io_writeData_4_valid & io_writeData_4_addr == 5'hb & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_229 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_233 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_237 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_239 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 152:43] - wire [5:0] valid_10 = {_valid_T_221,_valid_T_225,_valid_T_229,_valid_T_233,_valid_T_237,_valid_T_239}; // @[Cat.scala 31:58] + wire _valid_T_201 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 143:43] + wire _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'hb; // @[Regfile.scala 144:43] + wire _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 151:43] + wire [5:0] valid_10 = {_valid_T_201,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58] wire [31:0] _data_T_161 = valid_10[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_163 = valid_10[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 155:55] + wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 154:55] wire [31:0] _data_T_166 = valid_10[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 156:55] + wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 155:55] wire [31:0] _data_T_169 = valid_10[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 157:55] + wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 156:55] wire [31:0] _data_T_172 = valid_10[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 158:55] + wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 157:55] wire [31:0] _data_T_175 = valid_10[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 159:55] - wire writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 158:55] + wire writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_209 = valid_10[1] + valid_10[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_61 = {{1'd0}, valid_10[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_211 = _GEN_61 + _T_209; // @[Bitwise.scala 48:55] @@ -545,25 +543,25 @@ wire [1:0] _GEN_62 = {{1'd0}, valid_10[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_215 = _GEN_62 + _T_213; // @[Bitwise.scala 48:55] wire [2:0] _T_217 = _T_211[1:0] + _T_215[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_243 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 143:43] - wire _valid_T_247 = io_writeData_4_valid & io_writeData_4_addr == 5'hc & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_251 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_255 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_259 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_261 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 152:43] - wire [5:0] valid_11 = {_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_259,_valid_T_261}; // @[Cat.scala 31:58] + wire _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 143:43] + wire _valid_T_223 = io_writeData_4_valid & io_writeData_4_addr == 5'hc; // @[Regfile.scala 144:43] + wire _valid_T_227 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_231 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_235 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_237 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 151:43] + wire [5:0] valid_11 = {_valid_T_221,_valid_T_223,_valid_T_227,_valid_T_231,_valid_T_235,_valid_T_237}; // @[Cat.scala 31:58] wire [31:0] _data_T_177 = valid_11[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_179 = valid_11[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 155:55] + wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 154:55] wire [31:0] _data_T_182 = valid_11[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 156:55] + wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 155:55] wire [31:0] _data_T_185 = valid_11[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 157:55] + wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 156:55] wire [31:0] _data_T_188 = valid_11[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 158:55] + wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 157:55] wire [31:0] _data_T_191 = valid_11[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 159:55] - wire writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 158:55] + wire writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_229 = valid_11[1] + valid_11[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_63 = {{1'd0}, valid_11[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_231 = _GEN_63 + _T_229; // @[Bitwise.scala 48:55] @@ -571,25 +569,25 @@ wire [1:0] _GEN_64 = {{1'd0}, valid_11[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_235 = _GEN_64 + _T_233; // @[Bitwise.scala 48:55] wire [2:0] _T_237 = _T_231[1:0] + _T_235[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_265 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 143:43] - wire _valid_T_269 = io_writeData_4_valid & io_writeData_4_addr == 5'hd & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_273 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_277 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_281 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_283 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 152:43] - wire [5:0] valid_12 = {_valid_T_265,_valid_T_269,_valid_T_273,_valid_T_277,_valid_T_281,_valid_T_283}; // @[Cat.scala 31:58] + wire _valid_T_241 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 143:43] + wire _valid_T_243 = io_writeData_4_valid & io_writeData_4_addr == 5'hd; // @[Regfile.scala 144:43] + wire _valid_T_247 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_251 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_255 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_257 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 151:43] + wire [5:0] valid_12 = {_valid_T_241,_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_257}; // @[Cat.scala 31:58] wire [31:0] _data_T_193 = valid_12[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_195 = valid_12[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 155:55] + wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 154:55] wire [31:0] _data_T_198 = valid_12[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 156:55] + wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 155:55] wire [31:0] _data_T_201 = valid_12[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 157:55] + wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 156:55] wire [31:0] _data_T_204 = valid_12[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 158:55] + wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 157:55] wire [31:0] _data_T_207 = valid_12[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 159:55] - wire writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 158:55] + wire writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_249 = valid_12[1] + valid_12[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_65 = {{1'd0}, valid_12[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_251 = _GEN_65 + _T_249; // @[Bitwise.scala 48:55] @@ -597,25 +595,25 @@ wire [1:0] _GEN_66 = {{1'd0}, valid_12[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_255 = _GEN_66 + _T_253; // @[Bitwise.scala 48:55] wire [2:0] _T_257 = _T_251[1:0] + _T_255[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_287 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 143:43] - wire _valid_T_291 = io_writeData_4_valid & io_writeData_4_addr == 5'he & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_295 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_299 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_303 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_305 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 152:43] - wire [5:0] valid_13 = {_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_299,_valid_T_303,_valid_T_305}; // @[Cat.scala 31:58] + wire _valid_T_261 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 143:43] + wire _valid_T_263 = io_writeData_4_valid & io_writeData_4_addr == 5'he; // @[Regfile.scala 144:43] + wire _valid_T_267 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_271 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_275 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_277 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 151:43] + wire [5:0] valid_13 = {_valid_T_261,_valid_T_263,_valid_T_267,_valid_T_271,_valid_T_275,_valid_T_277}; // @[Cat.scala 31:58] wire [31:0] _data_T_209 = valid_13[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_211 = valid_13[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 155:55] + wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 154:55] wire [31:0] _data_T_214 = valid_13[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 156:55] + wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 155:55] wire [31:0] _data_T_217 = valid_13[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 157:55] + wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 156:55] wire [31:0] _data_T_220 = valid_13[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 158:55] + wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 157:55] wire [31:0] _data_T_223 = valid_13[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 159:55] - wire writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 158:55] + wire writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_269 = valid_13[1] + valid_13[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_67 = {{1'd0}, valid_13[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_271 = _GEN_67 + _T_269; // @[Bitwise.scala 48:55] @@ -623,25 +621,25 @@ wire [1:0] _GEN_68 = {{1'd0}, valid_13[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_275 = _GEN_68 + _T_273; // @[Bitwise.scala 48:55] wire [2:0] _T_277 = _T_271[1:0] + _T_275[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_309 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 143:43] - wire _valid_T_313 = io_writeData_4_valid & io_writeData_4_addr == 5'hf & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_317 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_321 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_325 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_327 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 152:43] - wire [5:0] valid_14 = {_valid_T_309,_valid_T_313,_valid_T_317,_valid_T_321,_valid_T_325,_valid_T_327}; // @[Cat.scala 31:58] + wire _valid_T_281 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 143:43] + wire _valid_T_283 = io_writeData_4_valid & io_writeData_4_addr == 5'hf; // @[Regfile.scala 144:43] + wire _valid_T_287 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_291 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_295 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_297 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 151:43] + wire [5:0] valid_14 = {_valid_T_281,_valid_T_283,_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_297}; // @[Cat.scala 31:58] wire [31:0] _data_T_225 = valid_14[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_227 = valid_14[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 155:55] + wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 154:55] wire [31:0] _data_T_230 = valid_14[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 156:55] + wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 155:55] wire [31:0] _data_T_233 = valid_14[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 157:55] + wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 156:55] wire [31:0] _data_T_236 = valid_14[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 158:55] + wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 157:55] wire [31:0] _data_T_239 = valid_14[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 159:55] - wire writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 158:55] + wire writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_289 = valid_14[1] + valid_14[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_69 = {{1'd0}, valid_14[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_291 = _GEN_69 + _T_289; // @[Bitwise.scala 48:55] @@ -649,25 +647,25 @@ wire [1:0] _GEN_70 = {{1'd0}, valid_14[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_295 = _GEN_70 + _T_293; // @[Bitwise.scala 48:55] wire [2:0] _T_297 = _T_291[1:0] + _T_295[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_331 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 143:43] - wire _valid_T_335 = io_writeData_4_valid & io_writeData_4_addr == 5'h10 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_339 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_343 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_347 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_349 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 152:43] - wire [5:0] valid_15 = {_valid_T_331,_valid_T_335,_valid_T_339,_valid_T_343,_valid_T_347,_valid_T_349}; // @[Cat.scala 31:58] + wire _valid_T_301 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 143:43] + wire _valid_T_303 = io_writeData_4_valid & io_writeData_4_addr == 5'h10; // @[Regfile.scala 144:43] + wire _valid_T_307 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_311 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_315 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_317 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 151:43] + wire [5:0] valid_15 = {_valid_T_301,_valid_T_303,_valid_T_307,_valid_T_311,_valid_T_315,_valid_T_317}; // @[Cat.scala 31:58] wire [31:0] _data_T_241 = valid_15[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_243 = valid_15[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 155:55] + wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 154:55] wire [31:0] _data_T_246 = valid_15[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 156:55] + wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 155:55] wire [31:0] _data_T_249 = valid_15[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 157:55] + wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 156:55] wire [31:0] _data_T_252 = valid_15[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 158:55] + wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 157:55] wire [31:0] _data_T_255 = valid_15[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 159:55] - wire writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 158:55] + wire writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_309 = valid_15[1] + valid_15[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_71 = {{1'd0}, valid_15[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_311 = _GEN_71 + _T_309; // @[Bitwise.scala 48:55] @@ -675,25 +673,25 @@ wire [1:0] _GEN_72 = {{1'd0}, valid_15[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_315 = _GEN_72 + _T_313; // @[Bitwise.scala 48:55] wire [2:0] _T_317 = _T_311[1:0] + _T_315[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_353 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 143:43] - wire _valid_T_357 = io_writeData_4_valid & io_writeData_4_addr == 5'h11 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_361 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_365 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_369 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_371 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 152:43] - wire [5:0] valid_16 = {_valid_T_353,_valid_T_357,_valid_T_361,_valid_T_365,_valid_T_369,_valid_T_371}; // @[Cat.scala 31:58] + wire _valid_T_321 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 143:43] + wire _valid_T_323 = io_writeData_4_valid & io_writeData_4_addr == 5'h11; // @[Regfile.scala 144:43] + wire _valid_T_327 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_331 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_335 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_337 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 151:43] + wire [5:0] valid_16 = {_valid_T_321,_valid_T_323,_valid_T_327,_valid_T_331,_valid_T_335,_valid_T_337}; // @[Cat.scala 31:58] wire [31:0] _data_T_257 = valid_16[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_259 = valid_16[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 155:55] + wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 154:55] wire [31:0] _data_T_262 = valid_16[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 156:55] + wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 155:55] wire [31:0] _data_T_265 = valid_16[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 157:55] + wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 156:55] wire [31:0] _data_T_268 = valid_16[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 158:55] + wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 157:55] wire [31:0] _data_T_271 = valid_16[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 159:55] - wire writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 158:55] + wire writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_329 = valid_16[1] + valid_16[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_73 = {{1'd0}, valid_16[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_331 = _GEN_73 + _T_329; // @[Bitwise.scala 48:55] @@ -701,25 +699,25 @@ wire [1:0] _GEN_74 = {{1'd0}, valid_16[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_335 = _GEN_74 + _T_333; // @[Bitwise.scala 48:55] wire [2:0] _T_337 = _T_331[1:0] + _T_335[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_375 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 143:43] - wire _valid_T_379 = io_writeData_4_valid & io_writeData_4_addr == 5'h12 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_383 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_387 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_391 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_393 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 152:43] - wire [5:0] valid_17 = {_valid_T_375,_valid_T_379,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_393}; // @[Cat.scala 31:58] + wire _valid_T_341 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 143:43] + wire _valid_T_343 = io_writeData_4_valid & io_writeData_4_addr == 5'h12; // @[Regfile.scala 144:43] + wire _valid_T_347 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_351 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_355 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_357 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 151:43] + wire [5:0] valid_17 = {_valid_T_341,_valid_T_343,_valid_T_347,_valid_T_351,_valid_T_355,_valid_T_357}; // @[Cat.scala 31:58] wire [31:0] _data_T_273 = valid_17[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_275 = valid_17[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 155:55] + wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 154:55] wire [31:0] _data_T_278 = valid_17[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 156:55] + wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 155:55] wire [31:0] _data_T_281 = valid_17[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 157:55] + wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 156:55] wire [31:0] _data_T_284 = valid_17[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 158:55] + wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 157:55] wire [31:0] _data_T_287 = valid_17[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 159:55] - wire writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 158:55] + wire writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_349 = valid_17[1] + valid_17[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_75 = {{1'd0}, valid_17[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_351 = _GEN_75 + _T_349; // @[Bitwise.scala 48:55] @@ -727,25 +725,25 @@ wire [1:0] _GEN_76 = {{1'd0}, valid_17[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_355 = _GEN_76 + _T_353; // @[Bitwise.scala 48:55] wire [2:0] _T_357 = _T_351[1:0] + _T_355[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_397 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 143:43] - wire _valid_T_401 = io_writeData_4_valid & io_writeData_4_addr == 5'h13 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_405 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_409 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_413 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_415 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 152:43] - wire [5:0] valid_18 = {_valid_T_397,_valid_T_401,_valid_T_405,_valid_T_409,_valid_T_413,_valid_T_415}; // @[Cat.scala 31:58] + wire _valid_T_361 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 143:43] + wire _valid_T_363 = io_writeData_4_valid & io_writeData_4_addr == 5'h13; // @[Regfile.scala 144:43] + wire _valid_T_367 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_371 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_375 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_377 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 151:43] + wire [5:0] valid_18 = {_valid_T_361,_valid_T_363,_valid_T_367,_valid_T_371,_valid_T_375,_valid_T_377}; // @[Cat.scala 31:58] wire [31:0] _data_T_289 = valid_18[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_291 = valid_18[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 155:55] + wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 154:55] wire [31:0] _data_T_294 = valid_18[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 156:55] + wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 155:55] wire [31:0] _data_T_297 = valid_18[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 157:55] + wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 156:55] wire [31:0] _data_T_300 = valid_18[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 158:55] + wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 157:55] wire [31:0] _data_T_303 = valid_18[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 159:55] - wire writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 158:55] + wire writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_369 = valid_18[1] + valid_18[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_77 = {{1'd0}, valid_18[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_371 = _GEN_77 + _T_369; // @[Bitwise.scala 48:55] @@ -753,25 +751,25 @@ wire [1:0] _GEN_78 = {{1'd0}, valid_18[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_375 = _GEN_78 + _T_373; // @[Bitwise.scala 48:55] wire [2:0] _T_377 = _T_371[1:0] + _T_375[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_419 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 143:43] - wire _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h14 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 152:43] - wire [5:0] valid_19 = {_valid_T_419,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58] + wire _valid_T_381 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 143:43] + wire _valid_T_383 = io_writeData_4_valid & io_writeData_4_addr == 5'h14; // @[Regfile.scala 144:43] + wire _valid_T_387 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_391 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_395 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_397 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 151:43] + wire [5:0] valid_19 = {_valid_T_381,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_395,_valid_T_397}; // @[Cat.scala 31:58] wire [31:0] _data_T_305 = valid_19[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_307 = valid_19[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 155:55] + wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 154:55] wire [31:0] _data_T_310 = valid_19[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 156:55] + wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 155:55] wire [31:0] _data_T_313 = valid_19[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 157:55] + wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 156:55] wire [31:0] _data_T_316 = valid_19[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 158:55] + wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 157:55] wire [31:0] _data_T_319 = valid_19[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 159:55] - wire writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 158:55] + wire writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_389 = valid_19[1] + valid_19[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_79 = {{1'd0}, valid_19[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_391 = _GEN_79 + _T_389; // @[Bitwise.scala 48:55] @@ -779,25 +777,25 @@ wire [1:0] _GEN_80 = {{1'd0}, valid_19[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_395 = _GEN_80 + _T_393; // @[Bitwise.scala 48:55] wire [2:0] _T_397 = _T_391[1:0] + _T_395[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 143:43] - wire _valid_T_445 = io_writeData_4_valid & io_writeData_4_addr == 5'h15 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_449 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_453 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_457 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_459 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 152:43] - wire [5:0] valid_20 = {_valid_T_441,_valid_T_445,_valid_T_449,_valid_T_453,_valid_T_457,_valid_T_459}; // @[Cat.scala 31:58] + wire _valid_T_401 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 143:43] + wire _valid_T_403 = io_writeData_4_valid & io_writeData_4_addr == 5'h15; // @[Regfile.scala 144:43] + wire _valid_T_407 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_411 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_415 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_417 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 151:43] + wire [5:0] valid_20 = {_valid_T_401,_valid_T_403,_valid_T_407,_valid_T_411,_valid_T_415,_valid_T_417}; // @[Cat.scala 31:58] wire [31:0] _data_T_321 = valid_20[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_323 = valid_20[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 155:55] + wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 154:55] wire [31:0] _data_T_326 = valid_20[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 156:55] + wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 155:55] wire [31:0] _data_T_329 = valid_20[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 157:55] + wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 156:55] wire [31:0] _data_T_332 = valid_20[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 158:55] + wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 157:55] wire [31:0] _data_T_335 = valid_20[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 159:55] - wire writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 158:55] + wire writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_409 = valid_20[1] + valid_20[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_81 = {{1'd0}, valid_20[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_411 = _GEN_81 + _T_409; // @[Bitwise.scala 48:55] @@ -805,25 +803,25 @@ wire [1:0] _GEN_82 = {{1'd0}, valid_20[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_415 = _GEN_82 + _T_413; // @[Bitwise.scala 48:55] wire [2:0] _T_417 = _T_411[1:0] + _T_415[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_463 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 143:43] - wire _valid_T_467 = io_writeData_4_valid & io_writeData_4_addr == 5'h16 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_471 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_475 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_479 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_481 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 152:43] - wire [5:0] valid_21 = {_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_479,_valid_T_481}; // @[Cat.scala 31:58] + wire _valid_T_421 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 143:43] + wire _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h16; // @[Regfile.scala 144:43] + wire _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 151:43] + wire [5:0] valid_21 = {_valid_T_421,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58] wire [31:0] _data_T_337 = valid_21[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_339 = valid_21[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 155:55] + wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 154:55] wire [31:0] _data_T_342 = valid_21[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 156:55] + wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 155:55] wire [31:0] _data_T_345 = valid_21[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 157:55] + wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 156:55] wire [31:0] _data_T_348 = valid_21[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 158:55] + wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 157:55] wire [31:0] _data_T_351 = valid_21[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 159:55] - wire writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 158:55] + wire writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_429 = valid_21[1] + valid_21[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_83 = {{1'd0}, valid_21[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_431 = _GEN_83 + _T_429; // @[Bitwise.scala 48:55] @@ -831,25 +829,25 @@ wire [1:0] _GEN_84 = {{1'd0}, valid_21[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_435 = _GEN_84 + _T_433; // @[Bitwise.scala 48:55] wire [2:0] _T_437 = _T_431[1:0] + _T_435[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_485 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 143:43] - wire _valid_T_489 = io_writeData_4_valid & io_writeData_4_addr == 5'h17 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_493 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_497 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_501 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_503 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 152:43] - wire [5:0] valid_22 = {_valid_T_485,_valid_T_489,_valid_T_493,_valid_T_497,_valid_T_501,_valid_T_503}; // @[Cat.scala 31:58] + wire _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 143:43] + wire _valid_T_443 = io_writeData_4_valid & io_writeData_4_addr == 5'h17; // @[Regfile.scala 144:43] + wire _valid_T_447 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_451 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_455 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_457 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 151:43] + wire [5:0] valid_22 = {_valid_T_441,_valid_T_443,_valid_T_447,_valid_T_451,_valid_T_455,_valid_T_457}; // @[Cat.scala 31:58] wire [31:0] _data_T_353 = valid_22[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_355 = valid_22[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 155:55] + wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 154:55] wire [31:0] _data_T_358 = valid_22[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 156:55] + wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 155:55] wire [31:0] _data_T_361 = valid_22[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 157:55] + wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 156:55] wire [31:0] _data_T_364 = valid_22[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 158:55] + wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 157:55] wire [31:0] _data_T_367 = valid_22[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 159:55] - wire writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 158:55] + wire writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_449 = valid_22[1] + valid_22[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_85 = {{1'd0}, valid_22[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_451 = _GEN_85 + _T_449; // @[Bitwise.scala 48:55] @@ -857,25 +855,25 @@ wire [1:0] _GEN_86 = {{1'd0}, valid_22[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_455 = _GEN_86 + _T_453; // @[Bitwise.scala 48:55] wire [2:0] _T_457 = _T_451[1:0] + _T_455[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_507 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 143:43] - wire _valid_T_511 = io_writeData_4_valid & io_writeData_4_addr == 5'h18 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_515 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_519 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_523 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_525 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 152:43] - wire [5:0] valid_23 = {_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_519,_valid_T_523,_valid_T_525}; // @[Cat.scala 31:58] + wire _valid_T_461 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 143:43] + wire _valid_T_463 = io_writeData_4_valid & io_writeData_4_addr == 5'h18; // @[Regfile.scala 144:43] + wire _valid_T_467 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_471 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_475 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_477 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 151:43] + wire [5:0] valid_23 = {_valid_T_461,_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_477}; // @[Cat.scala 31:58] wire [31:0] _data_T_369 = valid_23[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_371 = valid_23[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 155:55] + wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 154:55] wire [31:0] _data_T_374 = valid_23[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 156:55] + wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 155:55] wire [31:0] _data_T_377 = valid_23[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 157:55] + wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 156:55] wire [31:0] _data_T_380 = valid_23[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 158:55] + wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 157:55] wire [31:0] _data_T_383 = valid_23[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 159:55] - wire writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 158:55] + wire writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_469 = valid_23[1] + valid_23[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_87 = {{1'd0}, valid_23[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_471 = _GEN_87 + _T_469; // @[Bitwise.scala 48:55] @@ -883,25 +881,25 @@ wire [1:0] _GEN_88 = {{1'd0}, valid_23[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_475 = _GEN_88 + _T_473; // @[Bitwise.scala 48:55] wire [2:0] _T_477 = _T_471[1:0] + _T_475[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_529 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 143:43] - wire _valid_T_533 = io_writeData_4_valid & io_writeData_4_addr == 5'h19 & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_537 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_541 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_545 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_547 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 152:43] - wire [5:0] valid_24 = {_valid_T_529,_valid_T_533,_valid_T_537,_valid_T_541,_valid_T_545,_valid_T_547}; // @[Cat.scala 31:58] + wire _valid_T_481 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 143:43] + wire _valid_T_483 = io_writeData_4_valid & io_writeData_4_addr == 5'h19; // @[Regfile.scala 144:43] + wire _valid_T_487 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_491 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_495 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_497 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 151:43] + wire [5:0] valid_24 = {_valid_T_481,_valid_T_483,_valid_T_487,_valid_T_491,_valid_T_495,_valid_T_497}; // @[Cat.scala 31:58] wire [31:0] _data_T_385 = valid_24[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_387 = valid_24[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 155:55] + wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 154:55] wire [31:0] _data_T_390 = valid_24[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 156:55] + wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 155:55] wire [31:0] _data_T_393 = valid_24[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 157:55] + wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 156:55] wire [31:0] _data_T_396 = valid_24[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 158:55] + wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 157:55] wire [31:0] _data_T_399 = valid_24[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 159:55] - wire writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 158:55] + wire writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_489 = valid_24[1] + valid_24[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_89 = {{1'd0}, valid_24[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_491 = _GEN_89 + _T_489; // @[Bitwise.scala 48:55] @@ -909,25 +907,25 @@ wire [1:0] _GEN_90 = {{1'd0}, valid_24[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_495 = _GEN_90 + _T_493; // @[Bitwise.scala 48:55] wire [2:0] _T_497 = _T_491[1:0] + _T_495[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_551 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 143:43] - wire _valid_T_555 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_559 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_563 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_567 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_569 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 152:43] - wire [5:0] valid_25 = {_valid_T_551,_valid_T_555,_valid_T_559,_valid_T_563,_valid_T_567,_valid_T_569}; // @[Cat.scala 31:58] + wire _valid_T_501 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 143:43] + wire _valid_T_503 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a; // @[Regfile.scala 144:43] + wire _valid_T_507 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_511 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_515 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_517 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 151:43] + wire [5:0] valid_25 = {_valid_T_501,_valid_T_503,_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_517}; // @[Cat.scala 31:58] wire [31:0] _data_T_401 = valid_25[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_403 = valid_25[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 155:55] + wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 154:55] wire [31:0] _data_T_406 = valid_25[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 156:55] + wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 155:55] wire [31:0] _data_T_409 = valid_25[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 157:55] + wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 156:55] wire [31:0] _data_T_412 = valid_25[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 158:55] + wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 157:55] wire [31:0] _data_T_415 = valid_25[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 159:55] - wire writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 158:55] + wire writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_509 = valid_25[1] + valid_25[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_91 = {{1'd0}, valid_25[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_511 = _GEN_91 + _T_509; // @[Bitwise.scala 48:55] @@ -935,25 +933,25 @@ wire [1:0] _GEN_92 = {{1'd0}, valid_25[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_515 = _GEN_92 + _T_513; // @[Bitwise.scala 48:55] wire [2:0] _T_517 = _T_511[1:0] + _T_515[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_573 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 143:43] - wire _valid_T_577 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_581 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_585 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_589 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_591 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 152:43] - wire [5:0] valid_26 = {_valid_T_573,_valid_T_577,_valid_T_581,_valid_T_585,_valid_T_589,_valid_T_591}; // @[Cat.scala 31:58] + wire _valid_T_521 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 143:43] + wire _valid_T_523 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b; // @[Regfile.scala 144:43] + wire _valid_T_527 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_531 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_535 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_537 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 151:43] + wire [5:0] valid_26 = {_valid_T_521,_valid_T_523,_valid_T_527,_valid_T_531,_valid_T_535,_valid_T_537}; // @[Cat.scala 31:58] wire [31:0] _data_T_417 = valid_26[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_419 = valid_26[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 155:55] + wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 154:55] wire [31:0] _data_T_422 = valid_26[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 156:55] + wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 155:55] wire [31:0] _data_T_425 = valid_26[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 157:55] + wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 156:55] wire [31:0] _data_T_428 = valid_26[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 158:55] + wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 157:55] wire [31:0] _data_T_431 = valid_26[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 159:55] - wire writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 158:55] + wire writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_529 = valid_26[1] + valid_26[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_93 = {{1'd0}, valid_26[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_531 = _GEN_93 + _T_529; // @[Bitwise.scala 48:55] @@ -961,25 +959,25 @@ wire [1:0] _GEN_94 = {{1'd0}, valid_26[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_535 = _GEN_94 + _T_533; // @[Bitwise.scala 48:55] wire [2:0] _T_537 = _T_531[1:0] + _T_535[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_595 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 143:43] - wire _valid_T_599 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_603 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_607 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_611 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_613 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 152:43] - wire [5:0] valid_27 = {_valid_T_595,_valid_T_599,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_613}; // @[Cat.scala 31:58] + wire _valid_T_541 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 143:43] + wire _valid_T_543 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c; // @[Regfile.scala 144:43] + wire _valid_T_547 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_551 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_555 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_557 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 151:43] + wire [5:0] valid_27 = {_valid_T_541,_valid_T_543,_valid_T_547,_valid_T_551,_valid_T_555,_valid_T_557}; // @[Cat.scala 31:58] wire [31:0] _data_T_433 = valid_27[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_435 = valid_27[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 155:55] + wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 154:55] wire [31:0] _data_T_438 = valid_27[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 156:55] + wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 155:55] wire [31:0] _data_T_441 = valid_27[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 157:55] + wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 156:55] wire [31:0] _data_T_444 = valid_27[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 158:55] + wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 157:55] wire [31:0] _data_T_447 = valid_27[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 159:55] - wire writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 158:55] + wire writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_549 = valid_27[1] + valid_27[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_95 = {{1'd0}, valid_27[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_551 = _GEN_95 + _T_549; // @[Bitwise.scala 48:55] @@ -987,25 +985,25 @@ wire [1:0] _GEN_96 = {{1'd0}, valid_27[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_555 = _GEN_96 + _T_553; // @[Bitwise.scala 48:55] wire [2:0] _T_557 = _T_551[1:0] + _T_555[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_617 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 143:43] - wire _valid_T_621 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_625 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_629 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_633 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_635 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 152:43] - wire [5:0] valid_28 = {_valid_T_617,_valid_T_621,_valid_T_625,_valid_T_629,_valid_T_633,_valid_T_635}; // @[Cat.scala 31:58] + wire _valid_T_561 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 143:43] + wire _valid_T_563 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d; // @[Regfile.scala 144:43] + wire _valid_T_567 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_571 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_575 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_577 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 151:43] + wire [5:0] valid_28 = {_valid_T_561,_valid_T_563,_valid_T_567,_valid_T_571,_valid_T_575,_valid_T_577}; // @[Cat.scala 31:58] wire [31:0] _data_T_449 = valid_28[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_451 = valid_28[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 155:55] + wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 154:55] wire [31:0] _data_T_454 = valid_28[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 156:55] + wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 155:55] wire [31:0] _data_T_457 = valid_28[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 157:55] + wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 156:55] wire [31:0] _data_T_460 = valid_28[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 158:55] + wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 157:55] wire [31:0] _data_T_463 = valid_28[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 159:55] - wire writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 158:55] + wire writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_569 = valid_28[1] + valid_28[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_97 = {{1'd0}, valid_28[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_571 = _GEN_97 + _T_569; // @[Bitwise.scala 48:55] @@ -1013,25 +1011,25 @@ wire [1:0] _GEN_98 = {{1'd0}, valid_28[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_575 = _GEN_98 + _T_573; // @[Bitwise.scala 48:55] wire [2:0] _T_577 = _T_571[1:0] + _T_575[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_639 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 143:43] - wire _valid_T_643 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_647 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_651 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_655 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_657 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 152:43] - wire [5:0] valid_29 = {_valid_T_639,_valid_T_643,_valid_T_647,_valid_T_651,_valid_T_655,_valid_T_657}; // @[Cat.scala 31:58] + wire _valid_T_581 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 143:43] + wire _valid_T_583 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e; // @[Regfile.scala 144:43] + wire _valid_T_587 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_591 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_595 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_597 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 151:43] + wire [5:0] valid_29 = {_valid_T_581,_valid_T_583,_valid_T_587,_valid_T_591,_valid_T_595,_valid_T_597}; // @[Cat.scala 31:58] wire [31:0] _data_T_465 = valid_29[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_467 = valid_29[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 155:55] + wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 154:55] wire [31:0] _data_T_470 = valid_29[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 156:55] + wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 155:55] wire [31:0] _data_T_473 = valid_29[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 157:55] + wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 156:55] wire [31:0] _data_T_476 = valid_29[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 158:55] + wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 157:55] wire [31:0] _data_T_479 = valid_29[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 159:55] - wire writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 158:55] + wire writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_589 = valid_29[1] + valid_29[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_99 = {{1'd0}, valid_29[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_591 = _GEN_99 + _T_589; // @[Bitwise.scala 48:55] @@ -1039,25 +1037,25 @@ wire [1:0] _GEN_100 = {{1'd0}, valid_29[3]}; // @[Bitwise.scala 48:55] wire [2:0] _T_595 = _GEN_100 + _T_593; // @[Bitwise.scala 48:55] wire [2:0] _T_597 = _T_591[1:0] + _T_595[1:0]; // @[Bitwise.scala 48:55] - wire _valid_T_661 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 143:43] - wire _valid_T_665 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f & _valid_T_4; // @[Regfile.scala 144:75] - wire _valid_T_669 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_8; // @[Regfile.scala 146:75] - wire _valid_T_673 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_12; // @[Regfile.scala 148:75] - wire _valid_T_677 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_16; // @[Regfile.scala 150:75] - wire _valid_T_679 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 152:43] - wire [5:0] valid_30 = {_valid_T_661,_valid_T_665,_valid_T_669,_valid_T_673,_valid_T_677,_valid_T_679}; // @[Cat.scala 31:58] + wire _valid_T_601 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 143:43] + wire _valid_T_603 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f; // @[Regfile.scala 144:43] + wire _valid_T_607 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_6; // @[Regfile.scala 145:75] + wire _valid_T_611 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_10; // @[Regfile.scala 147:75] + wire _valid_T_615 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_14; // @[Regfile.scala 149:75] + wire _valid_T_617 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 151:43] + wire [5:0] valid_30 = {_valid_T_601,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_615,_valid_T_617}; // @[Cat.scala 31:58] wire [31:0] _data_T_481 = valid_30[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _data_T_483 = valid_30[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 155:55] + wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 154:55] wire [31:0] _data_T_486 = valid_30[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 156:55] + wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 155:55] wire [31:0] _data_T_489 = valid_30[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 157:55] + wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 156:55] wire [31:0] _data_T_492 = valid_30[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 158:55] + wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 157:55] wire [31:0] _data_T_495 = valid_30[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 159:55] - wire writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 162:28] + wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 158:55] + wire writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 161:28] wire [1:0] _T_609 = valid_30[1] + valid_30[2]; // @[Bitwise.scala 48:55] wire [1:0] _GEN_101 = {{1'd0}, valid_30[0]}; // @[Bitwise.scala 48:55] wire [2:0] _T_611 = _GEN_101 + _T_609; // @[Bitwise.scala 48:55] @@ -1250,7 +1248,7 @@ wire [31:0] wdata_0_value_4_0 = wdata_0_value_3_0 | wdata_0_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_0_value_4_1 = wdata_0_value_3_2 | wdata_0_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_0_value_5_0 = wdata_0_value_4_0 | wdata_0_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 184:21] wire write_value_6_0 = 5'h0 == io_readAddr_1_addr; // @[Library.scala 102:27] wire write_value_6_1 = 5'h1 == io_readAddr_1_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_6_2 = 5'h2 == io_readAddr_1_addr & writeValid_2; // @[Library.scala 102:22] @@ -1436,7 +1434,7 @@ wire [31:0] wdata_1_value_4_0 = wdata_1_value_3_0 | wdata_1_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_1_value_4_1 = wdata_1_value_3_2 | wdata_1_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_1_value_5_0 = wdata_1_value_4_0 | wdata_1_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 184:21] wire write_value_12_0 = 5'h0 == io_readAddr_2_addr; // @[Library.scala 102:27] wire write_value_12_1 = 5'h1 == io_readAddr_2_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_12_2 = 5'h2 == io_readAddr_2_addr & writeValid_2; // @[Library.scala 102:22] @@ -1622,7 +1620,7 @@ wire [31:0] wdata_2_value_4_0 = wdata_2_value_3_0 | wdata_2_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_2_value_4_1 = wdata_2_value_3_2 | wdata_2_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_2_value_5_0 = wdata_2_value_4_0 | wdata_2_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 184:21] wire write_value_18_0 = 5'h0 == io_readAddr_3_addr; // @[Library.scala 102:27] wire write_value_18_1 = 5'h1 == io_readAddr_3_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_18_2 = 5'h2 == io_readAddr_3_addr & writeValid_2; // @[Library.scala 102:22] @@ -1808,7 +1806,7 @@ wire [31:0] wdata_3_value_4_0 = wdata_3_value_3_0 | wdata_3_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_3_value_4_1 = wdata_3_value_3_2 | wdata_3_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_3_value_5_0 = wdata_3_value_4_0 | wdata_3_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 184:21] wire write_value_24_0 = 5'h0 == io_readAddr_4_addr; // @[Library.scala 102:27] wire write_value_24_1 = 5'h1 == io_readAddr_4_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_24_2 = 5'h2 == io_readAddr_4_addr & writeValid_2; // @[Library.scala 102:22] @@ -1994,7 +1992,7 @@ wire [31:0] wdata_4_value_4_0 = wdata_4_value_3_0 | wdata_4_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_4_value_4_1 = wdata_4_value_3_2 | wdata_4_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_4_value_5_0 = wdata_4_value_4_0 | wdata_4_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 184:21] wire write_value_30_0 = 5'h0 == io_readAddr_5_addr; // @[Library.scala 102:27] wire write_value_30_1 = 5'h1 == io_readAddr_5_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_30_2 = 5'h2 == io_readAddr_5_addr & writeValid_2; // @[Library.scala 102:22] @@ -2180,7 +2178,7 @@ wire [31:0] wdata_5_value_4_0 = wdata_5_value_3_0 | wdata_5_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_5_value_4_1 = wdata_5_value_3_2 | wdata_5_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_5_value_5_0 = wdata_5_value_4_0 | wdata_5_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 184:21] wire write_value_36_0 = 5'h0 == io_readAddr_6_addr; // @[Library.scala 102:27] wire write_value_36_1 = 5'h1 == io_readAddr_6_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_36_2 = 5'h2 == io_readAddr_6_addr & writeValid_2; // @[Library.scala 102:22] @@ -2366,7 +2364,7 @@ wire [31:0] wdata_6_value_4_0 = wdata_6_value_3_0 | wdata_6_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_6_value_4_1 = wdata_6_value_3_2 | wdata_6_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_6_value_5_0 = wdata_6_value_4_0 | wdata_6_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 185:21] + wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 184:21] wire write_value_42_0 = 5'h0 == io_readAddr_7_addr; // @[Library.scala 102:27] wire write_value_42_1 = 5'h1 == io_readAddr_7_addr & writeValid_1; // @[Library.scala 102:22] wire write_value_42_2 = 5'h2 == io_readAddr_7_addr & writeValid_2; // @[Library.scala 102:22] @@ -2552,86 +2550,86 @@ wire [31:0] wdata_7_value_4_0 = wdata_7_value_3_0 | wdata_7_value_3_1; // @[Library.scala 116:37] wire [31:0] wdata_7_value_4_1 = wdata_7_value_3_2 | wdata_7_value_3_3; // @[Library.scala 116:37] wire [31:0] wdata_7_value_5_0 = wdata_7_value_4_0 | wdata_7_value_4_1; // @[Library.scala 116:37] - wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 185:21] - wire nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 192:49] - wire nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 192:49] - wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 210:57] - wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 210:22] - wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 210:57] - wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 210:57] - wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 210:57] - reg write_fail; // @[Regfile.scala 240:31] - wire _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 241:68] - wire _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 243:42] - reg write_fail_1; // @[Regfile.scala 240:31] - wire _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 241:68] - reg write_fail_2; // @[Regfile.scala 240:31] - wire _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 241:68] - reg write_fail_3; // @[Regfile.scala 240:31] - wire _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 241:68] - reg write_fail_4; // @[Regfile.scala 240:31] - wire _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 241:68] - reg write_fail_5; // @[Regfile.scala 240:31] - wire _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 241:68] - wire _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 243:42] - reg write_fail_6; // @[Regfile.scala 240:31] - wire _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 241:68] - reg write_fail_7; // @[Regfile.scala 240:31] - wire _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 241:68] - reg write_fail_8; // @[Regfile.scala 240:31] - wire _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 241:68] - reg write_fail_9; // @[Regfile.scala 240:31] - wire _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 241:68] - wire _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 243:42] - reg write_fail_10; // @[Regfile.scala 240:31] - wire _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 241:68] - reg write_fail_11; // @[Regfile.scala 240:31] - wire _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 241:68] - reg write_fail_12; // @[Regfile.scala 240:31] - wire _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 241:68] - wire _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 243:42] - reg write_fail_13; // @[Regfile.scala 240:31] - wire _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 241:68] - reg write_fail_14; // @[Regfile.scala 240:31] - wire _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 242:42] - wire _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 241:68] - wire _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 243:42] - reg scoreboard_error; // @[Regfile.scala 248:33] - wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 249:35] - assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 209:22] - assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 209:22] - assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 209:22] - assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 209:22] - assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 227:24] - assign io_linkPort_value = regfile_1; // @[Regfile.scala 228:21] - assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 209:22] - assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 209:22] - assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 209:22] - assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 209:22] - assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 196:30] - assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 196:30] - assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 196:30] - assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 196:30] + wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 184:21] + wire nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 191:49] + wire nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 191:49] + wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 209:57] + wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 209:22] + wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 209:57] + wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 209:57] + wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 209:57] + reg write_fail; // @[Regfile.scala 239:31] + wire _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 240:68] + wire _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 242:42] + reg write_fail_1; // @[Regfile.scala 239:31] + wire _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 240:68] + reg write_fail_2; // @[Regfile.scala 239:31] + wire _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 240:68] + reg write_fail_3; // @[Regfile.scala 239:31] + wire _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 240:68] + reg write_fail_4; // @[Regfile.scala 239:31] + wire _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 240:68] + reg write_fail_5; // @[Regfile.scala 239:31] + wire _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 240:68] + wire _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 242:42] + reg write_fail_6; // @[Regfile.scala 239:31] + wire _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 240:68] + reg write_fail_7; // @[Regfile.scala 239:31] + wire _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 240:68] + reg write_fail_8; // @[Regfile.scala 239:31] + wire _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 240:68] + reg write_fail_9; // @[Regfile.scala 239:31] + wire _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 240:68] + wire _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 242:42] + reg write_fail_10; // @[Regfile.scala 239:31] + wire _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 240:68] + reg write_fail_11; // @[Regfile.scala 239:31] + wire _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 240:68] + reg write_fail_12; // @[Regfile.scala 239:31] + wire _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 240:68] + wire _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 242:42] + reg write_fail_13; // @[Regfile.scala 239:31] + wire _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 240:68] + reg write_fail_14; // @[Regfile.scala 239:31] + wire _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 241:42] + wire _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 240:68] + wire _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 242:42] + reg scoreboard_error; // @[Regfile.scala 247:33] + wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 248:35] + assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 208:22] + assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 208:22] + assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 208:22] + assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 208:22] + assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 226:24] + assign io_linkPort_value = regfile_1; // @[Regfile.scala 227:21] + assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 208:22] + assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 208:22] + assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 208:22] + assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 208:22] + assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 195:30] + assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 195:30] + assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 195:30] + assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 195:30] assign io_readData_0_valid = readDataReady_0; // @[Regfile.scala 129:26] assign io_readData_0_data = readDataBits_0; // @[Regfile.scala 130:26] assign io_readData_1_valid = readDataReady_1; // @[Regfile.scala 129:26] @@ -2651,166 +2649,166 @@ assign io_scoreboard_regd = scoreboard; // @[Regfile.scala 118:22] assign io_scoreboard_comb = scoreboard & _nxtScoreboard_T; // @[Regfile.scala 119:36] always @(posedge clock) begin - if (writeValid_1) begin // @[Regfile.scala 169:26] - regfile_1 <= data; // @[Regfile.scala 170:18] + if (writeValid_1) begin // @[Regfile.scala 168:26] + regfile_1 <= data; // @[Regfile.scala 169:18] end - if (writeValid_2) begin // @[Regfile.scala 169:26] - regfile_2 <= data_1; // @[Regfile.scala 170:18] + if (writeValid_2) begin // @[Regfile.scala 168:26] + regfile_2 <= data_1; // @[Regfile.scala 169:18] end - if (writeValid_3) begin // @[Regfile.scala 169:26] - regfile_3 <= data_2; // @[Regfile.scala 170:18] + if (writeValid_3) begin // @[Regfile.scala 168:26] + regfile_3 <= data_2; // @[Regfile.scala 169:18] end - if (writeValid_4) begin // @[Regfile.scala 169:26] - regfile_4 <= data_3; // @[Regfile.scala 170:18] + if (writeValid_4) begin // @[Regfile.scala 168:26] + regfile_4 <= data_3; // @[Regfile.scala 169:18] end - if (writeValid_5) begin // @[Regfile.scala 169:26] - regfile_5 <= data_4; // @[Regfile.scala 170:18] + if (writeValid_5) begin // @[Regfile.scala 168:26] + regfile_5 <= data_4; // @[Regfile.scala 169:18] end - if (writeValid_6) begin // @[Regfile.scala 169:26] - regfile_6 <= data_5; // @[Regfile.scala 170:18] + if (writeValid_6) begin // @[Regfile.scala 168:26] + regfile_6 <= data_5; // @[Regfile.scala 169:18] end - if (writeValid_7) begin // @[Regfile.scala 169:26] - regfile_7 <= data_6; // @[Regfile.scala 170:18] + if (writeValid_7) begin // @[Regfile.scala 168:26] + regfile_7 <= data_6; // @[Regfile.scala 169:18] end - if (writeValid_8) begin // @[Regfile.scala 169:26] - regfile_8 <= data_7; // @[Regfile.scala 170:18] + if (writeValid_8) begin // @[Regfile.scala 168:26] + regfile_8 <= data_7; // @[Regfile.scala 169:18] end - if (writeValid_9) begin // @[Regfile.scala 169:26] - regfile_9 <= data_8; // @[Regfile.scala 170:18] + if (writeValid_9) begin // @[Regfile.scala 168:26] + regfile_9 <= data_8; // @[Regfile.scala 169:18] end - if (writeValid_10) begin // @[Regfile.scala 169:26] - regfile_10 <= data_9; // @[Regfile.scala 170:18] + if (writeValid_10) begin // @[Regfile.scala 168:26] + regfile_10 <= data_9; // @[Regfile.scala 169:18] end - if (writeValid_11) begin // @[Regfile.scala 169:26] - regfile_11 <= data_10; // @[Regfile.scala 170:18] + if (writeValid_11) begin // @[Regfile.scala 168:26] + regfile_11 <= data_10; // @[Regfile.scala 169:18] end - if (writeValid_12) begin // @[Regfile.scala 169:26] - regfile_12 <= data_11; // @[Regfile.scala 170:18] + if (writeValid_12) begin // @[Regfile.scala 168:26] + regfile_12 <= data_11; // @[Regfile.scala 169:18] end - if (writeValid_13) begin // @[Regfile.scala 169:26] - regfile_13 <= data_12; // @[Regfile.scala 170:18] + if (writeValid_13) begin // @[Regfile.scala 168:26] + regfile_13 <= data_12; // @[Regfile.scala 169:18] end - if (writeValid_14) begin // @[Regfile.scala 169:26] - regfile_14 <= data_13; // @[Regfile.scala 170:18] + if (writeValid_14) begin // @[Regfile.scala 168:26] + regfile_14 <= data_13; // @[Regfile.scala 169:18] end - if (writeValid_15) begin // @[Regfile.scala 169:26] - regfile_15 <= data_14; // @[Regfile.scala 170:18] + if (writeValid_15) begin // @[Regfile.scala 168:26] + regfile_15 <= data_14; // @[Regfile.scala 169:18] end - if (writeValid_16) begin // @[Regfile.scala 169:26] - regfile_16 <= data_15; // @[Regfile.scala 170:18] + if (writeValid_16) begin // @[Regfile.scala 168:26] + regfile_16 <= data_15; // @[Regfile.scala 169:18] end - if (writeValid_17) begin // @[Regfile.scala 169:26] - regfile_17 <= data_16; // @[Regfile.scala 170:18] + if (writeValid_17) begin // @[Regfile.scala 168:26] + regfile_17 <= data_16; // @[Regfile.scala 169:18] end - if (writeValid_18) begin // @[Regfile.scala 169:26] - regfile_18 <= data_17; // @[Regfile.scala 170:18] + if (writeValid_18) begin // @[Regfile.scala 168:26] + regfile_18 <= data_17; // @[Regfile.scala 169:18] end - if (writeValid_19) begin // @[Regfile.scala 169:26] - regfile_19 <= data_18; // @[Regfile.scala 170:18] + if (writeValid_19) begin // @[Regfile.scala 168:26] + regfile_19 <= data_18; // @[Regfile.scala 169:18] end - if (writeValid_20) begin // @[Regfile.scala 169:26] - regfile_20 <= data_19; // @[Regfile.scala 170:18] + if (writeValid_20) begin // @[Regfile.scala 168:26] + regfile_20 <= data_19; // @[Regfile.scala 169:18] end - if (writeValid_21) begin // @[Regfile.scala 169:26] - regfile_21 <= data_20; // @[Regfile.scala 170:18] + if (writeValid_21) begin // @[Regfile.scala 168:26] + regfile_21 <= data_20; // @[Regfile.scala 169:18] end - if (writeValid_22) begin // @[Regfile.scala 169:26] - regfile_22 <= data_21; // @[Regfile.scala 170:18] + if (writeValid_22) begin // @[Regfile.scala 168:26] + regfile_22 <= data_21; // @[Regfile.scala 169:18] end - if (writeValid_23) begin // @[Regfile.scala 169:26] - regfile_23 <= data_22; // @[Regfile.scala 170:18] + if (writeValid_23) begin // @[Regfile.scala 168:26] + regfile_23 <= data_22; // @[Regfile.scala 169:18] end - if (writeValid_24) begin // @[Regfile.scala 169:26] - regfile_24 <= data_23; // @[Regfile.scala 170:18] + if (writeValid_24) begin // @[Regfile.scala 168:26] + regfile_24 <= data_23; // @[Regfile.scala 169:18] end - if (writeValid_25) begin // @[Regfile.scala 169:26] - regfile_25 <= data_24; // @[Regfile.scala 170:18] + if (writeValid_25) begin // @[Regfile.scala 168:26] + regfile_25 <= data_24; // @[Regfile.scala 169:18] end - if (writeValid_26) begin // @[Regfile.scala 169:26] - regfile_26 <= data_25; // @[Regfile.scala 170:18] + if (writeValid_26) begin // @[Regfile.scala 168:26] + regfile_26 <= data_25; // @[Regfile.scala 169:18] end - if (writeValid_27) begin // @[Regfile.scala 169:26] - regfile_27 <= data_26; // @[Regfile.scala 170:18] + if (writeValid_27) begin // @[Regfile.scala 168:26] + regfile_27 <= data_26; // @[Regfile.scala 169:18] end - if (writeValid_28) begin // @[Regfile.scala 169:26] - regfile_28 <= data_27; // @[Regfile.scala 170:18] + if (writeValid_28) begin // @[Regfile.scala 168:26] + regfile_28 <= data_27; // @[Regfile.scala 169:18] end - if (writeValid_29) begin // @[Regfile.scala 169:26] - regfile_29 <= data_28; // @[Regfile.scala 170:18] + if (writeValid_29) begin // @[Regfile.scala 168:26] + regfile_29 <= data_28; // @[Regfile.scala 169:18] end - if (writeValid_30) begin // @[Regfile.scala 169:26] - regfile_30 <= data_29; // @[Regfile.scala 170:18] + if (writeValid_30) begin // @[Regfile.scala 168:26] + regfile_30 <= data_29; // @[Regfile.scala 169:18] end - if (writeValid_31) begin // @[Regfile.scala 169:26] - regfile_31 <= data_30; // @[Regfile.scala 170:18] + if (writeValid_31) begin // @[Regfile.scala 168:26] + regfile_31 <= data_30; // @[Regfile.scala 169:18] end - if (nxtReadDataReady) begin // @[Regfile.scala 198:29] - if (io_readSet_0_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady) begin // @[Regfile.scala 197:29] + if (io_readSet_0_valid) begin // @[Regfile.scala 195:30] readDataBits_0 <= io_readSet_0_value; - end else if (write_value_5_0) begin // @[Regfile.scala 185:21] + end else if (write_value_5_0) begin // @[Regfile.scala 184:21] readDataBits_0 <= wdata_0_value_5_0; end else begin readDataBits_0 <= rdata_0_value_5_0; end end - if (nxtReadDataReady_1) begin // @[Regfile.scala 198:29] - if (io_readSet_1_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_1) begin // @[Regfile.scala 197:29] + if (io_readSet_1_valid) begin // @[Regfile.scala 195:30] readDataBits_1 <= io_readSet_1_value; - end else if (write_value_11_0) begin // @[Regfile.scala 185:21] + end else if (write_value_11_0) begin // @[Regfile.scala 184:21] readDataBits_1 <= wdata_1_value_5_0; end else begin readDataBits_1 <= rdata_1_value_5_0; end end - if (nxtReadDataReady_2) begin // @[Regfile.scala 198:29] - if (io_readSet_2_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_2) begin // @[Regfile.scala 197:29] + if (io_readSet_2_valid) begin // @[Regfile.scala 195:30] readDataBits_2 <= io_readSet_2_value; - end else if (write_value_17_0) begin // @[Regfile.scala 185:21] + end else if (write_value_17_0) begin // @[Regfile.scala 184:21] readDataBits_2 <= wdata_2_value_5_0; end else begin readDataBits_2 <= rdata_2_value_5_0; end end - if (nxtReadDataReady_3) begin // @[Regfile.scala 198:29] - if (io_readSet_3_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_3) begin // @[Regfile.scala 197:29] + if (io_readSet_3_valid) begin // @[Regfile.scala 195:30] readDataBits_3 <= io_readSet_3_value; - end else if (write_value_23_0) begin // @[Regfile.scala 185:21] + end else if (write_value_23_0) begin // @[Regfile.scala 184:21] readDataBits_3 <= wdata_3_value_5_0; end else begin readDataBits_3 <= rdata_3_value_5_0; end end - if (nxtReadDataReady_4) begin // @[Regfile.scala 198:29] - if (io_readSet_4_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_4) begin // @[Regfile.scala 197:29] + if (io_readSet_4_valid) begin // @[Regfile.scala 195:30] readDataBits_4 <= io_readSet_4_value; - end else if (write_value_29_0) begin // @[Regfile.scala 185:21] + end else if (write_value_29_0) begin // @[Regfile.scala 184:21] readDataBits_4 <= wdata_4_value_5_0; end else begin readDataBits_4 <= rdata_4_value_5_0; end end - if (nxtReadDataReady_5) begin // @[Regfile.scala 198:29] - if (io_readSet_5_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_5) begin // @[Regfile.scala 197:29] + if (io_readSet_5_valid) begin // @[Regfile.scala 195:30] readDataBits_5 <= io_readSet_5_value; - end else if (write_value_35_0) begin // @[Regfile.scala 185:21] + end else if (write_value_35_0) begin // @[Regfile.scala 184:21] readDataBits_5 <= wdata_5_value_5_0; end else begin readDataBits_5 <= rdata_5_value_5_0; end end - if (nxtReadDataReady_6) begin // @[Regfile.scala 198:29] - if (io_readSet_6_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_6) begin // @[Regfile.scala 197:29] + if (io_readSet_6_valid) begin // @[Regfile.scala 195:30] readDataBits_6 <= io_readSet_6_value; - end else if (write_value_41_0) begin // @[Regfile.scala 185:21] + end else if (write_value_41_0) begin // @[Regfile.scala 184:21] readDataBits_6 <= wdata_6_value_5_0; end else begin readDataBits_6 <= rdata_6_value_5_0; end end - if (nxtReadDataReady_7) begin // @[Regfile.scala 198:29] - if (io_readSet_7_valid) begin // @[Regfile.scala 196:30] + if (nxtReadDataReady_7) begin // @[Regfile.scala 197:29] + if (io_readSet_7_valid) begin // @[Regfile.scala 195:30] readDataBits_7 <= io_readSet_7_value; - end else if (write_value_47_0) begin // @[Regfile.scala 185:21] + end else if (write_value_47_0) begin // @[Regfile.scala 184:21] readDataBits_7 <= wdata_7_value_5_0; end else begin readDataBits_7 <= rdata_7_value_5_0; @@ -2821,7 +2819,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_17 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2832,7 +2830,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_17 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2843,7 +2841,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_37 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2854,7 +2852,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_37 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2865,7 +2863,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_57 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2876,7 +2874,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_57 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2887,7 +2885,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_77 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2898,7 +2896,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_77 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2909,7 +2907,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_97 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2920,7 +2918,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_97 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2931,7 +2929,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_117 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2942,7 +2940,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_117 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2953,7 +2951,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_137 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2964,7 +2962,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_137 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2975,7 +2973,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_157 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -2986,7 +2984,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_157 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -2997,7 +2995,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_177 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3008,7 +3006,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_177 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3019,7 +3017,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_197 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3030,7 +3028,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_197 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3041,7 +3039,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_217 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3052,7 +3050,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_217 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3063,7 +3061,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_237 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3074,7 +3072,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_237 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3085,7 +3083,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_257 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3096,7 +3094,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_257 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3107,7 +3105,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_277 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3118,7 +3116,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_277 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3129,7 +3127,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_297 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3140,7 +3138,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_297 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3151,7 +3149,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_317 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3162,7 +3160,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_317 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3173,7 +3171,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_337 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3184,7 +3182,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_337 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3195,7 +3193,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_357 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3206,7 +3204,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_357 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3217,7 +3215,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_377 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3228,7 +3226,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_377 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3239,7 +3237,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_397 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3250,7 +3248,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_397 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3261,7 +3259,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_417 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3272,7 +3270,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_417 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3283,7 +3281,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_437 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3294,7 +3292,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_437 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3305,7 +3303,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_457 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3316,7 +3314,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_457 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3327,7 +3325,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_477 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3338,7 +3336,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_477 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3349,7 +3347,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_497 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3360,7 +3358,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_497 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3371,7 +3369,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_517 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3382,7 +3380,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_517 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3393,7 +3391,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_537 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3404,7 +3402,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_537 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3415,7 +3413,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_557 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3426,7 +3424,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_557 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3437,7 +3435,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_577 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3448,7 +3446,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_577 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3459,7 +3457,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_597 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3470,7 +3468,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_597 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3481,7 +3479,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(_T_617 <= 3'h1)) begin - $fatal; // @[Regfile.scala 165:11] + $fatal; // @[Regfile.scala 164:11] end `ifdef STOP_COND end @@ -3492,7 +3490,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(_T_617 <= 3'h1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:165 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 165:11] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11] end `ifdef PRINTF_COND end @@ -3503,7 +3501,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3514,7 +3512,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3525,7 +3523,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_1)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3536,7 +3534,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_1)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3547,7 +3545,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_2)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3558,7 +3556,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_2)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3569,7 +3567,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_3)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3580,7 +3578,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_3)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3591,7 +3589,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_4)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3602,7 +3600,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_4)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3613,7 +3611,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_5)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3624,7 +3622,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_5)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3635,7 +3633,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_6)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3646,7 +3644,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_6)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3657,7 +3655,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_7)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3668,7 +3666,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_7)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3679,7 +3677,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_8)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3690,7 +3688,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_8)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3701,7 +3699,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_9)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3712,7 +3710,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_9)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3723,7 +3721,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_10)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3734,7 +3732,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_10)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3745,7 +3743,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_11)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3756,7 +3754,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_11)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3767,7 +3765,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_12)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3778,7 +3776,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_12)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3789,7 +3787,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_13)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3800,7 +3798,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_13)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3811,7 +3809,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~write_fail_14)) begin - $fatal; // @[Regfile.scala 244:13] + $fatal; // @[Regfile.scala 243:13] end `ifdef STOP_COND end @@ -3822,7 +3820,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~write_fail_14)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:244 assert(!write_fail)\n"); // @[Regfile.scala 244:13] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13] end `ifdef PRINTF_COND end @@ -3833,7 +3831,7 @@ if (`STOP_COND) begin `endif if (_T_21 & ~(~scoreboard_error)) begin - $fatal; // @[Regfile.scala 250:9] + $fatal; // @[Regfile.scala 249:9] end `ifdef STOP_COND end @@ -3844,7 +3842,7 @@ if (`PRINTF_COND) begin `endif if (_T_21 & ~(~scoreboard_error)) begin - $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:250 assert(!scoreboard_error)\n"); // @[Regfile.scala 250:9] + $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:249 assert(!scoreboard_error)\n"); // @[Regfile.scala 249:9] end `ifdef PRINTF_COND end @@ -3859,168 +3857,168 @@ end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_0 <= 1'h0; end else begin readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_1 <= 1'h0; end else begin readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_2 <= 1'h0; end else begin readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_3 <= 1'h0; end else begin readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_4 <= 1'h0; end else begin readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_5 <= 1'h0; end else begin readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_6 <= 1'h0; end else begin readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 192:49] + if (reset) begin // @[Regfile.scala 191:49] readDataReady_7 <= 1'h0; end else begin readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail <= 1'h0; end else begin write_fail <= _write_fail_T_2 & _write_fail_T_3; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_1 <= 1'h0; end else begin write_fail_1 <= _write_fail_T_7 & _write_fail_T_3; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_2 <= 1'h0; end else begin write_fail_2 <= _write_fail_T_12 & _write_fail_T_3; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_3 <= 1'h0; end else begin write_fail_3 <= _write_fail_T_17 & _write_fail_T_3; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_4 <= 1'h0; end else begin write_fail_4 <= _write_fail_T_22 & _write_fail_T_3; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_5 <= 1'h0; end else begin write_fail_5 <= _write_fail_T_27 & _write_fail_T_28; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_6 <= 1'h0; end else begin write_fail_6 <= _write_fail_T_32 & _write_fail_T_28; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_7 <= 1'h0; end else begin write_fail_7 <= _write_fail_T_37 & _write_fail_T_28; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_8 <= 1'h0; end else begin write_fail_8 <= _write_fail_T_42 & _write_fail_T_28; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_9 <= 1'h0; end else begin write_fail_9 <= _write_fail_T_47 & _write_fail_T_48; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_10 <= 1'h0; end else begin write_fail_10 <= _write_fail_T_52 & _write_fail_T_48; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_11 <= 1'h0; end else begin write_fail_11 <= _write_fail_T_57 & _write_fail_T_48; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_12 <= 1'h0; end else begin write_fail_12 <= _write_fail_T_62 & _write_fail_T_63; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_13 <= 1'h0; end else begin write_fail_13 <= _write_fail_T_67 & _write_fail_T_63; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 242:67] + if (reset) begin // @[Regfile.scala 241:67] write_fail_14 <= 1'h0; end else begin write_fail_14 <= _write_fail_T_72 & _write_fail_T_73; end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Regfile.scala 249:53] + if (reset) begin // @[Regfile.scala 248:53] scoreboard_error <= 1'h0; end else begin scoreboard_error <= _scoreboard_error_T != scoreboard_clr; @@ -7946,8 +7944,8 @@ wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 317:48] wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 314:48] wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 566:89] - wire _io_getvl_T_20 = io_inst[19:15] != 5'h0; // @[Decode.scala 566:132] + wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89] + wire _io_getvl_T_20 = io_inst[19:15] != 5'h0; // @[Decode.scala 565:132] wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 314:48] @@ -7967,11 +7965,11 @@ wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 314:48] wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 579:72] - wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 580:20] - wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 584:22] - wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 583:28] - wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 584:30] + wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72] + wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20] + wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22] + wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28] + wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30] wire _io_ebreak_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 314:48] wire _io_ebreak_T_11 = _io_ebreak_T_10 & io_inst[20]; // @[Library.scala 317:48] @@ -8126,8 +8124,8 @@ wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 195:39] wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 195:39] wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 195:39] - reg onehot_failed; // @[Decode.scala 652:30] - wire _T_2 = ~reset; // @[Decode.scala 653:9] + reg onehot_failed; // @[Decode.scala 651:30] + wire _T_2 = ~reset; // @[Decode.scala 652:9] wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55] wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55] wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55] @@ -8217,14 +8215,14 @@ wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55] wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55] wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55] - wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 656:24] - wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 656:24] - wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 656:36] + wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24] + wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24] + wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36] assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58] assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58] assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58] assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58] - assign io_immcsr = {{27'd0}, io_inst[19:15]}; // @[Decode.scala 492:13] + assign io_immcsr = {{27'd0}, io_inst[19:15]}; // @[Decode.scala 491:13] assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58] assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -8287,11 +8285,11 @@ assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 566:97] - assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 567:76] + assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97] + assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76] assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 572:71] - assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 585:20] + assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71] + assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20] assign io_ebreak = _io_ebreak_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_ecall = _io_ecall_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_eexit = _io_eexit_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -8299,9 +8297,9 @@ assign io_ectxsw = _io_ectxsw_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_mpause = _io_mpause_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_mret = _io_mret_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 649:15] + assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15] assign io_fencei = _io_fencei_T_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_flushat = _io_flushat_T_23 & _io_getvl_T_20; // @[Decode.scala 598:76] + assign io_flushat = _io_flushat_T_23 & _io_getvl_T_20; // @[Decode.scala 597:76] assign io_flushall = _io_flushall_T_25 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_slog = _slog_T_21 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] always @(posedge clock) begin @@ -8310,7 +8308,7 @@ if (`STOP_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fatal; // @[Decode.scala 653:9] + $fatal; // @[Decode.scala 652:9] end `ifdef STOP_COND end @@ -8321,7 +8319,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:653 assert(!onehot_failed)\n"); // @[Decode.scala 653:9] + $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9] end `ifdef PRINTF_COND end @@ -8333,7 +8331,7 @@ `endif if (_T_6 & _T_2) begin $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,1'h0 - ); // @[Decode.scala 658:11] + ); // @[Decode.scala 657:11] end `ifdef PRINTF_COND end @@ -8341,10 +8339,10 @@ `endif // SYNTHESIS end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Decode.scala 656:45] - onehot_failed <= 1'h0; // @[Decode.scala 657:19] + if (reset) begin // @[Decode.scala 655:45] + onehot_failed <= 1'h0; // @[Decode.scala 656:19] end else begin - onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 652:30] + onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30] end end // Register and memory initialization @@ -8752,11 +8750,11 @@ wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 338:28] wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 350:65] wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 349:8] - wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 354:47] - wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 357:30] - wire _io_inst_ready_T_5 = aluEn & bruEn & lsuEn & dvuEn & vinstEn & fenceEn; // @[Decode.scala 362:73] - wire _io_serializeOut_jump_T_2 = bruOp_0 | d_io_jalr | d_io_ebreak; // @[Decode.scala 371:72] - wire _io_serializeOut_jump_T_5 = _io_serializeOut_jump_T_2 | d_io_ecall | d_io_eexit | d_io_eyield; // @[Decode.scala 372:67] + wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47] + wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30] + wire _io_inst_ready_T_5 = aluEn & bruEn & lsuEn & dvuEn & vinstEn & fenceEn; // @[Decode.scala 361:73] + wire _io_serializeOut_jump_T_2 = bruOp_0 | d_io_jalr | d_io_ebreak; // @[Decode.scala 370:72] + wire _io_serializeOut_jump_T_5 = _io_serializeOut_jump_T_2 | d_io_ecall | d_io_eexit | d_io_eyield; // @[Decode.scala 371:67] DecodedInstruction d ( // @[Decode.scala 88:17] .clock(d_clock), .reset(d_reset), @@ -8847,7 +8845,7 @@ .io_flushall(d_io_flushall), .io_slog(d_io_slog) ); - assign io_inst_ready = _io_inst_ready_T_5 & ~io_halted & ~io_interlock; // @[Decode.scala 363:55] + assign io_inst_ready = _io_inst_ready_T_5 & ~io_halted & ~io_interlock; // @[Decode.scala 362:55] assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58] assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 307:32] assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 315:25] @@ -8860,7 +8858,7 @@ assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 341:31] assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 95:20] assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 348:52] - assign io_busRead_immen = ~d_io_flushat; // @[Decode.scala 355:23] + assign io_busRead_immen = ~d_io_flushat; // @[Decode.scala 354:23] assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58] assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 166:28] assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 95:20] @@ -8889,8 +8887,8 @@ assign io_vinst_inst = io_inst_inst; // @[Decode.scala 294:17] assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 295:26] assign io_serializeOut_mul = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 195:39] - assign io_serializeOut_jump = _io_serializeOut_jump_T_5 | d_io_ectxsw | d_io_mpause | d_io_mret; // @[Decode.scala 373:69] - assign io_serializeOut_brcond = bruOp_2 | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 375:65] + assign io_serializeOut_jump = _io_serializeOut_jump_T_5 | d_io_ectxsw | d_io_mpause | d_io_mret; // @[Decode.scala 372:69] + assign io_serializeOut_brcond = bruOp_2 | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 374:65] assign io_slog = decodeEn & d_io_slog; // @[Decode.scala 304:23] assign d_clock = clock; assign d_reset = reset; @@ -9271,7 +9269,7 @@ wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 317:48] wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 314:48] wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 566:89] + wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89] wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 314:48] @@ -9291,11 +9289,11 @@ wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 314:48] wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 579:72] - wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 580:20] - wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 584:22] - wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 583:28] - wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 584:30] + wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72] + wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20] + wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22] + wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28] + wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30] wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58] wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat, io_flushall,io_slog}; // @[Cat.scala 31:58] @@ -9384,8 +9382,8 @@ wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 195:39] wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 195:39] wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 195:39] - reg onehot_failed; // @[Decode.scala 652:30] - wire _T_2 = ~reset; // @[Decode.scala 653:9] + reg onehot_failed; // @[Decode.scala 651:30] + wire _T_2 = ~reset; // @[Decode.scala 652:9] wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55] wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55] wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55] @@ -9475,9 +9473,9 @@ wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55] wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55] wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55] - wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 656:24] - wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 656:24] - wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 656:36] + wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24] + wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24] + wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36] assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58] assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58] assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58] @@ -9493,9 +9491,9 @@ assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_csrrw = 1'h0; // @[Decode.scala 606:14] - assign io_csrrs = 1'h0; // @[Decode.scala 607:14] - assign io_csrrc = 1'h0; // @[Decode.scala 608:14] + assign io_csrrw = 1'h0; // @[Decode.scala 605:14] + assign io_csrrs = 1'h0; // @[Decode.scala 606:14] + assign io_csrrc = 1'h0; // @[Decode.scala 607:14] assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -9504,7 +9502,7 @@ assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_fence = 1'h0; // @[Decode.scala 623:17] + assign io_fence = 1'h0; // @[Decode.scala 622:17] assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -9533,10 +9531,10 @@ assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_div = 1'h0; // @[Decode.scala 610:12] - assign io_divu = 1'h0; // @[Decode.scala 611:13] - assign io_rem = 1'h0; // @[Decode.scala 612:12] - assign io_remu = 1'h0; // @[Decode.scala 613:13] + assign io_div = 1'h0; // @[Decode.scala 609:12] + assign io_divu = 1'h0; // @[Decode.scala 610:13] + assign io_rem = 1'h0; // @[Decode.scala 611:12] + assign io_remu = 1'h0; // @[Decode.scala 612:13] assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -9544,30 +9542,30 @@ assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 566:97] - assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 567:76] + assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97] + assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76] assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 572:71] - assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 585:20] - assign io_ebreak = 1'h0; // @[Decode.scala 615:15] - assign io_ecall = 1'h0; // @[Decode.scala 616:15] - assign io_eexit = 1'h0; // @[Decode.scala 617:15] - assign io_eyield = 1'h0; // @[Decode.scala 618:15] - assign io_ectxsw = 1'h0; // @[Decode.scala 619:15] - assign io_mpause = 1'h0; // @[Decode.scala 620:15] - assign io_mret = 1'h0; // @[Decode.scala 621:15] - assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 649:15] - assign io_fencei = 1'h0; // @[Decode.scala 624:17] - assign io_flushat = 1'h0; // @[Decode.scala 625:17] - assign io_flushall = 1'h0; // @[Decode.scala 626:17] - assign io_slog = 1'h0; // @[Decode.scala 628:13] + assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71] + assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20] + assign io_ebreak = 1'h0; // @[Decode.scala 614:15] + assign io_ecall = 1'h0; // @[Decode.scala 615:15] + assign io_eexit = 1'h0; // @[Decode.scala 616:15] + assign io_eyield = 1'h0; // @[Decode.scala 617:15] + assign io_ectxsw = 1'h0; // @[Decode.scala 618:15] + assign io_mpause = 1'h0; // @[Decode.scala 619:15] + assign io_mret = 1'h0; // @[Decode.scala 620:15] + assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15] + assign io_fencei = 1'h0; // @[Decode.scala 623:17] + assign io_flushat = 1'h0; // @[Decode.scala 624:17] + assign io_flushall = 1'h0; // @[Decode.scala 625:17] + assign io_slog = 1'h0; // @[Decode.scala 627:13] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fatal; // @[Decode.scala 653:9] + $fatal; // @[Decode.scala 652:9] end `ifdef STOP_COND end @@ -9578,7 +9576,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:653 assert(!onehot_failed)\n"); // @[Decode.scala 653:9] + $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9] end `ifdef PRINTF_COND end @@ -9590,7 +9588,7 @@ `endif if (_T_6 & _T_2) begin $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,1'h1 - ); // @[Decode.scala 658:11] + ); // @[Decode.scala 657:11] end `ifdef PRINTF_COND end @@ -9598,10 +9596,10 @@ `endif // SYNTHESIS end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Decode.scala 656:45] - onehot_failed <= 1'h0; // @[Decode.scala 657:19] + if (reset) begin // @[Decode.scala 655:45] + onehot_failed <= 1'h0; // @[Decode.scala 656:19] end else begin - onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 652:30] + onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30] end end // Register and memory initialization @@ -9828,6 +9826,7 @@ wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 140:35] wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 139:58] wire _lsuEn_T = ~isLsu; // @[Decode.scala 143:15] + wire _lsuEn_T_4 = ~io_serializeIn_brcond; // @[Decode.scala 145:26] wire _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 145:23] wire _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 144:51] wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 146:20] @@ -9836,7 +9835,7 @@ wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 146:15] wire _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 145:50] wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 143:22] - wire mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 151:22] + wire mulEn = (~isMul | ~io_serializeIn_mul) & _lsuEn_T_4; // @[Decode.scala 151:47] wire _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 156:17] wire vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 155:76] wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 195:39] @@ -9981,12 +9980,12 @@ wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 338:28] wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 350:65] wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 349:8] - wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 354:47] - wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 357:30] - wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 363:20] - wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 362:84] - wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 364:43] - wire _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 374:51] + wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47] + wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30] + wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 362:20] + wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 361:84] + wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 363:43] + wire _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 373:51] DecodedInstruction_1 d ( // @[Decode.scala 88:17] .clock(d_clock), .reset(d_reset), @@ -10076,7 +10075,7 @@ .io_flushall(d_io_flushall), .io_slog(d_io_slog) ); - assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 363:72] + assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 362:72] assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58] assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 307:32] assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 315:25] @@ -10111,9 +10110,9 @@ assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 95:20] assign io_vinst_inst = io_inst_inst; // @[Decode.scala 294:17] assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 295:26] - assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 370:46] - assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 371:59] - assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 375:65] + assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 369:46] + assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 370:59] + assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 374:65] assign d_clock = clock; assign d_reset = reset; assign d_io_addr = io_inst_addr; // @[Decode.scala 89:13] @@ -10493,7 +10492,7 @@ wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 317:48] wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 314:48] wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 566:89] + wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89] wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 314:48] @@ -10513,11 +10512,11 @@ wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 314:48] wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 579:72] - wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 580:20] - wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 584:22] - wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 583:28] - wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 584:30] + wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72] + wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20] + wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22] + wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28] + wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30] wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58] wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat, io_flushall,io_slog}; // @[Cat.scala 31:58] @@ -10606,8 +10605,8 @@ wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 195:39] wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 195:39] wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 195:39] - reg onehot_failed; // @[Decode.scala 652:30] - wire _T_2 = ~reset; // @[Decode.scala 653:9] + reg onehot_failed; // @[Decode.scala 651:30] + wire _T_2 = ~reset; // @[Decode.scala 652:9] wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55] wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55] wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55] @@ -10697,9 +10696,9 @@ wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55] wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55] wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55] - wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 656:24] - wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 656:24] - wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 656:36] + wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24] + wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24] + wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36] assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58] assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58] assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58] @@ -10715,9 +10714,9 @@ assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_csrrw = 1'h0; // @[Decode.scala 606:14] - assign io_csrrs = 1'h0; // @[Decode.scala 607:14] - assign io_csrrc = 1'h0; // @[Decode.scala 608:14] + assign io_csrrw = 1'h0; // @[Decode.scala 605:14] + assign io_csrrs = 1'h0; // @[Decode.scala 606:14] + assign io_csrrc = 1'h0; // @[Decode.scala 607:14] assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -10726,7 +10725,7 @@ assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_fence = 1'h0; // @[Decode.scala 623:17] + assign io_fence = 1'h0; // @[Decode.scala 622:17] assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -10755,10 +10754,10 @@ assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_div = 1'h0; // @[Decode.scala 610:12] - assign io_divu = 1'h0; // @[Decode.scala 611:13] - assign io_rem = 1'h0; // @[Decode.scala 612:12] - assign io_remu = 1'h0; // @[Decode.scala 613:13] + assign io_div = 1'h0; // @[Decode.scala 609:12] + assign io_divu = 1'h0; // @[Decode.scala 610:13] + assign io_rem = 1'h0; // @[Decode.scala 611:12] + assign io_remu = 1'h0; // @[Decode.scala 612:13] assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -10766,30 +10765,30 @@ assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 566:97] - assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 567:76] + assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97] + assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76] assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 572:71] - assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 585:20] - assign io_ebreak = 1'h0; // @[Decode.scala 615:15] - assign io_ecall = 1'h0; // @[Decode.scala 616:15] - assign io_eexit = 1'h0; // @[Decode.scala 617:15] - assign io_eyield = 1'h0; // @[Decode.scala 618:15] - assign io_ectxsw = 1'h0; // @[Decode.scala 619:15] - assign io_mpause = 1'h0; // @[Decode.scala 620:15] - assign io_mret = 1'h0; // @[Decode.scala 621:15] - assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 649:15] - assign io_fencei = 1'h0; // @[Decode.scala 624:17] - assign io_flushat = 1'h0; // @[Decode.scala 625:17] - assign io_flushall = 1'h0; // @[Decode.scala 626:17] - assign io_slog = 1'h0; // @[Decode.scala 628:13] + assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71] + assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20] + assign io_ebreak = 1'h0; // @[Decode.scala 614:15] + assign io_ecall = 1'h0; // @[Decode.scala 615:15] + assign io_eexit = 1'h0; // @[Decode.scala 616:15] + assign io_eyield = 1'h0; // @[Decode.scala 617:15] + assign io_ectxsw = 1'h0; // @[Decode.scala 618:15] + assign io_mpause = 1'h0; // @[Decode.scala 619:15] + assign io_mret = 1'h0; // @[Decode.scala 620:15] + assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15] + assign io_fencei = 1'h0; // @[Decode.scala 623:17] + assign io_flushat = 1'h0; // @[Decode.scala 624:17] + assign io_flushall = 1'h0; // @[Decode.scala 625:17] + assign io_slog = 1'h0; // @[Decode.scala 627:13] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fatal; // @[Decode.scala 653:9] + $fatal; // @[Decode.scala 652:9] end `ifdef STOP_COND end @@ -10800,7 +10799,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:653 assert(!onehot_failed)\n"); // @[Decode.scala 653:9] + $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9] end `ifdef PRINTF_COND end @@ -10812,7 +10811,7 @@ `endif if (_T_6 & _T_2) begin $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,2'h2 - ); // @[Decode.scala 658:11] + ); // @[Decode.scala 657:11] end `ifdef PRINTF_COND end @@ -10820,10 +10819,10 @@ `endif // SYNTHESIS end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Decode.scala 656:45] - onehot_failed <= 1'h0; // @[Decode.scala 657:19] + if (reset) begin // @[Decode.scala 655:45] + onehot_failed <= 1'h0; // @[Decode.scala 656:19] end else begin - onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 652:30] + onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30] end end // Register and memory initialization @@ -11050,6 +11049,7 @@ wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 140:35] wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 139:58] wire _lsuEn_T = ~isLsu; // @[Decode.scala 143:15] + wire _lsuEn_T_4 = ~io_serializeIn_brcond; // @[Decode.scala 145:26] wire _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 145:23] wire _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 144:51] wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 146:20] @@ -11058,7 +11058,7 @@ wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 146:15] wire _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 145:50] wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 143:22] - wire mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 151:22] + wire mulEn = (~isMul | ~io_serializeIn_mul) & _lsuEn_T_4; // @[Decode.scala 151:47] wire _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 156:17] wire vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 155:76] wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 195:39] @@ -11203,12 +11203,12 @@ wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 338:28] wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 350:65] wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 349:8] - wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 354:47] - wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 357:30] - wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 363:20] - wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 362:84] - wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 364:43] - wire _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 374:51] + wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47] + wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30] + wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 362:20] + wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 361:84] + wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 363:43] + wire _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 373:51] DecodedInstruction_2 d ( // @[Decode.scala 88:17] .clock(d_clock), .reset(d_reset), @@ -11298,7 +11298,7 @@ .io_flushall(d_io_flushall), .io_slog(d_io_slog) ); - assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 363:72] + assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 362:72] assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58] assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 307:32] assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 315:25] @@ -11333,9 +11333,9 @@ assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 95:20] assign io_vinst_inst = io_inst_inst; // @[Decode.scala 294:17] assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 295:26] - assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 370:46] - assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 371:59] - assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 375:65] + assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 369:46] + assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 370:59] + assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 374:65] assign d_clock = clock; assign d_reset = reset; assign d_io_addr = io_inst_addr; // @[Decode.scala 89:13] @@ -11715,7 +11715,7 @@ wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 317:48] wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 314:48] wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 566:89] + wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89] wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 314:48] @@ -11735,11 +11735,11 @@ wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 314:48] wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 579:72] - wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 580:20] - wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 584:22] - wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 583:28] - wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 584:30] + wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72] + wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20] + wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22] + wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28] + wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30] wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58] wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat, io_flushall,io_slog}; // @[Cat.scala 31:58] @@ -11828,8 +11828,8 @@ wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 195:39] wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 195:39] wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 195:39] - reg onehot_failed; // @[Decode.scala 652:30] - wire _T_2 = ~reset; // @[Decode.scala 653:9] + reg onehot_failed; // @[Decode.scala 651:30] + wire _T_2 = ~reset; // @[Decode.scala 652:9] wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55] wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55] wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55] @@ -11919,9 +11919,9 @@ wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55] wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55] wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55] - wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 656:24] - wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 656:24] - wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 656:36] + wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24] + wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24] + wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36] assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58] assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58] assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58] @@ -11937,9 +11937,9 @@ assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_csrrw = 1'h0; // @[Decode.scala 606:14] - assign io_csrrs = 1'h0; // @[Decode.scala 607:14] - assign io_csrrc = 1'h0; // @[Decode.scala 608:14] + assign io_csrrw = 1'h0; // @[Decode.scala 605:14] + assign io_csrrs = 1'h0; // @[Decode.scala 606:14] + assign io_csrrc = 1'h0; // @[Decode.scala 607:14] assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -11948,7 +11948,7 @@ assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_fence = 1'h0; // @[Decode.scala 623:17] + assign io_fence = 1'h0; // @[Decode.scala 622:17] assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -11977,10 +11977,10 @@ assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_div = 1'h0; // @[Decode.scala 610:12] - assign io_divu = 1'h0; // @[Decode.scala 611:13] - assign io_rem = 1'h0; // @[Decode.scala 612:12] - assign io_remu = 1'h0; // @[Decode.scala 613:13] + assign io_div = 1'h0; // @[Decode.scala 609:12] + assign io_divu = 1'h0; // @[Decode.scala 610:13] + assign io_rem = 1'h0; // @[Decode.scala 611:12] + assign io_remu = 1'h0; // @[Decode.scala 612:13] assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] @@ -11988,30 +11988,30 @@ assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 566:97] - assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 567:76] + assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97] + assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76] assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 317:48] - assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 572:71] - assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 585:20] - assign io_ebreak = 1'h0; // @[Decode.scala 615:15] - assign io_ecall = 1'h0; // @[Decode.scala 616:15] - assign io_eexit = 1'h0; // @[Decode.scala 617:15] - assign io_eyield = 1'h0; // @[Decode.scala 618:15] - assign io_ectxsw = 1'h0; // @[Decode.scala 619:15] - assign io_mpause = 1'h0; // @[Decode.scala 620:15] - assign io_mret = 1'h0; // @[Decode.scala 621:15] - assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 649:15] - assign io_fencei = 1'h0; // @[Decode.scala 624:17] - assign io_flushat = 1'h0; // @[Decode.scala 625:17] - assign io_flushall = 1'h0; // @[Decode.scala 626:17] - assign io_slog = 1'h0; // @[Decode.scala 628:13] + assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71] + assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20] + assign io_ebreak = 1'h0; // @[Decode.scala 614:15] + assign io_ecall = 1'h0; // @[Decode.scala 615:15] + assign io_eexit = 1'h0; // @[Decode.scala 616:15] + assign io_eyield = 1'h0; // @[Decode.scala 617:15] + assign io_ectxsw = 1'h0; // @[Decode.scala 618:15] + assign io_mpause = 1'h0; // @[Decode.scala 619:15] + assign io_mret = 1'h0; // @[Decode.scala 620:15] + assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15] + assign io_fencei = 1'h0; // @[Decode.scala 623:17] + assign io_flushat = 1'h0; // @[Decode.scala 624:17] + assign io_flushall = 1'h0; // @[Decode.scala 625:17] + assign io_slog = 1'h0; // @[Decode.scala 627:13] always @(posedge clock) begin `ifndef SYNTHESIS `ifdef STOP_COND if (`STOP_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fatal; // @[Decode.scala 653:9] + $fatal; // @[Decode.scala 652:9] end `ifdef STOP_COND end @@ -12022,7 +12022,7 @@ if (`PRINTF_COND) begin `endif if (~reset & ~(~onehot_failed)) begin - $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:653 assert(!onehot_failed)\n"); // @[Decode.scala 653:9] + $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9] end `ifdef PRINTF_COND end @@ -12034,7 +12034,7 @@ `endif if (_T_6 & _T_2) begin $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,2'h3 - ); // @[Decode.scala 658:11] + ); // @[Decode.scala 657:11] end `ifdef PRINTF_COND end @@ -12042,10 +12042,10 @@ `endif // SYNTHESIS end always @(posedge clock or posedge reset) begin - if (reset) begin // @[Decode.scala 656:45] - onehot_failed <= 1'h0; // @[Decode.scala 657:19] + if (reset) begin // @[Decode.scala 655:45] + onehot_failed <= 1'h0; // @[Decode.scala 656:19] end else begin - onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 652:30] + onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30] end end // Register and memory initialization @@ -12268,6 +12268,7 @@ wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 140:35] wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 139:58] wire _lsuEn_T = ~isLsu; // @[Decode.scala 143:15] + wire _lsuEn_T_4 = ~io_serializeIn_brcond; // @[Decode.scala 145:26] wire _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 145:23] wire _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 144:51] wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 146:20] @@ -12276,7 +12277,7 @@ wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 146:15] wire _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 145:50] wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 143:22] - wire mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 151:22] + wire mulEn = (~isMul | ~io_serializeIn_mul) & _lsuEn_T_4; // @[Decode.scala 151:47] wire _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 156:17] wire vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 155:76] wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 195:39] @@ -12419,11 +12420,11 @@ wire rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 334:47] wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 350:65] wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 349:8] - wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 354:47] - wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 357:30] - wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 363:20] - wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 362:84] - wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 364:43] + wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47] + wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30] + wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 362:20] + wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 361:84] + wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 363:43] DecodedInstruction_3 d ( // @[Decode.scala 88:17] .clock(d_clock), .reset(d_reset), @@ -12513,7 +12514,7 @@ .io_flushall(d_io_flushall), .io_slog(d_io_slog) ); - assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 363:72] + assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 362:72] assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 307:32] assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 315:25] assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 321:31] @@ -21176,7 +21177,6 @@ reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; - reg [31:0] _RAND_3; `endif // RANDOMIZE_REG_INIT wire regfile_clock; // @[Regfile.scala 10:18] wire regfile_reset; // @[Regfile.scala 10:18] @@ -21281,7 +21281,6 @@ wire regfile_io_writeMask_1_valid; // @[Regfile.scala 10:18] wire regfile_io_writeMask_2_valid; // @[Regfile.scala 10:18] wire regfile_io_writeMask_3_valid; // @[Regfile.scala 10:18] - wire regfile_io_writeMask_4_valid; // @[Regfile.scala 10:18] wire [31:0] regfile_io_scoreboard_regd; // @[Regfile.scala 10:18] wire [31:0] regfile_io_scoreboard_comb; // @[Regfile.scala 10:18] wire fetch_clock; // @[Fetch.scala 10:18] @@ -21854,74 +21853,73 @@ wire _fetch_io_inst_lanes_0_ready_T = decode_0_io_inst_ready; // @[SCore.scala 91:61] wire [31:0] scoreboard_spec2 = decode_1_io_scoreboard_spec | decode_0_io_scoreboard_spec; // @[SCore.scala 114:55] wire [31:0] scoreboard_spec3 = decode_2_io_scoreboard_spec | scoreboard_spec2; // @[SCore.scala 115:55] - reg mluInvalidate; // @[SCore.scala 201:30] - wire _regfile_io_writeData_0_valid_T = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 231:48] + wire _regfile_io_writeData_0_valid_T = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 227:48] wire [4:0] _regfile_io_writeData_0_addr_T = csr_io_rd_valid ? csr_io_rd_addr : 5'h0; // @[Library.scala 9:8] wire [4:0] _regfile_io_writeData_0_addr_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_addr : 5'h0; // @[Library.scala 9:8] - wire [4:0] _regfile_io_writeData_0_addr_T_2 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_1; // @[SCore.scala 236:36] + wire [4:0] _regfile_io_writeData_0_addr_T_2 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_1; // @[SCore.scala 232:36] wire [4:0] _regfile_io_writeData_0_addr_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_addr : 5'h0; // @[Library.scala 9:8] - wire [4:0] _regfile_io_writeData_0_addr_T_4 = _regfile_io_writeData_0_addr_T_2 | _regfile_io_writeData_0_addr_T_3; // @[SCore.scala 237:54] + wire [4:0] _regfile_io_writeData_0_addr_T_4 = _regfile_io_writeData_0_addr_T_2 | _regfile_io_writeData_0_addr_T_3; // @[SCore.scala 233:54] wire [4:0] _regfile_io_writeData_0_addr_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_addr : 5'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_0_data_T = csr_io_rd_valid ? csr_io_rd_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_0_data_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _regfile_io_writeData_0_data_T_2 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_1; // @[SCore.scala 242:36] + wire [31:0] _regfile_io_writeData_0_data_T_2 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_1; // @[SCore.scala 238:36] wire [31:0] _regfile_io_writeData_0_data_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _regfile_io_writeData_0_data_T_4 = _regfile_io_writeData_0_data_T_2 | _regfile_io_writeData_0_data_T_3; // @[SCore.scala 243:54] + wire [31:0] _regfile_io_writeData_0_data_T_4 = _regfile_io_writeData_0_data_T_2 | _regfile_io_writeData_0_data_T_3; // @[SCore.scala 239:54] wire [31:0] _regfile_io_writeData_0_data_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_data : 32'h0; // @[Library.scala 9:8] - wire [1:0] _T_15 = csr_io_rd_valid + alu_0_io_rd_valid; // @[SCore.scala 247:23] - wire [1:0] _GEN_3 = {{1'd0}, bru_0_io_rd_valid}; // @[SCore.scala 248:32] - wire [2:0] _T_16 = _T_15 + _GEN_3; // @[SCore.scala 248:32] - wire [2:0] _GEN_4 = {{2'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 248:54] - wire [3:0] _T_17 = _T_16 + _GEN_4; // @[SCore.scala 248:54] - wire _T_18 = _T_17 <= 4'h1; // @[SCore.scala 249:35] - wire _regfile_io_writeData_1_valid_T = alu_1_io_rd_valid; // @[SCore.scala 231:48] + wire [1:0] _T_15 = csr_io_rd_valid + alu_0_io_rd_valid; // @[SCore.scala 243:23] + wire [1:0] _GEN_3 = {{1'd0}, bru_0_io_rd_valid}; // @[SCore.scala 244:32] + wire [2:0] _T_16 = _T_15 + _GEN_3; // @[SCore.scala 244:32] + wire [2:0] _GEN_4 = {{2'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 244:54] + wire [3:0] _T_17 = _T_16 + _GEN_4; // @[SCore.scala 244:54] + wire _T_18 = _T_17 <= 4'h1; // @[SCore.scala 245:35] + wire _regfile_io_writeData_1_valid_T = alu_1_io_rd_valid; // @[SCore.scala 227:48] wire [4:0] _regfile_io_writeData_1_addr_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_addr : 5'h0; // @[Library.scala 9:8] wire [4:0] _regfile_io_writeData_1_addr_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_addr : 5'h0; // @[Library.scala 9:8] - wire [4:0] _regfile_io_writeData_1_addr_T_4 = _regfile_io_writeData_1_addr_T_1 | _regfile_io_writeData_1_addr_T_3; // @[SCore.scala 237:54] + wire [4:0] _regfile_io_writeData_1_addr_T_4 = _regfile_io_writeData_1_addr_T_1 | _regfile_io_writeData_1_addr_T_3; // @[SCore.scala 233:54] wire [4:0] _regfile_io_writeData_1_addr_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_addr : 5'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_1_data_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_1_data_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _regfile_io_writeData_1_data_T_4 = _regfile_io_writeData_1_data_T_1 | _regfile_io_writeData_1_data_T_3; // @[SCore.scala 243:54] + wire [31:0] _regfile_io_writeData_1_data_T_4 = _regfile_io_writeData_1_data_T_1 | _regfile_io_writeData_1_data_T_3; // @[SCore.scala 239:54] wire [31:0] _regfile_io_writeData_1_data_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_data : 32'h0; // @[Library.scala 9:8] - wire [1:0] _T_22 = {{1'd0}, alu_1_io_rd_valid}; // @[SCore.scala 247:23] - wire [1:0] _GEN_5 = {{1'd0}, bru_1_io_rd_valid}; // @[SCore.scala 248:32] - wire [2:0] _T_23 = _T_22 + _GEN_5; // @[SCore.scala 248:32] - wire [2:0] _GEN_6 = {{2'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 248:54] - wire [3:0] _T_24 = _T_23 + _GEN_6; // @[SCore.scala 248:54] - wire _T_25 = _T_24 <= 4'h1; // @[SCore.scala 249:35] - wire _regfile_io_writeData_2_valid_T = alu_2_io_rd_valid; // @[SCore.scala 231:48] + wire [1:0] _T_22 = {{1'd0}, alu_1_io_rd_valid}; // @[SCore.scala 243:23] + wire [1:0] _GEN_5 = {{1'd0}, bru_1_io_rd_valid}; // @[SCore.scala 244:32] + wire [2:0] _T_23 = _T_22 + _GEN_5; // @[SCore.scala 244:32] + wire [2:0] _GEN_6 = {{2'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 244:54] + wire [3:0] _T_24 = _T_23 + _GEN_6; // @[SCore.scala 244:54] + wire _T_25 = _T_24 <= 4'h1; // @[SCore.scala 245:35] + wire _regfile_io_writeData_2_valid_T = alu_2_io_rd_valid; // @[SCore.scala 227:48] wire [4:0] _regfile_io_writeData_2_addr_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_addr : 5'h0; // @[Library.scala 9:8] wire [4:0] _regfile_io_writeData_2_addr_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_addr : 5'h0; // @[Library.scala 9:8] - wire [4:0] _regfile_io_writeData_2_addr_T_4 = _regfile_io_writeData_2_addr_T_1 | _regfile_io_writeData_2_addr_T_3; // @[SCore.scala 237:54] + wire [4:0] _regfile_io_writeData_2_addr_T_4 = _regfile_io_writeData_2_addr_T_1 | _regfile_io_writeData_2_addr_T_3; // @[SCore.scala 233:54] wire [4:0] _regfile_io_writeData_2_addr_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_addr : 5'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_2_data_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_2_data_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _regfile_io_writeData_2_data_T_4 = _regfile_io_writeData_2_data_T_1 | _regfile_io_writeData_2_data_T_3; // @[SCore.scala 243:54] + wire [31:0] _regfile_io_writeData_2_data_T_4 = _regfile_io_writeData_2_data_T_1 | _regfile_io_writeData_2_data_T_3; // @[SCore.scala 239:54] wire [31:0] _regfile_io_writeData_2_data_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_data : 32'h0; // @[Library.scala 9:8] - wire [1:0] _T_29 = {{1'd0}, alu_2_io_rd_valid}; // @[SCore.scala 247:23] - wire [1:0] _GEN_7 = {{1'd0}, bru_2_io_rd_valid}; // @[SCore.scala 248:32] - wire [2:0] _T_30 = _T_29 + _GEN_7; // @[SCore.scala 248:32] - wire [2:0] _GEN_8 = {{2'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 248:54] - wire [3:0] _T_31 = _T_30 + _GEN_8; // @[SCore.scala 248:54] - wire _T_32 = _T_31 <= 4'h1; // @[SCore.scala 249:35] - wire _regfile_io_writeData_3_valid_T = alu_3_io_rd_valid; // @[SCore.scala 231:48] + wire [1:0] _T_29 = {{1'd0}, alu_2_io_rd_valid}; // @[SCore.scala 243:23] + wire [1:0] _GEN_7 = {{1'd0}, bru_2_io_rd_valid}; // @[SCore.scala 244:32] + wire [2:0] _T_30 = _T_29 + _GEN_7; // @[SCore.scala 244:32] + wire [2:0] _GEN_8 = {{2'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 244:54] + wire [3:0] _T_31 = _T_30 + _GEN_8; // @[SCore.scala 244:54] + wire _T_32 = _T_31 <= 4'h1; // @[SCore.scala 245:35] + wire _regfile_io_writeData_3_valid_T = alu_3_io_rd_valid; // @[SCore.scala 227:48] wire [4:0] _regfile_io_writeData_3_addr_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_addr : 5'h0; // @[Library.scala 9:8] wire [4:0] _regfile_io_writeData_3_addr_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_addr : 5'h0; // @[Library.scala 9:8] - wire [4:0] _regfile_io_writeData_3_addr_T_4 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_3; // @[SCore.scala 237:54] + wire [4:0] _regfile_io_writeData_3_addr_T_4 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_3; // @[SCore.scala 233:54] wire [4:0] _regfile_io_writeData_3_addr_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_addr : 5'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_3_data_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_data : 32'h0; // @[Library.scala 9:8] wire [31:0] _regfile_io_writeData_3_data_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_data : 32'h0; // @[Library.scala 9:8] - wire [31:0] _regfile_io_writeData_3_data_T_4 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_3; // @[SCore.scala 243:54] + wire [31:0] _regfile_io_writeData_3_data_T_4 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_3; // @[SCore.scala 239:54] wire [31:0] _regfile_io_writeData_3_data_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_data : 32'h0; // @[Library.scala 9:8] - wire [1:0] _T_36 = {{1'd0}, alu_3_io_rd_valid}; // @[SCore.scala 247:23] - wire [1:0] _GEN_9 = {{1'd0}, bru_3_io_rd_valid}; // @[SCore.scala 248:32] - wire [2:0] _T_37 = _T_36 + _GEN_9; // @[SCore.scala 248:32] - wire [2:0] _GEN_10 = {{2'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 248:54] - wire [3:0] _T_38 = _T_37 + _GEN_10; // @[SCore.scala 248:54] - wire _T_39 = _T_38 <= 4'h1; // @[SCore.scala 249:35] - reg slogValid; // @[SCore.scala 293:26] - reg [1:0] slogAddr; // @[SCore.scala 294:21] - wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 298:17 299:14 294:21] + wire [1:0] _T_36 = {{1'd0}, alu_3_io_rd_valid}; // @[SCore.scala 243:23] + wire [1:0] _GEN_9 = {{1'd0}, bru_3_io_rd_valid}; // @[SCore.scala 244:32] + wire [2:0] _T_37 = _T_36 + _GEN_9; // @[SCore.scala 244:32] + wire [2:0] _GEN_10 = {{2'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 244:54] + wire [3:0] _T_38 = _T_37 + _GEN_10; // @[SCore.scala 244:54] + wire _T_39 = _T_38 <= 4'h1; // @[SCore.scala 245:35] + reg slogValid; // @[SCore.scala 288:26] + reg [1:0] slogAddr; // @[SCore.scala 289:21] + wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 293:17 294:14 289:21] wire [1:0] _io_slog_addr_T = slogValid ? slogAddr : 2'h0; // @[Library.scala 9:8] Regfile regfile ( // @[Regfile.scala 10:18] .clock(regfile_clock), @@ -22027,7 +22025,6 @@ .io_writeMask_1_valid(regfile_io_writeMask_1_valid), .io_writeMask_2_valid(regfile_io_writeMask_2_valid), .io_writeMask_3_valid(regfile_io_writeMask_3_valid), - .io_writeMask_4_valid(regfile_io_writeMask_4_valid), .io_scoreboard_regd(regfile_io_scoreboard_regd), .io_scoreboard_comb(regfile_io_scoreboard_comb) ); @@ -22627,130 +22624,129 @@ ); assign io_halted = csr_io_halted; // @[SCore.scala 170:13] assign io_fault = csr_io_fault; // @[SCore.scala 171:13] - assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 282:11] - assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 282:11] - assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 286:11] - assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 286:11] - assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 286:11] - assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 286:11] - assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 286:11] - assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 286:11] - assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 286:11] - assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 287:11] - assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 287:11] - assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 287:11] - assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 287:11] - assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 287:11] - assign io_vldst = lsu_io_vldst; // @[SCore.scala 289:12] - assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 273:23] - assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 273:23] - assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 273:23] - assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 273:23] - assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 273:23] - assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 273:23] - assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 273:23] - assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 273:23] - assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 273:23] - assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 273:23] - assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 273:23] - assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 273:23] - assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 273:23] - assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 273:23] - assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 273:23] - assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 273:23] - assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 277:20] - assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 277:20] - assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 277:20] - assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 277:20] - assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 277:20] - assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 277:20] - assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 277:20] - assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 277:20] + assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 277:11] + assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 277:11] + assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 281:11] + assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 281:11] + assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 281:11] + assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 281:11] + assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 281:11] + assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 281:11] + assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 281:11] + assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 282:11] + assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 282:11] + assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 282:11] + assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 282:11] + assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 282:11] + assign io_vldst = lsu_io_vldst; // @[SCore.scala 284:12] + assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 268:23] + assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 268:23] + assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 268:23] + assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 268:23] + assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 268:23] + assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 268:23] + assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 268:23] + assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 268:23] + assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 268:23] + assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 268:23] + assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 268:23] + assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 268:23] + assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 268:23] + assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 268:23] + assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 268:23] + assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 268:23] + assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 272:20] + assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 272:20] + assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 272:20] + assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 272:20] + assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 272:20] + assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 272:20] + assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 272:20] + assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 272:20] assign io_iflush_valid = iflush; // @[SCore.scala 157:19] assign io_dflush_valid = lsu_io_flush_valid; // @[SCore.scala 60:19] assign io_dflush_all = lsu_io_flush_all; // @[SCore.scala 61:19] - assign io_slog_valid = slogValid; // @[SCore.scala 302:17] - assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 303:17] + assign io_slog_valid = slogValid; // @[SCore.scala 297:17] + assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 298:17] assign io_slog_data = slogValid ? regfile_io_readData_0_data : 32'h0; // @[Library.scala 9:8] assign regfile_clock = clock; assign regfile_reset = reset; - assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 219:36] - assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 219:36] - assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 220:36] - assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 220:36] - assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 219:36] - assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 219:36] - assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 220:36] - assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 220:36] - assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 219:36] - assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 219:36] - assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 220:36] - assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 220:36] - assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 219:36] - assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 219:36] - assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 220:36] - assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 220:36] - assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 221:35] - assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 221:35] - assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 222:35] - assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 222:35] - assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 221:35] - assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 221:35] - assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 222:35] - assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 222:35] - assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 221:35] - assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 221:35] - assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 222:35] - assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 222:35] - assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 221:35] - assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 221:35] - assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 222:35] - assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 222:35] - assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 223:29] - assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 223:29] - assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 224:27] - assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 224:27] - assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 224:27] - assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 224:27] - assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 224:27] - assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 224:27] - assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 224:27] - assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 224:27] - assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 224:27] - assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 232:79] - assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_4 | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 238:54] - assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_4 | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 244:54] - assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 232:79] - assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_4 | _regfile_io_writeData_1_addr_T_5; // @[SCore.scala 238:54] - assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_4 | _regfile_io_writeData_1_data_T_5; // @[SCore.scala 244:54] - assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 232:79] - assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_4 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 238:54] - assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_4 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 244:54] - assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 232:79] - assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_4 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 238:54] - assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_4 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 244:54] - assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 252:52] - assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 253:38] - assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 254:38] - assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 257:33] - assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 258:33] - assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 259:33] - assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 261:33] - assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 262:66] - assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 264:66] - assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 266:66] - assign regfile_io_writeMask_4_valid = mluInvalidate; // @[SCore.scala 268:33] + assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 215:36] + assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 215:36] + assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 216:36] + assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 216:36] + assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 215:36] + assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 215:36] + assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 216:36] + assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 216:36] + assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 215:36] + assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 215:36] + assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 216:36] + assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 216:36] + assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 215:36] + assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 215:36] + assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 216:36] + assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 216:36] + assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 217:35] + assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 217:35] + assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 218:35] + assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 218:35] + assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 217:35] + assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 217:35] + assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 218:35] + assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 218:35] + assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 217:35] + assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 217:35] + assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 218:35] + assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 218:35] + assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 217:35] + assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 217:35] + assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 218:35] + assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 218:35] + assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 219:29] + assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 219:29] + assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 220:27] + assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 220:27] + assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 220:27] + assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 220:27] + assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 220:27] + assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 220:27] + assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 220:27] + assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 220:27] + assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 220:27] + assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 228:79] + assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_4 | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 234:54] + assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_4 | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 240:54] + assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 228:79] + assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_4 | _regfile_io_writeData_1_addr_T_5; // @[SCore.scala 234:54] + assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_4 | _regfile_io_writeData_1_data_T_5; // @[SCore.scala 240:54] + assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 228:79] + assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_4 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 234:54] + assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_4 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 240:54] + assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 228:79] + assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_4 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 234:54] + assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_4 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 240:54] + assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 248:52] + assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 249:38] + assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 250:38] + assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 253:33] + assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 254:33] + assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 255:33] + assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 257:33] + assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 258:66] + assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 260:66] + assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 262:66] assign fetch_clock = clock; assign fetch_reset = reset; assign fetch_io_csr_value_0 = io_csr_in_value_0; // @[SCore.scala 71:16] - assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 282:11] - assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 282:11] + assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 277:11] + assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 277:11] assign fetch_io_inst_lanes_0_ready = decode_0_io_inst_ready; // @[SCore.scala 91:61] assign fetch_io_inst_lanes_1_ready = decode_1_io_inst_ready & decode_0_io_inst_ready; // @[SCore.scala 91:61] assign fetch_io_inst_lanes_2_ready = decode_2_io_inst_ready & mask_2; // @[SCore.scala 91:61] @@ -22777,8 +22773,8 @@ assign decode_0_io_scoreboard_comb = regfile_io_scoreboard_comb; // @[SCore.scala 120:32] assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 130:24] assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 182:28] - assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 206:14] - assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 273:23] + assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 202:14] + assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 268:23] assign decode_0_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43] assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 101:26] assign decode_1_clock = clock; @@ -22791,7 +22787,7 @@ assign decode_1_io_scoreboard_regd = regfile_io_scoreboard_regd | decode_0_io_scoreboard_spec; // @[SCore.scala 123:62] assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 122:62] assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 182:28] - assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 273:23] + assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 268:23] assign decode_1_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43] assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 102:26] assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 108:28] @@ -22807,7 +22803,7 @@ assign decode_2_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec2; // @[SCore.scala 125:62] assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 124:62] assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 182:28] - assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 273:23] + assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 268:23] assign decode_2_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43] assign decode_2_io_interlock = decode_1_io_interlock; // @[SCore.scala 103:26] assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 109:28] @@ -22823,7 +22819,7 @@ assign decode_3_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec3; // @[SCore.scala 127:62] assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 126:62] assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 182:28] - assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 273:23] + assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 268:23] assign decode_3_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43] assign decode_3_io_interlock = decode_2_io_interlock; // @[SCore.scala 104:26] assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 110:28] @@ -22971,11 +22967,11 @@ assign lsu_io_busPort_data_1 = regfile_io_busPort_data_1; // @[SCore.scala 175:18] assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 175:18] assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 175:18] - assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 286:11] - assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 286:11] + assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 281:11] + assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 281:11] assign lsu_io_flush_ready = io_dflush_ready; // @[SCore.scala 63:22] - assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 287:11] - assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 287:11] + assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 282:11] + assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 282:11] assign mlu_clock = clock; assign mlu_reset = reset; assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 187:17] @@ -23008,12 +23004,12 @@ assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 198:17] assign dvu_clock = clock; assign dvu_reset = reset; - assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 206:14] - assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 206:14] - assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 206:14] - assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 207:14] - assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 208:14] - assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 209:22] + assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 202:14] + assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 202:14] + assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 202:14] + assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 203:14] + assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 204:14] + assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 205:22] always @(posedge clock) begin slogAddr <= _GEN_2[1:0]; `ifndef SYNTHESIS @@ -23087,7 +23083,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_18) begin - $fatal; // @[SCore.scala 247:11] + $fatal; // @[SCore.scala 243:11] end `ifdef STOP_COND end @@ -23098,7 +23094,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_18) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:247 assert((csr0Valid +&\n"); // @[SCore.scala 247:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:243 assert((csr0Valid +&\n"); // @[SCore.scala 243:11] end `ifdef PRINTF_COND end @@ -23109,7 +23105,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_25) begin - $fatal; // @[SCore.scala 247:11] + $fatal; // @[SCore.scala 243:11] end `ifdef STOP_COND end @@ -23120,7 +23116,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_25) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:247 assert((csr0Valid +&\n"); // @[SCore.scala 247:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:243 assert((csr0Valid +&\n"); // @[SCore.scala 243:11] end `ifdef PRINTF_COND end @@ -23131,7 +23127,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_32) begin - $fatal; // @[SCore.scala 247:11] + $fatal; // @[SCore.scala 243:11] end `ifdef STOP_COND end @@ -23142,7 +23138,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_32) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:247 assert((csr0Valid +&\n"); // @[SCore.scala 247:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:243 assert((csr0Valid +&\n"); // @[SCore.scala 243:11] end `ifdef PRINTF_COND end @@ -23153,7 +23149,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~_T_39) begin - $fatal; // @[SCore.scala 247:11] + $fatal; // @[SCore.scala 243:11] end `ifdef STOP_COND end @@ -23164,7 +23160,7 @@ if (`PRINTF_COND) begin `endif if (_T_5 & ~_T_39) begin - $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:247 assert((csr0Valid +&\n"); // @[SCore.scala 247:11] + $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:243 assert((csr0Valid +&\n"); // @[SCore.scala 243:11] end `ifdef PRINTF_COND end @@ -23175,7 +23171,7 @@ if (`STOP_COND) begin `endif if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin - $fatal; // @[SCore.scala 255:9] + $fatal; // @[SCore.scala 251:9] end `ifdef STOP_COND end @@ -23187,8 +23183,8 @@ `endif if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin $fwrite(32'h80000002, - "Assertion failed\n at SCore.scala:255 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n" - ); // @[SCore.scala 255:9] + "Assertion failed\n at SCore.scala:251 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n" + ); // @[SCore.scala 251:9] end `ifdef PRINTF_COND end @@ -23203,17 +23199,10 @@ end end always @(posedge clock or posedge reset) begin - if (reset) begin // @[SCore.scala 47:43] - mluInvalidate <= 1'h0; + if (reset) begin // @[SCore.scala 288:26] + slogValid <= 1'h0; // @[SCore.scala 288:26] end else begin - mluInvalidate <= _branchTaken_T_1 | bru_3_io_taken_valid; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin // @[SCore.scala 293:26] - slogValid <= 1'h0; // @[SCore.scala 293:26] - end else begin - slogValid <= decode_0_io_slog; // @[SCore.scala 297:13] + slogValid <= decode_0_io_slog; // @[SCore.scala 292:13] end end // Register and memory initialization @@ -23255,19 +23244,14 @@ _RAND_0 = {1{`RANDOM}}; iflush = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - mluInvalidate = _RAND_1[0:0]; + slogValid = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - slogValid = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - slogAddr = _RAND_3[1:0]; + slogAddr = _RAND_2[1:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin iflush = 1'h0; end if (reset) begin - mluInvalidate = 1'h0; - end - if (reset) begin slogValid = 1'h0; end `endif // RANDOMIZE