Merge "Add 3 pwrmgr tests to edacloud"
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 3802447..4452cc6 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -1083,20 +1083,20 @@
{
name: chip_sw_pwrmgr_full_aon_reset
uvm_test_seq: chip_sw_full_aon_reset_vseq
- sw_images: ["//sw/device/tests:rstmgr_smoketest:1"]
+ sw_images: ["//sw/device/tests:rstmgr_smoketest:1:matcha"]
en_run_modes: ["sw_test_mode_test_rom"]
}
{
name: chip_sw_pwrmgr_main_power_glitch_reset
uvm_test_seq: chip_sw_main_power_glitch_vseq
- sw_images: ["//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:1"]
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:1:matcha"]
en_run_modes: ["sw_test_mode_test_rom"]
run_opts: ["+bypass_alert_ready_to_end_check=1"]
}
{
name: chip_sw_pwrmgr_sysrst_ctrl_reset
uvm_test_seq: chip_sw_sysrst_ctrl_vseq
- sw_images: ["//sw/device/tests/sim_dv:pwrmgr_sysrst_ctrl_test:1"]
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_sysrst_ctrl_test:1:matcha"]
en_run_modes: ["sw_test_mode_test_rom"]
}
{
@@ -2150,10 +2150,13 @@
"chip_sw_otp_ctrl_escalation",
"chip_sw_otp_ctrl_smoketest",
"chip_sw_pwrmgr_deep_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_full_aon_reset",
+ "chip_sw_pwrmgr_main_power_glitch_reset",
"chip_sw_pwrmgr_normal_sleep_all_wake_ups"
"chip_sw_pwrmgr_sleep_disabled",
"chip_sw_pwrmgr_sleep_power_glitch_reset",
"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
+ "chip_sw_pwrmgr_sysrst_ctrl_reset",
"chip_sw_pwrmgr_wdog_reset",
"chip_sw_rom_ctrl_integrity_check",
"chip_sw_rstmgr_cpu_info",
@@ -2266,6 +2269,8 @@
"chip_sw_pwrmgr_deep_sleep_all_reset_reqs",
"chip_sw_pwrmgr_deep_sleep_all_wake_ups"
"chip_sw_pwrmgr_deep_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_full_aon_reset",
+ "chip_sw_pwrmgr_main_power_glitch_reset",
"chip_sw_pwrmgr_normal_sleep_all_reset_reqs",
"chip_sw_pwrmgr_normal_sleep_all_wake_ups",
"chip_sw_pwrmgr_random_sleep_all_reset_reqs",
@@ -2274,6 +2279,7 @@
"chip_sw_pwrmgr_sleep_disabled",
"chip_sw_pwrmgr_sleep_power_glitch_reset",
"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
+ "chip_sw_pwrmgr_sysrst_ctrl_reset",
"chip_sw_pwrmgr_wdog_reset",
"chip_sw_rom_ctrl_integrity_check",
"chip_sw_rstmgr_alert_info",
diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index 0ea6912..1f5e143 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -340,6 +340,26 @@
],
)
+matcha_dv_test(
+ name = "pwrmgr_sysrst_ctrl_test",
+ srcs = ["pwrmgr_sysrst_ctrl_test.c"],
+ deps = [
+ "//sw/device/lib/dif:pinmux",
+ "//sw/device/lib/dif:rstmgr",
+ "//sw/device/lib/testing:pinmux_testutils",
+ "//sw/device/tests:test_dv_lib",
+ "@lowrisc_opentitan//sw/device/lib/base:abs_mmio",
+ "@lowrisc_opentitan//sw/device/lib/dif:aon_timer",
+ "@lowrisc_opentitan//sw/device/lib/dif:flash_ctrl",
+ "@lowrisc_opentitan//sw/device/lib/dif:pwrmgr",
+ "@lowrisc_opentitan//sw/device/lib/dif:sysrst_ctrl",
+ "@lowrisc_opentitan//sw/device/lib/testing:aon_timer_testutils",
+ "@lowrisc_opentitan//sw/device/lib/testing:flash_ctrl_testutils",
+ "@lowrisc_opentitan//sw/device/lib/testing:pwrmgr_testutils",
+ "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
+ ],
+)
+
################################################################################
# Place the Opentitan-sourced DV test below. #
# Opentitan DV binary build flow does not support centOS7, so we pull the #
@@ -542,3 +562,13 @@
":lc_ctrl_transition_impl",
],
)
+
+matcha_dv_test(
+ name = "pwrmgr_main_power_glitch_test",
+ srcs = ["@lowrisc_opentitan//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test.c"],
+ deps = [
+ "//sw/device/lib/dif:rstmgr",
+ "//sw/device/tests:test_dv_lib_opentitan",
+ "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
+ ],
+)
diff --git a/sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c b/sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c
new file mode 100644
index 0000000..3f249dd
--- /dev/null
+++ b/sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c
@@ -0,0 +1,203 @@
+// Copyright 2023 Google LLC.
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <limits.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "hw/top_matcha/sw/autogen/top_matcha.h"
+#include "sw/device/lib/base/abs_mmio.h"
+#include "sw/device/lib/base/math.h"
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_aon_timer.h"
+#include "sw/device/lib/dif/dif_flash_ctrl.h"
+#include "sw/device/lib/dif/dif_pinmux.h"
+#include "sw/device/lib/dif/dif_pwrmgr.h"
+#include "sw/device/lib/dif/dif_rstmgr.h"
+#include "sw/device/lib/dif/dif_sysrst_ctrl.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/testing/aon_timer_testutils.h"
+#include "sw/device/lib/testing/flash_ctrl_testutils.h"
+#include "sw/device/lib/testing/pwrmgr_testutils.h"
+#include "sw/device/lib/testing/rstmgr_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+
+OTTF_DEFINE_TEST_CONFIG();
+static volatile const uint8_t RST_IDX[5] = {3, 30, 130, 5, 50};
+static dif_flash_ctrl_state_t flash_ctrl;
+
+/**
+ * Configure the sysrst.
+ */
+static void config_sysrst(const dif_pwrmgr_t *pwrmgr,
+ const dif_sysrst_ctrl_t *sysrst_ctrl_aon) {
+ LOG_INFO("sysrst enabled");
+
+ // Set sysrst as a reset source.
+ CHECK_DIF_OK(dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset,
+ kDifPwrmgrResetRequestSourceOne,
+ kDifToggleEnabled));
+ LOG_INFO("Reset Request SourceOne is set");
+
+ // Configure sysrst key combo
+ // reset pulse : 50 us
+ // detect durration : 50 us
+
+ dif_sysrst_ctrl_key_combo_config_t sysrst_ctrl_key_combo_config = {
+ .keys = kDifSysrstCtrlKeyAll,
+ .detection_time_threshold = 10,
+ .actions = kDifSysrstCtrlKeyComboActionAll,
+ .embedded_controller_reset_duration = 10};
+
+ CHECK_DIF_OK(dif_sysrst_ctrl_key_combo_detect_configure(
+ sysrst_ctrl_aon, kDifSysrstCtrlKeyCombo0, sysrst_ctrl_key_combo_config));
+ // Configure sysrst input change
+ // debounce durration : 100 us
+ dif_sysrst_ctrl_input_change_config_t sysrst_ctrl_input_change_config = {
+ .input_changes = kDifSysrstCtrlInputAll, .debounce_time_threshold = 20};
+
+ // Configure pinmux
+ dif_pinmux_t pinmux;
+ CHECK_DIF_OK(dif_pinmux_init(
+ mmio_region_from_addr(TOP_MATCHA_PINMUX_AON_BASE_ADDR), &pinmux));
+
+ CHECK_DIF_OK(dif_sysrst_ctrl_input_change_detect_configure(
+ sysrst_ctrl_aon, sysrst_ctrl_input_change_config));
+
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ &pinmux, kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In,
+ kTopMatchaPinmuxInselIor13));
+
+ // Wait for sysrst.
+ busy_spin_micros(10 * 1000);
+ // If we arrive here the test must fail.
+ CHECK(false, "Timeout waiting for sysrst reset!");
+}
+
+/**
+ * Configure the wdog.
+ */
+static void config_wdog(const dif_aon_timer_t *aon_timer,
+ const dif_pwrmgr_t *pwrmgr, uint64_t bark_time_us,
+ uint64_t bite_time_us) {
+ uint32_t bark_cycles =
+ aon_timer_testutils_get_aon_cycles_from_us(bark_time_us);
+ uint32_t bite_cycles =
+ aon_timer_testutils_get_aon_cycles_from_us(bite_time_us);
+
+ LOG_INFO("Wdog will bark after %u us and bite after %u us",
+ (uint32_t)bark_time_us, (uint32_t)bite_time_us);
+
+ // Set wdog as a reset source.
+ CHECK_DIF_OK(dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset,
+ kDifPwrmgrResetRequestSourceTwo,
+ kDifToggleEnabled));
+
+ // Setup the wdog bark and bite timeouts.
+ aon_timer_testutils_watchdog_config(aon_timer, bark_cycles, bite_cycles,
+ false);
+}
+
+/**
+ * Execute the aon timer wdog bite reset test.
+ */
+static void wdog_bite_test(const dif_aon_timer_t *aon_timer,
+ const dif_pwrmgr_t *pwrmgr, uint64_t bark_time_us) {
+ uint64_t bite_time_us = bark_time_us * 2;
+ config_wdog(aon_timer, pwrmgr, bark_time_us, bite_time_us);
+
+ // The `intr_state` takes 3 aon clock cycles to rise plus 2 extra cycles as a
+ // precaution.
+ uint32_t wait_us =
+ bark_time_us +
+ udiv64_slow(5 * 1000000 + kClockFreqAonHz - 1, kClockFreqAonHz, NULL);
+
+ // Wait bark time and check that the bark interrupt requested.
+ busy_spin_micros(wait_us);
+ bool is_pending = false;
+ CHECK_DIF_OK(dif_aon_timer_irq_is_pending(
+ aon_timer, kDifAonTimerIrqWdogTimerBark, &is_pending));
+ CHECK(is_pending, "Wdog bark irq did not rise after %u microseconds",
+ wait_us);
+
+ // Wait for the remaining time to the wdog bite.
+ busy_spin_micros(wait_us);
+ // If we arrive here the test must fail.
+ CHECK(false, "Timeout waiting for Wdog bite reset!");
+}
+
+bool test_main(void) {
+ // Initialize pwrmgr.
+ dif_pwrmgr_t pwrmgr;
+ CHECK_DIF_OK(dif_pwrmgr_init(
+ mmio_region_from_addr(TOP_MATCHA_PWRMGR_AON_BASE_ADDR), &pwrmgr));
+
+ // Initialize sysrst_ctrl.
+ dif_sysrst_ctrl_t sysrst_ctrl_aon;
+ CHECK_DIF_OK(dif_sysrst_ctrl_init(
+ mmio_region_from_addr(TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR),
+ &sysrst_ctrl_aon));
+
+ // Initialize rstmgr to check the reset reason.
+ dif_rstmgr_t rstmgr;
+ CHECK_DIF_OK(dif_rstmgr_init(
+ mmio_region_from_addr(TOP_MATCHA_RSTMGR_AON_BASE_ADDR), &rstmgr));
+
+ // Initialize aon timer to use the wdog.
+ dif_aon_timer_t aon_timer;
+ CHECK_DIF_OK(dif_aon_timer_init(
+ mmio_region_from_addr(TOP_MATCHA_AON_TIMER_AON_BASE_ADDR), &aon_timer));
+
+ // Initialize flash_ctrl
+ CHECK_DIF_OK(dif_flash_ctrl_init_state(
+ &flash_ctrl,
+ mmio_region_from_addr(TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR)));
+
+ // First check the flash stored value
+ uint32_t event_idx = flash_ctrl_testutils_counter_get(0);
+
+ // Enable flash access
+ flash_ctrl_testutils_default_region_access(&flash_ctrl,
+ /*rd_en*/ true,
+ /*prog_en*/ true,
+ /*erase_en*/ true,
+ /*scramble_en*/ false,
+ /*ecc_en*/ false,
+ /*he_en*/ false);
+
+ // Increment flash counter to know where we are
+ flash_ctrl_testutils_counter_increment(&flash_ctrl, 0);
+
+ LOG_INFO("Test round %d", event_idx);
+ LOG_INFO("RST_IDX[%d] = %d", event_idx, RST_IDX[event_idx]);
+
+ // Check if there was a HW reset caused by the wdog bite.
+ dif_rstmgr_reset_info_bitfield_t rst_info;
+ rst_info = rstmgr_testutils_reason_get();
+ rstmgr_testutils_reason_clear();
+
+ CHECK(rst_info == kDifRstmgrResetInfoPor ||
+ rst_info == kDifRstmgrResetInfoWatchdog ||
+ rst_info == kDifRstmgrResetInfoSysRstCtrl,
+ "Wrong reset reason %02X", rst_info);
+
+ if (rst_info == kDifRstmgrResetInfoPor) {
+ LOG_INFO("Booting for the first time, setting sysrst");
+ config_sysrst(&pwrmgr, &sysrst_ctrl_aon);
+ } else if (rst_info == kDifRstmgrResetInfoSysRstCtrl) {
+ LOG_INFO("Booting for the second time due to system reset control reset");
+ // Executing the wdog bite reset test.
+ wdog_bite_test(&aon_timer, &pwrmgr, /*bark_time_us=*/200);
+ } else if (rst_info == kDifRstmgrResetInfoWatchdog) {
+ LOG_INFO("Booting for the third time due to wdog bite reset");
+ LOG_INFO("Last Booting");
+ LOG_INFO("Test finish");
+ return true;
+ }
+
+ // Reset reason is also checked above, so this is not strictly necessary.
+ return false;
+}
