sw/device/tests/smc/smc_isp_wrapper_test.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

// ISP TPG mode with user defined resolution: 120x64, which covers the reg
// access, dma to dl_mem path

#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/dif/dif_isp_wrapper.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t smc_uart;
static dif_isp_wrapper_t isp_wrapper;
uint32_t en_result;
uint32_t mem_val;
const uint32_t mp_frame_end_mask = 0x1;
void _ottf_main(void) {
  test_status_set(kTestStatusInTest);

  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }

  LOG_INFO("Hello from the SMC!");

  CHECK_DIF_OK(dif_isp_wrapper_init(
                   mmio_region_from_addr(TOP_MATCHA_ISP_WRAPPER_BASE_ADDR),
                   &isp_wrapper),
               "isp_wrapper_start failed");

  CHECK_DIF_OK(dif_isp_wrapper_set_en(&isp_wrapper), "isp_wrapper_en failed");

  while ((en_result & mp_frame_end_mask) == 0) {
    CHECK_DIF_OK(dif_isp_wrapper_read_en(&isp_wrapper, &en_result));
    busy_spin_micros(200);
  }

  // Note: passing a test in the SMC ends the simulation, even if the secure
  // core is in the middle of a test.
  mmio_region_t ml_dmem_base_addr =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x200);
  CHECK(mem_val == 0xfcfcfcfc,
        "ISP Write to ML_DMEM value offset 0x200 - Expected: 0xfcfcfcfc | "
        "Actual: %x",
        mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x23C);
  CHECK(mem_val == 0x90909090,
        "ISP Write to ML_DMEM value offset 0x23C - Expected: 0x90909090 | "
        "Actual: %x",
        mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0010);
  CHECK(mem_val == 0xd8d8d8d8,
        "ISP Write to ML_DMEM value offset 0x0010 - Expected: 0xd8d8d8d8 | "
        "Actual: %x",
        mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0030);
  CHECK(mem_val == 0x90909090,
        "ISP Write to ML_DMEM value offset 0x0030 - Expected: 0x90909090 | "
        "Actual: %x",
        mem_val);

  test_status_set(kTestStatusPassed);
}