Add the 3 escalation tests back to edacloud

Change-Id: I7d1ff59b44f6b98e4be23fa8dbb634181f546406

hw/top_matcha/dv/chip_sim_cfg.hjson

diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 4452cc6..7d7f041 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -646,14 +646,14 @@
     {
       name: chip_sw_rstmgr_rst_cnsty_escalation
       uvm_test_seq: chip_sw_rstmgr_cnsty_fault_vseq
-      sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1"]
     }
     {
       name: chip_sw_data_integrity_escalation
       uvm_test_seq: chip_sw_data_integrity_vseq
-      sw_images: ["//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1"]
       reseed: 6
@@ -1846,7 +1846,7 @@
     {
       name: chip_sw_rv_dm_access_after_escalation_reset
       uvm_test_seq: "chip_sw_rv_dm_access_after_escalation_reset_vseq"
-      sw_images: ["//sw/device/tests/sim_dv:alert_handler_escalation_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:alert_handler_escalation_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+use_jtag_dmi=1"]
     }
@@ -2129,6 +2129,7 @@
         "chip_sw_clkmgr_smoketest",
         "chip_sw_crt_test",
         "chip_sw_csrng_smoketest",
+        "chip_sw_data_integrity_escalation",
         "chip_sw_dma_main_test",
         "chip_sw_entropy_src_smoketest",
         "chip_sw_example_flash",
@@ -2160,11 +2161,13 @@
         "chip_sw_pwrmgr_wdog_reset",
         "chip_sw_rom_ctrl_integrity_check",
         "chip_sw_rstmgr_cpu_info",
+        "chip_sw_rstmgr_rst_cnsty_escalation",
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
         "chip_sw_rstmgr_sw_rst",
         "chip_sw_rv_core_ibex_nmi_irq",
         "chip_sw_rv_core_ibex_rnd",
+        "chip_sw_rv_dm_access_after_escalation_reset",
         "chip_sw_rv_dm_access_after_wakeup",
         "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
         "chip_sw_rv_plic_smoketest",
@@ -2245,6 +2248,7 @@
         "chip_sw_clkmgr_smoketest",
         "chip_sw_crt_test",
         "chip_sw_csrng_smoketest",
+        "chip_sw_data_integrity_escalation",
         "chip_sw_dma_main_test",
         "chip_sw_entropy_src_smoketest",
         "chip_sw_example_flash",
@@ -2284,11 +2288,13 @@
         "chip_sw_rom_ctrl_integrity_check",
         "chip_sw_rstmgr_alert_info",
         "chip_sw_rstmgr_cpu_info",
+        "chip_sw_rstmgr_rst_cnsty_escalation",
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
         "chip_sw_rstmgr_sw_rst",
         "chip_sw_rv_core_ibex_nmi_irq",
         "chip_sw_rv_core_ibex_rnd",
+        "chip_sw_rv_dm_access_after_escalation_reset",
         "chip_sw_rv_dm_access_after_wakeup",
         "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
         "chip_sw_rv_plic_smoketest",

sw/device/tests/sim_dv/BUILD

diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index 1f5e143..ee50442 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -360,6 +360,26 @@
     ],
 )
 
+matcha_dv_test(
+    name = "data_integrity_escalation_reset_test",
+    srcs = ["@lowrisc_opentitan//sw/device/tests/sim_dv:data_integrity_escalation_reset_test.c"],
+    deps = [
+        "//sw/device/lib/dif:alert_handler",
+        "//sw/device/lib/dif:rstmgr",
+        "//sw/device/lib/dif:rv_plic_sec",
+        "//sw/device/tests:test_dv_lib_opentitan",
+        "@lowrisc_opentitan//sw/device/lib/dif:aon_timer",
+        "@lowrisc_opentitan//sw/device/lib/dif:flash_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/dif:rv_core_ibex",
+        "@lowrisc_opentitan//sw/device/lib/dif:sram_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/testing:alert_handler_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:aon_timer_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:flash_ctrl_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:rv_plic_testutils",
+    ],
+)
+
 ################################################################################
 #  Place the Opentitan-sourced DV test below.                                  #
 #  Opentitan DV binary build flow does not support centOS7, so we pull the     #