[HW TOP AST] Add audio source in ast to fix DV. 1. Add audio source /osc in AST, before it was using USB clock. however it will cause DV failure since USB clock is off at low power mode. 2. For SMC/ML/Video, still use exisitng sys_clk (100Mhz) and its Val signal. VSI eventually will have their own version of ast.sv to matcha the exact HW implmentation. Change-Id: I109dcf09ca67616789ce98e29a8360b1317d5615
diff --git a/hw/top_matcha/ip/ast/ast.core b/hw/top_matcha/ip/ast/ast.core index 9211b6c..ac3dadc 100644 --- a/hw/top_matcha/ip/ast/ast.core +++ b/hw/top_matcha/ip/ast/ast.core
@@ -45,6 +45,8 @@ - rtl/sys_osc.sv - rtl/usb_clk.sv - rtl/usb_osc.sv + - rtl/audio_clk.sv + - rtl/audio_osc.sv - rtl/gfr_clk_mux2.sv - rtl/ast_clks_byp.sv - rtl/rglts_pdm_3p3v.sv
diff --git a/hw/top_matcha/ip/ast/rtl/ast.sv b/hw/top_matcha/ip/ast/rtl/ast.sv index 0c7c900..5f00c1c 100644 --- a/hw/top_matcha/ip/ast/rtl/ast.sv +++ b/hw/top_matcha/ip/ast/rtl/ast.sv
@@ -98,18 +98,22 @@ output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o, // USB IO Pull-up Calibration Setting // smc source clock + input clk_src_smc_en_i, // SMC Source Clock Enable output logic clk_src_smc_o, // SMC Source Clock output logic clk_src_smc_val_o, // SMC Source Clock Valid // ml source clock + input clk_src_ml_en_i, // ML Source Clock Enable output logic clk_src_ml_o, // ML Source Clock output logic clk_src_ml_val_o, // ML Source Clock Valid // video source clock + input clk_src_video_en_i, // VideO Source Clock Enable output logic clk_src_video_o, // Video Source Clock output logic clk_src_video_val_o, // Video Source Clock Valid // audio source clock + input clk_src_audio_en_i, // AUDIO Source Clock Enable output logic clk_src_audio_o, // audio Source Clock output logic clk_src_audio_val_o, // audio Source Clock Valid @@ -518,6 +522,36 @@ /////////////////////////////////////// +// AUDIO Clock (Always ON) +/////////////////////////////////////// +logic rst_audio_clk_n, clk_audio_pd_n; +logic clk_src_audio_en, clk_osc_audio, clk_osc_audio_val; + +assign rst_audio_clk_n = vcmain_pok_por && vcc_pok; +assign clk_audio_pd_n = scan_mode || !deep_sleep; + +`ifdef AST_BYPASS_CLK +logic clk_audio_ext; +assign clk_audio_ext = clk_osc_byp_i.audio; +`endif + +assign clk_src_audio_en = clk_src_audio_en_i; + +audio_clk u_audio_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_audio_pd_ni ( clk_audio_pd_n ), + .rst_audio_clk_ni ( rst_audio_clk_n ), + .clk_src_audio_en_i ( clk_src_audio_en ), + .scan_mode_i ( scan_mode ), + .audio_osc_cal_i ( sys_io_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_audio_ext_i ( clk_audio_ext ), +`endif + .clk_src_audio_o ( clk_osc_audio ), + .clk_src_audio_val_o ( clk_osc_audio_val ) +); + +/////////////////////////////////////// // AST Clocks Bypass /////////////////////////////////////// logic clk_src_sys, clk_src_io, clk_src_usb, clk_src_aon; @@ -536,6 +570,9 @@ .clk_osc_usb_val_i ( clk_osc_usb_val ), .clk_osc_aon_i ( clk_osc_aon ), .clk_osc_aon_val_i ( clk_osc_aon_val ), + .clk_src_audio_en_i ( clk_src_audio_en_i ), + .clk_osc_audio_i ( clk_osc_audio ), + .clk_osc_audio_val_i ( clk_osc_audio_val ), .clk_ast_ext_i ( clk_ast_ext_i ), .io_clk_byp_req_i ( io_clk_byp_req_i ), .all_clk_byp_req_i ( all_clk_byp_req_i ), @@ -550,7 +587,9 @@ .clk_src_usb_o ( clk_src_usb ), .clk_src_usb_val_o ( clk_src_usb_val_o ), .clk_src_aon_o ( clk_src_aon ), - .clk_src_aon_val_o ( clk_src_aon_val_o ) + .clk_src_aon_val_o ( clk_src_aon_val_o ), + .clk_src_audio_o ( clk_src_audio ), + .clk_src_audio_val_o ( clk_src_audio_val_o ) ); // System source clock buffer @@ -590,47 +629,48 @@ ); -// TO-DO(pbf): Add PLL output for new clocks: smc, ml, video, audio -// For now, just use the same clock as clk_osc_ss - -assign clk_src_smc_val_o = 1'b1; -assign clk_src_ml_val_o = 1'b1; -assign clk_src_video_val_o = 1'b1; -assign clk_src_audio_val_o = 1'b1; +// TO-DO(VSI): Add PLL output for new clocks: smc, ml, video +// For DV test purpose as of now, smc/ml/video clock will just use the same clock as clk_src_syc. // SMC source clock buffer //////////////////////////////////////// prim_clock_buf #( .NoFpgaBuf ( 1'b1 ) ) u_clk_src_smc_buf ( - .clk_i ( clk_src_sys ), // TO-DO(pbf): use the sys_clk for now. Change to different clock late. + .clk_i ( clk_src_sys ), // TO-DO(VSI): use the sys_clk for now. Change to SMC clock late. .clk_o ( clk_src_smc_o ) ); +assign clk_src_smc_val_o = clk_src_sys_val_o; + // ML source clock buffer //////////////////////////////////////// prim_clock_buf #( .NoFpgaBuf ( 1'b1 ) ) u_clk_src_ml_buf ( - .clk_i ( clk_src_sys ), // TO-DO(pbf):use the sys_clk for now. Change to different clock late. + .clk_i ( clk_src_sys ), // TO-DO(VSI):use the sys_clk for now. Change to ML clock late. .clk_o ( clk_src_ml_o ) ); +assign clk_src_ml_val_o = clk_src_sys_val_o; + // video source clock buffer //////////////////////////////////////// prim_clock_buf #( .NoFpgaBuf ( 1'b1 ) ) u_clk_src_video_buf ( - .clk_i ( clk_src_sys ), // TO-DO(pbf):use the sys_clk for now. Change to different clock late. + .clk_i ( clk_src_sys ), // TO-DO(VSI):use the sys_clk for now. Change to video clock late. .clk_o ( clk_src_video_o ) ); +assign clk_src_video_val_o = clk_src_sys_val_o; + // audio source clock buffer //////////////////////////////////////// prim_clock_buf #( .NoFpgaBuf ( 1'b1 ) ) u_clk_src_audio_buf ( - .clk_i ( clk_src_usb ), // TO-DO(pbf): use 48Mhz usb clock as audio clock for FPGA for now. + .clk_i ( clk_src_audio ), .clk_o ( clk_src_audio_o ) );
diff --git a/hw/top_matcha/ip/ast/rtl/ast_clks_byp.sv b/hw/top_matcha/ip/ast/rtl/ast_clks_byp.sv index f7d6c0e..f21c774 100644 --- a/hw/top_matcha/ip/ast/rtl/ast_clks_byp.sv +++ b/hw/top_matcha/ip/ast/rtl/ast_clks_byp.sv
@@ -26,6 +26,9 @@ input clk_osc_usb_val_i, // USB Oscillator Clock Valid input clk_osc_aon_i, // AON Oscillator Clock input clk_osc_aon_val_i, // AON Oscillator Clock Valid + input clk_src_audio_en_i, // IO Source Clock Enable + input clk_osc_audio_i, // AUDIO Oscillator Clock + input clk_osc_audio_val_i, // AUDIO Oscillator Clock Valid input clk_ast_ext_i, // External Clock input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // External IO clock mux for OTP bootstrap input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override @@ -40,7 +43,9 @@ output logic clk_src_usb_o, // USB Source Clock output logic clk_src_usb_val_o, // USB Source Clock Valid output logic clk_src_aon_o, // AON Source Clock - output logic clk_src_aon_val_o // AON Source Clock Valid + output logic clk_src_aon_val_o, // AON Source Clock Valid + output logic clk_src_audio_o, // AON Source Clock + output logic clk_src_audio_val_o // AON Source Clock Valid ); logic scan_mode_i, scan_reset_ni; @@ -267,7 +272,32 @@ .clk_o ( clk_ext_usb ) ); +// AUDIO External Clock Enable +//////////////////////////////////////// +logic clk_ext_audio, clk_ext_audio_en, clk_ext_audio_val; +logic clk_src_audio_en; +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_audio_en_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_audio_en_i ), + .q_o ( clk_src_audio_en ) +); + +assign clk_ext_audio_en = deep_sleep_n && clk_src_audio_en; +assign clk_ext_audio_val = clk_ext_audio_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_audio_ckgt ( + .clk_i ( clk_ext ), + .en_i ( clk_ext_audio_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_audio ) +); //////////////////////////////////////// // SW Bypass select logic //////////////////////////////////////// @@ -305,16 +335,17 @@ ); // Decode logic -logic ot_all_clk_byp, ot_sys_clk_byp, ot_io_clk_byp, ot_usb_clk_byp, ot_aon_clk_byp; +logic ot_all_clk_byp, ot_sys_clk_byp, ot_io_clk_byp, ot_usb_clk_byp, ot_aon_clk_byp, ot_audio_clk_byp; prim_mubi4_dec u_all_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_all_clk_byp ) ); prim_mubi4_dec u_sys_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_sys_clk_byp ) ); prim_mubi4_dec u_io_byp_sel ( .mubi_i ( ot_io_clk_byp_req ), .mubi_dec_o ( ot_io_clk_byp ) ); prim_mubi4_dec u_usb_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_usb_clk_byp ) ); prim_mubi4_dec u_aon_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_aon_clk_byp ) ); +prim_mubi4_dec u_audio_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_audio_clk_byp ) ); // De-Glitch selects (decode "noise") -logic sw_sys_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp, sw_exfr_is_96m; +logic sw_sys_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp, sw_exfr_is_96m, sw_audio_clk_byp; prim_flop #( .Width ( 1 ), @@ -376,6 +407,16 @@ .q_o ( sw_exfr_is_96m ) ); +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_audio_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_audio_clk_byp ), + .q_o ( sw_audio_clk_byp ) +); + logic sys_clk_byp; assign sys_clk_byp = sw_sys_clk_byp; @@ -408,9 +449,13 @@ assign extfreq_is_96m = sw_exfr_is_96m; +logic audio_clk_byp; + +assign audio_clk_byp = sw_audio_clk_byp; + // Block changes during scan mode //////////////////////////////////////// -logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel; +logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel, audio_clk_byp_sel; always_latch begin if ( !scan_mode_i ) begin @@ -419,6 +464,7 @@ usb_clk_byp_sel = usb_clk_byp; aon_clk_byp_sel = aon_clk_byp; ext_freq_is_96m = extfreq_is_96m; + audio_clk_byp_sel = audio_clk_byp; end end @@ -426,8 +472,8 @@ //////////////////////////////////////// // Clocks Bypass Muxes //////////////////////////////////////// -logic sys_clk_osc_en, io_clk_osc_en, usb_clk_osc_en, aon_clk_osc_en; -logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en; +logic sys_clk_osc_en, io_clk_osc_en, usb_clk_osc_en, aon_clk_osc_en, audio_clk_osc_en; +logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en, audio_clk_byp_en; logic rst_clk_osc_n, rst_clk_ext_n; assign rst_clk_osc_n = vcaon_pok; @@ -455,6 +501,7 @@ logic rst_clk_osc_sys_n, rst_clk_ext_sys_n, rst_clk_osc_io_n, rst_clk_ext_io_n; logic rst_clk_osc_usb_n, rst_clk_ext_usb_n, rst_clk_osc_aon_n, rst_clk_ext_aon_n; +logic rst_clk_osc_audio_n, rst_clk_ext_audio_n; prim_buf u_rst_clk_osc_sys ( .in_i ( rst_clk_osc_n ), @@ -496,6 +543,16 @@ .out_o ( rst_clk_ext_aon_n ) ); +prim_buf u_rst_clk_osc_audio ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_audio_n ) +); + +prim_buf u_rst_clk_ext_audio ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_audio_n ) +); + // SYS Clock Bypass Mux //////////////////////////////////////// gfr_clk_mux2 u_clk_src_sys_sel ( @@ -560,6 +617,22 @@ .clk_o ( clk_src_aon_o ) ); +// AUDIO Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_audio_sel ( + .clk_osc_i ( clk_osc_audio_i ), + .clk_osc_val_i ( clk_osc_audio_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_audio_n ), + .clk_ext_i ( clk_ext_audio ), + .clk_ext_val_i ( clk_ext_audio_val ), + .rst_clk_ext_ni ( rst_clk_ext_audio_n ), + .ext_sel_i ( audio_clk_byp_sel ), + .clk_osc_en_o ( audio_clk_osc_en ), + .clk_ext_en_o ( audio_clk_byp_en ), + .clk_val_o ( clk_src_audio_val_o ), + .clk_o ( clk_src_audio_o ) +); + // rst_aon_n deasset to io clock //////////////////////////////////////// logic rst_aon_n_ioda, rst_aon_ioda_n; @@ -585,7 +658,7 @@ all_clks_byp_en_src <= 1'b0; end else begin all_clks_byp_en_src <= sw_all_clk_byp && sys_clk_byp_en && io_clk_byp_en && - usb_clk_byp_en && aon_clk_byp_en; + usb_clk_byp_en && aon_clk_byp_en && audio_clk_byp_en; end end
diff --git a/hw/top_matcha/ip/ast/rtl/audio_clk.sv b/hw/top_matcha/ip/ast/rtl/audio_clk.sv new file mode 100644 index 0000000..4ad7d32 --- /dev/null +++ b/hw/top_matcha/ip/ast/rtl/audio_clk.sv
@@ -0,0 +1,63 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: audio_clk +// *Module Description: AUDIO Clock +//############################################################################ + +module audio_clk ( + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input clk_audio_pd_ni, // IO Clock Power-down + input rst_audio_clk_ni, // IO Clock Logic reset + input clk_src_audio_en_i, // IO Source Clock Enable + input scan_mode_i, // Scan Mode + input audio_osc_cal_i, // IO Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_audio_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic clk_src_audio_o, // IO Source Clock + output logic clk_src_audio_val_o // IO Source Clock Valid +); + +logic clk, osc_en, audio_clk_en; + +assign osc_en = (clk_src_audio_en_i && clk_audio_pd_ni && rst_audio_clk_ni); +assign audio_clk_en = scan_mode_i || osc_en; + +// Clock Oscilator +/////////////////////////////////////// +audio_osc u_audio_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .audio_en_i ( audio_clk_en ), + .audio_osc_cal_i ( audio_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_audio_ext_i ( clk_audio_ext_i ), +`endif + .audio_clk_o ( clk ) +); // of u_audio_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_audio_buf( + .clk_i ( clk ), + .clk_o ( clk_src_audio_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = audio_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_audio_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_audio_val_o ) +); + +endmodule : audio_clk
diff --git a/hw/top_matcha/ip/ast/rtl/audio_osc.sv b/hw/top_matcha/ip/ast/rtl/audio_osc.sv new file mode 100644 index 0000000..c24f4e7 --- /dev/null +++ b/hw/top_matcha/ip/ast/rtl/audio_osc.sv
@@ -0,0 +1,131 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: audio_osc +// *Module Description: AUDIO Clock Oscilator +//############################################################################ + +module audio_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input audio_en_i, // IO Source Clock Enable + input audio_osc_cal_i, // IO Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_audio_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic audio_clk_o // IO Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 1ps; + +real CLK_PERIOD; + +reg init_start; +initial init_start = 1'b0; + +initial begin + #1; + init_start = 1'b1; + #1; + $display("\n%m: IO Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD)); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re; +buf #(ast_bhv_pkg::IO_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && audio_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; + + +// Clock Oscillator +//////////////////////////////////////// +real CalIoClkPeriod, UncIoClkPeriod, IoClkPeriod; + +initial CalIoClkPeriod = $itor( 1000000/48 ); // ~20833.333333ps (48MHz) +initial UncIoClkPeriod = $itor( $urandom_range(55555, 25000) ); // 55555-25000ps (18-40MHz) + +assign IoClkPeriod = (audio_osc_cal_i && init_start) ? CalIoClkPeriod : UncIoClkPeriod; +assign CLK_PERIOD = IoClkPeriod/1000; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk, clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && audio_en_i; + +logic clk, en_osc; +assign clk = 1'b0; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && audio_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_audio_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( audio_clk_o ) +); + + +`ifdef SYNTHESIS +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ audio_osc_cal_i }; +`endif + +endmodule : audio_osc
diff --git a/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv b/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv index 2475bdd..9f4cb53 100644 --- a/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv +++ b/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv
@@ -1036,15 +1036,19 @@ .clk_src_usb_o ( ast_base_clks.clk_usb ), .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), // smc source clock + .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ), .clk_src_smc_o ( ast_base_clks.clk_smc ), .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val), // ml source clock + .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ), .clk_src_ml_o ( ast_base_clks.clk_ml ), .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val), // video source clock + .clk_src_video_en_i ( base_ast_pwr.video_clk_en ), .clk_src_video_o ( ast_base_clks.clk_video ), .clk_src_video_val_o ( ast_base_pwr.video_clk_val), // audio source clock + .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ), .clk_src_audio_o ( ast_base_clks.clk_audio ), .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val), // adc
diff --git a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv index fad1369..f8fb1dd 100644 --- a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv +++ b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
@@ -824,15 +824,19 @@ .clk_src_usb_o ( ast_base_clks.clk_usb ), .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), // smc source clock + .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ), .clk_src_smc_o ( ast_base_clks.clk_smc ), .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val), // ml source clock + .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ), .clk_src_ml_o ( ast_base_clks.clk_ml ), .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val), // video source clock + .clk_src_video_en_i ( base_ast_pwr.video_clk_en ), .clk_src_video_o ( ast_base_clks.clk_video ), .clk_src_video_val_o ( ast_base_pwr.video_clk_val), // audio source clock + .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ), .clk_src_audio_o ( ast_base_clks.clk_audio ), .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val), // adc
diff --git a/hw/top_matcha/rtl/chip_matcha_verilator.sv b/hw/top_matcha/rtl/chip_matcha_verilator.sv index d66f69b..8bee784 100644 --- a/hw/top_matcha/rtl/chip_matcha_verilator.sv +++ b/hw/top_matcha/rtl/chip_matcha_verilator.sv
@@ -486,15 +486,19 @@ .clk_src_usb_o ( ast_base_clks.clk_usb ), .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), // smc source clock + .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ), .clk_src_smc_o ( ast_base_clks.clk_smc ), .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val), // ml source clock + .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ), .clk_src_ml_o ( ast_base_clks.clk_ml ), .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val), // video source clock + .clk_src_video_en_i ( base_ast_pwr.video_clk_en ), .clk_src_video_o ( ast_base_clks.clk_video ), .clk_src_video_val_o ( ast_base_pwr.video_clk_val), // audio source clock + .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ), .clk_src_audio_o ( ast_base_clks.clk_audio ), .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val), // adc
diff --git a/util/topgen_matcha/templates/chiplevel.sv.tpl b/util/topgen_matcha/templates/chiplevel.sv.tpl index 1c0daf1..87945c3 100644 --- a/util/topgen_matcha/templates/chiplevel.sv.tpl +++ b/util/topgen_matcha/templates/chiplevel.sv.tpl
@@ -697,15 +697,19 @@ .clk_src_usb_o ( ast_base_clks.clk_usb ), .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), // smc source clock + .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ), .clk_src_smc_o ( ast_base_clks.clk_smc ), .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val), // ml source clock + .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ), .clk_src_ml_o ( ast_base_clks.clk_ml ), .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val), // video source clock + .clk_src_video_en_i ( base_ast_pwr.video_clk_en ), .clk_src_video_o ( ast_base_clks.clk_video ), .clk_src_video_val_o ( ast_base_pwr.video_clk_val), // audio source clock + .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ), .clk_src_audio_o ( ast_base_clks.clk_audio ), .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val), // adc