Merge "Add clkmgr tests to edacloud"
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 2f574e4..8be09e9 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -409,98 +409,100 @@
tests: [
{
name: chip_sw_smc_isp_wrapper_tpg_64_64_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_tpg_64_64_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_env_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_env_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_isp_wrapper_irq_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_irq_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_tlul_mailbox_test
- uvm_test_seq: chip_sw_smc_base_vseq
- sw_images: ["//sw/device/tests/smc:smc_tlul_mailbox_test:6:matcha"]
- en_run_modes: ["sw_test_mode_test_simple_sec"]
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: [
+ "//sw/device/tests:tlul_mailbox_test:1:ot_flash_binary:matcha",
+ "//sw/device/tests/smc:smc_tlul_mailbox_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom_with_smc"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_cam_irq_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_cam_irq_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_ml_sram_smoketest
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_ml_dmem_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_kelvin_hello_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_kelvin_hello_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_ml_top_irq_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_ml_top_irq_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_supervisor_mode_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_supervisor_mode_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_virtual_memory_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_virtual_memory_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_interrupt_boundary_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_interrupt_boundary_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_lsu_interrupt_boundary_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_lsu_interrupt_boundary_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_page_boundary_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_page_boundary_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_lsu_page_boundary_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_lsu_page_boundary_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
@@ -508,8 +510,8 @@
{
name: chip_sw_atomics_test
uvm_test_seq: chip_sw_base_vseq
- sw_images: ["//sw/device/tests:atomics_test:1:ot_flash_binary:matcha"]
- en_run_modes: ["sw_test_mode_test_rom"]
+ sw_images: ["//sw/device/tests/smc:smc_atomics_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
@@ -549,35 +551,35 @@
}
{
name: chip_sw_smc_i2s_rx_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_i2s_rx_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_i2s_tx_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_i2s_tx_test:6:matcha"]
- en_run_modes: ["sw_test_mode_test_rom"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_rv_timer_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_rv_timer_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_kelvin_checksum_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_kelvin_checksum_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
name: chip_sw_smc_isp_wrapper_test
- uvm_test_seq: chip_sw_smc_base_vseq
+ uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_test:6:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
@@ -2011,6 +2013,7 @@
tests: [
"chip_sw_alert_test",
"chip_sw_aon_timer_smoketest",
+ "chip_sw_atomics_test",
"chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_smoketest",
"chip_sw_crt_test",
@@ -2031,6 +2034,7 @@
"chip_sw_smc_ctrl_test",
"chip_sw_smc_env_test",
"chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
"chip_sw_smc_interrupt_boundary_test",
"chip_sw_smc_isp_wrapper_irq_test",
"chip_sw_smc_isp_wrapper_test",
@@ -2042,6 +2046,7 @@
"chip_sw_smc_page_boundary_test",
"chip_sw_smc_rv_timer_test",
"chip_sw_smc_supervisor_mode_test",
+ "chip_sw_smc_tlul_mailbox_test",
"chip_sw_smc_virtual_memory_test",
"chip_sw_spi_device_tx_rx",
"chip_sw_spi_host_tx_rx",
@@ -2062,6 +2067,7 @@
"chip_sw_alert_test",
"chip_sw_aon_timer_smoketest",
"chip_sw_ast_clk_rst_inputs",
+ "chip_sw_atomics_test",
"chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_external_clk_src_for_sw_fast",
"chip_sw_clkmgr_external_clk_src_for_sw_slow",
@@ -2109,6 +2115,7 @@
"chip_sw_smc_ctrl_test",
"chip_sw_smc_env_test",
"chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
"chip_sw_smc_interrupt_boundary_test",
"chip_sw_smc_isp_wrapper_irq_test",
"chip_sw_smc_isp_wrapper_test",
@@ -2120,6 +2127,7 @@
"chip_sw_smc_page_boundary_test",
"chip_sw_smc_rv_timer_test",
"chip_sw_smc_supervisor_mode_test",
+ "chip_sw_smc_tlul_mailbox_test",
"chip_sw_smc_virtual_memory_test",
"chip_sw_spi_device_pass_through",
"chip_sw_spi_device_tx_rx",
diff --git a/hw/top_matcha/dv/env/chip_env.core b/hw/top_matcha/dv/env/chip_env.core
index 8b229e1..28fb4bf 100644
--- a/hw/top_matcha/dv/env/chip_env.core
+++ b/hw/top_matcha/dv/env/chip_env.core
@@ -55,7 +55,6 @@
- seq_lib/chip_prim_tl_access_vseq.sv: {is_include_file: true}
- seq_lib/chip_tap_straps_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_base_vseq.sv: {is_include_file: true}
- - seq_lib/chip_sw_smc_base_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_uart_smoke_vseq.sv: {is_include_file: true}
- seq_lib/chip_jtag_base_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_alert_handler_entropy_vseq.sv: {is_include_file: true}
diff --git a/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
index f2a74c4..ad8fdc2 100644
--- a/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
+++ b/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -1,4 +1,3 @@
-// Copyright 2023 Google LLC.
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
@@ -59,6 +58,7 @@
`uvm_info(`gfn, "Starting cpu_init", UVM_MEDIUM)
// Initialize the sw logger interface.
+ // SEC
foreach (cfg.sw_images[i]) begin
if (i inside {SwTypeRom, SwTypeDebug, SwTypeTestSlotA, SwTypeTestSlotB}) begin
cfg.sw_logger_vif.add_sw_log_db(cfg.sw_images[i]);
@@ -67,9 +67,19 @@
cfg.sw_logger_vif.sw_log_addr = SW_DV_LOG_ADDR;
cfg.sw_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file;
cfg.sw_logger_vif.ready();
+ // SMC
+ foreach (cfg.sw_images[i]) begin
+ if (i inside {SwTypeSmc}) begin
+ cfg.sw_smc_logger_vif.add_sw_log_db(cfg.sw_images[i]);
+ end
+ end
+ cfg.sw_smc_logger_vif.sw_log_addr = SW_DV_SMC_LOG_ADDR;
+ cfg.sw_smc_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file;
+ cfg.sw_smc_logger_vif.ready();
// Initialize the sw test status.
- cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
+ cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
+ cfg.sw_smc_test_status_vif.sw_test_status_addr = SW_DV_SMC_TEST_STATUS_ADDR;
`uvm_info(`gfn, "Initializing SRAMs", UVM_MEDIUM)
@@ -119,6 +129,11 @@
cfg.mem_bkdr_util_h[FlashBank1Data].load_mem_from_file(
{cfg.sw_images[SwTypeTestSlotB], ".64.scr.vmem"});
end
+ // SMC RAM sw imsage load
+ if (cfg.sw_images.exists(SwTypeSmc)) begin
+ cfg.mem_bkdr_util_h[Smc_ram].load_mem_from_file(
+ {cfg.sw_images[SwTypeSmc], ".32.vmem"});
+ end
config_jitter();
@@ -232,7 +247,7 @@
fork
begin: isolation_thread
fork
- wait (cfg.sw_test_status_vif.sw_test_done);
+ wait (cfg.sw_test_status_vif.sw_test_done || cfg.sw_smc_test_status_vif.sw_test_done);
#(cfg.sw_test_timeout_ns * 1ns);
join_any
disable fork;
@@ -243,15 +258,24 @@
// Print pass / fail message to the log.
virtual function void log_sw_test_status();
- case (cfg.sw_test_status_vif.sw_test_status)
- SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW)
- SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!")
- default: begin
- // If the SW test has not reached the passed / failed state, then it timed out.
+ if(cfg.sw_test_status_vif.sw_test_done || cfg.sw_smc_test_status_vif.sw_test_done) begin
+ if(cfg.sw_test_status_vif.sw_test_done) begin
+ case (cfg.sw_test_status_vif.sw_test_status)
+ SwTestStatusPassed: `uvm_info(`gfn, "[SEC] SW TEST PASSED!", UVM_LOW)
+ SwTestStatusFailed: `uvm_error(`gfn, "[SEC] SW TEST FAILED!")
+ endcase
+ end
+ if(cfg.sw_smc_test_status_vif.sw_test_done) begin
+ case (cfg.sw_smc_test_status_vif.sw_test_status)
+ SwTestStatusPassed: `uvm_info(`gfn, "[SMC] SW TEST PASSED!", UVM_LOW)
+ SwTestStatusFailed: `uvm_error(`gfn, "[SMC] SW TEST FAILED!")
+ endcase
+ end
+ end
+ else begin
`uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n",
- cfg.sw_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns))
- end
- endcase
+ cfg.sw_smc_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns))
+ end
endfunction
// Configure the provided spi_agent_cfg to use flash mode, and add the
diff --git a/hw/top_matcha/dv/env/seq_lib/chip_sw_smc_base_vseq.sv b/hw/top_matcha/dv/env/seq_lib/chip_sw_smc_base_vseq.sv
deleted file mode 100644
index 612c3f2..0000000
--- a/hw/top_matcha/dv/env/seq_lib/chip_sw_smc_base_vseq.sv
+++ /dev/null
@@ -1,69 +0,0 @@
-// Copyright 2023 Google LLC.
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-class chip_sw_smc_base_vseq extends chip_sw_base_vseq;
- `uvm_object_utils(chip_sw_smc_base_vseq)
-
- `uvm_object_new
-
- virtual task cpu_init();
- super.cpu_init();
-
- `uvm_info(`gfn, "Starting SMC cpu_init", UVM_MEDIUM)
-
- foreach (cfg.sw_images[i]) begin
- if (i inside {SwTypeSmc}) begin
- cfg.sw_smc_logger_vif.add_sw_log_db(cfg.sw_images[i]);
- end
- end
- cfg.sw_smc_logger_vif.sw_log_addr = SW_DV_SMC_LOG_ADDR;
- cfg.sw_smc_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file;
- cfg.sw_smc_logger_vif.ready();
-
- // Initialize the sw test status.
- cfg.sw_smc_test_status_vif.sw_test_status_addr = SW_DV_SMC_TEST_STATUS_ADDR;
-
- // SMC RAM sw image load
- if (cfg.sw_images.exists(SwTypeSmc)) begin
- cfg.mem_bkdr_util_h[Smc_ram].load_mem_from_file(
- {cfg.sw_images[SwTypeSmc], ".32.vmem"});
- end
-
- `uvm_info(`gfn, "SMC cpu_init completed", UVM_MEDIUM)
- endtask
-
- virtual task body();
- cfg.sw_smc_test_status_vif.set_num_iterations(num_trans);
- // Initialize the CPU to kick off the sw test. TODO: Should be called in pre_start() instead.
- cpu_init();
- endtask
-
- virtual task wait_for_sw_test_done();
- `uvm_info(`gfn, "Waiting for the SW test to finish", UVM_MEDIUM)
- fork
- begin: isolation_thread
- fork
- wait (cfg.sw_smc_test_status_vif.sw_test_done);
- #(cfg.sw_test_timeout_ns * 1ns);
- join_any
- disable fork;
- log_sw_test_status();
- end: isolation_thread
- join
- endtask
-
- virtual function void log_sw_test_status();
- case (cfg.sw_smc_test_status_vif.sw_test_status)
- SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW)
- SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!")
- default: begin
- // If the SW test has not reached the passed / failed state, then it timed out.
- `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n",
- cfg.sw_smc_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns))
- end
- endcase
- endfunction
-
-endclass
diff --git a/hw/top_matcha/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_matcha/dv/env/seq_lib/chip_vseq_list.sv
index 3701ea8..ebe1a2b 100644
--- a/hw/top_matcha/dv/env/seq_lib/chip_vseq_list.sv
+++ b/hw/top_matcha/dv/env/seq_lib/chip_vseq_list.sv
@@ -11,7 +11,6 @@
`include "chip_jtag_mem_vseq.sv"
// This needs to be listed prior to all sequences that derive from it.
`include "chip_sw_base_vseq.sv"
-`include "chip_sw_smc_base_vseq.sv"
`include "chip_sw_uart_smoke_vseq.sv"
`include "chip_jtag_base_vseq.sv"
`include "chip_prim_tl_access_vseq.sv"
diff --git a/sw/device/tests/smc/BUILD b/sw/device/tests/smc/BUILD
index ede3404..66f08d0 100644
--- a/sw/device/tests/smc/BUILD
+++ b/sw/device/tests/smc/BUILD
@@ -347,8 +347,8 @@
],
deps = [
"//sw/device/lib/dif:i2s",
+ "//sw/device/lib/dif:rv_plic_smc",
"//sw/device/tests:test_lib_smc",
- "@lowrisc_opentitan//sw/device/lib/dif:rv_plic",
"@lowrisc_opentitan//sw/device/lib/runtime:irq",
],
)
@@ -365,8 +365,8 @@
],
deps = [
"//sw/device/lib/dif:i2s",
+ "//sw/device/lib/dif:rv_plic_smc",
"//sw/device/tests:test_lib_smc",
- "@lowrisc_opentitan//sw/device/lib/dif:rv_plic",
"@lowrisc_opentitan//sw/device/lib/runtime:irq",
],
)
diff --git a/sw/device/tests/smc/smc_i2s_tx_test.c b/sw/device/tests/smc/smc_i2s_tx_test.c
index 7f14988..efd556c 100644
--- a/sw/device/tests/smc/smc_i2s_tx_test.c
+++ b/sw/device/tests/smc/smc_i2s_tx_test.c
@@ -125,7 +125,7 @@
48); // divide by 96
mmio_region_write32(i2s.base_addr, I2S_CTRL_REG_OFFSET, reg_val);
- uint32_t samples_to_tx = kDeviceType == kDeviceSimVerilator
+ uint32_t samples_to_tx = kDeviceType == kDeviceSimVerilator || kDeviceType == kDeviceSimDV
? 6
: (i2s_440hz_audio_tx_len / sizeof(uint32_t));
while (tx_audio_count < samples_to_tx) {
