[sencha/hw] Reduce ML DMEM SRAM from 4MB to 2MB - Reduced in an effort to reduce potential die size as we investigate reading weights directly from off chip memory Change-Id: Icb206f16feee12b96e2a25f06956161d345ac324
diff --git a/hw/top_sencha/data/top_sencha.hjson b/hw/top_sencha/data/top_sencha.hjson index c745e84..0efc7ae 100644 --- a/hw/top_sencha/data/top_sencha.hjson +++ b/hw/top_sencha/data/top_sencha.hjson
@@ -973,7 +973,7 @@ swaccess: "rw", exec: "True", byte_write: "True", - size: "0x400000" + size: "0x200000" } } intr_to: "smc",
diff --git a/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv index 3b1a329..3179984 100644 --- a/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv
@@ -185,7 +185,7 @@ '{32'h54050000, 32'h5405000f} }}, '{"ml_top__dmem", '{ - '{32'h5a000000, 32'h5a3fffff} + '{32'h5a000000, 32'h5a1fffff} }}, '{"ml_top__core", '{ '{32'h5c000000, 32'h5c00003f}
diff --git a/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg b/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg index d95716d..e541abd 100644 --- a/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg
@@ -253,7 +253,7 @@ -node tb.dut*.u_cam_ctrl tl_*i.a_address[27:27] -node tb.dut*.u_cam_ctrl tl_*i.a_address[29:29] -node tb.dut*.u_cam_ctrl tl_*i.a_address[31:31] --node tb.dut*.u_ml_top dmem_tl_*i.a_address[24:22] +-node tb.dut*.u_ml_top dmem_tl_*i.a_address[24:21] -node tb.dut*.u_ml_top dmem_tl_*i.a_address[26:26] -node tb.dut*.u_ml_top dmem_tl_*i.a_address[29:29] -node tb.dut*.u_ml_top dmem_tl_*i.a_address[31:31]
diff --git a/hw/top_sencha/dv/verilator/chip_sim_tb.cc b/hw/top_sencha/dv/verilator/chip_sim_tb.cc index 77de8c7..703b443 100644 --- a/hw/top_sencha/dv/verilator/chip_sim_tb.cc +++ b/hw/top_sencha/dv/verilator/chip_sim_tb.cc
@@ -56,7 +56,7 @@ MemArea ram_smc(top_scope + ".u_ram1p_ram_smc.u_mem.gen_generic.u_impl_generic", 0x80000 / 4, 4); MemArea ml_dmem(top_scope + ".u_ml_top.u_ml_dmem.u_ram1p_dmem.u_mem.gen_generic.u_impl_generic", - 0x400000 / 32, 32); + 0x200000 / 32, 32); memutil.RegisterMemoryArea("rom", 0x8000, &rom); memutil.RegisterMemoryArea("ram", 0x10000000u, &ram);
diff --git a/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson index df01b1c..24f8ee1 100644 --- a/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson +++ b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson
@@ -378,7 +378,7 @@ [ { base_addr: 0x5a000000 - size_byte: 0x400000 + size_byte: 0x200000 } ] xbar: false
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg index 3d8e80a..deb844a 100644 --- a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg +++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg
@@ -60,7 +60,7 @@ -node tb.dut tl_cam_ctrl_o.a_address[27:27] -node tb.dut tl_cam_ctrl_o.a_address[29:29] -node tb.dut tl_cam_ctrl_o.a_address[31:31] --node tb.dut tl_ml_top__dmem_o.a_address[24:22] +-node tb.dut tl_ml_top__dmem_o.a_address[24:21] -node tb.dut tl_ml_top__dmem_o.a_address[26:26] -node tb.dut tl_ml_top__dmem_o.a_address[29:29] -node tb.dut tl_ml_top__dmem_o.a_address[31:31]
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv index a9c3eb4..db2159b 100644 --- a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv
@@ -35,7 +35,7 @@ '{32'h54050000, 32'h5405000f} }}, '{"ml_top__dmem", '{ - '{32'h5a000000, 32'h5a3fffff} + '{32'h5a000000, 32'h5a1fffff} }}, '{"ml_top__core", '{ '{32'h5c000000, 32'h5c00003f}
diff --git a/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv b/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv index d13fe00..f276129 100644 --- a/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv +++ b/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv
@@ -35,7 +35,7 @@ localparam logic [31:0] ADDR_MASK_SMC_CTRL = 32'h 00000007; localparam logic [31:0] ADDR_MASK_CAM_I2C = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_CAM_CTRL = 32'h 0000000f; - localparam logic [31:0] ADDR_MASK_ML_TOP__DMEM = 32'h 003fffff; + localparam logic [31:0] ADDR_MASK_ML_TOP__DMEM = 32'h 001fffff; localparam logic [31:0] ADDR_MASK_ML_TOP__CORE = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_ISP_WRAPPER = 32'h 00001fff; localparam logic [31:0] ADDR_MASK_DMA_SMC = 32'h 0000003f;
diff --git a/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv b/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv index a2a7c0d..ec31ed9 100644 --- a/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv +++ b/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv
@@ -638,7 +638,7 @@ /** * Peripheral size in bytes for dmem device on ml_top in top sencha. */ - parameter int unsigned TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES = 32'h400000; + parameter int unsigned TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES = 32'h200000; /** * Peripheral base address for spi_host2 in top sencha. @@ -738,7 +738,7 @@ /** * Memory size for ram_ml_dmem in top sencha. */ - parameter int unsigned TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES = 32'h400000; + parameter int unsigned TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES = 32'h200000; // Enumeration of alert modules
diff --git a/hw/top_sencha/sw/autogen/top_sencha.h b/hw/top_sencha/sw/autogen/top_sencha.h index 4a4b6e4..086be4b 100644 --- a/hw/top_sencha/sw/autogen/top_sencha.h +++ b/hw/top_sencha/sw/autogen/top_sencha.h
@@ -1169,7 +1169,7 @@ * address between #TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR and * `TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR + TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES`. */ -#define TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000u +#define TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES 0x200000u /** * Peripheral base address for spi_host2 in top sencha. @@ -1302,7 +1302,7 @@ /** * Memory size for ram_ml_dmem in top sencha. */ -#define TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000u +#define TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES 0x200000u /**
diff --git a/hw/top_sencha/sw/autogen/top_sencha_memory.h b/hw/top_sencha/sw/autogen/top_sencha_memory.h index 3e90663..196c9a5 100644 --- a/hw/top_sencha/sw/autogen/top_sencha_memory.h +++ b/hw/top_sencha/sw/autogen/top_sencha_memory.h
@@ -69,7 +69,7 @@ /** * Memory size for ml_top_ram_ml_dmem in top sencha. */ -#define TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000 +#define TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES 0x200000 /** @@ -1153,7 +1153,7 @@ * address between #TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR and * `TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR + TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES`. */ -#define TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000 +#define TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES 0x200000 /** * Peripheral base address for spi_host2 in top sencha. *
diff --git a/hw/top_sencha/sw/autogen/top_sencha_memory.ld b/hw/top_sencha/sw/autogen/top_sencha_memory.ld index 01746d6..eb381a1 100644 --- a/hw/top_sencha/sw/autogen/top_sencha_memory.ld +++ b/hw/top_sencha/sw/autogen/top_sencha_memory.ld
@@ -12,7 +12,7 @@ eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000 - ram_ml_dmem(rwx) : ORIGIN = 0x5A000000, LENGTH = 0x400000 + ram_ml_dmem(rwx) : ORIGIN = 0x5A000000, LENGTH = 0x200000 ram_smc(rw) : ORIGIN = 0x50000000, LENGTH = 0x80000 rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000 owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000