Add 2 rv_core_ibex tests and chip_sw_otp_ctrl_escalation to edacloud

Change-Id: I3d54e764b88507269622310ae5744cb19ecc4261

hw/top_matcha/dv/chip_sim_cfg.hjson

diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 31a5426..8163848 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -947,7 +947,7 @@
     {
       name: chip_sw_otp_ctrl_escalation
       uvm_test_seq: chip_sw_otp_ctrl_escalation_vseq
-      sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1"]
       reseed: 1
@@ -1261,7 +1261,7 @@
     {
       name: chip_sw_rv_core_ibex_rnd
       uvm_test_seq: chip_sw_base_vseq
-      sw_images: ["sw/device/tests:rv_core_ibex_rnd_test:1"]
+      sw_images: ["sw/device/tests:rv_core_ibex_rnd_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       // Timeout based on a 10min dvsim runtime.
       run_opts: ["+sw_test_timeout_ns=10_000_000"]
@@ -1269,7 +1269,7 @@
     {
       name: chip_sw_rv_core_ibex_nmi_irq
       uvm_test_seq: chip_sw_base_vseq
-      sw_images: ["sw/device/tests:rv_core_ibex_nmi_irq_test:1"]
+      sw_images: ["sw/device/tests:rv_core_ibex_nmi_irq_test:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+sw_test_timeout_ns=10_000_000"]
     }
@@ -2078,12 +2078,15 @@
         "chip_sw_kmac_smoketest",
         "chip_sw_lc_ctrl_otp_hw_cfg",
         "chip_sw_otbn_smoketest",
+        "chip_sw_otp_ctrl_escalation",
         "chip_sw_otp_ctrl_smoketest",
         "chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
         "chip_sw_rom_ctrl_integrity_check",
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
         "chip_sw_rstmgr_sw_rst",
+        "chip_sw_rv_core_ibex_nmi_irq",
+        "chip_sw_rv_core_ibex_rnd",
         "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
         "chip_sw_rv_plic_smoketest",
         "chip_sw_rv_timer_irq",
@@ -2148,12 +2151,15 @@
         "chip_sw_kmac_smoketest",
         "chip_sw_lc_ctrl_otp_hw_cfg",
         "chip_sw_otbn_smoketest",
+        "chip_sw_otp_ctrl_escalation",
         "chip_sw_otp_ctrl_smoketest",
         "chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
         "chip_sw_rom_ctrl_integrity_check",
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
         "chip_sw_rstmgr_sw_rst",
+        "chip_sw_rv_core_ibex_nmi_irq",
+        "chip_sw_rv_core_ibex_rnd",
         "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
         "chip_sw_rv_plic_smoketest",
         "chip_sw_rv_timer_irq",

sw/device/tests/BUILD

diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index e7f62af..47263e1 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -867,6 +867,36 @@
     ],
 )
 
+matcha_dv_test(
+    name = "rv_core_ibex_rnd_test",
+    srcs = [
+        "@lowrisc_opentitan//sw/device/tests:rv_core_ibex_rnd_test.S",
+        "@lowrisc_opentitan//sw/device/tests:rv_core_ibex_rnd_test.c",
+    ],
+    deps = [
+        ":test_dv_lib_opentitan",
+        "@lowrisc_opentitan//sw/device/lib/dif:edn",
+        "@lowrisc_opentitan//sw/device/lib/dif:rv_core_ibex",
+        "@lowrisc_opentitan//sw/device/lib/testing:entropy_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:rv_core_ibex_testutils",
+    ],
+)
+
+matcha_dv_test(
+    name = "rv_core_ibex_nmi_irq_test",
+    srcs = ["@lowrisc_opentitan//sw/device/tests:rv_core_ibex_nmi_irq_test.c"],
+    deps = [
+        ":test_dv_lib_opentitan",
+        "//sw/device/lib/dif:alert_handler",
+        "@lowrisc_opentitan//sw/device/lib/dif:aon_timer",
+        "@lowrisc_opentitan//sw/device/lib/dif:rv_core_ibex",
+        "@lowrisc_opentitan//sw/device/lib/testing:alert_handler_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:aon_timer_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:isr_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:pwrmgr_testutils",
+    ],
+)
+
 # Smoke tests
 matcha_dv_test(
     name = "aes_smoketest",

sw/device/tests/sim_dv/BUILD

diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index 9bccd8c..db41246 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -134,3 +134,31 @@
         "@lowrisc_opentitan//sw/device/lib/testing:rv_plic_testutils",
     ],
 )
+
+matcha_dv_test(
+    name = "all_escalation_resets_test",
+    srcs = ["@lowrisc_opentitan//sw/device/tests/sim_dv:all_escalation_resets_test.c"],
+    deps = [
+        "//sw/device/lib/dif:alert_handler",
+        "//sw/device/lib/dif:clkmgr",
+        "//sw/device/lib/dif:rstmgr",
+        "//sw/device/lib/dif:rv_plic_sec",
+        "//sw/device/tests:test_dv_lib_opentitan",
+        "@lowrisc_opentitan//sw/device/lib/base:abs_mmio",
+        "@lowrisc_opentitan//sw/device/lib/dif:aes",
+        "@lowrisc_opentitan//sw/device/lib/dif:aon_timer",
+        "@lowrisc_opentitan//sw/device/lib/dif:flash_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/dif:kmac",
+        "@lowrisc_opentitan//sw/device/lib/dif:lc_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/dif:otp_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/dif:pwrmgr",
+        "@lowrisc_opentitan//sw/device/lib/dif:rom_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/dif:rv_core_ibex",
+        "@lowrisc_opentitan//sw/device/lib/dif:sram_ctrl",
+        "@lowrisc_opentitan//sw/device/lib/testing:alert_handler_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:aon_timer_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:flash_ctrl_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
+        "@lowrisc_opentitan//sw/device/lib/testing:rv_plic_testutils",
+    ],
+)