Merge "[ml_top/hw] Update Kelvin with mlu mask on branch"
diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
index e9ef1b2..11a2160 100644
--- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v
+++ b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
@@ -1,4 +1,4 @@
-// SHA: fb78d8ccc36939bd88c4d4f55185d283831d14a6
+// SHA: b3c2fdb85d22f2ece7233db6b539026e8b51399f
module Regfile(
input clock,
input reset,
@@ -103,6 +103,7 @@
input io_writeMask_1_valid,
input io_writeMask_2_valid,
input io_writeMask_3_valid,
+ input io_writeMask_4_valid,
output [31:0] io_scoreboard_regd,
output [31:0] io_scoreboard_comb
);
@@ -254,27 +255,28 @@
reg [31:0] readDataBits_6; // @[Regfile.scala 124:26]
reg [31:0] readDataBits_7; // @[Regfile.scala 124:26]
wire _valid_T_1 = io_writeData_5_valid & io_writeData_5_addr == 5'h1; // @[Regfile.scala 142:43]
- wire _valid_T_3 = io_writeData_4_valid & io_writeData_4_addr == 5'h1; // @[Regfile.scala 143:43]
- wire _valid_T_6 = ~io_writeMask_3_valid; // @[Regfile.scala 145:23]
- wire _valid_T_7 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_10 = ~io_writeMask_2_valid; // @[Regfile.scala 147:23]
- wire _valid_T_11 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_14 = ~io_writeMask_1_valid; // @[Regfile.scala 149:23]
- wire _valid_T_15 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_17 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 150:43]
- wire [5:0] valid = {_valid_T_1,_valid_T_3,_valid_T_7,_valid_T_11,_valid_T_15,_valid_T_17}; // @[Cat.scala 31:58]
+ wire _valid_T_4 = ~io_writeMask_4_valid; // @[Regfile.scala 144:23]
+ wire _valid_T_5 = io_writeData_4_valid & io_writeData_4_addr == 5'h1 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_8 = ~io_writeMask_3_valid; // @[Regfile.scala 146:23]
+ wire _valid_T_9 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_12 = ~io_writeMask_2_valid; // @[Regfile.scala 148:23]
+ wire _valid_T_13 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_16 = ~io_writeMask_1_valid; // @[Regfile.scala 150:23]
+ wire _valid_T_17 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_19 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 151:43]
+ wire [5:0] valid = {_valid_T_1,_valid_T_5,_valid_T_9,_valid_T_13,_valid_T_17,_valid_T_19}; // @[Cat.scala 31:58]
wire [31:0] _data_T_1 = valid[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_3 = valid[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 154:55]
wire [31:0] _data_T_6 = valid[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 155:55]
wire [31:0] _data_T_9 = valid[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 156:55]
wire [31:0] _data_T_12 = valid[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 157:55]
wire [31:0] _data_T_15 = valid[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 157:55]
- wire writeValid_1 = valid != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 158:55]
+ wire writeValid_1 = valid != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_9 = valid[1] + valid[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_41 = {{1'd0}, valid[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_11 = _GEN_41 + _T_9; // @[Bitwise.scala 48:55]
@@ -282,26 +284,26 @@
wire [1:0] _GEN_42 = {{1'd0}, valid[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_15 = _GEN_42 + _T_13; // @[Bitwise.scala 48:55]
wire [2:0] _T_17 = _T_11[1:0] + _T_15[1:0]; // @[Bitwise.scala 48:55]
- wire _T_21 = ~reset; // @[Regfile.scala 163:11]
- wire _valid_T_21 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 142:43]
- wire _valid_T_23 = io_writeData_4_valid & io_writeData_4_addr == 5'h2; // @[Regfile.scala 143:43]
- wire _valid_T_27 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_31 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_35 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_37 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 150:43]
- wire [5:0] valid_1 = {_valid_T_21,_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_37}; // @[Cat.scala 31:58]
+ wire _T_21 = ~reset; // @[Regfile.scala 164:11]
+ wire _valid_T_23 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 142:43]
+ wire _valid_T_27 = io_writeData_4_valid & io_writeData_4_addr == 5'h2 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_31 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_35 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_39 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_41 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 151:43]
+ wire [5:0] valid_1 = {_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_39,_valid_T_41}; // @[Cat.scala 31:58]
wire [31:0] _data_T_17 = valid_1[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_19 = valid_1[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 154:55]
wire [31:0] _data_T_22 = valid_1[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 155:55]
wire [31:0] _data_T_25 = valid_1[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 156:55]
wire [31:0] _data_T_28 = valid_1[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 157:55]
wire [31:0] _data_T_31 = valid_1[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 157:55]
- wire writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 158:55]
+ wire writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_29 = valid_1[1] + valid_1[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_43 = {{1'd0}, valid_1[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_31 = _GEN_43 + _T_29; // @[Bitwise.scala 48:55]
@@ -309,25 +311,25 @@
wire [1:0] _GEN_44 = {{1'd0}, valid_1[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_35 = _GEN_44 + _T_33; // @[Bitwise.scala 48:55]
wire [2:0] _T_37 = _T_31[1:0] + _T_35[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_41 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 142:43]
- wire _valid_T_43 = io_writeData_4_valid & io_writeData_4_addr == 5'h3; // @[Regfile.scala 143:43]
- wire _valid_T_47 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_51 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_55 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_57 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 150:43]
- wire [5:0] valid_2 = {_valid_T_41,_valid_T_43,_valid_T_47,_valid_T_51,_valid_T_55,_valid_T_57}; // @[Cat.scala 31:58]
+ wire _valid_T_45 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 142:43]
+ wire _valid_T_49 = io_writeData_4_valid & io_writeData_4_addr == 5'h3 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_53 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_57 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_61 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_63 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 151:43]
+ wire [5:0] valid_2 = {_valid_T_45,_valid_T_49,_valid_T_53,_valid_T_57,_valid_T_61,_valid_T_63}; // @[Cat.scala 31:58]
wire [31:0] _data_T_33 = valid_2[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_35 = valid_2[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 154:55]
wire [31:0] _data_T_38 = valid_2[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 155:55]
wire [31:0] _data_T_41 = valid_2[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 156:55]
wire [31:0] _data_T_44 = valid_2[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 157:55]
wire [31:0] _data_T_47 = valid_2[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 157:55]
- wire writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 158:55]
+ wire writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_49 = valid_2[1] + valid_2[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_45 = {{1'd0}, valid_2[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_51 = _GEN_45 + _T_49; // @[Bitwise.scala 48:55]
@@ -335,25 +337,25 @@
wire [1:0] _GEN_46 = {{1'd0}, valid_2[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_55 = _GEN_46 + _T_53; // @[Bitwise.scala 48:55]
wire [2:0] _T_57 = _T_51[1:0] + _T_55[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_61 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 142:43]
- wire _valid_T_63 = io_writeData_4_valid & io_writeData_4_addr == 5'h4; // @[Regfile.scala 143:43]
- wire _valid_T_67 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_71 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_75 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_77 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 150:43]
- wire [5:0] valid_3 = {_valid_T_61,_valid_T_63,_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_77}; // @[Cat.scala 31:58]
+ wire _valid_T_67 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 142:43]
+ wire _valid_T_71 = io_writeData_4_valid & io_writeData_4_addr == 5'h4 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_75 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_79 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_83 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_85 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 151:43]
+ wire [5:0] valid_3 = {_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_79,_valid_T_83,_valid_T_85}; // @[Cat.scala 31:58]
wire [31:0] _data_T_49 = valid_3[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_51 = valid_3[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 154:55]
wire [31:0] _data_T_54 = valid_3[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 155:55]
wire [31:0] _data_T_57 = valid_3[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 156:55]
wire [31:0] _data_T_60 = valid_3[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 157:55]
wire [31:0] _data_T_63 = valid_3[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 157:55]
- wire writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 158:55]
+ wire writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_69 = valid_3[1] + valid_3[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_47 = {{1'd0}, valid_3[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_71 = _GEN_47 + _T_69; // @[Bitwise.scala 48:55]
@@ -361,25 +363,25 @@
wire [1:0] _GEN_48 = {{1'd0}, valid_3[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_75 = _GEN_48 + _T_73; // @[Bitwise.scala 48:55]
wire [2:0] _T_77 = _T_71[1:0] + _T_75[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_81 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 142:43]
- wire _valid_T_83 = io_writeData_4_valid & io_writeData_4_addr == 5'h5; // @[Regfile.scala 143:43]
- wire _valid_T_87 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_91 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_95 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_97 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 150:43]
- wire [5:0] valid_4 = {_valid_T_81,_valid_T_83,_valid_T_87,_valid_T_91,_valid_T_95,_valid_T_97}; // @[Cat.scala 31:58]
+ wire _valid_T_89 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 142:43]
+ wire _valid_T_93 = io_writeData_4_valid & io_writeData_4_addr == 5'h5 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_97 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_101 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_105 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_107 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 151:43]
+ wire [5:0] valid_4 = {_valid_T_89,_valid_T_93,_valid_T_97,_valid_T_101,_valid_T_105,_valid_T_107}; // @[Cat.scala 31:58]
wire [31:0] _data_T_65 = valid_4[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_67 = valid_4[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 154:55]
wire [31:0] _data_T_70 = valid_4[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 155:55]
wire [31:0] _data_T_73 = valid_4[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 156:55]
wire [31:0] _data_T_76 = valid_4[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 157:55]
wire [31:0] _data_T_79 = valid_4[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 157:55]
- wire writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 158:55]
+ wire writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_89 = valid_4[1] + valid_4[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_49 = {{1'd0}, valid_4[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_91 = _GEN_49 + _T_89; // @[Bitwise.scala 48:55]
@@ -387,25 +389,25 @@
wire [1:0] _GEN_50 = {{1'd0}, valid_4[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_95 = _GEN_50 + _T_93; // @[Bitwise.scala 48:55]
wire [2:0] _T_97 = _T_91[1:0] + _T_95[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_101 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 142:43]
- wire _valid_T_103 = io_writeData_4_valid & io_writeData_4_addr == 5'h6; // @[Regfile.scala 143:43]
- wire _valid_T_107 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_111 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_115 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_117 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 150:43]
- wire [5:0] valid_5 = {_valid_T_101,_valid_T_103,_valid_T_107,_valid_T_111,_valid_T_115,_valid_T_117}; // @[Cat.scala 31:58]
+ wire _valid_T_111 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 142:43]
+ wire _valid_T_115 = io_writeData_4_valid & io_writeData_4_addr == 5'h6 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_119 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_123 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_127 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_129 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 151:43]
+ wire [5:0] valid_5 = {_valid_T_111,_valid_T_115,_valid_T_119,_valid_T_123,_valid_T_127,_valid_T_129}; // @[Cat.scala 31:58]
wire [31:0] _data_T_81 = valid_5[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_83 = valid_5[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 154:55]
wire [31:0] _data_T_86 = valid_5[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 155:55]
wire [31:0] _data_T_89 = valid_5[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 156:55]
wire [31:0] _data_T_92 = valid_5[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 157:55]
wire [31:0] _data_T_95 = valid_5[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 157:55]
- wire writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 158:55]
+ wire writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_109 = valid_5[1] + valid_5[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_51 = {{1'd0}, valid_5[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_111 = _GEN_51 + _T_109; // @[Bitwise.scala 48:55]
@@ -413,25 +415,25 @@
wire [1:0] _GEN_52 = {{1'd0}, valid_5[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_115 = _GEN_52 + _T_113; // @[Bitwise.scala 48:55]
wire [2:0] _T_117 = _T_111[1:0] + _T_115[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_121 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 142:43]
- wire _valid_T_123 = io_writeData_4_valid & io_writeData_4_addr == 5'h7; // @[Regfile.scala 143:43]
- wire _valid_T_127 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_131 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_135 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_137 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 150:43]
- wire [5:0] valid_6 = {_valid_T_121,_valid_T_123,_valid_T_127,_valid_T_131,_valid_T_135,_valid_T_137}; // @[Cat.scala 31:58]
+ wire _valid_T_133 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 142:43]
+ wire _valid_T_137 = io_writeData_4_valid & io_writeData_4_addr == 5'h7 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_141 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_145 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_149 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_151 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 151:43]
+ wire [5:0] valid_6 = {_valid_T_133,_valid_T_137,_valid_T_141,_valid_T_145,_valid_T_149,_valid_T_151}; // @[Cat.scala 31:58]
wire [31:0] _data_T_97 = valid_6[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_99 = valid_6[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 154:55]
wire [31:0] _data_T_102 = valid_6[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 155:55]
wire [31:0] _data_T_105 = valid_6[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 156:55]
wire [31:0] _data_T_108 = valid_6[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 157:55]
wire [31:0] _data_T_111 = valid_6[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 157:55]
- wire writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 158:55]
+ wire writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_129 = valid_6[1] + valid_6[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_53 = {{1'd0}, valid_6[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_131 = _GEN_53 + _T_129; // @[Bitwise.scala 48:55]
@@ -439,25 +441,25 @@
wire [1:0] _GEN_54 = {{1'd0}, valid_6[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_135 = _GEN_54 + _T_133; // @[Bitwise.scala 48:55]
wire [2:0] _T_137 = _T_131[1:0] + _T_135[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_141 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 142:43]
- wire _valid_T_143 = io_writeData_4_valid & io_writeData_4_addr == 5'h8; // @[Regfile.scala 143:43]
- wire _valid_T_147 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_151 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_155 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_157 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 150:43]
- wire [5:0] valid_7 = {_valid_T_141,_valid_T_143,_valid_T_147,_valid_T_151,_valid_T_155,_valid_T_157}; // @[Cat.scala 31:58]
+ wire _valid_T_155 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 142:43]
+ wire _valid_T_159 = io_writeData_4_valid & io_writeData_4_addr == 5'h8 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_163 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_167 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_171 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_173 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 151:43]
+ wire [5:0] valid_7 = {_valid_T_155,_valid_T_159,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_173}; // @[Cat.scala 31:58]
wire [31:0] _data_T_113 = valid_7[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_115 = valid_7[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 154:55]
wire [31:0] _data_T_118 = valid_7[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 155:55]
wire [31:0] _data_T_121 = valid_7[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 156:55]
wire [31:0] _data_T_124 = valid_7[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 157:55]
wire [31:0] _data_T_127 = valid_7[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 157:55]
- wire writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 158:55]
+ wire writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_149 = valid_7[1] + valid_7[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_55 = {{1'd0}, valid_7[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_151 = _GEN_55 + _T_149; // @[Bitwise.scala 48:55]
@@ -465,25 +467,25 @@
wire [1:0] _GEN_56 = {{1'd0}, valid_7[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_155 = _GEN_56 + _T_153; // @[Bitwise.scala 48:55]
wire [2:0] _T_157 = _T_151[1:0] + _T_155[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_161 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 142:43]
- wire _valid_T_163 = io_writeData_4_valid & io_writeData_4_addr == 5'h9; // @[Regfile.scala 143:43]
- wire _valid_T_167 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_171 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_175 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_177 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 150:43]
- wire [5:0] valid_8 = {_valid_T_161,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_175,_valid_T_177}; // @[Cat.scala 31:58]
+ wire _valid_T_177 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 142:43]
+ wire _valid_T_181 = io_writeData_4_valid & io_writeData_4_addr == 5'h9 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_185 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_189 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_193 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_195 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 151:43]
+ wire [5:0] valid_8 = {_valid_T_177,_valid_T_181,_valid_T_185,_valid_T_189,_valid_T_193,_valid_T_195}; // @[Cat.scala 31:58]
wire [31:0] _data_T_129 = valid_8[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_131 = valid_8[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 154:55]
wire [31:0] _data_T_134 = valid_8[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 155:55]
wire [31:0] _data_T_137 = valid_8[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 156:55]
wire [31:0] _data_T_140 = valid_8[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 157:55]
wire [31:0] _data_T_143 = valid_8[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 157:55]
- wire writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 158:55]
+ wire writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_169 = valid_8[1] + valid_8[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_57 = {{1'd0}, valid_8[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_171 = _GEN_57 + _T_169; // @[Bitwise.scala 48:55]
@@ -491,25 +493,25 @@
wire [1:0] _GEN_58 = {{1'd0}, valid_8[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_175 = _GEN_58 + _T_173; // @[Bitwise.scala 48:55]
wire [2:0] _T_177 = _T_171[1:0] + _T_175[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_181 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 142:43]
- wire _valid_T_183 = io_writeData_4_valid & io_writeData_4_addr == 5'ha; // @[Regfile.scala 143:43]
- wire _valid_T_187 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_191 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_195 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_197 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 150:43]
- wire [5:0] valid_9 = {_valid_T_181,_valid_T_183,_valid_T_187,_valid_T_191,_valid_T_195,_valid_T_197}; // @[Cat.scala 31:58]
+ wire _valid_T_199 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 142:43]
+ wire _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'ha & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 151:43]
+ wire [5:0] valid_9 = {_valid_T_199,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58]
wire [31:0] _data_T_145 = valid_9[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_147 = valid_9[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 154:55]
wire [31:0] _data_T_150 = valid_9[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 155:55]
wire [31:0] _data_T_153 = valid_9[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 156:55]
wire [31:0] _data_T_156 = valid_9[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 157:55]
wire [31:0] _data_T_159 = valid_9[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 157:55]
- wire writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 158:55]
+ wire writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_189 = valid_9[1] + valid_9[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_59 = {{1'd0}, valid_9[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_191 = _GEN_59 + _T_189; // @[Bitwise.scala 48:55]
@@ -517,25 +519,25 @@
wire [1:0] _GEN_60 = {{1'd0}, valid_9[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_195 = _GEN_60 + _T_193; // @[Bitwise.scala 48:55]
wire [2:0] _T_197 = _T_191[1:0] + _T_195[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_201 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 142:43]
- wire _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'hb; // @[Regfile.scala 143:43]
- wire _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 150:43]
- wire [5:0] valid_10 = {_valid_T_201,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58]
+ wire _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 142:43]
+ wire _valid_T_225 = io_writeData_4_valid & io_writeData_4_addr == 5'hb & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_229 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_233 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_237 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_239 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 151:43]
+ wire [5:0] valid_10 = {_valid_T_221,_valid_T_225,_valid_T_229,_valid_T_233,_valid_T_237,_valid_T_239}; // @[Cat.scala 31:58]
wire [31:0] _data_T_161 = valid_10[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_163 = valid_10[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 154:55]
wire [31:0] _data_T_166 = valid_10[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 155:55]
wire [31:0] _data_T_169 = valid_10[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 156:55]
wire [31:0] _data_T_172 = valid_10[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 157:55]
wire [31:0] _data_T_175 = valid_10[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 157:55]
- wire writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 158:55]
+ wire writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_209 = valid_10[1] + valid_10[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_61 = {{1'd0}, valid_10[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_211 = _GEN_61 + _T_209; // @[Bitwise.scala 48:55]
@@ -543,25 +545,25 @@
wire [1:0] _GEN_62 = {{1'd0}, valid_10[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_215 = _GEN_62 + _T_213; // @[Bitwise.scala 48:55]
wire [2:0] _T_217 = _T_211[1:0] + _T_215[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 142:43]
- wire _valid_T_223 = io_writeData_4_valid & io_writeData_4_addr == 5'hc; // @[Regfile.scala 143:43]
- wire _valid_T_227 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_231 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_235 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_237 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 150:43]
- wire [5:0] valid_11 = {_valid_T_221,_valid_T_223,_valid_T_227,_valid_T_231,_valid_T_235,_valid_T_237}; // @[Cat.scala 31:58]
+ wire _valid_T_243 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 142:43]
+ wire _valid_T_247 = io_writeData_4_valid & io_writeData_4_addr == 5'hc & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_251 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_255 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_259 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_261 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 151:43]
+ wire [5:0] valid_11 = {_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_259,_valid_T_261}; // @[Cat.scala 31:58]
wire [31:0] _data_T_177 = valid_11[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_179 = valid_11[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 154:55]
wire [31:0] _data_T_182 = valid_11[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 155:55]
wire [31:0] _data_T_185 = valid_11[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 156:55]
wire [31:0] _data_T_188 = valid_11[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 157:55]
wire [31:0] _data_T_191 = valid_11[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 157:55]
- wire writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 158:55]
+ wire writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_229 = valid_11[1] + valid_11[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_63 = {{1'd0}, valid_11[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_231 = _GEN_63 + _T_229; // @[Bitwise.scala 48:55]
@@ -569,25 +571,25 @@
wire [1:0] _GEN_64 = {{1'd0}, valid_11[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_235 = _GEN_64 + _T_233; // @[Bitwise.scala 48:55]
wire [2:0] _T_237 = _T_231[1:0] + _T_235[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_241 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 142:43]
- wire _valid_T_243 = io_writeData_4_valid & io_writeData_4_addr == 5'hd; // @[Regfile.scala 143:43]
- wire _valid_T_247 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_251 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_255 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_257 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 150:43]
- wire [5:0] valid_12 = {_valid_T_241,_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_257}; // @[Cat.scala 31:58]
+ wire _valid_T_265 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 142:43]
+ wire _valid_T_269 = io_writeData_4_valid & io_writeData_4_addr == 5'hd & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_273 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_277 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_281 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_283 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 151:43]
+ wire [5:0] valid_12 = {_valid_T_265,_valid_T_269,_valid_T_273,_valid_T_277,_valid_T_281,_valid_T_283}; // @[Cat.scala 31:58]
wire [31:0] _data_T_193 = valid_12[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_195 = valid_12[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 154:55]
wire [31:0] _data_T_198 = valid_12[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 155:55]
wire [31:0] _data_T_201 = valid_12[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 156:55]
wire [31:0] _data_T_204 = valid_12[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 157:55]
wire [31:0] _data_T_207 = valid_12[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 157:55]
- wire writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 158:55]
+ wire writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_249 = valid_12[1] + valid_12[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_65 = {{1'd0}, valid_12[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_251 = _GEN_65 + _T_249; // @[Bitwise.scala 48:55]
@@ -595,25 +597,25 @@
wire [1:0] _GEN_66 = {{1'd0}, valid_12[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_255 = _GEN_66 + _T_253; // @[Bitwise.scala 48:55]
wire [2:0] _T_257 = _T_251[1:0] + _T_255[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_261 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 142:43]
- wire _valid_T_263 = io_writeData_4_valid & io_writeData_4_addr == 5'he; // @[Regfile.scala 143:43]
- wire _valid_T_267 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_271 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_275 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_277 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 150:43]
- wire [5:0] valid_13 = {_valid_T_261,_valid_T_263,_valid_T_267,_valid_T_271,_valid_T_275,_valid_T_277}; // @[Cat.scala 31:58]
+ wire _valid_T_287 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 142:43]
+ wire _valid_T_291 = io_writeData_4_valid & io_writeData_4_addr == 5'he & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_295 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_299 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_303 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_305 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 151:43]
+ wire [5:0] valid_13 = {_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_299,_valid_T_303,_valid_T_305}; // @[Cat.scala 31:58]
wire [31:0] _data_T_209 = valid_13[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_211 = valid_13[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 154:55]
wire [31:0] _data_T_214 = valid_13[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 155:55]
wire [31:0] _data_T_217 = valid_13[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 156:55]
wire [31:0] _data_T_220 = valid_13[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 157:55]
wire [31:0] _data_T_223 = valid_13[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 157:55]
- wire writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 158:55]
+ wire writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_269 = valid_13[1] + valid_13[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_67 = {{1'd0}, valid_13[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_271 = _GEN_67 + _T_269; // @[Bitwise.scala 48:55]
@@ -621,25 +623,25 @@
wire [1:0] _GEN_68 = {{1'd0}, valid_13[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_275 = _GEN_68 + _T_273; // @[Bitwise.scala 48:55]
wire [2:0] _T_277 = _T_271[1:0] + _T_275[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_281 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 142:43]
- wire _valid_T_283 = io_writeData_4_valid & io_writeData_4_addr == 5'hf; // @[Regfile.scala 143:43]
- wire _valid_T_287 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_291 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_295 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_297 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 150:43]
- wire [5:0] valid_14 = {_valid_T_281,_valid_T_283,_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_297}; // @[Cat.scala 31:58]
+ wire _valid_T_309 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 142:43]
+ wire _valid_T_313 = io_writeData_4_valid & io_writeData_4_addr == 5'hf & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_317 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_321 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_325 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_327 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 151:43]
+ wire [5:0] valid_14 = {_valid_T_309,_valid_T_313,_valid_T_317,_valid_T_321,_valid_T_325,_valid_T_327}; // @[Cat.scala 31:58]
wire [31:0] _data_T_225 = valid_14[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_227 = valid_14[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 154:55]
wire [31:0] _data_T_230 = valid_14[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 155:55]
wire [31:0] _data_T_233 = valid_14[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 156:55]
wire [31:0] _data_T_236 = valid_14[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 157:55]
wire [31:0] _data_T_239 = valid_14[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 157:55]
- wire writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 158:55]
+ wire writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_289 = valid_14[1] + valid_14[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_69 = {{1'd0}, valid_14[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_291 = _GEN_69 + _T_289; // @[Bitwise.scala 48:55]
@@ -647,25 +649,25 @@
wire [1:0] _GEN_70 = {{1'd0}, valid_14[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_295 = _GEN_70 + _T_293; // @[Bitwise.scala 48:55]
wire [2:0] _T_297 = _T_291[1:0] + _T_295[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_301 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 142:43]
- wire _valid_T_303 = io_writeData_4_valid & io_writeData_4_addr == 5'h10; // @[Regfile.scala 143:43]
- wire _valid_T_307 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_311 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_315 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_317 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 150:43]
- wire [5:0] valid_15 = {_valid_T_301,_valid_T_303,_valid_T_307,_valid_T_311,_valid_T_315,_valid_T_317}; // @[Cat.scala 31:58]
+ wire _valid_T_331 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 142:43]
+ wire _valid_T_335 = io_writeData_4_valid & io_writeData_4_addr == 5'h10 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_339 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_343 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_347 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_349 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 151:43]
+ wire [5:0] valid_15 = {_valid_T_331,_valid_T_335,_valid_T_339,_valid_T_343,_valid_T_347,_valid_T_349}; // @[Cat.scala 31:58]
wire [31:0] _data_T_241 = valid_15[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_243 = valid_15[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 154:55]
wire [31:0] _data_T_246 = valid_15[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 155:55]
wire [31:0] _data_T_249 = valid_15[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 156:55]
wire [31:0] _data_T_252 = valid_15[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 157:55]
wire [31:0] _data_T_255 = valid_15[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 157:55]
- wire writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 158:55]
+ wire writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_309 = valid_15[1] + valid_15[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_71 = {{1'd0}, valid_15[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_311 = _GEN_71 + _T_309; // @[Bitwise.scala 48:55]
@@ -673,25 +675,25 @@
wire [1:0] _GEN_72 = {{1'd0}, valid_15[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_315 = _GEN_72 + _T_313; // @[Bitwise.scala 48:55]
wire [2:0] _T_317 = _T_311[1:0] + _T_315[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_321 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 142:43]
- wire _valid_T_323 = io_writeData_4_valid & io_writeData_4_addr == 5'h11; // @[Regfile.scala 143:43]
- wire _valid_T_327 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_331 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_335 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_337 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 150:43]
- wire [5:0] valid_16 = {_valid_T_321,_valid_T_323,_valid_T_327,_valid_T_331,_valid_T_335,_valid_T_337}; // @[Cat.scala 31:58]
+ wire _valid_T_353 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 142:43]
+ wire _valid_T_357 = io_writeData_4_valid & io_writeData_4_addr == 5'h11 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_361 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_365 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_369 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_371 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 151:43]
+ wire [5:0] valid_16 = {_valid_T_353,_valid_T_357,_valid_T_361,_valid_T_365,_valid_T_369,_valid_T_371}; // @[Cat.scala 31:58]
wire [31:0] _data_T_257 = valid_16[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_259 = valid_16[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 154:55]
wire [31:0] _data_T_262 = valid_16[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 155:55]
wire [31:0] _data_T_265 = valid_16[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 156:55]
wire [31:0] _data_T_268 = valid_16[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 157:55]
wire [31:0] _data_T_271 = valid_16[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 157:55]
- wire writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 158:55]
+ wire writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_329 = valid_16[1] + valid_16[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_73 = {{1'd0}, valid_16[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_331 = _GEN_73 + _T_329; // @[Bitwise.scala 48:55]
@@ -699,25 +701,25 @@
wire [1:0] _GEN_74 = {{1'd0}, valid_16[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_335 = _GEN_74 + _T_333; // @[Bitwise.scala 48:55]
wire [2:0] _T_337 = _T_331[1:0] + _T_335[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_341 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 142:43]
- wire _valid_T_343 = io_writeData_4_valid & io_writeData_4_addr == 5'h12; // @[Regfile.scala 143:43]
- wire _valid_T_347 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_351 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_355 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_357 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 150:43]
- wire [5:0] valid_17 = {_valid_T_341,_valid_T_343,_valid_T_347,_valid_T_351,_valid_T_355,_valid_T_357}; // @[Cat.scala 31:58]
+ wire _valid_T_375 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 142:43]
+ wire _valid_T_379 = io_writeData_4_valid & io_writeData_4_addr == 5'h12 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_383 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_387 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_391 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_393 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 151:43]
+ wire [5:0] valid_17 = {_valid_T_375,_valid_T_379,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_393}; // @[Cat.scala 31:58]
wire [31:0] _data_T_273 = valid_17[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_275 = valid_17[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 154:55]
wire [31:0] _data_T_278 = valid_17[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 155:55]
wire [31:0] _data_T_281 = valid_17[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 156:55]
wire [31:0] _data_T_284 = valid_17[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 157:55]
wire [31:0] _data_T_287 = valid_17[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 157:55]
- wire writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 158:55]
+ wire writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_349 = valid_17[1] + valid_17[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_75 = {{1'd0}, valid_17[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_351 = _GEN_75 + _T_349; // @[Bitwise.scala 48:55]
@@ -725,25 +727,25 @@
wire [1:0] _GEN_76 = {{1'd0}, valid_17[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_355 = _GEN_76 + _T_353; // @[Bitwise.scala 48:55]
wire [2:0] _T_357 = _T_351[1:0] + _T_355[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_361 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 142:43]
- wire _valid_T_363 = io_writeData_4_valid & io_writeData_4_addr == 5'h13; // @[Regfile.scala 143:43]
- wire _valid_T_367 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_371 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_375 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_377 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 150:43]
- wire [5:0] valid_18 = {_valid_T_361,_valid_T_363,_valid_T_367,_valid_T_371,_valid_T_375,_valid_T_377}; // @[Cat.scala 31:58]
+ wire _valid_T_397 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 142:43]
+ wire _valid_T_401 = io_writeData_4_valid & io_writeData_4_addr == 5'h13 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_405 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_409 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_413 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_415 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 151:43]
+ wire [5:0] valid_18 = {_valid_T_397,_valid_T_401,_valid_T_405,_valid_T_409,_valid_T_413,_valid_T_415}; // @[Cat.scala 31:58]
wire [31:0] _data_T_289 = valid_18[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_291 = valid_18[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 154:55]
wire [31:0] _data_T_294 = valid_18[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 155:55]
wire [31:0] _data_T_297 = valid_18[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 156:55]
wire [31:0] _data_T_300 = valid_18[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 157:55]
wire [31:0] _data_T_303 = valid_18[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 157:55]
- wire writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 158:55]
+ wire writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_369 = valid_18[1] + valid_18[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_77 = {{1'd0}, valid_18[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_371 = _GEN_77 + _T_369; // @[Bitwise.scala 48:55]
@@ -751,25 +753,25 @@
wire [1:0] _GEN_78 = {{1'd0}, valid_18[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_375 = _GEN_78 + _T_373; // @[Bitwise.scala 48:55]
wire [2:0] _T_377 = _T_371[1:0] + _T_375[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_381 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 142:43]
- wire _valid_T_383 = io_writeData_4_valid & io_writeData_4_addr == 5'h14; // @[Regfile.scala 143:43]
- wire _valid_T_387 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_391 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_395 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_397 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 150:43]
- wire [5:0] valid_19 = {_valid_T_381,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_395,_valid_T_397}; // @[Cat.scala 31:58]
+ wire _valid_T_419 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 142:43]
+ wire _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h14 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 151:43]
+ wire [5:0] valid_19 = {_valid_T_419,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58]
wire [31:0] _data_T_305 = valid_19[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_307 = valid_19[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 154:55]
wire [31:0] _data_T_310 = valid_19[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 155:55]
wire [31:0] _data_T_313 = valid_19[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 156:55]
wire [31:0] _data_T_316 = valid_19[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 157:55]
wire [31:0] _data_T_319 = valid_19[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 157:55]
- wire writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 158:55]
+ wire writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_389 = valid_19[1] + valid_19[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_79 = {{1'd0}, valid_19[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_391 = _GEN_79 + _T_389; // @[Bitwise.scala 48:55]
@@ -777,25 +779,25 @@
wire [1:0] _GEN_80 = {{1'd0}, valid_19[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_395 = _GEN_80 + _T_393; // @[Bitwise.scala 48:55]
wire [2:0] _T_397 = _T_391[1:0] + _T_395[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_401 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 142:43]
- wire _valid_T_403 = io_writeData_4_valid & io_writeData_4_addr == 5'h15; // @[Regfile.scala 143:43]
- wire _valid_T_407 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_411 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_415 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_417 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 150:43]
- wire [5:0] valid_20 = {_valid_T_401,_valid_T_403,_valid_T_407,_valid_T_411,_valid_T_415,_valid_T_417}; // @[Cat.scala 31:58]
+ wire _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 142:43]
+ wire _valid_T_445 = io_writeData_4_valid & io_writeData_4_addr == 5'h15 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_449 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_453 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_457 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_459 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 151:43]
+ wire [5:0] valid_20 = {_valid_T_441,_valid_T_445,_valid_T_449,_valid_T_453,_valid_T_457,_valid_T_459}; // @[Cat.scala 31:58]
wire [31:0] _data_T_321 = valid_20[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_323 = valid_20[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 154:55]
wire [31:0] _data_T_326 = valid_20[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 155:55]
wire [31:0] _data_T_329 = valid_20[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 156:55]
wire [31:0] _data_T_332 = valid_20[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 157:55]
wire [31:0] _data_T_335 = valid_20[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 157:55]
- wire writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 158:55]
+ wire writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_409 = valid_20[1] + valid_20[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_81 = {{1'd0}, valid_20[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_411 = _GEN_81 + _T_409; // @[Bitwise.scala 48:55]
@@ -803,25 +805,25 @@
wire [1:0] _GEN_82 = {{1'd0}, valid_20[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_415 = _GEN_82 + _T_413; // @[Bitwise.scala 48:55]
wire [2:0] _T_417 = _T_411[1:0] + _T_415[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_421 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 142:43]
- wire _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h16; // @[Regfile.scala 143:43]
- wire _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 150:43]
- wire [5:0] valid_21 = {_valid_T_421,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58]
+ wire _valid_T_463 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 142:43]
+ wire _valid_T_467 = io_writeData_4_valid & io_writeData_4_addr == 5'h16 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_471 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_475 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_479 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_481 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 151:43]
+ wire [5:0] valid_21 = {_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_479,_valid_T_481}; // @[Cat.scala 31:58]
wire [31:0] _data_T_337 = valid_21[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_339 = valid_21[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 154:55]
wire [31:0] _data_T_342 = valid_21[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 155:55]
wire [31:0] _data_T_345 = valid_21[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 156:55]
wire [31:0] _data_T_348 = valid_21[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 157:55]
wire [31:0] _data_T_351 = valid_21[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 157:55]
- wire writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 158:55]
+ wire writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_429 = valid_21[1] + valid_21[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_83 = {{1'd0}, valid_21[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_431 = _GEN_83 + _T_429; // @[Bitwise.scala 48:55]
@@ -829,25 +831,25 @@
wire [1:0] _GEN_84 = {{1'd0}, valid_21[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_435 = _GEN_84 + _T_433; // @[Bitwise.scala 48:55]
wire [2:0] _T_437 = _T_431[1:0] + _T_435[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 142:43]
- wire _valid_T_443 = io_writeData_4_valid & io_writeData_4_addr == 5'h17; // @[Regfile.scala 143:43]
- wire _valid_T_447 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_451 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_455 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_457 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 150:43]
- wire [5:0] valid_22 = {_valid_T_441,_valid_T_443,_valid_T_447,_valid_T_451,_valid_T_455,_valid_T_457}; // @[Cat.scala 31:58]
+ wire _valid_T_485 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 142:43]
+ wire _valid_T_489 = io_writeData_4_valid & io_writeData_4_addr == 5'h17 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_493 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_497 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_501 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_503 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 151:43]
+ wire [5:0] valid_22 = {_valid_T_485,_valid_T_489,_valid_T_493,_valid_T_497,_valid_T_501,_valid_T_503}; // @[Cat.scala 31:58]
wire [31:0] _data_T_353 = valid_22[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_355 = valid_22[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 154:55]
wire [31:0] _data_T_358 = valid_22[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 155:55]
wire [31:0] _data_T_361 = valid_22[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 156:55]
wire [31:0] _data_T_364 = valid_22[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 157:55]
wire [31:0] _data_T_367 = valid_22[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 157:55]
- wire writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 158:55]
+ wire writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_449 = valid_22[1] + valid_22[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_85 = {{1'd0}, valid_22[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_451 = _GEN_85 + _T_449; // @[Bitwise.scala 48:55]
@@ -855,25 +857,25 @@
wire [1:0] _GEN_86 = {{1'd0}, valid_22[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_455 = _GEN_86 + _T_453; // @[Bitwise.scala 48:55]
wire [2:0] _T_457 = _T_451[1:0] + _T_455[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_461 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 142:43]
- wire _valid_T_463 = io_writeData_4_valid & io_writeData_4_addr == 5'h18; // @[Regfile.scala 143:43]
- wire _valid_T_467 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_471 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_475 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_477 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 150:43]
- wire [5:0] valid_23 = {_valid_T_461,_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_477}; // @[Cat.scala 31:58]
+ wire _valid_T_507 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 142:43]
+ wire _valid_T_511 = io_writeData_4_valid & io_writeData_4_addr == 5'h18 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_515 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_519 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_523 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_525 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 151:43]
+ wire [5:0] valid_23 = {_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_519,_valid_T_523,_valid_T_525}; // @[Cat.scala 31:58]
wire [31:0] _data_T_369 = valid_23[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_371 = valid_23[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 154:55]
wire [31:0] _data_T_374 = valid_23[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 155:55]
wire [31:0] _data_T_377 = valid_23[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 156:55]
wire [31:0] _data_T_380 = valid_23[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 157:55]
wire [31:0] _data_T_383 = valid_23[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 157:55]
- wire writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 158:55]
+ wire writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_469 = valid_23[1] + valid_23[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_87 = {{1'd0}, valid_23[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_471 = _GEN_87 + _T_469; // @[Bitwise.scala 48:55]
@@ -881,25 +883,25 @@
wire [1:0] _GEN_88 = {{1'd0}, valid_23[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_475 = _GEN_88 + _T_473; // @[Bitwise.scala 48:55]
wire [2:0] _T_477 = _T_471[1:0] + _T_475[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_481 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 142:43]
- wire _valid_T_483 = io_writeData_4_valid & io_writeData_4_addr == 5'h19; // @[Regfile.scala 143:43]
- wire _valid_T_487 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_491 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_495 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_497 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 150:43]
- wire [5:0] valid_24 = {_valid_T_481,_valid_T_483,_valid_T_487,_valid_T_491,_valid_T_495,_valid_T_497}; // @[Cat.scala 31:58]
+ wire _valid_T_529 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 142:43]
+ wire _valid_T_533 = io_writeData_4_valid & io_writeData_4_addr == 5'h19 & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_537 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_541 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_545 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_547 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 151:43]
+ wire [5:0] valid_24 = {_valid_T_529,_valid_T_533,_valid_T_537,_valid_T_541,_valid_T_545,_valid_T_547}; // @[Cat.scala 31:58]
wire [31:0] _data_T_385 = valid_24[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_387 = valid_24[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 154:55]
wire [31:0] _data_T_390 = valid_24[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 155:55]
wire [31:0] _data_T_393 = valid_24[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 156:55]
wire [31:0] _data_T_396 = valid_24[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 157:55]
wire [31:0] _data_T_399 = valid_24[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 157:55]
- wire writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 158:55]
+ wire writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_489 = valid_24[1] + valid_24[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_89 = {{1'd0}, valid_24[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_491 = _GEN_89 + _T_489; // @[Bitwise.scala 48:55]
@@ -907,25 +909,25 @@
wire [1:0] _GEN_90 = {{1'd0}, valid_24[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_495 = _GEN_90 + _T_493; // @[Bitwise.scala 48:55]
wire [2:0] _T_497 = _T_491[1:0] + _T_495[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_501 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 142:43]
- wire _valid_T_503 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a; // @[Regfile.scala 143:43]
- wire _valid_T_507 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_511 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_515 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_517 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 150:43]
- wire [5:0] valid_25 = {_valid_T_501,_valid_T_503,_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_517}; // @[Cat.scala 31:58]
+ wire _valid_T_551 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 142:43]
+ wire _valid_T_555 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_559 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_563 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_567 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_569 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 151:43]
+ wire [5:0] valid_25 = {_valid_T_551,_valid_T_555,_valid_T_559,_valid_T_563,_valid_T_567,_valid_T_569}; // @[Cat.scala 31:58]
wire [31:0] _data_T_401 = valid_25[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_403 = valid_25[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 154:55]
wire [31:0] _data_T_406 = valid_25[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 155:55]
wire [31:0] _data_T_409 = valid_25[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 156:55]
wire [31:0] _data_T_412 = valid_25[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 157:55]
wire [31:0] _data_T_415 = valid_25[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 157:55]
- wire writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 158:55]
+ wire writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_509 = valid_25[1] + valid_25[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_91 = {{1'd0}, valid_25[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_511 = _GEN_91 + _T_509; // @[Bitwise.scala 48:55]
@@ -933,25 +935,25 @@
wire [1:0] _GEN_92 = {{1'd0}, valid_25[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_515 = _GEN_92 + _T_513; // @[Bitwise.scala 48:55]
wire [2:0] _T_517 = _T_511[1:0] + _T_515[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_521 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 142:43]
- wire _valid_T_523 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b; // @[Regfile.scala 143:43]
- wire _valid_T_527 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_531 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_535 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_537 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 150:43]
- wire [5:0] valid_26 = {_valid_T_521,_valid_T_523,_valid_T_527,_valid_T_531,_valid_T_535,_valid_T_537}; // @[Cat.scala 31:58]
+ wire _valid_T_573 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 142:43]
+ wire _valid_T_577 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_581 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_585 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_589 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_591 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 151:43]
+ wire [5:0] valid_26 = {_valid_T_573,_valid_T_577,_valid_T_581,_valid_T_585,_valid_T_589,_valid_T_591}; // @[Cat.scala 31:58]
wire [31:0] _data_T_417 = valid_26[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_419 = valid_26[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 154:55]
wire [31:0] _data_T_422 = valid_26[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 155:55]
wire [31:0] _data_T_425 = valid_26[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 156:55]
wire [31:0] _data_T_428 = valid_26[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 157:55]
wire [31:0] _data_T_431 = valid_26[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 157:55]
- wire writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 158:55]
+ wire writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_529 = valid_26[1] + valid_26[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_93 = {{1'd0}, valid_26[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_531 = _GEN_93 + _T_529; // @[Bitwise.scala 48:55]
@@ -959,25 +961,25 @@
wire [1:0] _GEN_94 = {{1'd0}, valid_26[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_535 = _GEN_94 + _T_533; // @[Bitwise.scala 48:55]
wire [2:0] _T_537 = _T_531[1:0] + _T_535[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_541 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 142:43]
- wire _valid_T_543 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c; // @[Regfile.scala 143:43]
- wire _valid_T_547 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_551 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_555 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_557 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 150:43]
- wire [5:0] valid_27 = {_valid_T_541,_valid_T_543,_valid_T_547,_valid_T_551,_valid_T_555,_valid_T_557}; // @[Cat.scala 31:58]
+ wire _valid_T_595 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 142:43]
+ wire _valid_T_599 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_603 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_607 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_611 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_613 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 151:43]
+ wire [5:0] valid_27 = {_valid_T_595,_valid_T_599,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_613}; // @[Cat.scala 31:58]
wire [31:0] _data_T_433 = valid_27[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_435 = valid_27[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 154:55]
wire [31:0] _data_T_438 = valid_27[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 155:55]
wire [31:0] _data_T_441 = valid_27[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 156:55]
wire [31:0] _data_T_444 = valid_27[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 157:55]
wire [31:0] _data_T_447 = valid_27[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 157:55]
- wire writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 158:55]
+ wire writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_549 = valid_27[1] + valid_27[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_95 = {{1'd0}, valid_27[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_551 = _GEN_95 + _T_549; // @[Bitwise.scala 48:55]
@@ -985,25 +987,25 @@
wire [1:0] _GEN_96 = {{1'd0}, valid_27[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_555 = _GEN_96 + _T_553; // @[Bitwise.scala 48:55]
wire [2:0] _T_557 = _T_551[1:0] + _T_555[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_561 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 142:43]
- wire _valid_T_563 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d; // @[Regfile.scala 143:43]
- wire _valid_T_567 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_571 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_575 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_577 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 150:43]
- wire [5:0] valid_28 = {_valid_T_561,_valid_T_563,_valid_T_567,_valid_T_571,_valid_T_575,_valid_T_577}; // @[Cat.scala 31:58]
+ wire _valid_T_617 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 142:43]
+ wire _valid_T_621 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_625 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_629 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_633 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_635 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 151:43]
+ wire [5:0] valid_28 = {_valid_T_617,_valid_T_621,_valid_T_625,_valid_T_629,_valid_T_633,_valid_T_635}; // @[Cat.scala 31:58]
wire [31:0] _data_T_449 = valid_28[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_451 = valid_28[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 154:55]
wire [31:0] _data_T_454 = valid_28[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 155:55]
wire [31:0] _data_T_457 = valid_28[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 156:55]
wire [31:0] _data_T_460 = valid_28[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 157:55]
wire [31:0] _data_T_463 = valid_28[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 157:55]
- wire writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 158:55]
+ wire writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_569 = valid_28[1] + valid_28[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_97 = {{1'd0}, valid_28[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_571 = _GEN_97 + _T_569; // @[Bitwise.scala 48:55]
@@ -1011,25 +1013,25 @@
wire [1:0] _GEN_98 = {{1'd0}, valid_28[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_575 = _GEN_98 + _T_573; // @[Bitwise.scala 48:55]
wire [2:0] _T_577 = _T_571[1:0] + _T_575[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_581 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 142:43]
- wire _valid_T_583 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e; // @[Regfile.scala 143:43]
- wire _valid_T_587 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_591 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_595 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_597 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 150:43]
- wire [5:0] valid_29 = {_valid_T_581,_valid_T_583,_valid_T_587,_valid_T_591,_valid_T_595,_valid_T_597}; // @[Cat.scala 31:58]
+ wire _valid_T_639 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 142:43]
+ wire _valid_T_643 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_647 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_651 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_655 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_657 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 151:43]
+ wire [5:0] valid_29 = {_valid_T_639,_valid_T_643,_valid_T_647,_valid_T_651,_valid_T_655,_valid_T_657}; // @[Cat.scala 31:58]
wire [31:0] _data_T_465 = valid_29[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_467 = valid_29[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 154:55]
wire [31:0] _data_T_470 = valid_29[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 155:55]
wire [31:0] _data_T_473 = valid_29[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 156:55]
wire [31:0] _data_T_476 = valid_29[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 157:55]
wire [31:0] _data_T_479 = valid_29[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 157:55]
- wire writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 158:55]
+ wire writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_589 = valid_29[1] + valid_29[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_99 = {{1'd0}, valid_29[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_591 = _GEN_99 + _T_589; // @[Bitwise.scala 48:55]
@@ -1037,25 +1039,25 @@
wire [1:0] _GEN_100 = {{1'd0}, valid_29[3]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_595 = _GEN_100 + _T_593; // @[Bitwise.scala 48:55]
wire [2:0] _T_597 = _T_591[1:0] + _T_595[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_601 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 142:43]
- wire _valid_T_603 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f; // @[Regfile.scala 143:43]
- wire _valid_T_607 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_6; // @[Regfile.scala 144:75]
- wire _valid_T_611 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_10; // @[Regfile.scala 146:75]
- wire _valid_T_615 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_14; // @[Regfile.scala 148:75]
- wire _valid_T_617 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 150:43]
- wire [5:0] valid_30 = {_valid_T_601,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_615,_valid_T_617}; // @[Cat.scala 31:58]
+ wire _valid_T_661 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 142:43]
+ wire _valid_T_665 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f & _valid_T_4; // @[Regfile.scala 143:75]
+ wire _valid_T_669 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_8; // @[Regfile.scala 145:75]
+ wire _valid_T_673 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_12; // @[Regfile.scala 147:75]
+ wire _valid_T_677 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_16; // @[Regfile.scala 149:75]
+ wire _valid_T_679 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 151:43]
+ wire [5:0] valid_30 = {_valid_T_661,_valid_T_665,_valid_T_669,_valid_T_673,_valid_T_677,_valid_T_679}; // @[Cat.scala 31:58]
wire [31:0] _data_T_481 = valid_30[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _data_T_483 = valid_30[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 153:55]
+ wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 154:55]
wire [31:0] _data_T_486 = valid_30[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 154:55]
+ wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 155:55]
wire [31:0] _data_T_489 = valid_30[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 155:55]
+ wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 156:55]
wire [31:0] _data_T_492 = valid_30[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 156:55]
+ wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 157:55]
wire [31:0] _data_T_495 = valid_30[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 157:55]
- wire writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 160:28]
+ wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 158:55]
+ wire writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 161:28]
wire [1:0] _T_609 = valid_30[1] + valid_30[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_101 = {{1'd0}, valid_30[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _T_611 = _GEN_101 + _T_609; // @[Bitwise.scala 48:55]
@@ -1248,7 +1250,7 @@
wire [31:0] wdata_0_value_4_0 = wdata_0_value_3_0 | wdata_0_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_0_value_4_1 = wdata_0_value_3_2 | wdata_0_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_0_value_5_0 = wdata_0_value_4_0 | wdata_0_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 184:21]
wire write_value_6_0 = 5'h0 == io_readAddr_1_addr; // @[Library.scala 101:27]
wire write_value_6_1 = 5'h1 == io_readAddr_1_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_6_2 = 5'h2 == io_readAddr_1_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1434,7 +1436,7 @@
wire [31:0] wdata_1_value_4_0 = wdata_1_value_3_0 | wdata_1_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_1_value_4_1 = wdata_1_value_3_2 | wdata_1_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_1_value_5_0 = wdata_1_value_4_0 | wdata_1_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 184:21]
wire write_value_12_0 = 5'h0 == io_readAddr_2_addr; // @[Library.scala 101:27]
wire write_value_12_1 = 5'h1 == io_readAddr_2_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_12_2 = 5'h2 == io_readAddr_2_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1620,7 +1622,7 @@
wire [31:0] wdata_2_value_4_0 = wdata_2_value_3_0 | wdata_2_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_2_value_4_1 = wdata_2_value_3_2 | wdata_2_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_2_value_5_0 = wdata_2_value_4_0 | wdata_2_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 184:21]
wire write_value_18_0 = 5'h0 == io_readAddr_3_addr; // @[Library.scala 101:27]
wire write_value_18_1 = 5'h1 == io_readAddr_3_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_18_2 = 5'h2 == io_readAddr_3_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1806,7 +1808,7 @@
wire [31:0] wdata_3_value_4_0 = wdata_3_value_3_0 | wdata_3_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_3_value_4_1 = wdata_3_value_3_2 | wdata_3_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_3_value_5_0 = wdata_3_value_4_0 | wdata_3_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 184:21]
wire write_value_24_0 = 5'h0 == io_readAddr_4_addr; // @[Library.scala 101:27]
wire write_value_24_1 = 5'h1 == io_readAddr_4_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_24_2 = 5'h2 == io_readAddr_4_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1992,7 +1994,7 @@
wire [31:0] wdata_4_value_4_0 = wdata_4_value_3_0 | wdata_4_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_4_value_4_1 = wdata_4_value_3_2 | wdata_4_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_4_value_5_0 = wdata_4_value_4_0 | wdata_4_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 184:21]
wire write_value_30_0 = 5'h0 == io_readAddr_5_addr; // @[Library.scala 101:27]
wire write_value_30_1 = 5'h1 == io_readAddr_5_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_30_2 = 5'h2 == io_readAddr_5_addr & writeValid_2; // @[Library.scala 101:22]
@@ -2178,7 +2180,7 @@
wire [31:0] wdata_5_value_4_0 = wdata_5_value_3_0 | wdata_5_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_5_value_4_1 = wdata_5_value_3_2 | wdata_5_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_5_value_5_0 = wdata_5_value_4_0 | wdata_5_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 184:21]
wire write_value_36_0 = 5'h0 == io_readAddr_6_addr; // @[Library.scala 101:27]
wire write_value_36_1 = 5'h1 == io_readAddr_6_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_36_2 = 5'h2 == io_readAddr_6_addr & writeValid_2; // @[Library.scala 101:22]
@@ -2364,7 +2366,7 @@
wire [31:0] wdata_6_value_4_0 = wdata_6_value_3_0 | wdata_6_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_6_value_4_1 = wdata_6_value_3_2 | wdata_6_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_6_value_5_0 = wdata_6_value_4_0 | wdata_6_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 183:21]
+ wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 184:21]
wire write_value_42_0 = 5'h0 == io_readAddr_7_addr; // @[Library.scala 101:27]
wire write_value_42_1 = 5'h1 == io_readAddr_7_addr & writeValid_1; // @[Library.scala 101:22]
wire write_value_42_2 = 5'h2 == io_readAddr_7_addr & writeValid_2; // @[Library.scala 101:22]
@@ -2550,86 +2552,86 @@
wire [31:0] wdata_7_value_4_0 = wdata_7_value_3_0 | wdata_7_value_3_1; // @[Library.scala 115:37]
wire [31:0] wdata_7_value_4_1 = wdata_7_value_3_2 | wdata_7_value_3_3; // @[Library.scala 115:37]
wire [31:0] wdata_7_value_5_0 = wdata_7_value_4_0 | wdata_7_value_4_1; // @[Library.scala 115:37]
- wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 183:21]
- wire nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 190:49]
- wire nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 190:49]
- wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 208:57]
- wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 208:22]
- wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 208:57]
- wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 208:57]
- wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 208:57]
- reg write_fail; // @[Regfile.scala 238:31]
- wire _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 239:68]
- wire _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 241:42]
- reg write_fail_1; // @[Regfile.scala 238:31]
- wire _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 239:68]
- reg write_fail_2; // @[Regfile.scala 238:31]
- wire _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 239:68]
- reg write_fail_3; // @[Regfile.scala 238:31]
- wire _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 239:68]
- reg write_fail_4; // @[Regfile.scala 238:31]
- wire _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 239:68]
- reg write_fail_5; // @[Regfile.scala 238:31]
- wire _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 239:68]
- wire _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 241:42]
- reg write_fail_6; // @[Regfile.scala 238:31]
- wire _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 239:68]
- reg write_fail_7; // @[Regfile.scala 238:31]
- wire _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 239:68]
- reg write_fail_8; // @[Regfile.scala 238:31]
- wire _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 239:68]
- reg write_fail_9; // @[Regfile.scala 238:31]
- wire _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 239:68]
- wire _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 241:42]
- reg write_fail_10; // @[Regfile.scala 238:31]
- wire _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 239:68]
- reg write_fail_11; // @[Regfile.scala 238:31]
- wire _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 239:68]
- reg write_fail_12; // @[Regfile.scala 238:31]
- wire _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 239:68]
- wire _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 241:42]
- reg write_fail_13; // @[Regfile.scala 238:31]
- wire _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 239:68]
- reg write_fail_14; // @[Regfile.scala 238:31]
- wire _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
- wire _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 239:68]
- wire _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 241:42]
- reg scoreboard_error; // @[Regfile.scala 246:33]
- wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 247:35]
- assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 207:22]
- assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 207:22]
- assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 207:22]
- assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 207:22]
- assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 225:24]
- assign io_linkPort_value = regfile_1; // @[Regfile.scala 226:21]
- assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 207:22]
- assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 207:22]
- assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 207:22]
- assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 207:22]
- assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 194:30]
- assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 194:30]
- assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 194:30]
- assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 194:30]
+ wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 184:21]
+ wire nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 191:49]
+ wire nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 191:49]
+ wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 209:57]
+ wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 209:22]
+ wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 209:57]
+ wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 209:57]
+ wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 209:57]
+ reg write_fail; // @[Regfile.scala 239:31]
+ wire _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 240:68]
+ wire _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 242:42]
+ reg write_fail_1; // @[Regfile.scala 239:31]
+ wire _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 240:68]
+ reg write_fail_2; // @[Regfile.scala 239:31]
+ wire _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 240:68]
+ reg write_fail_3; // @[Regfile.scala 239:31]
+ wire _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 240:68]
+ reg write_fail_4; // @[Regfile.scala 239:31]
+ wire _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 240:68]
+ reg write_fail_5; // @[Regfile.scala 239:31]
+ wire _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 240:68]
+ wire _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 242:42]
+ reg write_fail_6; // @[Regfile.scala 239:31]
+ wire _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 240:68]
+ reg write_fail_7; // @[Regfile.scala 239:31]
+ wire _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 240:68]
+ reg write_fail_8; // @[Regfile.scala 239:31]
+ wire _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 240:68]
+ reg write_fail_9; // @[Regfile.scala 239:31]
+ wire _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 240:68]
+ wire _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 242:42]
+ reg write_fail_10; // @[Regfile.scala 239:31]
+ wire _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 240:68]
+ reg write_fail_11; // @[Regfile.scala 239:31]
+ wire _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 240:68]
+ reg write_fail_12; // @[Regfile.scala 239:31]
+ wire _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 240:68]
+ wire _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 242:42]
+ reg write_fail_13; // @[Regfile.scala 239:31]
+ wire _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 240:68]
+ reg write_fail_14; // @[Regfile.scala 239:31]
+ wire _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+ wire _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 240:68]
+ wire _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 242:42]
+ reg scoreboard_error; // @[Regfile.scala 247:33]
+ wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 248:35]
+ assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 208:22]
+ assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 208:22]
+ assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 208:22]
+ assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 208:22]
+ assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 226:24]
+ assign io_linkPort_value = regfile_1; // @[Regfile.scala 227:21]
+ assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 208:22]
+ assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 208:22]
+ assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 208:22]
+ assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 208:22]
+ assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 195:30]
+ assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 195:30]
+ assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 195:30]
+ assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 195:30]
assign io_readData_0_valid = readDataReady_0; // @[Regfile.scala 128:26]
assign io_readData_0_data = readDataBits_0; // @[Regfile.scala 129:26]
assign io_readData_1_valid = readDataReady_1; // @[Regfile.scala 128:26]
@@ -2649,166 +2651,166 @@
assign io_scoreboard_regd = scoreboard; // @[Regfile.scala 117:22]
assign io_scoreboard_comb = scoreboard & _nxtScoreboard_T; // @[Regfile.scala 118:36]
always @(posedge clock) begin
- if (writeValid_1) begin // @[Regfile.scala 167:26]
- regfile_1 <= data; // @[Regfile.scala 168:18]
+ if (writeValid_1) begin // @[Regfile.scala 168:26]
+ regfile_1 <= data; // @[Regfile.scala 169:18]
end
- if (writeValid_2) begin // @[Regfile.scala 167:26]
- regfile_2 <= data_1; // @[Regfile.scala 168:18]
+ if (writeValid_2) begin // @[Regfile.scala 168:26]
+ regfile_2 <= data_1; // @[Regfile.scala 169:18]
end
- if (writeValid_3) begin // @[Regfile.scala 167:26]
- regfile_3 <= data_2; // @[Regfile.scala 168:18]
+ if (writeValid_3) begin // @[Regfile.scala 168:26]
+ regfile_3 <= data_2; // @[Regfile.scala 169:18]
end
- if (writeValid_4) begin // @[Regfile.scala 167:26]
- regfile_4 <= data_3; // @[Regfile.scala 168:18]
+ if (writeValid_4) begin // @[Regfile.scala 168:26]
+ regfile_4 <= data_3; // @[Regfile.scala 169:18]
end
- if (writeValid_5) begin // @[Regfile.scala 167:26]
- regfile_5 <= data_4; // @[Regfile.scala 168:18]
+ if (writeValid_5) begin // @[Regfile.scala 168:26]
+ regfile_5 <= data_4; // @[Regfile.scala 169:18]
end
- if (writeValid_6) begin // @[Regfile.scala 167:26]
- regfile_6 <= data_5; // @[Regfile.scala 168:18]
+ if (writeValid_6) begin // @[Regfile.scala 168:26]
+ regfile_6 <= data_5; // @[Regfile.scala 169:18]
end
- if (writeValid_7) begin // @[Regfile.scala 167:26]
- regfile_7 <= data_6; // @[Regfile.scala 168:18]
+ if (writeValid_7) begin // @[Regfile.scala 168:26]
+ regfile_7 <= data_6; // @[Regfile.scala 169:18]
end
- if (writeValid_8) begin // @[Regfile.scala 167:26]
- regfile_8 <= data_7; // @[Regfile.scala 168:18]
+ if (writeValid_8) begin // @[Regfile.scala 168:26]
+ regfile_8 <= data_7; // @[Regfile.scala 169:18]
end
- if (writeValid_9) begin // @[Regfile.scala 167:26]
- regfile_9 <= data_8; // @[Regfile.scala 168:18]
+ if (writeValid_9) begin // @[Regfile.scala 168:26]
+ regfile_9 <= data_8; // @[Regfile.scala 169:18]
end
- if (writeValid_10) begin // @[Regfile.scala 167:26]
- regfile_10 <= data_9; // @[Regfile.scala 168:18]
+ if (writeValid_10) begin // @[Regfile.scala 168:26]
+ regfile_10 <= data_9; // @[Regfile.scala 169:18]
end
- if (writeValid_11) begin // @[Regfile.scala 167:26]
- regfile_11 <= data_10; // @[Regfile.scala 168:18]
+ if (writeValid_11) begin // @[Regfile.scala 168:26]
+ regfile_11 <= data_10; // @[Regfile.scala 169:18]
end
- if (writeValid_12) begin // @[Regfile.scala 167:26]
- regfile_12 <= data_11; // @[Regfile.scala 168:18]
+ if (writeValid_12) begin // @[Regfile.scala 168:26]
+ regfile_12 <= data_11; // @[Regfile.scala 169:18]
end
- if (writeValid_13) begin // @[Regfile.scala 167:26]
- regfile_13 <= data_12; // @[Regfile.scala 168:18]
+ if (writeValid_13) begin // @[Regfile.scala 168:26]
+ regfile_13 <= data_12; // @[Regfile.scala 169:18]
end
- if (writeValid_14) begin // @[Regfile.scala 167:26]
- regfile_14 <= data_13; // @[Regfile.scala 168:18]
+ if (writeValid_14) begin // @[Regfile.scala 168:26]
+ regfile_14 <= data_13; // @[Regfile.scala 169:18]
end
- if (writeValid_15) begin // @[Regfile.scala 167:26]
- regfile_15 <= data_14; // @[Regfile.scala 168:18]
+ if (writeValid_15) begin // @[Regfile.scala 168:26]
+ regfile_15 <= data_14; // @[Regfile.scala 169:18]
end
- if (writeValid_16) begin // @[Regfile.scala 167:26]
- regfile_16 <= data_15; // @[Regfile.scala 168:18]
+ if (writeValid_16) begin // @[Regfile.scala 168:26]
+ regfile_16 <= data_15; // @[Regfile.scala 169:18]
end
- if (writeValid_17) begin // @[Regfile.scala 167:26]
- regfile_17 <= data_16; // @[Regfile.scala 168:18]
+ if (writeValid_17) begin // @[Regfile.scala 168:26]
+ regfile_17 <= data_16; // @[Regfile.scala 169:18]
end
- if (writeValid_18) begin // @[Regfile.scala 167:26]
- regfile_18 <= data_17; // @[Regfile.scala 168:18]
+ if (writeValid_18) begin // @[Regfile.scala 168:26]
+ regfile_18 <= data_17; // @[Regfile.scala 169:18]
end
- if (writeValid_19) begin // @[Regfile.scala 167:26]
- regfile_19 <= data_18; // @[Regfile.scala 168:18]
+ if (writeValid_19) begin // @[Regfile.scala 168:26]
+ regfile_19 <= data_18; // @[Regfile.scala 169:18]
end
- if (writeValid_20) begin // @[Regfile.scala 167:26]
- regfile_20 <= data_19; // @[Regfile.scala 168:18]
+ if (writeValid_20) begin // @[Regfile.scala 168:26]
+ regfile_20 <= data_19; // @[Regfile.scala 169:18]
end
- if (writeValid_21) begin // @[Regfile.scala 167:26]
- regfile_21 <= data_20; // @[Regfile.scala 168:18]
+ if (writeValid_21) begin // @[Regfile.scala 168:26]
+ regfile_21 <= data_20; // @[Regfile.scala 169:18]
end
- if (writeValid_22) begin // @[Regfile.scala 167:26]
- regfile_22 <= data_21; // @[Regfile.scala 168:18]
+ if (writeValid_22) begin // @[Regfile.scala 168:26]
+ regfile_22 <= data_21; // @[Regfile.scala 169:18]
end
- if (writeValid_23) begin // @[Regfile.scala 167:26]
- regfile_23 <= data_22; // @[Regfile.scala 168:18]
+ if (writeValid_23) begin // @[Regfile.scala 168:26]
+ regfile_23 <= data_22; // @[Regfile.scala 169:18]
end
- if (writeValid_24) begin // @[Regfile.scala 167:26]
- regfile_24 <= data_23; // @[Regfile.scala 168:18]
+ if (writeValid_24) begin // @[Regfile.scala 168:26]
+ regfile_24 <= data_23; // @[Regfile.scala 169:18]
end
- if (writeValid_25) begin // @[Regfile.scala 167:26]
- regfile_25 <= data_24; // @[Regfile.scala 168:18]
+ if (writeValid_25) begin // @[Regfile.scala 168:26]
+ regfile_25 <= data_24; // @[Regfile.scala 169:18]
end
- if (writeValid_26) begin // @[Regfile.scala 167:26]
- regfile_26 <= data_25; // @[Regfile.scala 168:18]
+ if (writeValid_26) begin // @[Regfile.scala 168:26]
+ regfile_26 <= data_25; // @[Regfile.scala 169:18]
end
- if (writeValid_27) begin // @[Regfile.scala 167:26]
- regfile_27 <= data_26; // @[Regfile.scala 168:18]
+ if (writeValid_27) begin // @[Regfile.scala 168:26]
+ regfile_27 <= data_26; // @[Regfile.scala 169:18]
end
- if (writeValid_28) begin // @[Regfile.scala 167:26]
- regfile_28 <= data_27; // @[Regfile.scala 168:18]
+ if (writeValid_28) begin // @[Regfile.scala 168:26]
+ regfile_28 <= data_27; // @[Regfile.scala 169:18]
end
- if (writeValid_29) begin // @[Regfile.scala 167:26]
- regfile_29 <= data_28; // @[Regfile.scala 168:18]
+ if (writeValid_29) begin // @[Regfile.scala 168:26]
+ regfile_29 <= data_28; // @[Regfile.scala 169:18]
end
- if (writeValid_30) begin // @[Regfile.scala 167:26]
- regfile_30 <= data_29; // @[Regfile.scala 168:18]
+ if (writeValid_30) begin // @[Regfile.scala 168:26]
+ regfile_30 <= data_29; // @[Regfile.scala 169:18]
end
- if (writeValid_31) begin // @[Regfile.scala 167:26]
- regfile_31 <= data_30; // @[Regfile.scala 168:18]
+ if (writeValid_31) begin // @[Regfile.scala 168:26]
+ regfile_31 <= data_30; // @[Regfile.scala 169:18]
end
- if (nxtReadDataReady) begin // @[Regfile.scala 196:29]
- if (io_readSet_0_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady) begin // @[Regfile.scala 197:29]
+ if (io_readSet_0_valid) begin // @[Regfile.scala 195:30]
readDataBits_0 <= io_readSet_0_value;
- end else if (write_value_5_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_5_0) begin // @[Regfile.scala 184:21]
readDataBits_0 <= wdata_0_value_5_0;
end else begin
readDataBits_0 <= rdata_0_value_5_0;
end
end
- if (nxtReadDataReady_1) begin // @[Regfile.scala 196:29]
- if (io_readSet_1_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_1) begin // @[Regfile.scala 197:29]
+ if (io_readSet_1_valid) begin // @[Regfile.scala 195:30]
readDataBits_1 <= io_readSet_1_value;
- end else if (write_value_11_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_11_0) begin // @[Regfile.scala 184:21]
readDataBits_1 <= wdata_1_value_5_0;
end else begin
readDataBits_1 <= rdata_1_value_5_0;
end
end
- if (nxtReadDataReady_2) begin // @[Regfile.scala 196:29]
- if (io_readSet_2_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_2) begin // @[Regfile.scala 197:29]
+ if (io_readSet_2_valid) begin // @[Regfile.scala 195:30]
readDataBits_2 <= io_readSet_2_value;
- end else if (write_value_17_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_17_0) begin // @[Regfile.scala 184:21]
readDataBits_2 <= wdata_2_value_5_0;
end else begin
readDataBits_2 <= rdata_2_value_5_0;
end
end
- if (nxtReadDataReady_3) begin // @[Regfile.scala 196:29]
- if (io_readSet_3_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_3) begin // @[Regfile.scala 197:29]
+ if (io_readSet_3_valid) begin // @[Regfile.scala 195:30]
readDataBits_3 <= io_readSet_3_value;
- end else if (write_value_23_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_23_0) begin // @[Regfile.scala 184:21]
readDataBits_3 <= wdata_3_value_5_0;
end else begin
readDataBits_3 <= rdata_3_value_5_0;
end
end
- if (nxtReadDataReady_4) begin // @[Regfile.scala 196:29]
- if (io_readSet_4_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_4) begin // @[Regfile.scala 197:29]
+ if (io_readSet_4_valid) begin // @[Regfile.scala 195:30]
readDataBits_4 <= io_readSet_4_value;
- end else if (write_value_29_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_29_0) begin // @[Regfile.scala 184:21]
readDataBits_4 <= wdata_4_value_5_0;
end else begin
readDataBits_4 <= rdata_4_value_5_0;
end
end
- if (nxtReadDataReady_5) begin // @[Regfile.scala 196:29]
- if (io_readSet_5_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_5) begin // @[Regfile.scala 197:29]
+ if (io_readSet_5_valid) begin // @[Regfile.scala 195:30]
readDataBits_5 <= io_readSet_5_value;
- end else if (write_value_35_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_35_0) begin // @[Regfile.scala 184:21]
readDataBits_5 <= wdata_5_value_5_0;
end else begin
readDataBits_5 <= rdata_5_value_5_0;
end
end
- if (nxtReadDataReady_6) begin // @[Regfile.scala 196:29]
- if (io_readSet_6_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_6) begin // @[Regfile.scala 197:29]
+ if (io_readSet_6_valid) begin // @[Regfile.scala 195:30]
readDataBits_6 <= io_readSet_6_value;
- end else if (write_value_41_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_41_0) begin // @[Regfile.scala 184:21]
readDataBits_6 <= wdata_6_value_5_0;
end else begin
readDataBits_6 <= rdata_6_value_5_0;
end
end
- if (nxtReadDataReady_7) begin // @[Regfile.scala 196:29]
- if (io_readSet_7_valid) begin // @[Regfile.scala 194:30]
+ if (nxtReadDataReady_7) begin // @[Regfile.scala 197:29]
+ if (io_readSet_7_valid) begin // @[Regfile.scala 195:30]
readDataBits_7 <= io_readSet_7_value;
- end else if (write_value_47_0) begin // @[Regfile.scala 183:21]
+ end else if (write_value_47_0) begin // @[Regfile.scala 184:21]
readDataBits_7 <= wdata_7_value_5_0;
end else begin
readDataBits_7 <= rdata_7_value_5_0;
@@ -2819,7 +2821,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_17 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2830,7 +2832,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_17 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2841,7 +2843,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_37 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2852,7 +2854,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_37 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2863,7 +2865,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_57 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2874,7 +2876,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_57 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2885,7 +2887,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_77 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2896,7 +2898,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_77 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2907,7 +2909,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_97 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2918,7 +2920,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_97 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2929,7 +2931,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_117 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2940,7 +2942,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_117 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2951,7 +2953,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_137 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2962,7 +2964,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_137 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2973,7 +2975,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_157 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -2984,7 +2986,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_157 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -2995,7 +2997,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_177 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3006,7 +3008,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_177 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3017,7 +3019,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_197 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3028,7 +3030,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_197 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3039,7 +3041,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_217 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3050,7 +3052,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_217 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3061,7 +3063,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_237 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3072,7 +3074,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_237 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3083,7 +3085,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_257 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3094,7 +3096,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_257 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3105,7 +3107,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_277 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3116,7 +3118,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_277 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3127,7 +3129,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_297 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3138,7 +3140,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_297 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3149,7 +3151,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_317 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3160,7 +3162,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_317 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3171,7 +3173,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_337 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3182,7 +3184,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_337 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3193,7 +3195,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_357 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3204,7 +3206,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_357 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3215,7 +3217,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_377 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3226,7 +3228,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_377 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3237,7 +3239,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_397 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3248,7 +3250,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_397 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3259,7 +3261,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_417 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3270,7 +3272,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_417 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3281,7 +3283,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_437 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3292,7 +3294,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_437 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3303,7 +3305,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_457 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3314,7 +3316,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_457 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3325,7 +3327,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_477 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3336,7 +3338,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_477 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3347,7 +3349,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_497 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3358,7 +3360,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_497 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3369,7 +3371,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_517 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3380,7 +3382,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_517 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3391,7 +3393,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_537 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3402,7 +3404,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_537 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3413,7 +3415,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_557 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3424,7 +3426,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_557 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3435,7 +3437,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_577 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3446,7 +3448,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_577 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3457,7 +3459,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_597 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3468,7 +3470,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_597 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3479,7 +3481,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(_T_617 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 163:11]
+ $fatal; // @[Regfile.scala 164:11]
end
`ifdef STOP_COND
end
@@ -3490,7 +3492,7 @@
if (`PRINTF_COND) begin
`endif
if (~reset & ~(_T_617 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
end
`ifdef PRINTF_COND
end
@@ -3501,7 +3503,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3512,7 +3514,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3523,7 +3525,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_1)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3534,7 +3536,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3545,7 +3547,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_2)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3556,7 +3558,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_2)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3567,7 +3569,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_3)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3578,7 +3580,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3589,7 +3591,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_4)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3600,7 +3602,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3611,7 +3613,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_5)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3622,7 +3624,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_5)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3633,7 +3635,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_6)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3644,7 +3646,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_6)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3655,7 +3657,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_7)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3666,7 +3668,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_7)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3677,7 +3679,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_8)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3688,7 +3690,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3699,7 +3701,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_9)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3710,7 +3712,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_9)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3721,7 +3723,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_10)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3732,7 +3734,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_10)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3743,7 +3745,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_11)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3754,7 +3756,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_11)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3765,7 +3767,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_12)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3776,7 +3778,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_12)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3787,7 +3789,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_13)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3798,7 +3800,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_13)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3809,7 +3811,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~write_fail_14)) begin
- $fatal; // @[Regfile.scala 242:13]
+ $fatal; // @[Regfile.scala 243:13]
end
`ifdef STOP_COND
end
@@ -3820,7 +3822,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~write_fail_14)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
end
`ifdef PRINTF_COND
end
@@ -3831,7 +3833,7 @@
if (`STOP_COND) begin
`endif
if (_T_21 & ~(~scoreboard_error)) begin
- $fatal; // @[Regfile.scala 248:9]
+ $fatal; // @[Regfile.scala 249:9]
end
`ifdef STOP_COND
end
@@ -3842,7 +3844,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_21 & ~(~scoreboard_error)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:248 assert(!scoreboard_error)\n"); // @[Regfile.scala 248:9]
+ $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:249 assert(!scoreboard_error)\n"); // @[Regfile.scala 249:9]
end
`ifdef PRINTF_COND
end
@@ -3857,168 +3859,168 @@
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_0 <= 1'h0;
end else begin
readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_1 <= 1'h0;
end else begin
readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_2 <= 1'h0;
end else begin
readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_3 <= 1'h0;
end else begin
readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_4 <= 1'h0;
end else begin
readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_5 <= 1'h0;
end else begin
readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_6 <= 1'h0;
end else begin
readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 190:49]
+ if (reset) begin // @[Regfile.scala 191:49]
readDataReady_7 <= 1'h0;
end else begin
readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail <= 1'h0;
end else begin
write_fail <= _write_fail_T_2 & _write_fail_T_3;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_1 <= 1'h0;
end else begin
write_fail_1 <= _write_fail_T_7 & _write_fail_T_3;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_2 <= 1'h0;
end else begin
write_fail_2 <= _write_fail_T_12 & _write_fail_T_3;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_3 <= 1'h0;
end else begin
write_fail_3 <= _write_fail_T_17 & _write_fail_T_3;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_4 <= 1'h0;
end else begin
write_fail_4 <= _write_fail_T_22 & _write_fail_T_3;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_5 <= 1'h0;
end else begin
write_fail_5 <= _write_fail_T_27 & _write_fail_T_28;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_6 <= 1'h0;
end else begin
write_fail_6 <= _write_fail_T_32 & _write_fail_T_28;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_7 <= 1'h0;
end else begin
write_fail_7 <= _write_fail_T_37 & _write_fail_T_28;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_8 <= 1'h0;
end else begin
write_fail_8 <= _write_fail_T_42 & _write_fail_T_28;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_9 <= 1'h0;
end else begin
write_fail_9 <= _write_fail_T_47 & _write_fail_T_48;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_10 <= 1'h0;
end else begin
write_fail_10 <= _write_fail_T_52 & _write_fail_T_48;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_11 <= 1'h0;
end else begin
write_fail_11 <= _write_fail_T_57 & _write_fail_T_48;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_12 <= 1'h0;
end else begin
write_fail_12 <= _write_fail_T_62 & _write_fail_T_63;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_13 <= 1'h0;
end else begin
write_fail_13 <= _write_fail_T_67 & _write_fail_T_63;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 240:67]
+ if (reset) begin // @[Regfile.scala 241:67]
write_fail_14 <= 1'h0;
end else begin
write_fail_14 <= _write_fail_T_72 & _write_fail_T_73;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 247:53]
+ if (reset) begin // @[Regfile.scala 248:53]
scoreboard_error <= 1'h0;
end else begin
scoreboard_error <= _scoreboard_error_T != scoreboard_clr;
@@ -30284,6 +30286,7 @@
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
wire regfile_clock; // @[Regfile.scala 9:18]
wire regfile_reset; // @[Regfile.scala 9:18]
@@ -30388,6 +30391,7 @@
wire regfile_io_writeMask_1_valid; // @[Regfile.scala 9:18]
wire regfile_io_writeMask_2_valid; // @[Regfile.scala 9:18]
wire regfile_io_writeMask_3_valid; // @[Regfile.scala 9:18]
+ wire regfile_io_writeMask_4_valid; // @[Regfile.scala 9:18]
wire [31:0] regfile_io_scoreboard_regd; // @[Regfile.scala 9:18]
wire [31:0] regfile_io_scoreboard_comb; // @[Regfile.scala 9:18]
wire fetch_clock; // @[Fetch.scala 9:18]
@@ -31022,91 +31026,92 @@
wire [4:0] fwriteMask_shiftAmount = decode_0_io_fpu_waddr; // @[OneHot.scala 63:49]
wire [31:0] _fwriteMask_T = 32'h1 << fwriteMask_shiftAmount; // @[OneHot.scala 64:12]
wire [31:0] fwriteMask = decode_0_io_fpu_valid ? _fwriteMask_T : 32'h0; // @[Library.scala 8:8]
- wire _regfile_io_writeData_0_valid_T_2 = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 259:74]
+ reg mluInvalidate; // @[SCore.scala 226:30]
+ wire _regfile_io_writeData_0_valid_T_2 = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 263:74]
wire [4:0] _regfile_io_writeData_0_addr_T = csr_io_rd_valid ? csr_io_rd_addr : 5'h0; // @[Library.scala 8:8]
wire [4:0] _regfile_io_writeData_0_addr_T_5 = alu_0_io_rd_valid ? alu_0_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_0_addr_T_6 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 266:36]
+ wire [4:0] _regfile_io_writeData_0_addr_T_6 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 270:36]
wire [4:0] _regfile_io_writeData_0_addr_T_7 = bru_0_io_rd_valid ? bru_0_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_0_addr_T_8 = _regfile_io_writeData_0_addr_T_6 | _regfile_io_writeData_0_addr_T_7; // @[SCore.scala 267:54]
+ wire [4:0] _regfile_io_writeData_0_addr_T_8 = _regfile_io_writeData_0_addr_T_6 | _regfile_io_writeData_0_addr_T_7; // @[SCore.scala 271:54]
wire [4:0] _regfile_io_writeData_0_addr_T_9 = io_vcore_rd_0_valid ? io_vcore_rd_0_addr : 5'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_0_data_T = csr_io_rd_valid ? csr_io_rd_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_0_data_T_5 = alu_0_io_rd_valid ? alu_0_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_0_data_T_6 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 274:36]
+ wire [31:0] _regfile_io_writeData_0_data_T_6 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 278:36]
wire [31:0] _regfile_io_writeData_0_data_T_7 = bru_0_io_rd_valid ? bru_0_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_0_data_T_8 = _regfile_io_writeData_0_data_T_6 | _regfile_io_writeData_0_data_T_7; // @[SCore.scala 275:54]
+ wire [31:0] _regfile_io_writeData_0_data_T_8 = _regfile_io_writeData_0_data_T_6 | _regfile_io_writeData_0_data_T_7; // @[SCore.scala 279:54]
wire [31:0] _regfile_io_writeData_0_data_T_9 = io_vcore_rd_0_valid ? io_vcore_rd_0_data : 32'h0; // @[Library.scala 8:8]
- wire [1:0] _T_15 = {{1'd0}, csr_io_rd_valid}; // @[SCore.scala 279:23]
- wire [2:0] _T_16 = {{1'd0}, _T_15}; // @[SCore.scala 279:36]
- wire [2:0] _GEN_3 = {{2'd0}, alu_0_io_rd_valid}; // @[SCore.scala 279:49]
- wire [3:0] _T_17 = _T_16 + _GEN_3; // @[SCore.scala 279:49]
- wire [3:0] _GEN_4 = {{3'd0}, bru_0_io_rd_valid}; // @[SCore.scala 280:32]
- wire [4:0] _T_18 = _T_17 + _GEN_4; // @[SCore.scala 280:32]
- wire [4:0] _GEN_5 = {{4'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 280:54]
- wire [5:0] _T_19 = _T_18 + _GEN_5; // @[SCore.scala 280:54]
- wire _T_20 = _T_19 <= 6'h1; // @[SCore.scala 281:35]
- wire _regfile_io_writeData_1_valid_T_2 = alu_1_io_rd_valid; // @[SCore.scala 259:74]
+ wire [1:0] _T_15 = {{1'd0}, csr_io_rd_valid}; // @[SCore.scala 283:23]
+ wire [2:0] _T_16 = {{1'd0}, _T_15}; // @[SCore.scala 283:36]
+ wire [2:0] _GEN_3 = {{2'd0}, alu_0_io_rd_valid}; // @[SCore.scala 283:49]
+ wire [3:0] _T_17 = _T_16 + _GEN_3; // @[SCore.scala 283:49]
+ wire [3:0] _GEN_4 = {{3'd0}, bru_0_io_rd_valid}; // @[SCore.scala 284:32]
+ wire [4:0] _T_18 = _T_17 + _GEN_4; // @[SCore.scala 284:32]
+ wire [4:0] _GEN_5 = {{4'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 284:54]
+ wire [5:0] _T_19 = _T_18 + _GEN_5; // @[SCore.scala 284:54]
+ wire _T_20 = _T_19 <= 6'h1; // @[SCore.scala 285:35]
+ wire _regfile_io_writeData_1_valid_T_2 = alu_1_io_rd_valid; // @[SCore.scala 263:74]
wire [4:0] _regfile_io_writeData_1_addr_T_5 = alu_1_io_rd_valid ? alu_1_io_rd_addr : 5'h0; // @[Library.scala 8:8]
wire [4:0] _regfile_io_writeData_1_addr_T_7 = bru_1_io_rd_valid ? bru_1_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_1_addr_T_8 = _regfile_io_writeData_1_addr_T_5 | _regfile_io_writeData_1_addr_T_7; // @[SCore.scala 267:54]
+ wire [4:0] _regfile_io_writeData_1_addr_T_8 = _regfile_io_writeData_1_addr_T_5 | _regfile_io_writeData_1_addr_T_7; // @[SCore.scala 271:54]
wire [4:0] _regfile_io_writeData_1_addr_T_9 = io_vcore_rd_1_valid ? io_vcore_rd_1_addr : 5'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_1_data_T_5 = alu_1_io_rd_valid ? alu_1_io_rd_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_1_data_T_7 = bru_1_io_rd_valid ? bru_1_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_1_data_T_8 = _regfile_io_writeData_1_data_T_5 | _regfile_io_writeData_1_data_T_7; // @[SCore.scala 275:54]
+ wire [31:0] _regfile_io_writeData_1_data_T_8 = _regfile_io_writeData_1_data_T_5 | _regfile_io_writeData_1_data_T_7; // @[SCore.scala 279:54]
wire [31:0] _regfile_io_writeData_1_data_T_9 = io_vcore_rd_1_valid ? io_vcore_rd_1_data : 32'h0; // @[Library.scala 8:8]
- wire [2:0] _GEN_6 = {{2'd0}, alu_1_io_rd_valid}; // @[SCore.scala 279:49]
- wire [3:0] _T_26 = {{1'd0}, _GEN_6}; // @[SCore.scala 279:49]
- wire [3:0] _GEN_7 = {{3'd0}, bru_1_io_rd_valid}; // @[SCore.scala 280:32]
- wire [4:0] _T_27 = _T_26 + _GEN_7; // @[SCore.scala 280:32]
- wire [4:0] _GEN_8 = {{4'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 280:54]
- wire [5:0] _T_28 = _T_27 + _GEN_8; // @[SCore.scala 280:54]
- wire _T_29 = _T_28 <= 6'h1; // @[SCore.scala 281:35]
- wire _regfile_io_writeData_2_valid_T_2 = fpu_io_writeData_1_valid | alu_2_io_rd_valid; // @[SCore.scala 259:74]
+ wire [2:0] _GEN_6 = {{2'd0}, alu_1_io_rd_valid}; // @[SCore.scala 283:49]
+ wire [3:0] _T_26 = {{1'd0}, _GEN_6}; // @[SCore.scala 283:49]
+ wire [3:0] _GEN_7 = {{3'd0}, bru_1_io_rd_valid}; // @[SCore.scala 284:32]
+ wire [4:0] _T_27 = _T_26 + _GEN_7; // @[SCore.scala 284:32]
+ wire [4:0] _GEN_8 = {{4'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 284:54]
+ wire [5:0] _T_28 = _T_27 + _GEN_8; // @[SCore.scala 284:54]
+ wire _T_29 = _T_28 <= 6'h1; // @[SCore.scala 285:35]
+ wire _regfile_io_writeData_2_valid_T_2 = fpu_io_writeData_1_valid | alu_2_io_rd_valid; // @[SCore.scala 263:74]
wire [4:0] _regfile_io_writeData_2_addr_T_3 = fpu_io_writeData_1_valid ? fpu_io_writeData_1_addr : 5'h0; // @[Library.scala 8:8]
wire [4:0] _regfile_io_writeData_2_addr_T_5 = alu_2_io_rd_valid ? alu_2_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_2_addr_T_6 = _regfile_io_writeData_2_addr_T_3 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 266:36]
+ wire [4:0] _regfile_io_writeData_2_addr_T_6 = _regfile_io_writeData_2_addr_T_3 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 270:36]
wire [4:0] _regfile_io_writeData_2_addr_T_7 = bru_2_io_rd_valid ? bru_2_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_2_addr_T_8 = _regfile_io_writeData_2_addr_T_6 | _regfile_io_writeData_2_addr_T_7; // @[SCore.scala 267:54]
+ wire [4:0] _regfile_io_writeData_2_addr_T_8 = _regfile_io_writeData_2_addr_T_6 | _regfile_io_writeData_2_addr_T_7; // @[SCore.scala 271:54]
wire [4:0] _regfile_io_writeData_2_addr_T_9 = io_vcore_rd_2_valid ? io_vcore_rd_2_addr : 5'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_2_data_T_3 = fpu_io_writeData_1_valid ? fpu_io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_2_data_T_5 = alu_2_io_rd_valid ? alu_2_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_2_data_T_6 = _regfile_io_writeData_2_data_T_3 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 274:36]
+ wire [31:0] _regfile_io_writeData_2_data_T_6 = _regfile_io_writeData_2_data_T_3 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 278:36]
wire [31:0] _regfile_io_writeData_2_data_T_7 = bru_2_io_rd_valid ? bru_2_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_2_data_T_8 = _regfile_io_writeData_2_data_T_6 | _regfile_io_writeData_2_data_T_7; // @[SCore.scala 275:54]
+ wire [31:0] _regfile_io_writeData_2_data_T_8 = _regfile_io_writeData_2_data_T_6 | _regfile_io_writeData_2_data_T_7; // @[SCore.scala 279:54]
wire [31:0] _regfile_io_writeData_2_data_T_9 = io_vcore_rd_2_valid ? io_vcore_rd_2_data : 32'h0; // @[Library.scala 8:8]
- wire [1:0] _GEN_9 = {{1'd0}, fpu_io_writeData_1_valid}; // @[SCore.scala 279:36]
- wire [2:0] _T_34 = {{1'd0}, _GEN_9}; // @[SCore.scala 279:36]
- wire [2:0] _GEN_10 = {{2'd0}, alu_2_io_rd_valid}; // @[SCore.scala 279:49]
- wire [3:0] _T_35 = _T_34 + _GEN_10; // @[SCore.scala 279:49]
- wire [3:0] _GEN_11 = {{3'd0}, bru_2_io_rd_valid}; // @[SCore.scala 280:32]
- wire [4:0] _T_36 = _T_35 + _GEN_11; // @[SCore.scala 280:32]
- wire [4:0] _GEN_12 = {{4'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 280:54]
- wire [5:0] _T_37 = _T_36 + _GEN_12; // @[SCore.scala 280:54]
- wire _T_38 = _T_37 <= 6'h1; // @[SCore.scala 281:35]
- wire _regfile_io_writeData_3_valid_T_2 = fpu_io_writeData_0_valid | alu_3_io_rd_valid; // @[SCore.scala 259:74]
+ wire [1:0] _GEN_9 = {{1'd0}, fpu_io_writeData_1_valid}; // @[SCore.scala 283:36]
+ wire [2:0] _T_34 = {{1'd0}, _GEN_9}; // @[SCore.scala 283:36]
+ wire [2:0] _GEN_10 = {{2'd0}, alu_2_io_rd_valid}; // @[SCore.scala 283:49]
+ wire [3:0] _T_35 = _T_34 + _GEN_10; // @[SCore.scala 283:49]
+ wire [3:0] _GEN_11 = {{3'd0}, bru_2_io_rd_valid}; // @[SCore.scala 284:32]
+ wire [4:0] _T_36 = _T_35 + _GEN_11; // @[SCore.scala 284:32]
+ wire [4:0] _GEN_12 = {{4'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 284:54]
+ wire [5:0] _T_37 = _T_36 + _GEN_12; // @[SCore.scala 284:54]
+ wire _T_38 = _T_37 <= 6'h1; // @[SCore.scala 285:35]
+ wire _regfile_io_writeData_3_valid_T_2 = fpu_io_writeData_0_valid | alu_3_io_rd_valid; // @[SCore.scala 263:74]
wire [4:0] _regfile_io_writeData_3_addr_T_1 = fpu_io_writeData_0_valid ? fpu_io_writeData_0_addr : 5'h0; // @[Library.scala 8:8]
wire [4:0] _regfile_io_writeData_3_addr_T_5 = alu_3_io_rd_valid ? alu_3_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_3_addr_T_6 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 266:36]
+ wire [4:0] _regfile_io_writeData_3_addr_T_6 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 270:36]
wire [4:0] _regfile_io_writeData_3_addr_T_7 = bru_3_io_rd_valid ? bru_3_io_rd_addr : 5'h0; // @[Library.scala 8:8]
- wire [4:0] _regfile_io_writeData_3_addr_T_8 = _regfile_io_writeData_3_addr_T_6 | _regfile_io_writeData_3_addr_T_7; // @[SCore.scala 267:54]
+ wire [4:0] _regfile_io_writeData_3_addr_T_8 = _regfile_io_writeData_3_addr_T_6 | _regfile_io_writeData_3_addr_T_7; // @[SCore.scala 271:54]
wire [4:0] _regfile_io_writeData_3_addr_T_9 = io_vcore_rd_3_valid ? io_vcore_rd_3_addr : 5'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_3_data_T_1 = fpu_io_writeData_0_valid ? fpu_io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
wire [31:0] _regfile_io_writeData_3_data_T_5 = alu_3_io_rd_valid ? alu_3_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_3_data_T_6 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 274:36]
+ wire [31:0] _regfile_io_writeData_3_data_T_6 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 278:36]
wire [31:0] _regfile_io_writeData_3_data_T_7 = bru_3_io_rd_valid ? bru_3_io_rd_data : 32'h0; // @[Library.scala 8:8]
- wire [31:0] _regfile_io_writeData_3_data_T_8 = _regfile_io_writeData_3_data_T_6 | _regfile_io_writeData_3_data_T_7; // @[SCore.scala 275:54]
+ wire [31:0] _regfile_io_writeData_3_data_T_8 = _regfile_io_writeData_3_data_T_6 | _regfile_io_writeData_3_data_T_7; // @[SCore.scala 279:54]
wire [31:0] _regfile_io_writeData_3_data_T_9 = io_vcore_rd_3_valid ? io_vcore_rd_3_data : 32'h0; // @[Library.scala 8:8]
- wire [1:0] _T_42 = {{1'd0}, fpu_io_writeData_0_valid}; // @[SCore.scala 279:23]
- wire [2:0] _T_43 = {{1'd0}, _T_42}; // @[SCore.scala 279:36]
- wire [2:0] _GEN_13 = {{2'd0}, alu_3_io_rd_valid}; // @[SCore.scala 279:49]
- wire [3:0] _T_44 = _T_43 + _GEN_13; // @[SCore.scala 279:49]
- wire [3:0] _GEN_14 = {{3'd0}, bru_3_io_rd_valid}; // @[SCore.scala 280:32]
- wire [4:0] _T_45 = _T_44 + _GEN_14; // @[SCore.scala 280:32]
- wire [4:0] _GEN_15 = {{4'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 280:54]
- wire [5:0] _T_46 = _T_45 + _GEN_15; // @[SCore.scala 280:54]
- wire _T_47 = _T_46 <= 6'h1; // @[SCore.scala 281:35]
- reg slogValid; // @[SCore.scala 344:26]
- reg [1:0] slogAddr; // @[SCore.scala 345:21]
- wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 349:17 350:14 345:21]
+ wire [1:0] _T_42 = {{1'd0}, fpu_io_writeData_0_valid}; // @[SCore.scala 283:23]
+ wire [2:0] _T_43 = {{1'd0}, _T_42}; // @[SCore.scala 283:36]
+ wire [2:0] _GEN_13 = {{2'd0}, alu_3_io_rd_valid}; // @[SCore.scala 283:49]
+ wire [3:0] _T_44 = _T_43 + _GEN_13; // @[SCore.scala 283:49]
+ wire [3:0] _GEN_14 = {{3'd0}, bru_3_io_rd_valid}; // @[SCore.scala 284:32]
+ wire [4:0] _T_45 = _T_44 + _GEN_14; // @[SCore.scala 284:32]
+ wire [4:0] _GEN_15 = {{4'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 284:54]
+ wire [5:0] _T_46 = _T_45 + _GEN_15; // @[SCore.scala 284:54]
+ wire _T_47 = _T_46 <= 6'h1; // @[SCore.scala 285:35]
+ reg slogValid; // @[SCore.scala 349:26]
+ reg [1:0] slogAddr; // @[SCore.scala 350:21]
+ wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 354:17 355:14 350:21]
wire [1:0] _io_slog_addr_T = slogValid ? slogAddr : 2'h0; // @[Library.scala 8:8]
Regfile regfile ( // @[Regfile.scala 9:18]
.clock(regfile_clock),
@@ -31212,6 +31217,7 @@
.io_writeMask_1_valid(regfile_io_writeMask_1_valid),
.io_writeMask_2_valid(regfile_io_writeMask_2_valid),
.io_writeMask_3_valid(regfile_io_writeMask_3_valid),
+ .io_writeMask_4_valid(regfile_io_writeMask_4_valid),
.io_scoreboard_regd(regfile_io_scoreboard_regd),
.io_scoreboard_comb(regfile_io_scoreboard_comb)
);
@@ -31867,133 +31873,134 @@
);
assign io_halted = csr_io_halted; // @[SCore.scala 194:13]
assign io_fault = csr_io_fault; // @[SCore.scala 195:13]
- assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 333:11]
- assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 333:11]
- assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 337:11]
- assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 337:11]
- assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 337:11]
- assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 337:11]
- assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 337:11]
- assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 337:11]
- assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 337:11]
- assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 338:11]
- assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 338:11]
- assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 338:11]
- assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 338:11]
- assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 338:11]
- assign io_vldst = lsu_io_vldst; // @[SCore.scala 340:12]
- assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 320:23]
- assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 320:23]
- assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 320:23]
- assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 320:23]
- assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 320:23]
- assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 320:23]
- assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 320:23]
- assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 320:23]
- assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 320:23]
- assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 320:23]
- assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 320:23]
- assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 320:23]
- assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 320:23]
- assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 320:23]
- assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 320:23]
- assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 320:23]
- assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 324:20]
- assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 324:20]
- assign io_vcore_fs_0_data = fpu_io_fs_0_data; // @[SCore.scala 328:20]
- assign io_vcore_fs_1_data = fpu_io_fs_1_data; // @[SCore.scala 328:20]
- assign io_vcore_fs_2_data = fpu_io_fs_2_data; // @[SCore.scala 328:20]
- assign io_vcore_fs_3_data = fpu_io_fs_3_data; // @[SCore.scala 328:20]
+ assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 338:11]
+ assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 338:11]
+ assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 342:11]
+ assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 342:11]
+ assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 342:11]
+ assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 342:11]
+ assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 342:11]
+ assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 342:11]
+ assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 342:11]
+ assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 343:11]
+ assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 343:11]
+ assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 343:11]
+ assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 343:11]
+ assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 343:11]
+ assign io_vldst = lsu_io_vldst; // @[SCore.scala 345:12]
+ assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 325:23]
+ assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 325:23]
+ assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 329:20]
+ assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 329:20]
+ assign io_vcore_fs_0_data = fpu_io_fs_0_data; // @[SCore.scala 333:20]
+ assign io_vcore_fs_1_data = fpu_io_fs_1_data; // @[SCore.scala 333:20]
+ assign io_vcore_fs_2_data = fpu_io_fs_2_data; // @[SCore.scala 333:20]
+ assign io_vcore_fs_3_data = fpu_io_fs_3_data; // @[SCore.scala 333:20]
assign io_iflush_valid = iflush; // @[SCore.scala 181:19]
assign io_dflush_valid = lsu_io_flush_valid; // @[SCore.scala 60:19]
assign io_dflush_all = lsu_io_flush_all; // @[SCore.scala 61:19]
- assign io_slog_valid = slogValid; // @[SCore.scala 353:17]
- assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 354:17]
+ assign io_slog_valid = slogValid; // @[SCore.scala 358:17]
+ assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 359:17]
assign io_slog_data = slogValid ? regfile_io_readData_0_data : 32'h0; // @[Library.scala 8:8]
assign regfile_clock = clock;
assign regfile_reset = reset;
- assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 240:36]
- assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 241:36]
- assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 241:36]
- assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 242:35]
- assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 242:35]
- assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 243:35]
- assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 243:35]
- assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 242:35]
- assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 242:35]
- assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 243:35]
- assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 243:35]
- assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 242:35]
- assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 242:35]
- assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 243:35]
- assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 243:35]
- assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 242:35]
- assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 242:35]
- assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 243:35]
- assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 243:35]
- assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 244:29]
- assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 244:29]
- assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 245:27]
- assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 245:27]
- assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T_2 | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 260:79]
- assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_8 | _regfile_io_writeData_0_addr_T_9; // @[SCore.scala 268:54]
- assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_8 | _regfile_io_writeData_0_data_T_9; // @[SCore.scala 276:54]
- assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T_2 | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 260:79]
- assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_8 | _regfile_io_writeData_1_addr_T_9; // @[SCore.scala 268:54]
- assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_8 | _regfile_io_writeData_1_data_T_9; // @[SCore.scala 276:54]
- assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T_2 | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 260:79]
- assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_8 | _regfile_io_writeData_2_addr_T_9; // @[SCore.scala 268:54]
- assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_8 | _regfile_io_writeData_2_data_T_9; // @[SCore.scala 276:54]
- assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T_2 | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 260:79]
- assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_8 | _regfile_io_writeData_3_addr_T_9; // @[SCore.scala 268:54]
- assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_8 | _regfile_io_writeData_3_data_T_9; // @[SCore.scala 276:54]
- assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 284:52]
- assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 285:38]
- assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 286:38]
- assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 289:33]
- assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 290:33]
- assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 291:33]
- assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 293:33]
- assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 294:66]
- assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 296:66]
- assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 298:66]
+ assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 244:36]
+ assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 245:36]
+ assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 245:36]
+ assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 246:35]
+ assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 247:35]
+ assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 247:35]
+ assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 248:29]
+ assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 248:29]
+ assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 249:27]
+ assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 249:27]
+ assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T_2 | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 264:79]
+ assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_8 | _regfile_io_writeData_0_addr_T_9; // @[SCore.scala 272:54]
+ assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_8 | _regfile_io_writeData_0_data_T_9; // @[SCore.scala 280:54]
+ assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T_2 | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 264:79]
+ assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_8 | _regfile_io_writeData_1_addr_T_9; // @[SCore.scala 272:54]
+ assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_8 | _regfile_io_writeData_1_data_T_9; // @[SCore.scala 280:54]
+ assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T_2 | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 264:79]
+ assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_8 | _regfile_io_writeData_2_addr_T_9; // @[SCore.scala 272:54]
+ assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_8 | _regfile_io_writeData_2_data_T_9; // @[SCore.scala 280:54]
+ assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T_2 | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 264:79]
+ assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_8 | _regfile_io_writeData_3_addr_T_9; // @[SCore.scala 272:54]
+ assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_8 | _regfile_io_writeData_3_data_T_9; // @[SCore.scala 280:54]
+ assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 288:52]
+ assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 289:38]
+ assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 290:38]
+ assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 293:33]
+ assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 294:33]
+ assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 295:33]
+ assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 297:33]
+ assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 298:66]
+ assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 300:66]
+ assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 302:66]
+ assign regfile_io_writeMask_4_valid = mluInvalidate; // @[SCore.scala 304:33]
assign fetch_clock = clock;
assign fetch_reset = reset;
assign fetch_io_csr_value_0 = io_csr_in_value_0; // @[SCore.scala 71:16]
- assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 333:11]
- assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 333:11]
+ assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 338:11]
+ assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 338:11]
assign fetch_io_inst_lanes_0_ready = decode_0_io_inst_ready; // @[SCore.scala 91:61]
assign fetch_io_inst_lanes_1_ready = decode_1_io_inst_ready & decode_0_io_inst_ready; // @[SCore.scala 91:61]
assign fetch_io_inst_lanes_2_ready = decode_2_io_inst_ready & mask_2; // @[SCore.scala 91:61]
@@ -32021,10 +32028,10 @@
assign decode_0_io_fscoreboard = fpu_io_fscoreboard; // @[SCore.scala 149:28]
assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 154:24]
assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 207:28]
- assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 227:14]
- assign decode_0_io_fpu_busyFDiv = fpu_io_req_0_busyFDiv; // @[SCore.scala 303:17]
- assign decode_0_io_fpu_busyFSqrt = fpu_io_req_0_busyFSqrt; // @[SCore.scala 303:17]
- assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 320:23]
+ assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 231:14]
+ assign decode_0_io_fpu_busyFDiv = fpu_io_req_0_busyFDiv; // @[SCore.scala 308:17]
+ assign decode_0_io_fpu_busyFSqrt = fpu_io_req_0_busyFSqrt; // @[SCore.scala 308:17]
+ assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 325:23]
assign decode_0_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 119:26]
assign decode_1_clock = clock;
@@ -32038,7 +32045,7 @@
assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 140:62]
assign decode_1_io_fscoreboard = fpu_io_fscoreboard | fwriteMask; // @[SCore.scala 150:50]
assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 207:28]
- assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 320:23]
+ assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 325:23]
assign decode_1_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 120:44]
assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 126:28]
@@ -32055,7 +32062,7 @@
assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 142:62]
assign decode_2_io_fscoreboard = fpu_io_fscoreboard | fwriteMask; // @[SCore.scala 151:50]
assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 207:28]
- assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 320:23]
+ assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 325:23]
assign decode_2_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
assign decode_2_io_interlock = interlockPipe2 | decode_1_io_interlock; // @[SCore.scala 121:44]
assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 127:28]
@@ -32072,7 +32079,7 @@
assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 144:62]
assign decode_3_io_fscoreboard = fpu_io_fscoreboard | fwriteMask; // @[SCore.scala 152:50]
assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 207:28]
- assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 320:23]
+ assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 325:23]
assign decode_3_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
assign decode_3_io_interlock = interlockPipe3 | decode_2_io_interlock; // @[SCore.scala 122:44]
assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 128:28]
@@ -32221,11 +32228,11 @@
assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 199:18]
assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 199:18]
assign lsu_io_fbusPort_data = fpu_io_fbusPort_data; // @[SCore.scala 200:19]
- assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 337:11]
- assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 337:11]
+ assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 342:11]
+ assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 342:11]
assign lsu_io_flush_ready = io_dflush_ready; // @[SCore.scala 63:22]
- assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 338:11]
- assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 338:11]
+ assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 343:11]
+ assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 343:11]
assign mlu_clock = clock;
assign mlu_reset = reset;
assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 212:17]
@@ -32258,30 +32265,30 @@
assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 223:17]
assign dvu_clock = clock;
assign dvu_reset = reset;
- assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 227:14]
- assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 227:14]
- assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 227:14]
- assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 228:14]
- assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 229:14]
- assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 230:22]
+ assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 231:14]
+ assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 231:14]
+ assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 231:14]
+ assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 232:14]
+ assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 233:14]
+ assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 234:22]
assign fpu_clock = clock;
assign fpu_reset = reset;
- assign fpu_io_req_0_valid = decode_0_io_fpu_valid; // @[SCore.scala 303:17]
- assign fpu_io_req_0_raddr_0 = decode_0_io_fpu_raddr_0; // @[SCore.scala 303:17]
- assign fpu_io_req_0_raddr_1 = decode_0_io_fpu_raddr_1; // @[SCore.scala 303:17]
- assign fpu_io_req_0_raddr_2 = decode_0_io_fpu_raddr_2; // @[SCore.scala 303:17]
- assign fpu_io_req_0_waddr = decode_0_io_fpu_waddr; // @[SCore.scala 303:17]
- assign fpu_io_req_0_op = decode_0_io_fpu_op; // @[SCore.scala 303:17]
- assign fpu_io_req_1_raddr_1 = decode_1_io_fpu_raddr_1; // @[SCore.scala 304:17]
- assign fpu_io_req_1_op = decode_1_io_fpu_op; // @[SCore.scala 304:17]
- assign fpu_io_req_2_raddr_1 = decode_2_io_fpu_raddr_1; // @[SCore.scala 305:17]
- assign fpu_io_req_2_op = decode_2_io_fpu_op; // @[SCore.scala 305:17]
- assign fpu_io_req_3_raddr_1 = decode_3_io_fpu_raddr_1; // @[SCore.scala 306:17]
- assign fpu_io_req_3_op = decode_3_io_fpu_op; // @[SCore.scala 306:17]
- assign fpu_io_fwriteData_valid = lsu_io_fd_valid; // @[SCore.scala 308:21]
- assign fpu_io_fwriteData_addr = lsu_io_fd_addr; // @[SCore.scala 308:21]
- assign fpu_io_fwriteData_data = lsu_io_fd_data; // @[SCore.scala 308:21]
- assign fpu_io_readData_data = regfile_io_readData_0_data; // @[SCore.scala 310:19]
+ assign fpu_io_req_0_valid = decode_0_io_fpu_valid; // @[SCore.scala 308:17]
+ assign fpu_io_req_0_raddr_0 = decode_0_io_fpu_raddr_0; // @[SCore.scala 308:17]
+ assign fpu_io_req_0_raddr_1 = decode_0_io_fpu_raddr_1; // @[SCore.scala 308:17]
+ assign fpu_io_req_0_raddr_2 = decode_0_io_fpu_raddr_2; // @[SCore.scala 308:17]
+ assign fpu_io_req_0_waddr = decode_0_io_fpu_waddr; // @[SCore.scala 308:17]
+ assign fpu_io_req_0_op = decode_0_io_fpu_op; // @[SCore.scala 308:17]
+ assign fpu_io_req_1_raddr_1 = decode_1_io_fpu_raddr_1; // @[SCore.scala 309:17]
+ assign fpu_io_req_1_op = decode_1_io_fpu_op; // @[SCore.scala 309:17]
+ assign fpu_io_req_2_raddr_1 = decode_2_io_fpu_raddr_1; // @[SCore.scala 310:17]
+ assign fpu_io_req_2_op = decode_2_io_fpu_op; // @[SCore.scala 310:17]
+ assign fpu_io_req_3_raddr_1 = decode_3_io_fpu_raddr_1; // @[SCore.scala 311:17]
+ assign fpu_io_req_3_op = decode_3_io_fpu_op; // @[SCore.scala 311:17]
+ assign fpu_io_fwriteData_valid = lsu_io_fd_valid; // @[SCore.scala 313:21]
+ assign fpu_io_fwriteData_addr = lsu_io_fd_addr; // @[SCore.scala 313:21]
+ assign fpu_io_fwriteData_data = lsu_io_fd_data; // @[SCore.scala 313:21]
+ assign fpu_io_readData_data = regfile_io_readData_0_data; // @[SCore.scala 315:19]
always @(posedge clock) begin
slogAddr <= _GEN_2[1:0];
`ifndef SYNTHESIS
@@ -32355,7 +32362,7 @@
if (`STOP_COND) begin
`endif
if (_T_5 & ~_T_20) begin
- $fatal; // @[SCore.scala 279:11]
+ $fatal; // @[SCore.scala 283:11]
end
`ifdef STOP_COND
end
@@ -32367,7 +32374,7 @@
`endif
if (_T_5 & ~_T_20) begin
$fwrite(32'h80000002,
- "Assertion failed\n at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+ "Assertion failed\n at SCore.scala:283 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 283:11]
end
`ifdef PRINTF_COND
end
@@ -32378,7 +32385,7 @@
if (`STOP_COND) begin
`endif
if (_T_5 & ~_T_29) begin
- $fatal; // @[SCore.scala 279:11]
+ $fatal; // @[SCore.scala 283:11]
end
`ifdef STOP_COND
end
@@ -32390,7 +32397,7 @@
`endif
if (_T_5 & ~_T_29) begin
$fwrite(32'h80000002,
- "Assertion failed\n at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+ "Assertion failed\n at SCore.scala:283 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 283:11]
end
`ifdef PRINTF_COND
end
@@ -32401,7 +32408,7 @@
if (`STOP_COND) begin
`endif
if (_T_5 & ~_T_38) begin
- $fatal; // @[SCore.scala 279:11]
+ $fatal; // @[SCore.scala 283:11]
end
`ifdef STOP_COND
end
@@ -32413,7 +32420,7 @@
`endif
if (_T_5 & ~_T_38) begin
$fwrite(32'h80000002,
- "Assertion failed\n at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+ "Assertion failed\n at SCore.scala:283 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 283:11]
end
`ifdef PRINTF_COND
end
@@ -32424,7 +32431,7 @@
if (`STOP_COND) begin
`endif
if (_T_5 & ~_T_47) begin
- $fatal; // @[SCore.scala 279:11]
+ $fatal; // @[SCore.scala 283:11]
end
`ifdef STOP_COND
end
@@ -32436,7 +32443,7 @@
`endif
if (_T_5 & ~_T_47) begin
$fwrite(32'h80000002,
- "Assertion failed\n at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+ "Assertion failed\n at SCore.scala:283 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 283:11]
end
`ifdef PRINTF_COND
end
@@ -32447,7 +32454,7 @@
if (`STOP_COND) begin
`endif
if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin
- $fatal; // @[SCore.scala 287:9]
+ $fatal; // @[SCore.scala 291:9]
end
`ifdef STOP_COND
end
@@ -32459,8 +32466,8 @@
`endif
if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at SCore.scala:287 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n"
- ); // @[SCore.scala 287:9]
+ "Assertion failed\n at SCore.scala:291 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n"
+ ); // @[SCore.scala 291:9]
end
`ifdef PRINTF_COND
end
@@ -32489,10 +32496,17 @@
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[SCore.scala 344:26]
- slogValid <= 1'h0; // @[SCore.scala 344:26]
+ if (reset) begin // @[SCore.scala 47:43]
+ mluInvalidate <= 1'h0;
end else begin
- slogValid <= decode_0_io_slog; // @[SCore.scala 348:13]
+ mluInvalidate <= _branchTaken_T_1 | bru_3_io_taken_valid;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[SCore.scala 349:26]
+ slogValid <= 1'h0; // @[SCore.scala 349:26]
+ end else begin
+ slogValid <= decode_0_io_slog; // @[SCore.scala 353:13]
end
end
// Register and memory initialization
@@ -32538,9 +32552,11 @@
_RAND_2 = {1{`RANDOM}};
interlockPipe3 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
- slogValid = _RAND_3[0:0];
+ mluInvalidate = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
- slogAddr = _RAND_4[1:0];
+ slogValid = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ slogAddr = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
iflush = 1'h0;
@@ -32552,6 +32568,9 @@
interlockPipe3 = 1'h0;
end
if (reset) begin
+ mluInvalidate = 1'h0;
+ end
+ if (reset) begin
slogValid = 1'h0;
end
`endif // RANDOMIZE
@@ -50704,28 +50723,28 @@
reg value_tin_cmdsync; // @[VCmdq.scala 37:18]
reg value_m; // @[VCmdq.scala 37:18]
reg [4:0] step; // @[VCmdq.scala 42:21]
- wire vevnodd = value_tin_op == 7'h5d | value_tin_op == 7'h5e | value_tin_op == 7'h5f; // @[VAlu.scala 221:60]
- wire vzip = value_tin_op == 7'h60; // @[VAlu.scala 222:22]
- wire _last_T = ~value_m; // @[VAlu.scala 224:16]
- wire last = ~value_m | step == 5'h3; // @[VAlu.scala 224:19]
- wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 226:31]
- wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 227:31]
- wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 228:31]
- wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 229:31]
- wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 230:31]
- wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 234:35]
- wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 237:35]
- wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 238:35]
- wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 233:27 234:21 237:21]
- wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 233:27 235:21 238:21]
- wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 230:17 231:25 232:19]
- wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 228:17 231:25]
- wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 229:17 231:25]
- wire _T_6 = ~reset; // @[VAlu.scala 242:13]
- wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 243:33]
- wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 244:33]
- wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 226:17 241:17 243:19]
- wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 227:17 241:17 244:19]
+ wire vevnodd = value_tin_op == 7'h5d | value_tin_op == 7'h5e | value_tin_op == 7'h5f; // @[VAlu.scala 201:60]
+ wire vzip = value_tin_op == 7'h60; // @[VAlu.scala 202:22]
+ wire _last_T = ~value_m; // @[VAlu.scala 204:16]
+ wire last = ~value_m | step == 5'h3; // @[VAlu.scala 204:19]
+ wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 206:31]
+ wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 207:31]
+ wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 208:31]
+ wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 209:31]
+ wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 210:31]
+ wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 214:35]
+ wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 217:35]
+ wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 218:35]
+ wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 213:27 214:21 217:21]
+ wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 213:27 215:21 218:21]
+ wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 210:17 211:25 212:19]
+ wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 208:17 211:25]
+ wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 209:17 211:25]
+ wire _T_6 = ~reset; // @[VAlu.scala 222:13]
+ wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 223:33]
+ wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 224:33]
+ wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 206:17 221:17 223:19]
+ wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 207:17 221:17 224:19]
wire _T_9 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
wire _T_10 = ~last; // @[VCmdq.scala 66:11]
wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 70:20]
@@ -50852,7 +50871,7 @@
wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_9 = f_io_in_bits_0_bits_tin_vt_valid ? active_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
@@ -50908,7 +50927,7 @@
wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_15 = f_io_in_bits_0_bits_tin_vu_valid ? active_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 254:74]
+ wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 234:74]
wire [63:0] _active_T_5 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 8:8]
wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -51028,7 +51047,7 @@
wire [63:0] _active_active_active_T_149 = _active_active_active_T_148 ? active_active_oh3_4 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_4 = _active_active_active_T_142 | _active_active_active_T_149; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_25 = f_io_in_bits_1_bits_tin_vt_valid ? active_active_active_4 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_5 = f_io_in_bits_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_5 = 16'h1 << active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_5 = {3'h0,active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5
@@ -51087,7 +51106,7 @@
wire [63:0] _active_active_active_T_179 = _active_active_active_T_178 ? active_active_oh3_5 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_5 = _active_active_active_T_172 | _active_active_active_T_179; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_31 = f_io_in_bits_1_bits_tin_vu_valid ? active_active_active_5 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 234:74]
wire [63:0] _active_T_11 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_12 = _active_T_5 | _active_T_11; // @[VCmdq.scala 108:90]
wire [3:0] active_active_oh_shiftAmount_6 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -51208,7 +51227,7 @@
wire [63:0] _active_active_active_T_239 = _active_active_active_T_238 ? active_active_oh3_7 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_7 = _active_active_active_T_232 | _active_active_active_T_239; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_41 = f_io_in_bits_2_bits_tin_vt_valid ? active_active_active_7 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_8 = f_io_in_bits_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_8 = 16'h1 << active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_8 = {3'h0,active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8
@@ -51267,7 +51286,7 @@
wire [63:0] _active_active_active_T_269 = _active_active_active_T_268 ? active_active_oh3_8 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_8 = _active_active_active_T_262 | _active_active_active_T_269; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_47 = f_io_in_bits_2_bits_tin_vu_valid ? active_active_active_8 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 234:74]
wire [63:0] _active_T_18 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_19 = _active_T_12 | _active_T_18; // @[VCmdq.scala 109:90]
wire [3:0] active_active_oh_shiftAmount_9 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -51388,7 +51407,7 @@
wire [63:0] _active_active_active_T_329 = _active_active_active_T_328 ? active_active_oh3_10 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_10 = _active_active_active_T_322 | _active_active_active_T_329; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_57 = f_io_in_bits_3_bits_tin_vt_valid ? active_active_active_10 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_11 = f_io_in_bits_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_11 = 16'h1 << active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_11 = {3'h0,active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,
@@ -51447,7 +51466,7 @@
wire [63:0] _active_active_active_T_359 = _active_active_active_T_358 ? active_active_oh3_11 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_11 = _active_active_active_T_352 | _active_active_active_T_359; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_63 = f_io_in_bits_3_bits_tin_vu_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 234:74]
wire [63:0] _active_T_25 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_26 = _active_T_19 | _active_T_25; // @[VCmdq.scala 110:90]
wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -51594,7 +51613,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_369 = f_io_entry_0_bits_tin_vt_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
@@ -51668,7 +51687,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_375 = f_io_entry_0_bits_tin_vu_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 234:74]
wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_12 : 64'h0; // @[Library.scala 8:8]
wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -51822,7 +51841,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_385 = f_io_entry_1_bits_tin_vt_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
@@ -51898,7 +51917,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_391 = f_io_entry_1_bits_tin_vu_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 234:74]
wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_13 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_28 = active_active_4 | active_active_5; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52053,7 +52072,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_401 = f_io_entry_2_bits_tin_vt_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_8 = f_io_entry_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_8 = 16'h1 << active_active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_8 = {3'h0,active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0
@@ -52129,7 +52148,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_8 = _active_active_active_active_T_262 | _active_active_active_active_T_269; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_407 = f_io_entry_2_bits_tin_vu_valid ? active_active_active_active_8 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 234:74]
wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_14 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_29 = _active_T_28 | active_active_6; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_9 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52284,7 +52303,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_10 = _active_active_active_active_T_322 | _active_active_active_active_T_329; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_417 = f_io_entry_3_bits_tin_vt_valid ? active_active_active_active_10 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_11 = f_io_entry_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_11 = 16'h1 << active_active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_11 = {3'h0,active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2]
@@ -52360,7 +52379,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_11 = _active_active_active_active_T_352 | _active_active_active_active_T_359; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_423 = f_io_entry_3_bits_tin_vu_valid ? active_active_active_active_11 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 234:74]
wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_15 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_30 = _active_T_29 | active_active_7; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_12 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52515,7 +52534,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_13 = _active_active_active_active_T_412 | _active_active_active_active_T_419; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_433 = f_io_entry_4_bits_tin_vt_valid ? active_active_active_active_13 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_14 = f_io_entry_4_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_14 = 16'h1 << active_active_active_oh_shiftAmount_14; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_14 = {3'h0,active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2]
@@ -52591,7 +52610,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_14 = _active_active_active_active_T_442 | _active_active_active_active_T_449; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_439 = f_io_entry_4_bits_tin_vu_valid ? active_active_active_active_14 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 234:74]
wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_16 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_31 = _active_T_30 | active_active_8; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_15 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52746,7 +52765,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_16 = _active_active_active_active_T_502 | _active_active_active_active_T_509; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_449 = f_io_entry_5_bits_tin_vt_valid ? active_active_active_active_16 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_17 = f_io_entry_5_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_17 = 16'h1 << active_active_active_oh_shiftAmount_17; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_17 = {3'h0,active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2]
@@ -52822,7 +52841,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_17 = _active_active_active_active_T_532 | _active_active_active_active_T_539; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_455 = f_io_entry_5_bits_tin_vu_valid ? active_active_active_active_17 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 234:74]
wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_17 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_32 = _active_T_31 | active_active_9; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_18 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52977,7 +52996,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_19 = _active_active_active_active_T_592 | _active_active_active_active_T_599; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_465 = f_io_entry_6_bits_tin_vt_valid ? active_active_active_active_19 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_20 = f_io_entry_6_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_20 = 16'h1 << active_active_active_oh_shiftAmount_20; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_20 = {3'h0,active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2]
@@ -53053,7 +53072,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_20 = _active_active_active_active_T_622 | _active_active_active_active_T_629; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_471 = f_io_entry_6_bits_tin_vu_valid ? active_active_active_active_20 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 234:74]
wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_18 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_33 = _active_T_32 | active_active_10; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_21 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -53208,7 +53227,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_22 = _active_active_active_active_T_682 | _active_active_active_active_T_689; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_481 = f_io_entry_7_bits_tin_vt_valid ? active_active_active_active_22 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_23 = f_io_entry_7_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_23 = 16'h1 << active_active_active_oh_shiftAmount_23; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_23 = {3'h0,active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2]
@@ -53284,7 +53303,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_23 = _active_active_active_active_T_712 | _active_active_active_active_T_719; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_487 = f_io_entry_7_bits_tin_vu_valid ? active_active_active_active_23 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 234:74]
wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_19 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_34 = _active_T_33 | active_active_11; // @[VCmdq.scala 91:24]
wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
@@ -53437,7 +53456,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active0_active_active_1 = _active_active0_active_active_T_52 | _active_active0_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active0_active_T_11 = value_tin_vt_valid ? active_active0_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 233:74]
wire [3:0] active_active0_active_oh_shiftAmount_2 = value_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active0_active_oh_2 = 16'h1 << active_active0_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
wire [15:0] active_active0_active_oh0_lo_lo_2 = {3'h0,active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2]
@@ -53513,7 +53532,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active0_active_active_2 = _active_active0_active_active_T_82 | _active_active0_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active0_active_T_18 = value_tin_vu_valid ? active_active0_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 254:74]
+ wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 234:74]
wire _active_active1_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _step_T_1[2:0] <= 3'h0
; // @[VCommon.scala 91:42]
wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -53557,7 +53576,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active1_active_active_1 = _active_active1_active_active_T_52 | _active_active1_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active1_active_T_11 = value_tin_vt_valid ? active_active1_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 233:74]
wire _active_active1_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _step_T_1[2:0]
<= 3'h0; // @[VCommon.scala 91:42]
wire [63:0] _active_active1_active_active_T_66 = _active_active1_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
@@ -53580,14 +53599,14 @@
; // @[Library.scala 18:8]
wire [63:0] active_active1_active_active_2 = _active_active1_active_active_T_82 | _active_active1_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active1_active_T_18 = value_tin_vu_valid ? active_active1_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 254:74]
+ wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 234:74]
wire _active_active_T_96 = ~io_out_ready; // @[VCmdq.scala 96:36]
wire _active_active_T_99 = valid & (~io_out_ready | _T_10); // @[VCmdq.scala 96:32]
wire [63:0] _active_active_T_101 = _active_active_T_96 ? active_active0 : active_active1; // @[VCmdq.scala 97:29]
wire [63:0] active_active_12 = _active_active_T_99 ? _active_active_T_101 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_35 = _active_T_34 | active_active_12; // @[VCmdq.scala 98:12]
wire [63:0] _active_T_36 = _active_T_26 | _active_T_35; // @[VCmdq.scala 111:90]
- wire _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 251:11]
+ wire _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 231:11]
Fifo4e f ( // @[Fifo4e.scala 10:11]
.clock(f_clock),
.reset(f_reset),
@@ -53778,80 +53797,80 @@
assign f_reset = reset;
assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 190:19 193:12]
- assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
- assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_0_bits_tin_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_0_bits_tin_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_0_bits_tin_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_0_bits_tin_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_0_bits_tin_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_0_bits_tin_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 170:19 173:12]
+ assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+ assign f_io_in_bits_0_bits_tin_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+ assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_0_bits_tin_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_0_bits_tin_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_0_bits_tin_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_0_bits_tin_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_0_bits_tin_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_0_bits_tin_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 190:19 193:12]
- assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
- assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_1_bits_tin_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_1_bits_tin_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_1_bits_tin_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_1_bits_tin_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_1_bits_tin_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_1_bits_tin_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 170:19 173:12]
+ assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+ assign f_io_in_bits_1_bits_tin_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+ assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_1_bits_tin_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_1_bits_tin_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_1_bits_tin_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_1_bits_tin_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_1_bits_tin_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_1_bits_tin_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 190:19 193:12]
- assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
- assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_2_bits_tin_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_2_bits_tin_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_2_bits_tin_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_2_bits_tin_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_2_bits_tin_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_2_bits_tin_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 170:19 173:12]
+ assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+ assign f_io_in_bits_2_bits_tin_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+ assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_2_bits_tin_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_2_bits_tin_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_2_bits_tin_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_2_bits_tin_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_2_bits_tin_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_2_bits_tin_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 190:19 193:12]
- assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
- assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
- assign f_io_in_bits_3_bits_tin_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_3_bits_tin_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_3_bits_tin_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
- assign f_io_in_bits_3_bits_tin_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_3_bits_tin_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_3_bits_tin_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 170:19 173:12]
+ assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+ assign f_io_in_bits_3_bits_tin_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+ assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+ assign f_io_in_bits_3_bits_tin_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_3_bits_tin_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_3_bits_tin_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+ assign f_io_in_bits_3_bits_tin_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_3_bits_tin_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_3_bits_tin_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
assign f_io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 57:28]
always @(posedge clock) begin
@@ -54020,7 +54039,7 @@
if (`STOP_COND) begin
`endif
if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fatal; // @[VAlu.scala 242:13]
+ $fatal; // @[VAlu.scala 222:13]
end
`ifdef STOP_COND
end
@@ -54031,7 +54050,7 @@
if (`PRINTF_COND) begin
`endif
if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:242 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:222 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 222:13]
end
`ifdef PRINTF_COND
end
@@ -54042,7 +54061,7 @@
if (`STOP_COND) begin
`endif
if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fatal; // @[VAlu.scala 251:11]
+ $fatal; // @[VAlu.scala 231:11]
end
`ifdef STOP_COND
end
@@ -54053,7 +54072,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
end
`ifdef PRINTF_COND
end
@@ -54130,7 +54149,7 @@
if (`STOP_COND) begin
`endif
if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fatal; // @[VAlu.scala 251:11]
+ $fatal; // @[VAlu.scala 231:11]
end
`ifdef STOP_COND
end
@@ -54141,7 +54160,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
end
`ifdef PRINTF_COND
end
@@ -54690,28 +54709,28 @@
reg value_tin_cmdsync; // @[VCmdq.scala 37:18]
reg value_m; // @[VCmdq.scala 37:18]
reg [4:0] step; // @[VCmdq.scala 42:21]
- wire vevnodd = value_tin_op == 7'h5d | value_tin_op == 7'h5e | value_tin_op == 7'h5f; // @[VAlu.scala 221:60]
- wire vzip = value_tin_op == 7'h60; // @[VAlu.scala 222:22]
- wire _last_T = ~value_m; // @[VAlu.scala 224:16]
- wire last = ~value_m | step == 5'h3; // @[VAlu.scala 224:19]
- wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 226:31]
- wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 227:31]
- wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 228:31]
- wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 229:31]
- wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 230:31]
- wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 234:35]
- wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 237:35]
- wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 238:35]
- wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 233:27 234:21 237:21]
- wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 233:27 235:21 238:21]
- wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 230:17 231:25 232:19]
- wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 228:17 231:25]
- wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 229:17 231:25]
- wire _T_6 = ~reset; // @[VAlu.scala 242:13]
- wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 243:33]
- wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 244:33]
- wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 226:17 241:17 243:19]
- wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 227:17 241:17 244:19]
+ wire vevnodd = value_tin_op == 7'h5d | value_tin_op == 7'h5e | value_tin_op == 7'h5f; // @[VAlu.scala 201:60]
+ wire vzip = value_tin_op == 7'h60; // @[VAlu.scala 202:22]
+ wire _last_T = ~value_m; // @[VAlu.scala 204:16]
+ wire last = ~value_m | step == 5'h3; // @[VAlu.scala 204:19]
+ wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 206:31]
+ wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 207:31]
+ wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 208:31]
+ wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 209:31]
+ wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 210:31]
+ wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 214:35]
+ wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 217:35]
+ wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 218:35]
+ wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 213:27 214:21 217:21]
+ wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 213:27 215:21 218:21]
+ wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 210:17 211:25 212:19]
+ wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 208:17 211:25]
+ wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 209:17 211:25]
+ wire _T_6 = ~reset; // @[VAlu.scala 222:13]
+ wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 223:33]
+ wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 224:33]
+ wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 206:17 221:17 223:19]
+ wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 207:17 221:17 224:19]
wire _T_9 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
wire _T_10 = ~last; // @[VCmdq.scala 66:11]
wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 70:20]
@@ -54838,7 +54857,7 @@
wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_9 = f_io_in_bits_0_bits_tin_vt_valid ? active_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
@@ -54894,7 +54913,7 @@
wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_15 = f_io_in_bits_0_bits_tin_vu_valid ? active_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 254:74]
+ wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 234:74]
wire [63:0] _active_T_5 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 8:8]
wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -55014,7 +55033,7 @@
wire [63:0] _active_active_active_T_149 = _active_active_active_T_148 ? active_active_oh3_4 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_4 = _active_active_active_T_142 | _active_active_active_T_149; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_25 = f_io_in_bits_1_bits_tin_vt_valid ? active_active_active_4 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_5 = f_io_in_bits_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_5 = 16'h1 << active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_5 = {3'h0,active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5
@@ -55073,7 +55092,7 @@
wire [63:0] _active_active_active_T_179 = _active_active_active_T_178 ? active_active_oh3_5 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_5 = _active_active_active_T_172 | _active_active_active_T_179; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_31 = f_io_in_bits_1_bits_tin_vu_valid ? active_active_active_5 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 234:74]
wire [63:0] _active_T_11 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_12 = _active_T_5 | _active_T_11; // @[VCmdq.scala 108:90]
wire [3:0] active_active_oh_shiftAmount_6 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -55194,7 +55213,7 @@
wire [63:0] _active_active_active_T_239 = _active_active_active_T_238 ? active_active_oh3_7 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_7 = _active_active_active_T_232 | _active_active_active_T_239; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_41 = f_io_in_bits_2_bits_tin_vt_valid ? active_active_active_7 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_8 = f_io_in_bits_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_8 = 16'h1 << active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_8 = {3'h0,active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8
@@ -55253,7 +55272,7 @@
wire [63:0] _active_active_active_T_269 = _active_active_active_T_268 ? active_active_oh3_8 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_8 = _active_active_active_T_262 | _active_active_active_T_269; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_47 = f_io_in_bits_2_bits_tin_vu_valid ? active_active_active_8 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 234:74]
wire [63:0] _active_T_18 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_19 = _active_T_12 | _active_T_18; // @[VCmdq.scala 109:90]
wire [3:0] active_active_oh_shiftAmount_9 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -55374,7 +55393,7 @@
wire [63:0] _active_active_active_T_329 = _active_active_active_T_328 ? active_active_oh3_10 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_10 = _active_active_active_T_322 | _active_active_active_T_329; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_57 = f_io_in_bits_3_bits_tin_vt_valid ? active_active_active_10 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 233:74]
wire [3:0] active_active_oh_shiftAmount_11 = f_io_in_bits_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_oh_11 = 16'h1 << active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
wire [15:0] active_active_oh0_lo_lo_11 = {3'h0,active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,
@@ -55433,7 +55452,7 @@
wire [63:0] _active_active_active_T_359 = _active_active_active_T_358 ? active_active_oh3_11 : 64'h0; // @[Library.scala 18:8]
wire [63:0] active_active_active_11 = _active_active_active_T_352 | _active_active_active_T_359; // @[VCommon.scala 93:68]
wire [63:0] _active_active_T_63 = f_io_in_bits_3_bits_tin_vu_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 234:74]
wire [63:0] _active_T_25 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_26 = _active_T_19 | _active_T_25; // @[VCmdq.scala 110:90]
wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -55580,7 +55599,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_369 = f_io_entry_0_bits_tin_vt_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
@@ -55654,7 +55673,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_375 = f_io_entry_0_bits_tin_vu_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 234:74]
wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_12 : 64'h0; // @[Library.scala 8:8]
wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -55808,7 +55827,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_385 = f_io_entry_1_bits_tin_vt_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
@@ -55884,7 +55903,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_391 = f_io_entry_1_bits_tin_vu_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 234:74]
wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_13 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_28 = active_active_4 | active_active_5; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56039,7 +56058,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_401 = f_io_entry_2_bits_tin_vt_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_8 = f_io_entry_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_8 = 16'h1 << active_active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_8 = {3'h0,active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0
@@ -56115,7 +56134,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_8 = _active_active_active_active_T_262 | _active_active_active_active_T_269; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_407 = f_io_entry_2_bits_tin_vu_valid ? active_active_active_active_8 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 234:74]
wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_14 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_29 = _active_T_28 | active_active_6; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_9 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56270,7 +56289,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_10 = _active_active_active_active_T_322 | _active_active_active_active_T_329; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_417 = f_io_entry_3_bits_tin_vt_valid ? active_active_active_active_10 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_11 = f_io_entry_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_11 = 16'h1 << active_active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_11 = {3'h0,active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2]
@@ -56346,7 +56365,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_11 = _active_active_active_active_T_352 | _active_active_active_active_T_359; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_423 = f_io_entry_3_bits_tin_vu_valid ? active_active_active_active_11 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 234:74]
wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_15 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_30 = _active_T_29 | active_active_7; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_12 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56501,7 +56520,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_13 = _active_active_active_active_T_412 | _active_active_active_active_T_419; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_433 = f_io_entry_4_bits_tin_vt_valid ? active_active_active_active_13 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_14 = f_io_entry_4_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_14 = 16'h1 << active_active_active_oh_shiftAmount_14; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_14 = {3'h0,active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2]
@@ -56577,7 +56596,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_14 = _active_active_active_active_T_442 | _active_active_active_active_T_449; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_439 = f_io_entry_4_bits_tin_vu_valid ? active_active_active_active_14 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 234:74]
wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_16 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_31 = _active_T_30 | active_active_8; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_15 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56732,7 +56751,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_16 = _active_active_active_active_T_502 | _active_active_active_active_T_509; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_449 = f_io_entry_5_bits_tin_vt_valid ? active_active_active_active_16 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_17 = f_io_entry_5_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_17 = 16'h1 << active_active_active_oh_shiftAmount_17; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_17 = {3'h0,active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2]
@@ -56808,7 +56827,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_17 = _active_active_active_active_T_532 | _active_active_active_active_T_539; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_455 = f_io_entry_5_bits_tin_vu_valid ? active_active_active_active_17 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 234:74]
wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_17 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_32 = _active_T_31 | active_active_9; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_18 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56963,7 +56982,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_19 = _active_active_active_active_T_592 | _active_active_active_active_T_599; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_465 = f_io_entry_6_bits_tin_vt_valid ? active_active_active_active_19 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_20 = f_io_entry_6_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_20 = 16'h1 << active_active_active_oh_shiftAmount_20; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_20 = {3'h0,active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2]
@@ -57039,7 +57058,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_20 = _active_active_active_active_T_622 | _active_active_active_active_T_629; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_471 = f_io_entry_6_bits_tin_vu_valid ? active_active_active_active_20 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 234:74]
wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_18 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_33 = _active_T_32 | active_active_10; // @[VCmdq.scala 91:24]
wire [3:0] active_active_active_oh_shiftAmount_21 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -57194,7 +57213,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_22 = _active_active_active_active_T_682 | _active_active_active_active_T_689; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_481 = f_io_entry_7_bits_tin_vt_valid ? active_active_active_active_22 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 233:74]
wire [3:0] active_active_active_oh_shiftAmount_23 = f_io_entry_7_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active_active_oh_23 = 16'h1 << active_active_active_oh_shiftAmount_23; // @[OneHot.scala 64:12]
wire [15:0] active_active_active_oh0_lo_lo_23 = {3'h0,active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2]
@@ -57270,7 +57289,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active_active_active_23 = _active_active_active_active_T_712 | _active_active_active_active_T_719; // @[VCommon.scala 93:68]
wire [63:0] _active_active_active_T_487 = f_io_entry_7_bits_tin_vu_valid ? active_active_active_active_23 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 254:74]
+ wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 234:74]
wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_19 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_34 = _active_T_33 | active_active_11; // @[VCmdq.scala 91:24]
wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
@@ -57423,7 +57442,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active0_active_active_1 = _active_active0_active_active_T_52 | _active_active0_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active0_active_T_11 = value_tin_vt_valid ? active_active0_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 233:74]
wire [3:0] active_active0_active_oh_shiftAmount_2 = value_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active0_active_oh_2 = 16'h1 << active_active0_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
wire [15:0] active_active0_active_oh0_lo_lo_2 = {3'h0,active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2]
@@ -57499,7 +57518,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active0_active_active_2 = _active_active0_active_active_T_82 | _active_active0_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active0_active_T_18 = value_tin_vu_valid ? active_active0_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 254:74]
+ wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 234:74]
wire _active_active1_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _step_T_1[2:0] <= 3'h0
; // @[VCommon.scala 91:42]
wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -57543,7 +57562,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active1_active_active_1 = _active_active1_active_active_T_52 | _active_active1_active_active_T_59; // @[VCommon.scala 93:68]
wire [63:0] _active_active1_active_T_11 = value_tin_vt_valid ? active_active1_active_active_1 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 253:74]
+ wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 233:74]
wire _active_active1_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _step_T_1[2:0]
<= 3'h0; // @[VCommon.scala 91:42]
wire [63:0] _active_active1_active_active_T_66 = _active_active1_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
@@ -57566,14 +57585,14 @@
; // @[Library.scala 18:8]
wire [63:0] active_active1_active_active_2 = _active_active1_active_active_T_82 | _active_active1_active_active_T_89; // @[VCommon.scala 93:68]
wire [63:0] _active_active1_active_T_18 = value_tin_vu_valid ? active_active1_active_active_2 : 64'h0; // @[Library.scala 8:8]
- wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 254:74]
+ wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 234:74]
wire _active_active_T_96 = ~io_out_ready; // @[VCmdq.scala 96:36]
wire _active_active_T_99 = valid & (~io_out_ready | _T_10); // @[VCmdq.scala 96:32]
wire [63:0] _active_active_T_101 = _active_active_T_96 ? active_active0 : active_active1; // @[VCmdq.scala 97:29]
wire [63:0] active_active_12 = _active_active_T_99 ? _active_active_T_101 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_35 = _active_T_34 | active_active_12; // @[VCmdq.scala 98:12]
wire [63:0] _active_T_36 = _active_T_26 | _active_T_35; // @[VCmdq.scala 111:90]
- wire _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 251:11]
+ wire _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 231:11]
Fifo4e f ( // @[Fifo4e.scala 10:11]
.clock(f_clock),
.reset(f_reset),
@@ -57764,124 +57783,124 @@
assign f_reset = reset;
assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 190:19 193:12]
+ assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 170:19 173:12]
assign f_io_in_bits_0_bits_tin_vd_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vd_addr :
- io_in_bits_0_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+ io_in_bits_0_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
assign f_io_in_bits_0_bits_tin_ve_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_ve_addr :
- io_in_bits_0_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+ io_in_bits_0_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
assign f_io_in_bits_0_bits_tin_vs_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_valid :
- io_in_bits_0_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_0_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_0_bits_tin_vs_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_addr :
- io_in_bits_0_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_0_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_0_bits_tin_vs_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_tag :
- io_in_bits_0_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_0_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_0_bits_tin_vt_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_valid :
- io_in_bits_0_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_0_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_0_bits_tin_vt_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_addr :
- io_in_bits_0_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_0_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_0_bits_tin_vt_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_tag :
- io_in_bits_0_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_0_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_0_bits_tin_vu_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_valid :
- io_in_bits_0_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_0_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_0_bits_tin_vu_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_addr :
- io_in_bits_0_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_0_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_0_bits_tin_vu_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_tag :
- io_in_bits_0_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ io_in_bits_0_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 190:19 193:12]
+ assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 170:19 173:12]
assign f_io_in_bits_1_bits_tin_vd_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vd_addr :
- io_in_bits_1_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+ io_in_bits_1_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
assign f_io_in_bits_1_bits_tin_ve_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_ve_addr :
- io_in_bits_1_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+ io_in_bits_1_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
assign f_io_in_bits_1_bits_tin_vs_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_valid :
- io_in_bits_1_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_1_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_1_bits_tin_vs_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_addr :
- io_in_bits_1_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_1_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_1_bits_tin_vs_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_tag :
- io_in_bits_1_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_1_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_1_bits_tin_vt_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_valid :
- io_in_bits_1_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_1_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_1_bits_tin_vt_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_addr :
- io_in_bits_1_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_1_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_1_bits_tin_vt_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_tag :
- io_in_bits_1_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_1_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_1_bits_tin_vu_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_valid :
- io_in_bits_1_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_1_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_1_bits_tin_vu_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_addr :
- io_in_bits_1_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_1_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_1_bits_tin_vu_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_tag :
- io_in_bits_1_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ io_in_bits_1_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 190:19 193:12]
+ assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 170:19 173:12]
assign f_io_in_bits_2_bits_tin_vd_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vd_addr :
- io_in_bits_2_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+ io_in_bits_2_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
assign f_io_in_bits_2_bits_tin_ve_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_ve_addr :
- io_in_bits_2_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+ io_in_bits_2_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
assign f_io_in_bits_2_bits_tin_vs_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_valid :
- io_in_bits_2_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_2_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_2_bits_tin_vs_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_addr :
- io_in_bits_2_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_2_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_2_bits_tin_vs_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_tag :
- io_in_bits_2_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_2_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_2_bits_tin_vt_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_valid :
- io_in_bits_2_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_2_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_2_bits_tin_vt_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_addr :
- io_in_bits_2_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_2_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_2_bits_tin_vt_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_tag :
- io_in_bits_2_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_2_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_2_bits_tin_vu_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_valid :
- io_in_bits_2_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_2_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_2_bits_tin_vu_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_addr :
- io_in_bits_2_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_2_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_2_bits_tin_vu_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_tag :
- io_in_bits_2_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ io_in_bits_2_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 190:19 191:12]
- assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 190:19 192:12]
- assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 190:19 193:12]
+ assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 170:19 171:12]
+ assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 170:19 172:12]
+ assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 170:19 173:12]
assign f_io_in_bits_3_bits_tin_vd_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vd_addr :
- io_in_bits_3_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+ io_in_bits_3_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
assign f_io_in_bits_3_bits_tin_ve_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_ve_addr :
- io_in_bits_3_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+ io_in_bits_3_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
assign f_io_in_bits_3_bits_tin_vs_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_valid :
- io_in_bits_3_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_3_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_3_bits_tin_vs_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_addr :
- io_in_bits_3_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_3_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_3_bits_tin_vs_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_tag :
- io_in_bits_3_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+ io_in_bits_3_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
assign f_io_in_bits_3_bits_tin_vt_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_valid :
- io_in_bits_3_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_3_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_3_bits_tin_vt_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_addr :
- io_in_bits_3_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_3_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_3_bits_tin_vt_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_tag :
- io_in_bits_3_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+ io_in_bits_3_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
assign f_io_in_bits_3_bits_tin_vu_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_valid :
- io_in_bits_3_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_3_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_3_bits_tin_vu_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_addr :
- io_in_bits_3_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+ io_in_bits_3_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
assign f_io_in_bits_3_bits_tin_vu_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_tag :
- io_in_bits_3_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
- assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 190:19 208:12]
- assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+ io_in_bits_3_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+ assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+ assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
assign f_io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 57:28]
always @(posedge clock) begin
@@ -58050,7 +58069,7 @@
if (`STOP_COND) begin
`endif
if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fatal; // @[VAlu.scala 242:13]
+ $fatal; // @[VAlu.scala 222:13]
end
`ifdef STOP_COND
end
@@ -58061,7 +58080,7 @@
if (`PRINTF_COND) begin
`endif
if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:242 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 242:13]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:222 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 222:13]
end
`ifdef PRINTF_COND
end
@@ -58072,7 +58091,7 @@
if (`STOP_COND) begin
`endif
if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fatal; // @[VAlu.scala 251:11]
+ $fatal; // @[VAlu.scala 231:11]
end
`ifdef STOP_COND
end
@@ -58083,7 +58102,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
end
`ifdef PRINTF_COND
end
@@ -58160,7 +58179,7 @@
if (`STOP_COND) begin
`endif
if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fatal; // @[VAlu.scala 251:11]
+ $fatal; // @[VAlu.scala 231:11]
end
`ifdef STOP_COND
end
@@ -58171,7 +58190,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
end
`ifdef PRINTF_COND
end
@@ -64250,7 +64269,7 @@
wire e_min = io_in_op == 7'h11; // @[VAluInt.scala 67:26]
wire e_rsub = io_in_op == 7'h8; // @[VAluInt.scala 68:26]
wire e_srans = io_in_op == 7'h25; // @[VAluInt.scala 69:26]
- wire e_sraqs = io_in_op == 7'h26; // @[VAluInt.scala 70:40]
+ wire e_sraqs = io_in_op == 7'h26; // @[VAluInt.scala 70:42]
wire _e_slidevn_T_3 = io_in_op == 7'h58; // @[VAluInt.scala 72:86]
wire e_slidevn = io_in_op == 7'h56 | io_in_op == 7'h57 | io_in_op == 7'h58; // @[VAluInt.scala 72:74]
wire _e_slidevp_T_3 = io_in_op == 7'h5b; // @[VAluInt.scala 73:86]
@@ -72972,558 +72991,558 @@
wire [31:0] q1_io_out_bits_sv_data; // @[VCmdq.scala 14:11]
wire q1_io_out_bits_cmdsync; // @[VCmdq.scala 14:11]
wire [63:0] q1_io_active; // @[VCmdq.scala 14:11]
- wire alu0_clock; // @[VAlu.scala 341:20]
- wire alu0_reset; // @[VAlu.scala 341:20]
- wire alu0_io_in_valid; // @[VAlu.scala 341:20]
- wire [6:0] alu0_io_in_op; // @[VAlu.scala 341:20]
- wire [2:0] alu0_io_in_f2; // @[VAlu.scala 341:20]
- wire [2:0] alu0_io_in_sz; // @[VAlu.scala 341:20]
- wire [5:0] alu0_io_in_vd_addr; // @[VAlu.scala 341:20]
- wire [5:0] alu0_io_in_ve_addr; // @[VAlu.scala 341:20]
- wire [31:0] alu0_io_in_sv_data; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_read_0_data; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_read_1_data; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_read_2_data; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_read_3_data; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_read_4_data; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_read_5_data; // @[VAlu.scala 341:20]
- wire alu0_io_write_0_valid; // @[VAlu.scala 341:20]
- wire [5:0] alu0_io_write_0_addr; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_write_0_data; // @[VAlu.scala 341:20]
- wire alu0_io_write_1_valid; // @[VAlu.scala 341:20]
- wire [5:0] alu0_io_write_1_addr; // @[VAlu.scala 341:20]
- wire [255:0] alu0_io_write_1_data; // @[VAlu.scala 341:20]
- wire alu0_io_whint_0_valid; // @[VAlu.scala 341:20]
- wire [5:0] alu0_io_whint_0_addr; // @[VAlu.scala 341:20]
- wire alu0_io_whint_1_valid; // @[VAlu.scala 341:20]
- wire [5:0] alu0_io_whint_1_addr; // @[VAlu.scala 341:20]
- wire alu1_clock; // @[VAlu.scala 375:20]
- wire alu1_reset; // @[VAlu.scala 375:20]
- wire alu1_io_in_valid; // @[VAlu.scala 375:20]
- wire [6:0] alu1_io_in_op; // @[VAlu.scala 375:20]
- wire [2:0] alu1_io_in_f2; // @[VAlu.scala 375:20]
- wire [2:0] alu1_io_in_sz; // @[VAlu.scala 375:20]
- wire [5:0] alu1_io_in_vd_addr; // @[VAlu.scala 375:20]
- wire [5:0] alu1_io_in_ve_addr; // @[VAlu.scala 375:20]
- wire [31:0] alu1_io_in_sv_data; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_read_0_data; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_read_1_data; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_read_2_data; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_read_3_data; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_read_4_data; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_read_5_data; // @[VAlu.scala 375:20]
- wire alu1_io_write_0_valid; // @[VAlu.scala 375:20]
- wire [5:0] alu1_io_write_0_addr; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_write_0_data; // @[VAlu.scala 375:20]
- wire alu1_io_write_1_valid; // @[VAlu.scala 375:20]
- wire [5:0] alu1_io_write_1_addr; // @[VAlu.scala 375:20]
- wire [255:0] alu1_io_write_1_data; // @[VAlu.scala 375:20]
- wire alu1_io_whint_0_valid; // @[VAlu.scala 375:20]
- wire [5:0] alu1_io_whint_0_addr; // @[VAlu.scala 375:20]
- wire alu1_io_whint_1_valid; // @[VAlu.scala 375:20]
- wire [5:0] alu1_io_whint_1_addr; // @[VAlu.scala 375:20]
- wire _T = io_in_valid & io_in_ready; // @[VAlu.scala 82:23]
- wire _supported_T_1 = io_in_bits_0_bits_op == 7'h37; // @[VAlu.scala 88:16]
- wire _supported_T_2 = io_in_bits_0_bits_op == 7'hf | _supported_T_1; // @[VAlu.scala 87:30]
- wire _supported_T_3 = io_in_bits_0_bits_op == 7'h6; // @[VAlu.scala 89:16]
- wire _supported_T_4 = _supported_T_2 | _supported_T_3; // @[VAlu.scala 88:29]
- wire _supported_T_5 = io_in_bits_0_bits_op == 7'h33; // @[VAlu.scala 90:16]
- wire _supported_T_6 = _supported_T_4 | _supported_T_5; // @[VAlu.scala 89:29]
- wire _supported_T_7 = io_in_bits_0_bits_op == 7'h35; // @[VAlu.scala 91:16]
- wire _supported_T_8 = _supported_T_6 | _supported_T_7; // @[VAlu.scala 90:30]
- wire _supported_T_9 = io_in_bits_0_bits_op == 7'h12; // @[VAlu.scala 92:16]
- wire _supported_T_10 = _supported_T_8 | _supported_T_9; // @[VAlu.scala 91:30]
- wire _supported_T_11 = io_in_bits_0_bits_op == 7'h1; // @[VAlu.scala 93:16]
- wire _supported_T_12 = _supported_T_10 | _supported_T_11; // @[VAlu.scala 92:30]
- wire _supported_T_13 = io_in_bits_0_bits_op == 7'h3a; // @[VAlu.scala 94:16]
- wire _supported_T_14 = _supported_T_12 | _supported_T_13; // @[VAlu.scala 93:29]
- wire _supported_T_15 = io_in_bits_0_bits_op == 7'h3b; // @[VAlu.scala 95:16]
- wire _supported_T_16 = _supported_T_14 | _supported_T_15; // @[VAlu.scala 94:30]
- wire _supported_T_17 = io_in_bits_0_bits_op == 7'h10; // @[VAlu.scala 96:16]
- wire _supported_T_18 = _supported_T_16 | _supported_T_17; // @[VAlu.scala 95:30]
- wire _supported_T_19 = io_in_bits_0_bits_op == 7'h11; // @[VAlu.scala 97:16]
- wire _supported_T_20 = _supported_T_18 | _supported_T_19; // @[VAlu.scala 96:29]
- wire _supported_T_21 = io_in_bits_0_bits_op == 7'h38; // @[VAlu.scala 98:16]
- wire _supported_T_22 = _supported_T_20 | _supported_T_21; // @[VAlu.scala 97:29]
- wire _supported_T_23 = io_in_bits_0_bits_op == 7'h39; // @[VAlu.scala 99:16]
- wire _supported_T_24 = _supported_T_22 | _supported_T_23; // @[VAlu.scala 98:30]
- wire _supported_T_25 = io_in_bits_0_bits_op == 7'h8; // @[VAlu.scala 100:16]
- wire _supported_T_26 = _supported_T_24 | _supported_T_25; // @[VAlu.scala 99:30]
- wire _supported_T_27 = io_in_bits_0_bits_op == 7'h7; // @[VAlu.scala 101:16]
- wire _supported_T_28 = _supported_T_26 | _supported_T_27; // @[VAlu.scala 100:30]
- wire _supported_T_29 = io_in_bits_0_bits_op == 7'h34; // @[VAlu.scala 102:16]
- wire _supported_T_30 = _supported_T_28 | _supported_T_29; // @[VAlu.scala 101:29]
- wire _supported_T_31 = io_in_bits_0_bits_op == 7'h36; // @[VAlu.scala 103:16]
- wire _supported_T_32 = _supported_T_30 | _supported_T_31; // @[VAlu.scala 102:30]
- wire _supported_T_33 = io_in_bits_0_bits_op == 7'h9; // @[VAlu.scala 105:16]
- wire _supported_T_34 = _supported_T_32 | _supported_T_33; // @[VAlu.scala 103:30]
- wire _supported_T_35 = io_in_bits_0_bits_op == 7'ha; // @[VAlu.scala 106:16]
- wire _supported_T_36 = _supported_T_34 | _supported_T_35; // @[VAlu.scala 105:28]
- wire _supported_T_37 = io_in_bits_0_bits_op == 7'hb; // @[VAlu.scala 107:16]
- wire _supported_T_38 = _supported_T_36 | _supported_T_37; // @[VAlu.scala 106:28]
- wire _supported_T_39 = io_in_bits_0_bits_op == 7'hc; // @[VAlu.scala 108:16]
- wire _supported_T_40 = _supported_T_38 | _supported_T_39; // @[VAlu.scala 107:28]
- wire _supported_T_41 = io_in_bits_0_bits_op == 7'hd; // @[VAlu.scala 109:16]
- wire _supported_T_42 = _supported_T_40 | _supported_T_41; // @[VAlu.scala 108:28]
- wire _supported_T_43 = io_in_bits_0_bits_op == 7'he; // @[VAlu.scala 110:16]
- wire _supported_T_44 = _supported_T_42 | _supported_T_43; // @[VAlu.scala 109:28]
- wire _supported_T_45 = io_in_bits_0_bits_op == 7'h13; // @[VAlu.scala 112:16]
- wire _supported_T_46 = _supported_T_44 | _supported_T_45; // @[VAlu.scala 110:28]
- wire _supported_T_47 = io_in_bits_0_bits_op == 7'h19; // @[VAlu.scala 113:16]
- wire _supported_T_48 = _supported_T_46 | _supported_T_47; // @[VAlu.scala 112:29]
- wire _supported_T_49 = io_in_bits_0_bits_op == 7'h1a; // @[VAlu.scala 114:16]
- wire _supported_T_50 = _supported_T_48 | _supported_T_49; // @[VAlu.scala 113:29]
- wire _supported_T_51 = io_in_bits_0_bits_op == 7'h1b; // @[VAlu.scala 115:16]
- wire _supported_T_52 = _supported_T_50 | _supported_T_51; // @[VAlu.scala 114:29]
- wire _supported_T_53 = io_in_bits_0_bits_op == 7'h1c; // @[VAlu.scala 116:16]
- wire _supported_T_54 = _supported_T_52 | _supported_T_53; // @[VAlu.scala 115:30]
- wire _supported_T_55 = io_in_bits_0_bits_op == 7'h1d; // @[VAlu.scala 117:16]
- wire _supported_T_56 = _supported_T_54 | _supported_T_55; // @[VAlu.scala 116:28]
- wire _supported_T_57 = io_in_bits_0_bits_op == 7'h1e; // @[VAlu.scala 118:16]
- wire _supported_T_58 = _supported_T_56 | _supported_T_57; // @[VAlu.scala 117:29]
- wire _supported_T_59 = io_in_bits_0_bits_op == 7'h21; // @[VAlu.scala 119:16]
- wire _supported_T_60 = _supported_T_58 | _supported_T_59; // @[VAlu.scala 118:29]
- wire _supported_T_61 = io_in_bits_0_bits_op == 7'h16; // @[VAlu.scala 120:16]
- wire _supported_T_62 = _supported_T_60 | _supported_T_61; // @[VAlu.scala 119:32]
- wire _supported_T_63 = io_in_bits_0_bits_op == 7'h14; // @[VAlu.scala 121:16]
- wire _supported_T_64 = _supported_T_62 | _supported_T_63; // @[VAlu.scala 120:29]
- wire _supported_T_65 = io_in_bits_0_bits_op == 7'h17; // @[VAlu.scala 122:16]
- wire _supported_T_66 = _supported_T_64 | _supported_T_65; // @[VAlu.scala 121:28]
- wire _supported_T_67 = io_in_bits_0_bits_op == 7'h18; // @[VAlu.scala 123:16]
- wire _supported_T_68 = _supported_T_66 | _supported_T_67; // @[VAlu.scala 122:29]
- wire _supported_T_69 = io_in_bits_0_bits_op == 7'h15; // @[VAlu.scala 124:16]
- wire _supported_T_70 = _supported_T_68 | _supported_T_69; // @[VAlu.scala 123:29]
- wire _supported_T_71 = io_in_bits_0_bits_op == 7'h22; // @[VAlu.scala 126:16]
- wire _supported_T_72 = _supported_T_70 | _supported_T_71; // @[VAlu.scala 124:29]
- wire _supported_T_73 = io_in_bits_0_bits_op == 7'h23; // @[VAlu.scala 127:16]
- wire _supported_T_74 = _supported_T_72 | _supported_T_73; // @[VAlu.scala 126:29]
- wire _supported_T_75 = io_in_bits_0_bits_op == 7'h24; // @[VAlu.scala 128:16]
- wire _supported_T_76 = _supported_T_74 | _supported_T_75; // @[VAlu.scala 127:29]
- wire _supported_T_77 = io_in_bits_0_bits_op == 7'h25; // @[VAlu.scala 129:16]
- wire _supported_T_78 = _supported_T_76 | _supported_T_77; // @[VAlu.scala 128:29]
- wire _supported_T_79 = io_in_bits_0_bits_op == 7'h26; // @[VAlu.scala 130:16]
- wire _supported_T_80 = _supported_T_78 | _supported_T_79; // @[VAlu.scala 129:31]
- wire _supported_T_81 = io_in_bits_0_bits_op == 7'h2d; // @[VAlu.scala 132:16]
- wire _supported_T_82 = _supported_T_80 | _supported_T_81; // @[VAlu.scala 130:31]
- wire _supported_T_83 = io_in_bits_0_bits_op == 7'h2e; // @[VAlu.scala 133:16]
- wire _supported_T_84 = _supported_T_82 | _supported_T_83; // @[VAlu.scala 132:31]
- wire _supported_T_85 = io_in_bits_0_bits_op == 7'h30; // @[VAlu.scala 134:16]
- wire _supported_T_86 = _supported_T_84 | _supported_T_85; // @[VAlu.scala 133:32]
- wire _supported_T_87 = io_in_bits_0_bits_op == 7'h27; // @[VAlu.scala 135:16]
- wire _supported_T_88 = _supported_T_86 | _supported_T_87; // @[VAlu.scala 134:30]
- wire _supported_T_89 = io_in_bits_0_bits_op == 7'h28; // @[VAlu.scala 136:16]
- wire _supported_T_90 = _supported_T_88 | _supported_T_89; // @[VAlu.scala 135:29]
- wire _supported_T_91 = io_in_bits_0_bits_op == 7'h2b; // @[VAlu.scala 137:16]
- wire _supported_T_92 = _supported_T_90 | _supported_T_91; // @[VAlu.scala 136:30]
- wire _supported_T_93 = io_in_bits_0_bits_op == 7'h2c; // @[VAlu.scala 138:16]
- wire _supported_T_94 = _supported_T_92 | _supported_T_93; // @[VAlu.scala 137:30]
- wire _supported_T_95 = io_in_bits_0_bits_op == 7'h29; // @[VAlu.scala 139:16]
- wire _supported_T_96 = _supported_T_94 | _supported_T_95; // @[VAlu.scala 138:31]
- wire _supported_T_97 = io_in_bits_0_bits_op == 7'h2a; // @[VAlu.scala 140:16]
- wire _supported_T_98 = _supported_T_96 | _supported_T_97; // @[VAlu.scala 139:30]
- wire _supported_T_99 = io_in_bits_0_bits_op == 7'h2f; // @[VAlu.scala 141:16]
- wire _supported_T_100 = _supported_T_98 | _supported_T_99; // @[VAlu.scala 140:31]
- wire _supported_T_101 = io_in_bits_0_bits_op == 7'h56; // @[VAlu.scala 143:16]
- wire _supported_T_102 = _supported_T_100 | _supported_T_101; // @[VAlu.scala 141:30]
- wire _supported_T_103 = io_in_bits_0_bits_op == 7'h59; // @[VAlu.scala 144:16]
- wire _supported_T_104 = _supported_T_102 | _supported_T_103; // @[VAlu.scala 143:33]
- wire _supported_T_105 = io_in_bits_0_bits_op == 7'h58; // @[VAlu.scala 145:16]
- wire _supported_T_106 = _supported_T_104 | _supported_T_105; // @[VAlu.scala 144:33]
- wire _supported_T_107 = io_in_bits_0_bits_op == 7'h5b; // @[VAlu.scala 146:16]
- wire _supported_T_108 = _supported_T_106 | _supported_T_107; // @[VAlu.scala 145:34]
- wire _supported_T_109 = io_in_bits_0_bits_op == 7'h5c; // @[VAlu.scala 147:16]
- wire _supported_T_110 = _supported_T_108 | _supported_T_109; // @[VAlu.scala 146:34]
- wire _supported_T_111 = io_in_bits_0_bits_op == 7'h5d; // @[VAlu.scala 148:16]
- wire _supported_T_112 = _supported_T_110 | _supported_T_111; // @[VAlu.scala 147:29]
- wire _supported_T_113 = io_in_bits_0_bits_op == 7'h5e; // @[VAlu.scala 149:16]
- wire _supported_T_114 = _supported_T_112 | _supported_T_113; // @[VAlu.scala 148:29]
- wire _supported_T_115 = io_in_bits_0_bits_op == 7'h5f; // @[VAlu.scala 150:16]
- wire _supported_T_116 = _supported_T_114 | _supported_T_115; // @[VAlu.scala 149:29]
- wire _supported_T_117 = io_in_bits_0_bits_op == 7'h60; // @[VAlu.scala 151:16]
- wire _supported_T_118 = _supported_T_116 | _supported_T_117; // @[VAlu.scala 150:32]
- wire _supported_T_119 = io_in_bits_0_bits_op == 7'h63; // @[VAlu.scala 153:16]
- wire _supported_T_120 = _supported_T_118 | _supported_T_119; // @[VAlu.scala 151:29]
- wire _supported_T_121 = io_in_bits_0_bits_op == 7'h64; // @[VAlu.scala 154:16]
- wire supported = _supported_T_120 | _supported_T_121; // @[VAlu.scala 153:32]
- wire _T_1 = ~supported; // @[VAlu.scala 156:15]
- wire _T_3 = ~reset; // @[VAlu.scala 157:17]
- wire _T_14 = _supported_T_119 | _supported_T_121; // @[VAlu.scala 163:34]
- wire [1:0] sparse = io_in_bits_0_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
- wire _supported_T_123 = io_in_bits_1_bits_op == 7'h37; // @[VAlu.scala 88:16]
- wire _supported_T_124 = io_in_bits_1_bits_op == 7'hf | _supported_T_123; // @[VAlu.scala 87:30]
- wire _supported_T_125 = io_in_bits_1_bits_op == 7'h6; // @[VAlu.scala 89:16]
- wire _supported_T_126 = _supported_T_124 | _supported_T_125; // @[VAlu.scala 88:29]
- wire _supported_T_127 = io_in_bits_1_bits_op == 7'h33; // @[VAlu.scala 90:16]
- wire _supported_T_128 = _supported_T_126 | _supported_T_127; // @[VAlu.scala 89:29]
- wire _supported_T_129 = io_in_bits_1_bits_op == 7'h35; // @[VAlu.scala 91:16]
- wire _supported_T_130 = _supported_T_128 | _supported_T_129; // @[VAlu.scala 90:30]
- wire _supported_T_131 = io_in_bits_1_bits_op == 7'h12; // @[VAlu.scala 92:16]
- wire _supported_T_132 = _supported_T_130 | _supported_T_131; // @[VAlu.scala 91:30]
- wire _supported_T_133 = io_in_bits_1_bits_op == 7'h1; // @[VAlu.scala 93:16]
- wire _supported_T_134 = _supported_T_132 | _supported_T_133; // @[VAlu.scala 92:30]
- wire _supported_T_135 = io_in_bits_1_bits_op == 7'h3a; // @[VAlu.scala 94:16]
- wire _supported_T_136 = _supported_T_134 | _supported_T_135; // @[VAlu.scala 93:29]
- wire _supported_T_137 = io_in_bits_1_bits_op == 7'h3b; // @[VAlu.scala 95:16]
- wire _supported_T_138 = _supported_T_136 | _supported_T_137; // @[VAlu.scala 94:30]
- wire _supported_T_139 = io_in_bits_1_bits_op == 7'h10; // @[VAlu.scala 96:16]
- wire _supported_T_140 = _supported_T_138 | _supported_T_139; // @[VAlu.scala 95:30]
- wire _supported_T_141 = io_in_bits_1_bits_op == 7'h11; // @[VAlu.scala 97:16]
- wire _supported_T_142 = _supported_T_140 | _supported_T_141; // @[VAlu.scala 96:29]
- wire _supported_T_143 = io_in_bits_1_bits_op == 7'h38; // @[VAlu.scala 98:16]
- wire _supported_T_144 = _supported_T_142 | _supported_T_143; // @[VAlu.scala 97:29]
- wire _supported_T_145 = io_in_bits_1_bits_op == 7'h39; // @[VAlu.scala 99:16]
- wire _supported_T_146 = _supported_T_144 | _supported_T_145; // @[VAlu.scala 98:30]
- wire _supported_T_147 = io_in_bits_1_bits_op == 7'h8; // @[VAlu.scala 100:16]
- wire _supported_T_148 = _supported_T_146 | _supported_T_147; // @[VAlu.scala 99:30]
- wire _supported_T_149 = io_in_bits_1_bits_op == 7'h7; // @[VAlu.scala 101:16]
- wire _supported_T_150 = _supported_T_148 | _supported_T_149; // @[VAlu.scala 100:30]
- wire _supported_T_151 = io_in_bits_1_bits_op == 7'h34; // @[VAlu.scala 102:16]
- wire _supported_T_152 = _supported_T_150 | _supported_T_151; // @[VAlu.scala 101:29]
- wire _supported_T_153 = io_in_bits_1_bits_op == 7'h36; // @[VAlu.scala 103:16]
- wire _supported_T_154 = _supported_T_152 | _supported_T_153; // @[VAlu.scala 102:30]
- wire _supported_T_155 = io_in_bits_1_bits_op == 7'h9; // @[VAlu.scala 105:16]
- wire _supported_T_156 = _supported_T_154 | _supported_T_155; // @[VAlu.scala 103:30]
- wire _supported_T_157 = io_in_bits_1_bits_op == 7'ha; // @[VAlu.scala 106:16]
- wire _supported_T_158 = _supported_T_156 | _supported_T_157; // @[VAlu.scala 105:28]
- wire _supported_T_159 = io_in_bits_1_bits_op == 7'hb; // @[VAlu.scala 107:16]
- wire _supported_T_160 = _supported_T_158 | _supported_T_159; // @[VAlu.scala 106:28]
- wire _supported_T_161 = io_in_bits_1_bits_op == 7'hc; // @[VAlu.scala 108:16]
- wire _supported_T_162 = _supported_T_160 | _supported_T_161; // @[VAlu.scala 107:28]
- wire _supported_T_163 = io_in_bits_1_bits_op == 7'hd; // @[VAlu.scala 109:16]
- wire _supported_T_164 = _supported_T_162 | _supported_T_163; // @[VAlu.scala 108:28]
- wire _supported_T_165 = io_in_bits_1_bits_op == 7'he; // @[VAlu.scala 110:16]
- wire _supported_T_166 = _supported_T_164 | _supported_T_165; // @[VAlu.scala 109:28]
- wire _supported_T_167 = io_in_bits_1_bits_op == 7'h13; // @[VAlu.scala 112:16]
- wire _supported_T_168 = _supported_T_166 | _supported_T_167; // @[VAlu.scala 110:28]
- wire _supported_T_169 = io_in_bits_1_bits_op == 7'h19; // @[VAlu.scala 113:16]
- wire _supported_T_170 = _supported_T_168 | _supported_T_169; // @[VAlu.scala 112:29]
- wire _supported_T_171 = io_in_bits_1_bits_op == 7'h1a; // @[VAlu.scala 114:16]
- wire _supported_T_172 = _supported_T_170 | _supported_T_171; // @[VAlu.scala 113:29]
- wire _supported_T_173 = io_in_bits_1_bits_op == 7'h1b; // @[VAlu.scala 115:16]
- wire _supported_T_174 = _supported_T_172 | _supported_T_173; // @[VAlu.scala 114:29]
- wire _supported_T_175 = io_in_bits_1_bits_op == 7'h1c; // @[VAlu.scala 116:16]
- wire _supported_T_176 = _supported_T_174 | _supported_T_175; // @[VAlu.scala 115:30]
- wire _supported_T_177 = io_in_bits_1_bits_op == 7'h1d; // @[VAlu.scala 117:16]
- wire _supported_T_178 = _supported_T_176 | _supported_T_177; // @[VAlu.scala 116:28]
- wire _supported_T_179 = io_in_bits_1_bits_op == 7'h1e; // @[VAlu.scala 118:16]
- wire _supported_T_180 = _supported_T_178 | _supported_T_179; // @[VAlu.scala 117:29]
- wire _supported_T_181 = io_in_bits_1_bits_op == 7'h21; // @[VAlu.scala 119:16]
- wire _supported_T_182 = _supported_T_180 | _supported_T_181; // @[VAlu.scala 118:29]
- wire _supported_T_183 = io_in_bits_1_bits_op == 7'h16; // @[VAlu.scala 120:16]
- wire _supported_T_184 = _supported_T_182 | _supported_T_183; // @[VAlu.scala 119:32]
- wire _supported_T_185 = io_in_bits_1_bits_op == 7'h14; // @[VAlu.scala 121:16]
- wire _supported_T_186 = _supported_T_184 | _supported_T_185; // @[VAlu.scala 120:29]
- wire _supported_T_187 = io_in_bits_1_bits_op == 7'h17; // @[VAlu.scala 122:16]
- wire _supported_T_188 = _supported_T_186 | _supported_T_187; // @[VAlu.scala 121:28]
- wire _supported_T_189 = io_in_bits_1_bits_op == 7'h18; // @[VAlu.scala 123:16]
- wire _supported_T_190 = _supported_T_188 | _supported_T_189; // @[VAlu.scala 122:29]
- wire _supported_T_191 = io_in_bits_1_bits_op == 7'h15; // @[VAlu.scala 124:16]
- wire _supported_T_192 = _supported_T_190 | _supported_T_191; // @[VAlu.scala 123:29]
- wire _supported_T_193 = io_in_bits_1_bits_op == 7'h22; // @[VAlu.scala 126:16]
- wire _supported_T_194 = _supported_T_192 | _supported_T_193; // @[VAlu.scala 124:29]
- wire _supported_T_195 = io_in_bits_1_bits_op == 7'h23; // @[VAlu.scala 127:16]
- wire _supported_T_196 = _supported_T_194 | _supported_T_195; // @[VAlu.scala 126:29]
- wire _supported_T_197 = io_in_bits_1_bits_op == 7'h24; // @[VAlu.scala 128:16]
- wire _supported_T_198 = _supported_T_196 | _supported_T_197; // @[VAlu.scala 127:29]
- wire _supported_T_199 = io_in_bits_1_bits_op == 7'h25; // @[VAlu.scala 129:16]
- wire _supported_T_200 = _supported_T_198 | _supported_T_199; // @[VAlu.scala 128:29]
- wire _supported_T_201 = io_in_bits_1_bits_op == 7'h26; // @[VAlu.scala 130:16]
- wire _supported_T_202 = _supported_T_200 | _supported_T_201; // @[VAlu.scala 129:31]
- wire _supported_T_203 = io_in_bits_1_bits_op == 7'h2d; // @[VAlu.scala 132:16]
- wire _supported_T_204 = _supported_T_202 | _supported_T_203; // @[VAlu.scala 130:31]
- wire _supported_T_205 = io_in_bits_1_bits_op == 7'h2e; // @[VAlu.scala 133:16]
- wire _supported_T_206 = _supported_T_204 | _supported_T_205; // @[VAlu.scala 132:31]
- wire _supported_T_207 = io_in_bits_1_bits_op == 7'h30; // @[VAlu.scala 134:16]
- wire _supported_T_208 = _supported_T_206 | _supported_T_207; // @[VAlu.scala 133:32]
- wire _supported_T_209 = io_in_bits_1_bits_op == 7'h27; // @[VAlu.scala 135:16]
- wire _supported_T_210 = _supported_T_208 | _supported_T_209; // @[VAlu.scala 134:30]
- wire _supported_T_211 = io_in_bits_1_bits_op == 7'h28; // @[VAlu.scala 136:16]
- wire _supported_T_212 = _supported_T_210 | _supported_T_211; // @[VAlu.scala 135:29]
- wire _supported_T_213 = io_in_bits_1_bits_op == 7'h2b; // @[VAlu.scala 137:16]
- wire _supported_T_214 = _supported_T_212 | _supported_T_213; // @[VAlu.scala 136:30]
- wire _supported_T_215 = io_in_bits_1_bits_op == 7'h2c; // @[VAlu.scala 138:16]
- wire _supported_T_216 = _supported_T_214 | _supported_T_215; // @[VAlu.scala 137:30]
- wire _supported_T_217 = io_in_bits_1_bits_op == 7'h29; // @[VAlu.scala 139:16]
- wire _supported_T_218 = _supported_T_216 | _supported_T_217; // @[VAlu.scala 138:31]
- wire _supported_T_219 = io_in_bits_1_bits_op == 7'h2a; // @[VAlu.scala 140:16]
- wire _supported_T_220 = _supported_T_218 | _supported_T_219; // @[VAlu.scala 139:30]
- wire _supported_T_221 = io_in_bits_1_bits_op == 7'h2f; // @[VAlu.scala 141:16]
- wire _supported_T_222 = _supported_T_220 | _supported_T_221; // @[VAlu.scala 140:31]
- wire _supported_T_223 = io_in_bits_1_bits_op == 7'h56; // @[VAlu.scala 143:16]
- wire _supported_T_224 = _supported_T_222 | _supported_T_223; // @[VAlu.scala 141:30]
- wire _supported_T_225 = io_in_bits_1_bits_op == 7'h59; // @[VAlu.scala 144:16]
- wire _supported_T_226 = _supported_T_224 | _supported_T_225; // @[VAlu.scala 143:33]
- wire _supported_T_227 = io_in_bits_1_bits_op == 7'h58; // @[VAlu.scala 145:16]
- wire _supported_T_228 = _supported_T_226 | _supported_T_227; // @[VAlu.scala 144:33]
- wire _supported_T_229 = io_in_bits_1_bits_op == 7'h5b; // @[VAlu.scala 146:16]
- wire _supported_T_230 = _supported_T_228 | _supported_T_229; // @[VAlu.scala 145:34]
- wire _supported_T_231 = io_in_bits_1_bits_op == 7'h5c; // @[VAlu.scala 147:16]
- wire _supported_T_232 = _supported_T_230 | _supported_T_231; // @[VAlu.scala 146:34]
- wire _supported_T_233 = io_in_bits_1_bits_op == 7'h5d; // @[VAlu.scala 148:16]
- wire _supported_T_234 = _supported_T_232 | _supported_T_233; // @[VAlu.scala 147:29]
- wire _supported_T_235 = io_in_bits_1_bits_op == 7'h5e; // @[VAlu.scala 149:16]
- wire _supported_T_236 = _supported_T_234 | _supported_T_235; // @[VAlu.scala 148:29]
- wire _supported_T_237 = io_in_bits_1_bits_op == 7'h5f; // @[VAlu.scala 150:16]
- wire _supported_T_238 = _supported_T_236 | _supported_T_237; // @[VAlu.scala 149:29]
- wire _supported_T_239 = io_in_bits_1_bits_op == 7'h60; // @[VAlu.scala 151:16]
- wire _supported_T_240 = _supported_T_238 | _supported_T_239; // @[VAlu.scala 150:32]
- wire _supported_T_241 = io_in_bits_1_bits_op == 7'h63; // @[VAlu.scala 153:16]
- wire _supported_T_242 = _supported_T_240 | _supported_T_241; // @[VAlu.scala 151:29]
- wire _supported_T_243 = io_in_bits_1_bits_op == 7'h64; // @[VAlu.scala 154:16]
- wire supported_1 = _supported_T_242 | _supported_T_243; // @[VAlu.scala 153:32]
- wire _T_32 = ~supported_1; // @[VAlu.scala 156:15]
- wire _T_45 = _supported_T_241 | _supported_T_243; // @[VAlu.scala 163:34]
- wire [1:0] sparse_1 = io_in_bits_1_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
- wire _supported_T_245 = io_in_bits_2_bits_op == 7'h37; // @[VAlu.scala 88:16]
- wire _supported_T_246 = io_in_bits_2_bits_op == 7'hf | _supported_T_245; // @[VAlu.scala 87:30]
- wire _supported_T_247 = io_in_bits_2_bits_op == 7'h6; // @[VAlu.scala 89:16]
- wire _supported_T_248 = _supported_T_246 | _supported_T_247; // @[VAlu.scala 88:29]
- wire _supported_T_249 = io_in_bits_2_bits_op == 7'h33; // @[VAlu.scala 90:16]
- wire _supported_T_250 = _supported_T_248 | _supported_T_249; // @[VAlu.scala 89:29]
- wire _supported_T_251 = io_in_bits_2_bits_op == 7'h35; // @[VAlu.scala 91:16]
- wire _supported_T_252 = _supported_T_250 | _supported_T_251; // @[VAlu.scala 90:30]
- wire _supported_T_253 = io_in_bits_2_bits_op == 7'h12; // @[VAlu.scala 92:16]
- wire _supported_T_254 = _supported_T_252 | _supported_T_253; // @[VAlu.scala 91:30]
- wire _supported_T_255 = io_in_bits_2_bits_op == 7'h1; // @[VAlu.scala 93:16]
- wire _supported_T_256 = _supported_T_254 | _supported_T_255; // @[VAlu.scala 92:30]
- wire _supported_T_257 = io_in_bits_2_bits_op == 7'h3a; // @[VAlu.scala 94:16]
- wire _supported_T_258 = _supported_T_256 | _supported_T_257; // @[VAlu.scala 93:29]
- wire _supported_T_259 = io_in_bits_2_bits_op == 7'h3b; // @[VAlu.scala 95:16]
- wire _supported_T_260 = _supported_T_258 | _supported_T_259; // @[VAlu.scala 94:30]
- wire _supported_T_261 = io_in_bits_2_bits_op == 7'h10; // @[VAlu.scala 96:16]
- wire _supported_T_262 = _supported_T_260 | _supported_T_261; // @[VAlu.scala 95:30]
- wire _supported_T_263 = io_in_bits_2_bits_op == 7'h11; // @[VAlu.scala 97:16]
- wire _supported_T_264 = _supported_T_262 | _supported_T_263; // @[VAlu.scala 96:29]
- wire _supported_T_265 = io_in_bits_2_bits_op == 7'h38; // @[VAlu.scala 98:16]
- wire _supported_T_266 = _supported_T_264 | _supported_T_265; // @[VAlu.scala 97:29]
- wire _supported_T_267 = io_in_bits_2_bits_op == 7'h39; // @[VAlu.scala 99:16]
- wire _supported_T_268 = _supported_T_266 | _supported_T_267; // @[VAlu.scala 98:30]
- wire _supported_T_269 = io_in_bits_2_bits_op == 7'h8; // @[VAlu.scala 100:16]
- wire _supported_T_270 = _supported_T_268 | _supported_T_269; // @[VAlu.scala 99:30]
- wire _supported_T_271 = io_in_bits_2_bits_op == 7'h7; // @[VAlu.scala 101:16]
- wire _supported_T_272 = _supported_T_270 | _supported_T_271; // @[VAlu.scala 100:30]
- wire _supported_T_273 = io_in_bits_2_bits_op == 7'h34; // @[VAlu.scala 102:16]
- wire _supported_T_274 = _supported_T_272 | _supported_T_273; // @[VAlu.scala 101:29]
- wire _supported_T_275 = io_in_bits_2_bits_op == 7'h36; // @[VAlu.scala 103:16]
- wire _supported_T_276 = _supported_T_274 | _supported_T_275; // @[VAlu.scala 102:30]
- wire _supported_T_277 = io_in_bits_2_bits_op == 7'h9; // @[VAlu.scala 105:16]
- wire _supported_T_278 = _supported_T_276 | _supported_T_277; // @[VAlu.scala 103:30]
- wire _supported_T_279 = io_in_bits_2_bits_op == 7'ha; // @[VAlu.scala 106:16]
- wire _supported_T_280 = _supported_T_278 | _supported_T_279; // @[VAlu.scala 105:28]
- wire _supported_T_281 = io_in_bits_2_bits_op == 7'hb; // @[VAlu.scala 107:16]
- wire _supported_T_282 = _supported_T_280 | _supported_T_281; // @[VAlu.scala 106:28]
- wire _supported_T_283 = io_in_bits_2_bits_op == 7'hc; // @[VAlu.scala 108:16]
- wire _supported_T_284 = _supported_T_282 | _supported_T_283; // @[VAlu.scala 107:28]
- wire _supported_T_285 = io_in_bits_2_bits_op == 7'hd; // @[VAlu.scala 109:16]
- wire _supported_T_286 = _supported_T_284 | _supported_T_285; // @[VAlu.scala 108:28]
- wire _supported_T_287 = io_in_bits_2_bits_op == 7'he; // @[VAlu.scala 110:16]
- wire _supported_T_288 = _supported_T_286 | _supported_T_287; // @[VAlu.scala 109:28]
- wire _supported_T_289 = io_in_bits_2_bits_op == 7'h13; // @[VAlu.scala 112:16]
- wire _supported_T_290 = _supported_T_288 | _supported_T_289; // @[VAlu.scala 110:28]
- wire _supported_T_291 = io_in_bits_2_bits_op == 7'h19; // @[VAlu.scala 113:16]
- wire _supported_T_292 = _supported_T_290 | _supported_T_291; // @[VAlu.scala 112:29]
- wire _supported_T_293 = io_in_bits_2_bits_op == 7'h1a; // @[VAlu.scala 114:16]
- wire _supported_T_294 = _supported_T_292 | _supported_T_293; // @[VAlu.scala 113:29]
- wire _supported_T_295 = io_in_bits_2_bits_op == 7'h1b; // @[VAlu.scala 115:16]
- wire _supported_T_296 = _supported_T_294 | _supported_T_295; // @[VAlu.scala 114:29]
- wire _supported_T_297 = io_in_bits_2_bits_op == 7'h1c; // @[VAlu.scala 116:16]
- wire _supported_T_298 = _supported_T_296 | _supported_T_297; // @[VAlu.scala 115:30]
- wire _supported_T_299 = io_in_bits_2_bits_op == 7'h1d; // @[VAlu.scala 117:16]
- wire _supported_T_300 = _supported_T_298 | _supported_T_299; // @[VAlu.scala 116:28]
- wire _supported_T_301 = io_in_bits_2_bits_op == 7'h1e; // @[VAlu.scala 118:16]
- wire _supported_T_302 = _supported_T_300 | _supported_T_301; // @[VAlu.scala 117:29]
- wire _supported_T_303 = io_in_bits_2_bits_op == 7'h21; // @[VAlu.scala 119:16]
- wire _supported_T_304 = _supported_T_302 | _supported_T_303; // @[VAlu.scala 118:29]
- wire _supported_T_305 = io_in_bits_2_bits_op == 7'h16; // @[VAlu.scala 120:16]
- wire _supported_T_306 = _supported_T_304 | _supported_T_305; // @[VAlu.scala 119:32]
- wire _supported_T_307 = io_in_bits_2_bits_op == 7'h14; // @[VAlu.scala 121:16]
- wire _supported_T_308 = _supported_T_306 | _supported_T_307; // @[VAlu.scala 120:29]
- wire _supported_T_309 = io_in_bits_2_bits_op == 7'h17; // @[VAlu.scala 122:16]
- wire _supported_T_310 = _supported_T_308 | _supported_T_309; // @[VAlu.scala 121:28]
- wire _supported_T_311 = io_in_bits_2_bits_op == 7'h18; // @[VAlu.scala 123:16]
- wire _supported_T_312 = _supported_T_310 | _supported_T_311; // @[VAlu.scala 122:29]
- wire _supported_T_313 = io_in_bits_2_bits_op == 7'h15; // @[VAlu.scala 124:16]
- wire _supported_T_314 = _supported_T_312 | _supported_T_313; // @[VAlu.scala 123:29]
- wire _supported_T_315 = io_in_bits_2_bits_op == 7'h22; // @[VAlu.scala 126:16]
- wire _supported_T_316 = _supported_T_314 | _supported_T_315; // @[VAlu.scala 124:29]
- wire _supported_T_317 = io_in_bits_2_bits_op == 7'h23; // @[VAlu.scala 127:16]
- wire _supported_T_318 = _supported_T_316 | _supported_T_317; // @[VAlu.scala 126:29]
- wire _supported_T_319 = io_in_bits_2_bits_op == 7'h24; // @[VAlu.scala 128:16]
- wire _supported_T_320 = _supported_T_318 | _supported_T_319; // @[VAlu.scala 127:29]
- wire _supported_T_321 = io_in_bits_2_bits_op == 7'h25; // @[VAlu.scala 129:16]
- wire _supported_T_322 = _supported_T_320 | _supported_T_321; // @[VAlu.scala 128:29]
- wire _supported_T_323 = io_in_bits_2_bits_op == 7'h26; // @[VAlu.scala 130:16]
- wire _supported_T_324 = _supported_T_322 | _supported_T_323; // @[VAlu.scala 129:31]
- wire _supported_T_325 = io_in_bits_2_bits_op == 7'h2d; // @[VAlu.scala 132:16]
- wire _supported_T_326 = _supported_T_324 | _supported_T_325; // @[VAlu.scala 130:31]
- wire _supported_T_327 = io_in_bits_2_bits_op == 7'h2e; // @[VAlu.scala 133:16]
- wire _supported_T_328 = _supported_T_326 | _supported_T_327; // @[VAlu.scala 132:31]
- wire _supported_T_329 = io_in_bits_2_bits_op == 7'h30; // @[VAlu.scala 134:16]
- wire _supported_T_330 = _supported_T_328 | _supported_T_329; // @[VAlu.scala 133:32]
- wire _supported_T_331 = io_in_bits_2_bits_op == 7'h27; // @[VAlu.scala 135:16]
- wire _supported_T_332 = _supported_T_330 | _supported_T_331; // @[VAlu.scala 134:30]
- wire _supported_T_333 = io_in_bits_2_bits_op == 7'h28; // @[VAlu.scala 136:16]
- wire _supported_T_334 = _supported_T_332 | _supported_T_333; // @[VAlu.scala 135:29]
- wire _supported_T_335 = io_in_bits_2_bits_op == 7'h2b; // @[VAlu.scala 137:16]
- wire _supported_T_336 = _supported_T_334 | _supported_T_335; // @[VAlu.scala 136:30]
- wire _supported_T_337 = io_in_bits_2_bits_op == 7'h2c; // @[VAlu.scala 138:16]
- wire _supported_T_338 = _supported_T_336 | _supported_T_337; // @[VAlu.scala 137:30]
- wire _supported_T_339 = io_in_bits_2_bits_op == 7'h29; // @[VAlu.scala 139:16]
- wire _supported_T_340 = _supported_T_338 | _supported_T_339; // @[VAlu.scala 138:31]
- wire _supported_T_341 = io_in_bits_2_bits_op == 7'h2a; // @[VAlu.scala 140:16]
- wire _supported_T_342 = _supported_T_340 | _supported_T_341; // @[VAlu.scala 139:30]
- wire _supported_T_343 = io_in_bits_2_bits_op == 7'h2f; // @[VAlu.scala 141:16]
- wire _supported_T_344 = _supported_T_342 | _supported_T_343; // @[VAlu.scala 140:31]
- wire _supported_T_345 = io_in_bits_2_bits_op == 7'h56; // @[VAlu.scala 143:16]
- wire _supported_T_346 = _supported_T_344 | _supported_T_345; // @[VAlu.scala 141:30]
- wire _supported_T_347 = io_in_bits_2_bits_op == 7'h59; // @[VAlu.scala 144:16]
- wire _supported_T_348 = _supported_T_346 | _supported_T_347; // @[VAlu.scala 143:33]
- wire _supported_T_349 = io_in_bits_2_bits_op == 7'h58; // @[VAlu.scala 145:16]
- wire _supported_T_350 = _supported_T_348 | _supported_T_349; // @[VAlu.scala 144:33]
- wire _supported_T_351 = io_in_bits_2_bits_op == 7'h5b; // @[VAlu.scala 146:16]
- wire _supported_T_352 = _supported_T_350 | _supported_T_351; // @[VAlu.scala 145:34]
- wire _supported_T_353 = io_in_bits_2_bits_op == 7'h5c; // @[VAlu.scala 147:16]
- wire _supported_T_354 = _supported_T_352 | _supported_T_353; // @[VAlu.scala 146:34]
- wire _supported_T_355 = io_in_bits_2_bits_op == 7'h5d; // @[VAlu.scala 148:16]
- wire _supported_T_356 = _supported_T_354 | _supported_T_355; // @[VAlu.scala 147:29]
- wire _supported_T_357 = io_in_bits_2_bits_op == 7'h5e; // @[VAlu.scala 149:16]
- wire _supported_T_358 = _supported_T_356 | _supported_T_357; // @[VAlu.scala 148:29]
- wire _supported_T_359 = io_in_bits_2_bits_op == 7'h5f; // @[VAlu.scala 150:16]
- wire _supported_T_360 = _supported_T_358 | _supported_T_359; // @[VAlu.scala 149:29]
- wire _supported_T_361 = io_in_bits_2_bits_op == 7'h60; // @[VAlu.scala 151:16]
- wire _supported_T_362 = _supported_T_360 | _supported_T_361; // @[VAlu.scala 150:32]
- wire _supported_T_363 = io_in_bits_2_bits_op == 7'h63; // @[VAlu.scala 153:16]
- wire _supported_T_364 = _supported_T_362 | _supported_T_363; // @[VAlu.scala 151:29]
- wire _supported_T_365 = io_in_bits_2_bits_op == 7'h64; // @[VAlu.scala 154:16]
- wire supported_2 = _supported_T_364 | _supported_T_365; // @[VAlu.scala 153:32]
- wire _T_63 = ~supported_2; // @[VAlu.scala 156:15]
- wire _T_76 = _supported_T_363 | _supported_T_365; // @[VAlu.scala 163:34]
- wire [1:0] sparse_2 = io_in_bits_2_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
- wire _supported_T_367 = io_in_bits_3_bits_op == 7'h37; // @[VAlu.scala 88:16]
- wire _supported_T_368 = io_in_bits_3_bits_op == 7'hf | _supported_T_367; // @[VAlu.scala 87:30]
- wire _supported_T_369 = io_in_bits_3_bits_op == 7'h6; // @[VAlu.scala 89:16]
- wire _supported_T_370 = _supported_T_368 | _supported_T_369; // @[VAlu.scala 88:29]
- wire _supported_T_371 = io_in_bits_3_bits_op == 7'h33; // @[VAlu.scala 90:16]
- wire _supported_T_372 = _supported_T_370 | _supported_T_371; // @[VAlu.scala 89:29]
- wire _supported_T_373 = io_in_bits_3_bits_op == 7'h35; // @[VAlu.scala 91:16]
- wire _supported_T_374 = _supported_T_372 | _supported_T_373; // @[VAlu.scala 90:30]
- wire _supported_T_375 = io_in_bits_3_bits_op == 7'h12; // @[VAlu.scala 92:16]
- wire _supported_T_376 = _supported_T_374 | _supported_T_375; // @[VAlu.scala 91:30]
- wire _supported_T_377 = io_in_bits_3_bits_op == 7'h1; // @[VAlu.scala 93:16]
- wire _supported_T_378 = _supported_T_376 | _supported_T_377; // @[VAlu.scala 92:30]
- wire _supported_T_379 = io_in_bits_3_bits_op == 7'h3a; // @[VAlu.scala 94:16]
- wire _supported_T_380 = _supported_T_378 | _supported_T_379; // @[VAlu.scala 93:29]
- wire _supported_T_381 = io_in_bits_3_bits_op == 7'h3b; // @[VAlu.scala 95:16]
- wire _supported_T_382 = _supported_T_380 | _supported_T_381; // @[VAlu.scala 94:30]
- wire _supported_T_383 = io_in_bits_3_bits_op == 7'h10; // @[VAlu.scala 96:16]
- wire _supported_T_384 = _supported_T_382 | _supported_T_383; // @[VAlu.scala 95:30]
- wire _supported_T_385 = io_in_bits_3_bits_op == 7'h11; // @[VAlu.scala 97:16]
- wire _supported_T_386 = _supported_T_384 | _supported_T_385; // @[VAlu.scala 96:29]
- wire _supported_T_387 = io_in_bits_3_bits_op == 7'h38; // @[VAlu.scala 98:16]
- wire _supported_T_388 = _supported_T_386 | _supported_T_387; // @[VAlu.scala 97:29]
- wire _supported_T_389 = io_in_bits_3_bits_op == 7'h39; // @[VAlu.scala 99:16]
- wire _supported_T_390 = _supported_T_388 | _supported_T_389; // @[VAlu.scala 98:30]
- wire _supported_T_391 = io_in_bits_3_bits_op == 7'h8; // @[VAlu.scala 100:16]
- wire _supported_T_392 = _supported_T_390 | _supported_T_391; // @[VAlu.scala 99:30]
- wire _supported_T_393 = io_in_bits_3_bits_op == 7'h7; // @[VAlu.scala 101:16]
- wire _supported_T_394 = _supported_T_392 | _supported_T_393; // @[VAlu.scala 100:30]
- wire _supported_T_395 = io_in_bits_3_bits_op == 7'h34; // @[VAlu.scala 102:16]
- wire _supported_T_396 = _supported_T_394 | _supported_T_395; // @[VAlu.scala 101:29]
- wire _supported_T_397 = io_in_bits_3_bits_op == 7'h36; // @[VAlu.scala 103:16]
- wire _supported_T_398 = _supported_T_396 | _supported_T_397; // @[VAlu.scala 102:30]
- wire _supported_T_399 = io_in_bits_3_bits_op == 7'h9; // @[VAlu.scala 105:16]
- wire _supported_T_400 = _supported_T_398 | _supported_T_399; // @[VAlu.scala 103:30]
- wire _supported_T_401 = io_in_bits_3_bits_op == 7'ha; // @[VAlu.scala 106:16]
- wire _supported_T_402 = _supported_T_400 | _supported_T_401; // @[VAlu.scala 105:28]
- wire _supported_T_403 = io_in_bits_3_bits_op == 7'hb; // @[VAlu.scala 107:16]
- wire _supported_T_404 = _supported_T_402 | _supported_T_403; // @[VAlu.scala 106:28]
- wire _supported_T_405 = io_in_bits_3_bits_op == 7'hc; // @[VAlu.scala 108:16]
- wire _supported_T_406 = _supported_T_404 | _supported_T_405; // @[VAlu.scala 107:28]
- wire _supported_T_407 = io_in_bits_3_bits_op == 7'hd; // @[VAlu.scala 109:16]
- wire _supported_T_408 = _supported_T_406 | _supported_T_407; // @[VAlu.scala 108:28]
- wire _supported_T_409 = io_in_bits_3_bits_op == 7'he; // @[VAlu.scala 110:16]
- wire _supported_T_410 = _supported_T_408 | _supported_T_409; // @[VAlu.scala 109:28]
- wire _supported_T_411 = io_in_bits_3_bits_op == 7'h13; // @[VAlu.scala 112:16]
- wire _supported_T_412 = _supported_T_410 | _supported_T_411; // @[VAlu.scala 110:28]
- wire _supported_T_413 = io_in_bits_3_bits_op == 7'h19; // @[VAlu.scala 113:16]
- wire _supported_T_414 = _supported_T_412 | _supported_T_413; // @[VAlu.scala 112:29]
- wire _supported_T_415 = io_in_bits_3_bits_op == 7'h1a; // @[VAlu.scala 114:16]
- wire _supported_T_416 = _supported_T_414 | _supported_T_415; // @[VAlu.scala 113:29]
- wire _supported_T_417 = io_in_bits_3_bits_op == 7'h1b; // @[VAlu.scala 115:16]
- wire _supported_T_418 = _supported_T_416 | _supported_T_417; // @[VAlu.scala 114:29]
- wire _supported_T_419 = io_in_bits_3_bits_op == 7'h1c; // @[VAlu.scala 116:16]
- wire _supported_T_420 = _supported_T_418 | _supported_T_419; // @[VAlu.scala 115:30]
- wire _supported_T_421 = io_in_bits_3_bits_op == 7'h1d; // @[VAlu.scala 117:16]
- wire _supported_T_422 = _supported_T_420 | _supported_T_421; // @[VAlu.scala 116:28]
- wire _supported_T_423 = io_in_bits_3_bits_op == 7'h1e; // @[VAlu.scala 118:16]
- wire _supported_T_424 = _supported_T_422 | _supported_T_423; // @[VAlu.scala 117:29]
- wire _supported_T_425 = io_in_bits_3_bits_op == 7'h21; // @[VAlu.scala 119:16]
- wire _supported_T_426 = _supported_T_424 | _supported_T_425; // @[VAlu.scala 118:29]
- wire _supported_T_427 = io_in_bits_3_bits_op == 7'h16; // @[VAlu.scala 120:16]
- wire _supported_T_428 = _supported_T_426 | _supported_T_427; // @[VAlu.scala 119:32]
- wire _supported_T_429 = io_in_bits_3_bits_op == 7'h14; // @[VAlu.scala 121:16]
- wire _supported_T_430 = _supported_T_428 | _supported_T_429; // @[VAlu.scala 120:29]
- wire _supported_T_431 = io_in_bits_3_bits_op == 7'h17; // @[VAlu.scala 122:16]
- wire _supported_T_432 = _supported_T_430 | _supported_T_431; // @[VAlu.scala 121:28]
- wire _supported_T_433 = io_in_bits_3_bits_op == 7'h18; // @[VAlu.scala 123:16]
- wire _supported_T_434 = _supported_T_432 | _supported_T_433; // @[VAlu.scala 122:29]
- wire _supported_T_435 = io_in_bits_3_bits_op == 7'h15; // @[VAlu.scala 124:16]
- wire _supported_T_436 = _supported_T_434 | _supported_T_435; // @[VAlu.scala 123:29]
- wire _supported_T_437 = io_in_bits_3_bits_op == 7'h22; // @[VAlu.scala 126:16]
- wire _supported_T_438 = _supported_T_436 | _supported_T_437; // @[VAlu.scala 124:29]
- wire _supported_T_439 = io_in_bits_3_bits_op == 7'h23; // @[VAlu.scala 127:16]
- wire _supported_T_440 = _supported_T_438 | _supported_T_439; // @[VAlu.scala 126:29]
- wire _supported_T_441 = io_in_bits_3_bits_op == 7'h24; // @[VAlu.scala 128:16]
- wire _supported_T_442 = _supported_T_440 | _supported_T_441; // @[VAlu.scala 127:29]
- wire _supported_T_443 = io_in_bits_3_bits_op == 7'h25; // @[VAlu.scala 129:16]
- wire _supported_T_444 = _supported_T_442 | _supported_T_443; // @[VAlu.scala 128:29]
- wire _supported_T_445 = io_in_bits_3_bits_op == 7'h26; // @[VAlu.scala 130:16]
- wire _supported_T_446 = _supported_T_444 | _supported_T_445; // @[VAlu.scala 129:31]
- wire _supported_T_447 = io_in_bits_3_bits_op == 7'h2d; // @[VAlu.scala 132:16]
- wire _supported_T_448 = _supported_T_446 | _supported_T_447; // @[VAlu.scala 130:31]
- wire _supported_T_449 = io_in_bits_3_bits_op == 7'h2e; // @[VAlu.scala 133:16]
- wire _supported_T_450 = _supported_T_448 | _supported_T_449; // @[VAlu.scala 132:31]
- wire _supported_T_451 = io_in_bits_3_bits_op == 7'h30; // @[VAlu.scala 134:16]
- wire _supported_T_452 = _supported_T_450 | _supported_T_451; // @[VAlu.scala 133:32]
- wire _supported_T_453 = io_in_bits_3_bits_op == 7'h27; // @[VAlu.scala 135:16]
- wire _supported_T_454 = _supported_T_452 | _supported_T_453; // @[VAlu.scala 134:30]
- wire _supported_T_455 = io_in_bits_3_bits_op == 7'h28; // @[VAlu.scala 136:16]
- wire _supported_T_456 = _supported_T_454 | _supported_T_455; // @[VAlu.scala 135:29]
- wire _supported_T_457 = io_in_bits_3_bits_op == 7'h2b; // @[VAlu.scala 137:16]
- wire _supported_T_458 = _supported_T_456 | _supported_T_457; // @[VAlu.scala 136:30]
- wire _supported_T_459 = io_in_bits_3_bits_op == 7'h2c; // @[VAlu.scala 138:16]
- wire _supported_T_460 = _supported_T_458 | _supported_T_459; // @[VAlu.scala 137:30]
- wire _supported_T_461 = io_in_bits_3_bits_op == 7'h29; // @[VAlu.scala 139:16]
- wire _supported_T_462 = _supported_T_460 | _supported_T_461; // @[VAlu.scala 138:31]
- wire _supported_T_463 = io_in_bits_3_bits_op == 7'h2a; // @[VAlu.scala 140:16]
- wire _supported_T_464 = _supported_T_462 | _supported_T_463; // @[VAlu.scala 139:30]
- wire _supported_T_465 = io_in_bits_3_bits_op == 7'h2f; // @[VAlu.scala 141:16]
- wire _supported_T_466 = _supported_T_464 | _supported_T_465; // @[VAlu.scala 140:31]
- wire _supported_T_467 = io_in_bits_3_bits_op == 7'h56; // @[VAlu.scala 143:16]
- wire _supported_T_468 = _supported_T_466 | _supported_T_467; // @[VAlu.scala 141:30]
- wire _supported_T_469 = io_in_bits_3_bits_op == 7'h59; // @[VAlu.scala 144:16]
- wire _supported_T_470 = _supported_T_468 | _supported_T_469; // @[VAlu.scala 143:33]
- wire _supported_T_471 = io_in_bits_3_bits_op == 7'h58; // @[VAlu.scala 145:16]
- wire _supported_T_472 = _supported_T_470 | _supported_T_471; // @[VAlu.scala 144:33]
- wire _supported_T_473 = io_in_bits_3_bits_op == 7'h5b; // @[VAlu.scala 146:16]
- wire _supported_T_474 = _supported_T_472 | _supported_T_473; // @[VAlu.scala 145:34]
- wire _supported_T_475 = io_in_bits_3_bits_op == 7'h5c; // @[VAlu.scala 147:16]
- wire _supported_T_476 = _supported_T_474 | _supported_T_475; // @[VAlu.scala 146:34]
- wire _supported_T_477 = io_in_bits_3_bits_op == 7'h5d; // @[VAlu.scala 148:16]
- wire _supported_T_478 = _supported_T_476 | _supported_T_477; // @[VAlu.scala 147:29]
- wire _supported_T_479 = io_in_bits_3_bits_op == 7'h5e; // @[VAlu.scala 149:16]
- wire _supported_T_480 = _supported_T_478 | _supported_T_479; // @[VAlu.scala 148:29]
- wire _supported_T_481 = io_in_bits_3_bits_op == 7'h5f; // @[VAlu.scala 150:16]
- wire _supported_T_482 = _supported_T_480 | _supported_T_481; // @[VAlu.scala 149:29]
- wire _supported_T_483 = io_in_bits_3_bits_op == 7'h60; // @[VAlu.scala 151:16]
- wire _supported_T_484 = _supported_T_482 | _supported_T_483; // @[VAlu.scala 150:32]
- wire _supported_T_485 = io_in_bits_3_bits_op == 7'h63; // @[VAlu.scala 153:16]
- wire _supported_T_486 = _supported_T_484 | _supported_T_485; // @[VAlu.scala 151:29]
- wire _supported_T_487 = io_in_bits_3_bits_op == 7'h64; // @[VAlu.scala 154:16]
- wire supported_3 = _supported_T_486 | _supported_T_487; // @[VAlu.scala 153:32]
- wire _T_94 = ~supported_3; // @[VAlu.scala 156:15]
- wire _T_107 = _supported_T_485 | _supported_T_487; // @[VAlu.scala 163:34]
- wire [1:0] sparse_3 = io_in_bits_3_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
+ wire alu0_clock; // @[VAlu.scala 321:20]
+ wire alu0_reset; // @[VAlu.scala 321:20]
+ wire alu0_io_in_valid; // @[VAlu.scala 321:20]
+ wire [6:0] alu0_io_in_op; // @[VAlu.scala 321:20]
+ wire [2:0] alu0_io_in_f2; // @[VAlu.scala 321:20]
+ wire [2:0] alu0_io_in_sz; // @[VAlu.scala 321:20]
+ wire [5:0] alu0_io_in_vd_addr; // @[VAlu.scala 321:20]
+ wire [5:0] alu0_io_in_ve_addr; // @[VAlu.scala 321:20]
+ wire [31:0] alu0_io_in_sv_data; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_read_0_data; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_read_1_data; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_read_2_data; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_read_3_data; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_read_4_data; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_read_5_data; // @[VAlu.scala 321:20]
+ wire alu0_io_write_0_valid; // @[VAlu.scala 321:20]
+ wire [5:0] alu0_io_write_0_addr; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_write_0_data; // @[VAlu.scala 321:20]
+ wire alu0_io_write_1_valid; // @[VAlu.scala 321:20]
+ wire [5:0] alu0_io_write_1_addr; // @[VAlu.scala 321:20]
+ wire [255:0] alu0_io_write_1_data; // @[VAlu.scala 321:20]
+ wire alu0_io_whint_0_valid; // @[VAlu.scala 321:20]
+ wire [5:0] alu0_io_whint_0_addr; // @[VAlu.scala 321:20]
+ wire alu0_io_whint_1_valid; // @[VAlu.scala 321:20]
+ wire [5:0] alu0_io_whint_1_addr; // @[VAlu.scala 321:20]
+ wire alu1_clock; // @[VAlu.scala 355:20]
+ wire alu1_reset; // @[VAlu.scala 355:20]
+ wire alu1_io_in_valid; // @[VAlu.scala 355:20]
+ wire [6:0] alu1_io_in_op; // @[VAlu.scala 355:20]
+ wire [2:0] alu1_io_in_f2; // @[VAlu.scala 355:20]
+ wire [2:0] alu1_io_in_sz; // @[VAlu.scala 355:20]
+ wire [5:0] alu1_io_in_vd_addr; // @[VAlu.scala 355:20]
+ wire [5:0] alu1_io_in_ve_addr; // @[VAlu.scala 355:20]
+ wire [31:0] alu1_io_in_sv_data; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_read_0_data; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_read_1_data; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_read_2_data; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_read_3_data; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_read_4_data; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_read_5_data; // @[VAlu.scala 355:20]
+ wire alu1_io_write_0_valid; // @[VAlu.scala 355:20]
+ wire [5:0] alu1_io_write_0_addr; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_write_0_data; // @[VAlu.scala 355:20]
+ wire alu1_io_write_1_valid; // @[VAlu.scala 355:20]
+ wire [5:0] alu1_io_write_1_addr; // @[VAlu.scala 355:20]
+ wire [255:0] alu1_io_write_1_data; // @[VAlu.scala 355:20]
+ wire alu1_io_whint_0_valid; // @[VAlu.scala 355:20]
+ wire [5:0] alu1_io_whint_0_addr; // @[VAlu.scala 355:20]
+ wire alu1_io_whint_1_valid; // @[VAlu.scala 355:20]
+ wire [5:0] alu1_io_whint_1_addr; // @[VAlu.scala 355:20]
+ wire _T = io_in_valid & io_in_ready; // @[VAlu.scala 62:23]
+ wire _supported_T_1 = io_in_bits_0_bits_op == 7'h37; // @[VAlu.scala 68:16]
+ wire _supported_T_2 = io_in_bits_0_bits_op == 7'hf | _supported_T_1; // @[VAlu.scala 67:30]
+ wire _supported_T_3 = io_in_bits_0_bits_op == 7'h6; // @[VAlu.scala 69:16]
+ wire _supported_T_4 = _supported_T_2 | _supported_T_3; // @[VAlu.scala 68:29]
+ wire _supported_T_5 = io_in_bits_0_bits_op == 7'h33; // @[VAlu.scala 70:16]
+ wire _supported_T_6 = _supported_T_4 | _supported_T_5; // @[VAlu.scala 69:29]
+ wire _supported_T_7 = io_in_bits_0_bits_op == 7'h35; // @[VAlu.scala 71:16]
+ wire _supported_T_8 = _supported_T_6 | _supported_T_7; // @[VAlu.scala 70:30]
+ wire _supported_T_9 = io_in_bits_0_bits_op == 7'h12; // @[VAlu.scala 72:16]
+ wire _supported_T_10 = _supported_T_8 | _supported_T_9; // @[VAlu.scala 71:30]
+ wire _supported_T_11 = io_in_bits_0_bits_op == 7'h1; // @[VAlu.scala 73:16]
+ wire _supported_T_12 = _supported_T_10 | _supported_T_11; // @[VAlu.scala 72:30]
+ wire _supported_T_13 = io_in_bits_0_bits_op == 7'h3a; // @[VAlu.scala 74:16]
+ wire _supported_T_14 = _supported_T_12 | _supported_T_13; // @[VAlu.scala 73:29]
+ wire _supported_T_15 = io_in_bits_0_bits_op == 7'h3b; // @[VAlu.scala 75:16]
+ wire _supported_T_16 = _supported_T_14 | _supported_T_15; // @[VAlu.scala 74:30]
+ wire _supported_T_17 = io_in_bits_0_bits_op == 7'h10; // @[VAlu.scala 76:16]
+ wire _supported_T_18 = _supported_T_16 | _supported_T_17; // @[VAlu.scala 75:30]
+ wire _supported_T_19 = io_in_bits_0_bits_op == 7'h11; // @[VAlu.scala 77:16]
+ wire _supported_T_20 = _supported_T_18 | _supported_T_19; // @[VAlu.scala 76:29]
+ wire _supported_T_21 = io_in_bits_0_bits_op == 7'h38; // @[VAlu.scala 78:16]
+ wire _supported_T_22 = _supported_T_20 | _supported_T_21; // @[VAlu.scala 77:29]
+ wire _supported_T_23 = io_in_bits_0_bits_op == 7'h39; // @[VAlu.scala 79:16]
+ wire _supported_T_24 = _supported_T_22 | _supported_T_23; // @[VAlu.scala 78:30]
+ wire _supported_T_25 = io_in_bits_0_bits_op == 7'h8; // @[VAlu.scala 80:16]
+ wire _supported_T_26 = _supported_T_24 | _supported_T_25; // @[VAlu.scala 79:30]
+ wire _supported_T_27 = io_in_bits_0_bits_op == 7'h7; // @[VAlu.scala 81:16]
+ wire _supported_T_28 = _supported_T_26 | _supported_T_27; // @[VAlu.scala 80:30]
+ wire _supported_T_29 = io_in_bits_0_bits_op == 7'h34; // @[VAlu.scala 82:16]
+ wire _supported_T_30 = _supported_T_28 | _supported_T_29; // @[VAlu.scala 81:29]
+ wire _supported_T_31 = io_in_bits_0_bits_op == 7'h36; // @[VAlu.scala 83:16]
+ wire _supported_T_32 = _supported_T_30 | _supported_T_31; // @[VAlu.scala 82:30]
+ wire _supported_T_33 = io_in_bits_0_bits_op == 7'h9; // @[VAlu.scala 85:16]
+ wire _supported_T_34 = _supported_T_32 | _supported_T_33; // @[VAlu.scala 83:30]
+ wire _supported_T_35 = io_in_bits_0_bits_op == 7'ha; // @[VAlu.scala 86:16]
+ wire _supported_T_36 = _supported_T_34 | _supported_T_35; // @[VAlu.scala 85:28]
+ wire _supported_T_37 = io_in_bits_0_bits_op == 7'hb; // @[VAlu.scala 87:16]
+ wire _supported_T_38 = _supported_T_36 | _supported_T_37; // @[VAlu.scala 86:28]
+ wire _supported_T_39 = io_in_bits_0_bits_op == 7'hc; // @[VAlu.scala 88:16]
+ wire _supported_T_40 = _supported_T_38 | _supported_T_39; // @[VAlu.scala 87:28]
+ wire _supported_T_41 = io_in_bits_0_bits_op == 7'hd; // @[VAlu.scala 89:16]
+ wire _supported_T_42 = _supported_T_40 | _supported_T_41; // @[VAlu.scala 88:28]
+ wire _supported_T_43 = io_in_bits_0_bits_op == 7'he; // @[VAlu.scala 90:16]
+ wire _supported_T_44 = _supported_T_42 | _supported_T_43; // @[VAlu.scala 89:28]
+ wire _supported_T_45 = io_in_bits_0_bits_op == 7'h13; // @[VAlu.scala 92:16]
+ wire _supported_T_46 = _supported_T_44 | _supported_T_45; // @[VAlu.scala 90:28]
+ wire _supported_T_47 = io_in_bits_0_bits_op == 7'h19; // @[VAlu.scala 93:16]
+ wire _supported_T_48 = _supported_T_46 | _supported_T_47; // @[VAlu.scala 92:29]
+ wire _supported_T_49 = io_in_bits_0_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+ wire _supported_T_50 = _supported_T_48 | _supported_T_49; // @[VAlu.scala 93:29]
+ wire _supported_T_51 = io_in_bits_0_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+ wire _supported_T_52 = _supported_T_50 | _supported_T_51; // @[VAlu.scala 94:29]
+ wire _supported_T_53 = io_in_bits_0_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+ wire _supported_T_54 = _supported_T_52 | _supported_T_53; // @[VAlu.scala 95:30]
+ wire _supported_T_55 = io_in_bits_0_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+ wire _supported_T_56 = _supported_T_54 | _supported_T_55; // @[VAlu.scala 96:28]
+ wire _supported_T_57 = io_in_bits_0_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+ wire _supported_T_58 = _supported_T_56 | _supported_T_57; // @[VAlu.scala 97:29]
+ wire _supported_T_59 = io_in_bits_0_bits_op == 7'h21; // @[VAlu.scala 99:16]
+ wire _supported_T_60 = _supported_T_58 | _supported_T_59; // @[VAlu.scala 98:29]
+ wire _supported_T_61 = io_in_bits_0_bits_op == 7'h16; // @[VAlu.scala 100:16]
+ wire _supported_T_62 = _supported_T_60 | _supported_T_61; // @[VAlu.scala 99:32]
+ wire _supported_T_63 = io_in_bits_0_bits_op == 7'h14; // @[VAlu.scala 101:16]
+ wire _supported_T_64 = _supported_T_62 | _supported_T_63; // @[VAlu.scala 100:29]
+ wire _supported_T_65 = io_in_bits_0_bits_op == 7'h17; // @[VAlu.scala 102:16]
+ wire _supported_T_66 = _supported_T_64 | _supported_T_65; // @[VAlu.scala 101:28]
+ wire _supported_T_67 = io_in_bits_0_bits_op == 7'h18; // @[VAlu.scala 103:16]
+ wire _supported_T_68 = _supported_T_66 | _supported_T_67; // @[VAlu.scala 102:29]
+ wire _supported_T_69 = io_in_bits_0_bits_op == 7'h15; // @[VAlu.scala 104:16]
+ wire _supported_T_70 = _supported_T_68 | _supported_T_69; // @[VAlu.scala 103:29]
+ wire _supported_T_71 = io_in_bits_0_bits_op == 7'h22; // @[VAlu.scala 106:16]
+ wire _supported_T_72 = _supported_T_70 | _supported_T_71; // @[VAlu.scala 104:29]
+ wire _supported_T_73 = io_in_bits_0_bits_op == 7'h23; // @[VAlu.scala 107:16]
+ wire _supported_T_74 = _supported_T_72 | _supported_T_73; // @[VAlu.scala 106:29]
+ wire _supported_T_75 = io_in_bits_0_bits_op == 7'h24; // @[VAlu.scala 108:16]
+ wire _supported_T_76 = _supported_T_74 | _supported_T_75; // @[VAlu.scala 107:29]
+ wire _supported_T_77 = io_in_bits_0_bits_op == 7'h25; // @[VAlu.scala 109:16]
+ wire _supported_T_78 = _supported_T_76 | _supported_T_77; // @[VAlu.scala 108:29]
+ wire _supported_T_79 = io_in_bits_0_bits_op == 7'h26; // @[VAlu.scala 110:16]
+ wire _supported_T_80 = _supported_T_78 | _supported_T_79; // @[VAlu.scala 109:31]
+ wire _supported_T_81 = io_in_bits_0_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+ wire _supported_T_82 = _supported_T_80 | _supported_T_81; // @[VAlu.scala 110:31]
+ wire _supported_T_83 = io_in_bits_0_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+ wire _supported_T_84 = _supported_T_82 | _supported_T_83; // @[VAlu.scala 112:31]
+ wire _supported_T_85 = io_in_bits_0_bits_op == 7'h30; // @[VAlu.scala 114:16]
+ wire _supported_T_86 = _supported_T_84 | _supported_T_85; // @[VAlu.scala 113:32]
+ wire _supported_T_87 = io_in_bits_0_bits_op == 7'h27; // @[VAlu.scala 115:16]
+ wire _supported_T_88 = _supported_T_86 | _supported_T_87; // @[VAlu.scala 114:30]
+ wire _supported_T_89 = io_in_bits_0_bits_op == 7'h28; // @[VAlu.scala 116:16]
+ wire _supported_T_90 = _supported_T_88 | _supported_T_89; // @[VAlu.scala 115:29]
+ wire _supported_T_91 = io_in_bits_0_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+ wire _supported_T_92 = _supported_T_90 | _supported_T_91; // @[VAlu.scala 116:30]
+ wire _supported_T_93 = io_in_bits_0_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+ wire _supported_T_94 = _supported_T_92 | _supported_T_93; // @[VAlu.scala 117:30]
+ wire _supported_T_95 = io_in_bits_0_bits_op == 7'h29; // @[VAlu.scala 119:16]
+ wire _supported_T_96 = _supported_T_94 | _supported_T_95; // @[VAlu.scala 118:31]
+ wire _supported_T_97 = io_in_bits_0_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+ wire _supported_T_98 = _supported_T_96 | _supported_T_97; // @[VAlu.scala 119:30]
+ wire _supported_T_99 = io_in_bits_0_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+ wire _supported_T_100 = _supported_T_98 | _supported_T_99; // @[VAlu.scala 120:31]
+ wire _supported_T_101 = io_in_bits_0_bits_op == 7'h56; // @[VAlu.scala 123:16]
+ wire _supported_T_102 = _supported_T_100 | _supported_T_101; // @[VAlu.scala 121:30]
+ wire _supported_T_103 = io_in_bits_0_bits_op == 7'h59; // @[VAlu.scala 124:16]
+ wire _supported_T_104 = _supported_T_102 | _supported_T_103; // @[VAlu.scala 123:33]
+ wire _supported_T_105 = io_in_bits_0_bits_op == 7'h58; // @[VAlu.scala 125:16]
+ wire _supported_T_106 = _supported_T_104 | _supported_T_105; // @[VAlu.scala 124:33]
+ wire _supported_T_107 = io_in_bits_0_bits_op == 7'h5b; // @[VAlu.scala 126:16]
+ wire _supported_T_108 = _supported_T_106 | _supported_T_107; // @[VAlu.scala 125:34]
+ wire _supported_T_109 = io_in_bits_0_bits_op == 7'h5c; // @[VAlu.scala 127:16]
+ wire _supported_T_110 = _supported_T_108 | _supported_T_109; // @[VAlu.scala 126:34]
+ wire _supported_T_111 = io_in_bits_0_bits_op == 7'h5d; // @[VAlu.scala 128:16]
+ wire _supported_T_112 = _supported_T_110 | _supported_T_111; // @[VAlu.scala 127:29]
+ wire _supported_T_113 = io_in_bits_0_bits_op == 7'h5e; // @[VAlu.scala 129:16]
+ wire _supported_T_114 = _supported_T_112 | _supported_T_113; // @[VAlu.scala 128:29]
+ wire _supported_T_115 = io_in_bits_0_bits_op == 7'h5f; // @[VAlu.scala 130:16]
+ wire _supported_T_116 = _supported_T_114 | _supported_T_115; // @[VAlu.scala 129:29]
+ wire _supported_T_117 = io_in_bits_0_bits_op == 7'h60; // @[VAlu.scala 131:16]
+ wire _supported_T_118 = _supported_T_116 | _supported_T_117; // @[VAlu.scala 130:32]
+ wire _supported_T_119 = io_in_bits_0_bits_op == 7'h63; // @[VAlu.scala 133:16]
+ wire _supported_T_120 = _supported_T_118 | _supported_T_119; // @[VAlu.scala 131:29]
+ wire _supported_T_121 = io_in_bits_0_bits_op == 7'h64; // @[VAlu.scala 134:16]
+ wire supported = _supported_T_120 | _supported_T_121; // @[VAlu.scala 133:32]
+ wire _T_1 = ~supported; // @[VAlu.scala 136:15]
+ wire _T_3 = ~reset; // @[VAlu.scala 137:17]
+ wire _T_14 = _supported_T_119 | _supported_T_121; // @[VAlu.scala 143:34]
+ wire [1:0] sparse = io_in_bits_0_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
+ wire _supported_T_123 = io_in_bits_1_bits_op == 7'h37; // @[VAlu.scala 68:16]
+ wire _supported_T_124 = io_in_bits_1_bits_op == 7'hf | _supported_T_123; // @[VAlu.scala 67:30]
+ wire _supported_T_125 = io_in_bits_1_bits_op == 7'h6; // @[VAlu.scala 69:16]
+ wire _supported_T_126 = _supported_T_124 | _supported_T_125; // @[VAlu.scala 68:29]
+ wire _supported_T_127 = io_in_bits_1_bits_op == 7'h33; // @[VAlu.scala 70:16]
+ wire _supported_T_128 = _supported_T_126 | _supported_T_127; // @[VAlu.scala 69:29]
+ wire _supported_T_129 = io_in_bits_1_bits_op == 7'h35; // @[VAlu.scala 71:16]
+ wire _supported_T_130 = _supported_T_128 | _supported_T_129; // @[VAlu.scala 70:30]
+ wire _supported_T_131 = io_in_bits_1_bits_op == 7'h12; // @[VAlu.scala 72:16]
+ wire _supported_T_132 = _supported_T_130 | _supported_T_131; // @[VAlu.scala 71:30]
+ wire _supported_T_133 = io_in_bits_1_bits_op == 7'h1; // @[VAlu.scala 73:16]
+ wire _supported_T_134 = _supported_T_132 | _supported_T_133; // @[VAlu.scala 72:30]
+ wire _supported_T_135 = io_in_bits_1_bits_op == 7'h3a; // @[VAlu.scala 74:16]
+ wire _supported_T_136 = _supported_T_134 | _supported_T_135; // @[VAlu.scala 73:29]
+ wire _supported_T_137 = io_in_bits_1_bits_op == 7'h3b; // @[VAlu.scala 75:16]
+ wire _supported_T_138 = _supported_T_136 | _supported_T_137; // @[VAlu.scala 74:30]
+ wire _supported_T_139 = io_in_bits_1_bits_op == 7'h10; // @[VAlu.scala 76:16]
+ wire _supported_T_140 = _supported_T_138 | _supported_T_139; // @[VAlu.scala 75:30]
+ wire _supported_T_141 = io_in_bits_1_bits_op == 7'h11; // @[VAlu.scala 77:16]
+ wire _supported_T_142 = _supported_T_140 | _supported_T_141; // @[VAlu.scala 76:29]
+ wire _supported_T_143 = io_in_bits_1_bits_op == 7'h38; // @[VAlu.scala 78:16]
+ wire _supported_T_144 = _supported_T_142 | _supported_T_143; // @[VAlu.scala 77:29]
+ wire _supported_T_145 = io_in_bits_1_bits_op == 7'h39; // @[VAlu.scala 79:16]
+ wire _supported_T_146 = _supported_T_144 | _supported_T_145; // @[VAlu.scala 78:30]
+ wire _supported_T_147 = io_in_bits_1_bits_op == 7'h8; // @[VAlu.scala 80:16]
+ wire _supported_T_148 = _supported_T_146 | _supported_T_147; // @[VAlu.scala 79:30]
+ wire _supported_T_149 = io_in_bits_1_bits_op == 7'h7; // @[VAlu.scala 81:16]
+ wire _supported_T_150 = _supported_T_148 | _supported_T_149; // @[VAlu.scala 80:30]
+ wire _supported_T_151 = io_in_bits_1_bits_op == 7'h34; // @[VAlu.scala 82:16]
+ wire _supported_T_152 = _supported_T_150 | _supported_T_151; // @[VAlu.scala 81:29]
+ wire _supported_T_153 = io_in_bits_1_bits_op == 7'h36; // @[VAlu.scala 83:16]
+ wire _supported_T_154 = _supported_T_152 | _supported_T_153; // @[VAlu.scala 82:30]
+ wire _supported_T_155 = io_in_bits_1_bits_op == 7'h9; // @[VAlu.scala 85:16]
+ wire _supported_T_156 = _supported_T_154 | _supported_T_155; // @[VAlu.scala 83:30]
+ wire _supported_T_157 = io_in_bits_1_bits_op == 7'ha; // @[VAlu.scala 86:16]
+ wire _supported_T_158 = _supported_T_156 | _supported_T_157; // @[VAlu.scala 85:28]
+ wire _supported_T_159 = io_in_bits_1_bits_op == 7'hb; // @[VAlu.scala 87:16]
+ wire _supported_T_160 = _supported_T_158 | _supported_T_159; // @[VAlu.scala 86:28]
+ wire _supported_T_161 = io_in_bits_1_bits_op == 7'hc; // @[VAlu.scala 88:16]
+ wire _supported_T_162 = _supported_T_160 | _supported_T_161; // @[VAlu.scala 87:28]
+ wire _supported_T_163 = io_in_bits_1_bits_op == 7'hd; // @[VAlu.scala 89:16]
+ wire _supported_T_164 = _supported_T_162 | _supported_T_163; // @[VAlu.scala 88:28]
+ wire _supported_T_165 = io_in_bits_1_bits_op == 7'he; // @[VAlu.scala 90:16]
+ wire _supported_T_166 = _supported_T_164 | _supported_T_165; // @[VAlu.scala 89:28]
+ wire _supported_T_167 = io_in_bits_1_bits_op == 7'h13; // @[VAlu.scala 92:16]
+ wire _supported_T_168 = _supported_T_166 | _supported_T_167; // @[VAlu.scala 90:28]
+ wire _supported_T_169 = io_in_bits_1_bits_op == 7'h19; // @[VAlu.scala 93:16]
+ wire _supported_T_170 = _supported_T_168 | _supported_T_169; // @[VAlu.scala 92:29]
+ wire _supported_T_171 = io_in_bits_1_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+ wire _supported_T_172 = _supported_T_170 | _supported_T_171; // @[VAlu.scala 93:29]
+ wire _supported_T_173 = io_in_bits_1_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+ wire _supported_T_174 = _supported_T_172 | _supported_T_173; // @[VAlu.scala 94:29]
+ wire _supported_T_175 = io_in_bits_1_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+ wire _supported_T_176 = _supported_T_174 | _supported_T_175; // @[VAlu.scala 95:30]
+ wire _supported_T_177 = io_in_bits_1_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+ wire _supported_T_178 = _supported_T_176 | _supported_T_177; // @[VAlu.scala 96:28]
+ wire _supported_T_179 = io_in_bits_1_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+ wire _supported_T_180 = _supported_T_178 | _supported_T_179; // @[VAlu.scala 97:29]
+ wire _supported_T_181 = io_in_bits_1_bits_op == 7'h21; // @[VAlu.scala 99:16]
+ wire _supported_T_182 = _supported_T_180 | _supported_T_181; // @[VAlu.scala 98:29]
+ wire _supported_T_183 = io_in_bits_1_bits_op == 7'h16; // @[VAlu.scala 100:16]
+ wire _supported_T_184 = _supported_T_182 | _supported_T_183; // @[VAlu.scala 99:32]
+ wire _supported_T_185 = io_in_bits_1_bits_op == 7'h14; // @[VAlu.scala 101:16]
+ wire _supported_T_186 = _supported_T_184 | _supported_T_185; // @[VAlu.scala 100:29]
+ wire _supported_T_187 = io_in_bits_1_bits_op == 7'h17; // @[VAlu.scala 102:16]
+ wire _supported_T_188 = _supported_T_186 | _supported_T_187; // @[VAlu.scala 101:28]
+ wire _supported_T_189 = io_in_bits_1_bits_op == 7'h18; // @[VAlu.scala 103:16]
+ wire _supported_T_190 = _supported_T_188 | _supported_T_189; // @[VAlu.scala 102:29]
+ wire _supported_T_191 = io_in_bits_1_bits_op == 7'h15; // @[VAlu.scala 104:16]
+ wire _supported_T_192 = _supported_T_190 | _supported_T_191; // @[VAlu.scala 103:29]
+ wire _supported_T_193 = io_in_bits_1_bits_op == 7'h22; // @[VAlu.scala 106:16]
+ wire _supported_T_194 = _supported_T_192 | _supported_T_193; // @[VAlu.scala 104:29]
+ wire _supported_T_195 = io_in_bits_1_bits_op == 7'h23; // @[VAlu.scala 107:16]
+ wire _supported_T_196 = _supported_T_194 | _supported_T_195; // @[VAlu.scala 106:29]
+ wire _supported_T_197 = io_in_bits_1_bits_op == 7'h24; // @[VAlu.scala 108:16]
+ wire _supported_T_198 = _supported_T_196 | _supported_T_197; // @[VAlu.scala 107:29]
+ wire _supported_T_199 = io_in_bits_1_bits_op == 7'h25; // @[VAlu.scala 109:16]
+ wire _supported_T_200 = _supported_T_198 | _supported_T_199; // @[VAlu.scala 108:29]
+ wire _supported_T_201 = io_in_bits_1_bits_op == 7'h26; // @[VAlu.scala 110:16]
+ wire _supported_T_202 = _supported_T_200 | _supported_T_201; // @[VAlu.scala 109:31]
+ wire _supported_T_203 = io_in_bits_1_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+ wire _supported_T_204 = _supported_T_202 | _supported_T_203; // @[VAlu.scala 110:31]
+ wire _supported_T_205 = io_in_bits_1_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+ wire _supported_T_206 = _supported_T_204 | _supported_T_205; // @[VAlu.scala 112:31]
+ wire _supported_T_207 = io_in_bits_1_bits_op == 7'h30; // @[VAlu.scala 114:16]
+ wire _supported_T_208 = _supported_T_206 | _supported_T_207; // @[VAlu.scala 113:32]
+ wire _supported_T_209 = io_in_bits_1_bits_op == 7'h27; // @[VAlu.scala 115:16]
+ wire _supported_T_210 = _supported_T_208 | _supported_T_209; // @[VAlu.scala 114:30]
+ wire _supported_T_211 = io_in_bits_1_bits_op == 7'h28; // @[VAlu.scala 116:16]
+ wire _supported_T_212 = _supported_T_210 | _supported_T_211; // @[VAlu.scala 115:29]
+ wire _supported_T_213 = io_in_bits_1_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+ wire _supported_T_214 = _supported_T_212 | _supported_T_213; // @[VAlu.scala 116:30]
+ wire _supported_T_215 = io_in_bits_1_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+ wire _supported_T_216 = _supported_T_214 | _supported_T_215; // @[VAlu.scala 117:30]
+ wire _supported_T_217 = io_in_bits_1_bits_op == 7'h29; // @[VAlu.scala 119:16]
+ wire _supported_T_218 = _supported_T_216 | _supported_T_217; // @[VAlu.scala 118:31]
+ wire _supported_T_219 = io_in_bits_1_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+ wire _supported_T_220 = _supported_T_218 | _supported_T_219; // @[VAlu.scala 119:30]
+ wire _supported_T_221 = io_in_bits_1_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+ wire _supported_T_222 = _supported_T_220 | _supported_T_221; // @[VAlu.scala 120:31]
+ wire _supported_T_223 = io_in_bits_1_bits_op == 7'h56; // @[VAlu.scala 123:16]
+ wire _supported_T_224 = _supported_T_222 | _supported_T_223; // @[VAlu.scala 121:30]
+ wire _supported_T_225 = io_in_bits_1_bits_op == 7'h59; // @[VAlu.scala 124:16]
+ wire _supported_T_226 = _supported_T_224 | _supported_T_225; // @[VAlu.scala 123:33]
+ wire _supported_T_227 = io_in_bits_1_bits_op == 7'h58; // @[VAlu.scala 125:16]
+ wire _supported_T_228 = _supported_T_226 | _supported_T_227; // @[VAlu.scala 124:33]
+ wire _supported_T_229 = io_in_bits_1_bits_op == 7'h5b; // @[VAlu.scala 126:16]
+ wire _supported_T_230 = _supported_T_228 | _supported_T_229; // @[VAlu.scala 125:34]
+ wire _supported_T_231 = io_in_bits_1_bits_op == 7'h5c; // @[VAlu.scala 127:16]
+ wire _supported_T_232 = _supported_T_230 | _supported_T_231; // @[VAlu.scala 126:34]
+ wire _supported_T_233 = io_in_bits_1_bits_op == 7'h5d; // @[VAlu.scala 128:16]
+ wire _supported_T_234 = _supported_T_232 | _supported_T_233; // @[VAlu.scala 127:29]
+ wire _supported_T_235 = io_in_bits_1_bits_op == 7'h5e; // @[VAlu.scala 129:16]
+ wire _supported_T_236 = _supported_T_234 | _supported_T_235; // @[VAlu.scala 128:29]
+ wire _supported_T_237 = io_in_bits_1_bits_op == 7'h5f; // @[VAlu.scala 130:16]
+ wire _supported_T_238 = _supported_T_236 | _supported_T_237; // @[VAlu.scala 129:29]
+ wire _supported_T_239 = io_in_bits_1_bits_op == 7'h60; // @[VAlu.scala 131:16]
+ wire _supported_T_240 = _supported_T_238 | _supported_T_239; // @[VAlu.scala 130:32]
+ wire _supported_T_241 = io_in_bits_1_bits_op == 7'h63; // @[VAlu.scala 133:16]
+ wire _supported_T_242 = _supported_T_240 | _supported_T_241; // @[VAlu.scala 131:29]
+ wire _supported_T_243 = io_in_bits_1_bits_op == 7'h64; // @[VAlu.scala 134:16]
+ wire supported_1 = _supported_T_242 | _supported_T_243; // @[VAlu.scala 133:32]
+ wire _T_32 = ~supported_1; // @[VAlu.scala 136:15]
+ wire _T_45 = _supported_T_241 | _supported_T_243; // @[VAlu.scala 143:34]
+ wire [1:0] sparse_1 = io_in_bits_1_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
+ wire _supported_T_245 = io_in_bits_2_bits_op == 7'h37; // @[VAlu.scala 68:16]
+ wire _supported_T_246 = io_in_bits_2_bits_op == 7'hf | _supported_T_245; // @[VAlu.scala 67:30]
+ wire _supported_T_247 = io_in_bits_2_bits_op == 7'h6; // @[VAlu.scala 69:16]
+ wire _supported_T_248 = _supported_T_246 | _supported_T_247; // @[VAlu.scala 68:29]
+ wire _supported_T_249 = io_in_bits_2_bits_op == 7'h33; // @[VAlu.scala 70:16]
+ wire _supported_T_250 = _supported_T_248 | _supported_T_249; // @[VAlu.scala 69:29]
+ wire _supported_T_251 = io_in_bits_2_bits_op == 7'h35; // @[VAlu.scala 71:16]
+ wire _supported_T_252 = _supported_T_250 | _supported_T_251; // @[VAlu.scala 70:30]
+ wire _supported_T_253 = io_in_bits_2_bits_op == 7'h12; // @[VAlu.scala 72:16]
+ wire _supported_T_254 = _supported_T_252 | _supported_T_253; // @[VAlu.scala 71:30]
+ wire _supported_T_255 = io_in_bits_2_bits_op == 7'h1; // @[VAlu.scala 73:16]
+ wire _supported_T_256 = _supported_T_254 | _supported_T_255; // @[VAlu.scala 72:30]
+ wire _supported_T_257 = io_in_bits_2_bits_op == 7'h3a; // @[VAlu.scala 74:16]
+ wire _supported_T_258 = _supported_T_256 | _supported_T_257; // @[VAlu.scala 73:29]
+ wire _supported_T_259 = io_in_bits_2_bits_op == 7'h3b; // @[VAlu.scala 75:16]
+ wire _supported_T_260 = _supported_T_258 | _supported_T_259; // @[VAlu.scala 74:30]
+ wire _supported_T_261 = io_in_bits_2_bits_op == 7'h10; // @[VAlu.scala 76:16]
+ wire _supported_T_262 = _supported_T_260 | _supported_T_261; // @[VAlu.scala 75:30]
+ wire _supported_T_263 = io_in_bits_2_bits_op == 7'h11; // @[VAlu.scala 77:16]
+ wire _supported_T_264 = _supported_T_262 | _supported_T_263; // @[VAlu.scala 76:29]
+ wire _supported_T_265 = io_in_bits_2_bits_op == 7'h38; // @[VAlu.scala 78:16]
+ wire _supported_T_266 = _supported_T_264 | _supported_T_265; // @[VAlu.scala 77:29]
+ wire _supported_T_267 = io_in_bits_2_bits_op == 7'h39; // @[VAlu.scala 79:16]
+ wire _supported_T_268 = _supported_T_266 | _supported_T_267; // @[VAlu.scala 78:30]
+ wire _supported_T_269 = io_in_bits_2_bits_op == 7'h8; // @[VAlu.scala 80:16]
+ wire _supported_T_270 = _supported_T_268 | _supported_T_269; // @[VAlu.scala 79:30]
+ wire _supported_T_271 = io_in_bits_2_bits_op == 7'h7; // @[VAlu.scala 81:16]
+ wire _supported_T_272 = _supported_T_270 | _supported_T_271; // @[VAlu.scala 80:30]
+ wire _supported_T_273 = io_in_bits_2_bits_op == 7'h34; // @[VAlu.scala 82:16]
+ wire _supported_T_274 = _supported_T_272 | _supported_T_273; // @[VAlu.scala 81:29]
+ wire _supported_T_275 = io_in_bits_2_bits_op == 7'h36; // @[VAlu.scala 83:16]
+ wire _supported_T_276 = _supported_T_274 | _supported_T_275; // @[VAlu.scala 82:30]
+ wire _supported_T_277 = io_in_bits_2_bits_op == 7'h9; // @[VAlu.scala 85:16]
+ wire _supported_T_278 = _supported_T_276 | _supported_T_277; // @[VAlu.scala 83:30]
+ wire _supported_T_279 = io_in_bits_2_bits_op == 7'ha; // @[VAlu.scala 86:16]
+ wire _supported_T_280 = _supported_T_278 | _supported_T_279; // @[VAlu.scala 85:28]
+ wire _supported_T_281 = io_in_bits_2_bits_op == 7'hb; // @[VAlu.scala 87:16]
+ wire _supported_T_282 = _supported_T_280 | _supported_T_281; // @[VAlu.scala 86:28]
+ wire _supported_T_283 = io_in_bits_2_bits_op == 7'hc; // @[VAlu.scala 88:16]
+ wire _supported_T_284 = _supported_T_282 | _supported_T_283; // @[VAlu.scala 87:28]
+ wire _supported_T_285 = io_in_bits_2_bits_op == 7'hd; // @[VAlu.scala 89:16]
+ wire _supported_T_286 = _supported_T_284 | _supported_T_285; // @[VAlu.scala 88:28]
+ wire _supported_T_287 = io_in_bits_2_bits_op == 7'he; // @[VAlu.scala 90:16]
+ wire _supported_T_288 = _supported_T_286 | _supported_T_287; // @[VAlu.scala 89:28]
+ wire _supported_T_289 = io_in_bits_2_bits_op == 7'h13; // @[VAlu.scala 92:16]
+ wire _supported_T_290 = _supported_T_288 | _supported_T_289; // @[VAlu.scala 90:28]
+ wire _supported_T_291 = io_in_bits_2_bits_op == 7'h19; // @[VAlu.scala 93:16]
+ wire _supported_T_292 = _supported_T_290 | _supported_T_291; // @[VAlu.scala 92:29]
+ wire _supported_T_293 = io_in_bits_2_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+ wire _supported_T_294 = _supported_T_292 | _supported_T_293; // @[VAlu.scala 93:29]
+ wire _supported_T_295 = io_in_bits_2_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+ wire _supported_T_296 = _supported_T_294 | _supported_T_295; // @[VAlu.scala 94:29]
+ wire _supported_T_297 = io_in_bits_2_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+ wire _supported_T_298 = _supported_T_296 | _supported_T_297; // @[VAlu.scala 95:30]
+ wire _supported_T_299 = io_in_bits_2_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+ wire _supported_T_300 = _supported_T_298 | _supported_T_299; // @[VAlu.scala 96:28]
+ wire _supported_T_301 = io_in_bits_2_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+ wire _supported_T_302 = _supported_T_300 | _supported_T_301; // @[VAlu.scala 97:29]
+ wire _supported_T_303 = io_in_bits_2_bits_op == 7'h21; // @[VAlu.scala 99:16]
+ wire _supported_T_304 = _supported_T_302 | _supported_T_303; // @[VAlu.scala 98:29]
+ wire _supported_T_305 = io_in_bits_2_bits_op == 7'h16; // @[VAlu.scala 100:16]
+ wire _supported_T_306 = _supported_T_304 | _supported_T_305; // @[VAlu.scala 99:32]
+ wire _supported_T_307 = io_in_bits_2_bits_op == 7'h14; // @[VAlu.scala 101:16]
+ wire _supported_T_308 = _supported_T_306 | _supported_T_307; // @[VAlu.scala 100:29]
+ wire _supported_T_309 = io_in_bits_2_bits_op == 7'h17; // @[VAlu.scala 102:16]
+ wire _supported_T_310 = _supported_T_308 | _supported_T_309; // @[VAlu.scala 101:28]
+ wire _supported_T_311 = io_in_bits_2_bits_op == 7'h18; // @[VAlu.scala 103:16]
+ wire _supported_T_312 = _supported_T_310 | _supported_T_311; // @[VAlu.scala 102:29]
+ wire _supported_T_313 = io_in_bits_2_bits_op == 7'h15; // @[VAlu.scala 104:16]
+ wire _supported_T_314 = _supported_T_312 | _supported_T_313; // @[VAlu.scala 103:29]
+ wire _supported_T_315 = io_in_bits_2_bits_op == 7'h22; // @[VAlu.scala 106:16]
+ wire _supported_T_316 = _supported_T_314 | _supported_T_315; // @[VAlu.scala 104:29]
+ wire _supported_T_317 = io_in_bits_2_bits_op == 7'h23; // @[VAlu.scala 107:16]
+ wire _supported_T_318 = _supported_T_316 | _supported_T_317; // @[VAlu.scala 106:29]
+ wire _supported_T_319 = io_in_bits_2_bits_op == 7'h24; // @[VAlu.scala 108:16]
+ wire _supported_T_320 = _supported_T_318 | _supported_T_319; // @[VAlu.scala 107:29]
+ wire _supported_T_321 = io_in_bits_2_bits_op == 7'h25; // @[VAlu.scala 109:16]
+ wire _supported_T_322 = _supported_T_320 | _supported_T_321; // @[VAlu.scala 108:29]
+ wire _supported_T_323 = io_in_bits_2_bits_op == 7'h26; // @[VAlu.scala 110:16]
+ wire _supported_T_324 = _supported_T_322 | _supported_T_323; // @[VAlu.scala 109:31]
+ wire _supported_T_325 = io_in_bits_2_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+ wire _supported_T_326 = _supported_T_324 | _supported_T_325; // @[VAlu.scala 110:31]
+ wire _supported_T_327 = io_in_bits_2_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+ wire _supported_T_328 = _supported_T_326 | _supported_T_327; // @[VAlu.scala 112:31]
+ wire _supported_T_329 = io_in_bits_2_bits_op == 7'h30; // @[VAlu.scala 114:16]
+ wire _supported_T_330 = _supported_T_328 | _supported_T_329; // @[VAlu.scala 113:32]
+ wire _supported_T_331 = io_in_bits_2_bits_op == 7'h27; // @[VAlu.scala 115:16]
+ wire _supported_T_332 = _supported_T_330 | _supported_T_331; // @[VAlu.scala 114:30]
+ wire _supported_T_333 = io_in_bits_2_bits_op == 7'h28; // @[VAlu.scala 116:16]
+ wire _supported_T_334 = _supported_T_332 | _supported_T_333; // @[VAlu.scala 115:29]
+ wire _supported_T_335 = io_in_bits_2_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+ wire _supported_T_336 = _supported_T_334 | _supported_T_335; // @[VAlu.scala 116:30]
+ wire _supported_T_337 = io_in_bits_2_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+ wire _supported_T_338 = _supported_T_336 | _supported_T_337; // @[VAlu.scala 117:30]
+ wire _supported_T_339 = io_in_bits_2_bits_op == 7'h29; // @[VAlu.scala 119:16]
+ wire _supported_T_340 = _supported_T_338 | _supported_T_339; // @[VAlu.scala 118:31]
+ wire _supported_T_341 = io_in_bits_2_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+ wire _supported_T_342 = _supported_T_340 | _supported_T_341; // @[VAlu.scala 119:30]
+ wire _supported_T_343 = io_in_bits_2_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+ wire _supported_T_344 = _supported_T_342 | _supported_T_343; // @[VAlu.scala 120:31]
+ wire _supported_T_345 = io_in_bits_2_bits_op == 7'h56; // @[VAlu.scala 123:16]
+ wire _supported_T_346 = _supported_T_344 | _supported_T_345; // @[VAlu.scala 121:30]
+ wire _supported_T_347 = io_in_bits_2_bits_op == 7'h59; // @[VAlu.scala 124:16]
+ wire _supported_T_348 = _supported_T_346 | _supported_T_347; // @[VAlu.scala 123:33]
+ wire _supported_T_349 = io_in_bits_2_bits_op == 7'h58; // @[VAlu.scala 125:16]
+ wire _supported_T_350 = _supported_T_348 | _supported_T_349; // @[VAlu.scala 124:33]
+ wire _supported_T_351 = io_in_bits_2_bits_op == 7'h5b; // @[VAlu.scala 126:16]
+ wire _supported_T_352 = _supported_T_350 | _supported_T_351; // @[VAlu.scala 125:34]
+ wire _supported_T_353 = io_in_bits_2_bits_op == 7'h5c; // @[VAlu.scala 127:16]
+ wire _supported_T_354 = _supported_T_352 | _supported_T_353; // @[VAlu.scala 126:34]
+ wire _supported_T_355 = io_in_bits_2_bits_op == 7'h5d; // @[VAlu.scala 128:16]
+ wire _supported_T_356 = _supported_T_354 | _supported_T_355; // @[VAlu.scala 127:29]
+ wire _supported_T_357 = io_in_bits_2_bits_op == 7'h5e; // @[VAlu.scala 129:16]
+ wire _supported_T_358 = _supported_T_356 | _supported_T_357; // @[VAlu.scala 128:29]
+ wire _supported_T_359 = io_in_bits_2_bits_op == 7'h5f; // @[VAlu.scala 130:16]
+ wire _supported_T_360 = _supported_T_358 | _supported_T_359; // @[VAlu.scala 129:29]
+ wire _supported_T_361 = io_in_bits_2_bits_op == 7'h60; // @[VAlu.scala 131:16]
+ wire _supported_T_362 = _supported_T_360 | _supported_T_361; // @[VAlu.scala 130:32]
+ wire _supported_T_363 = io_in_bits_2_bits_op == 7'h63; // @[VAlu.scala 133:16]
+ wire _supported_T_364 = _supported_T_362 | _supported_T_363; // @[VAlu.scala 131:29]
+ wire _supported_T_365 = io_in_bits_2_bits_op == 7'h64; // @[VAlu.scala 134:16]
+ wire supported_2 = _supported_T_364 | _supported_T_365; // @[VAlu.scala 133:32]
+ wire _T_63 = ~supported_2; // @[VAlu.scala 136:15]
+ wire _T_76 = _supported_T_363 | _supported_T_365; // @[VAlu.scala 143:34]
+ wire [1:0] sparse_2 = io_in_bits_2_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
+ wire _supported_T_367 = io_in_bits_3_bits_op == 7'h37; // @[VAlu.scala 68:16]
+ wire _supported_T_368 = io_in_bits_3_bits_op == 7'hf | _supported_T_367; // @[VAlu.scala 67:30]
+ wire _supported_T_369 = io_in_bits_3_bits_op == 7'h6; // @[VAlu.scala 69:16]
+ wire _supported_T_370 = _supported_T_368 | _supported_T_369; // @[VAlu.scala 68:29]
+ wire _supported_T_371 = io_in_bits_3_bits_op == 7'h33; // @[VAlu.scala 70:16]
+ wire _supported_T_372 = _supported_T_370 | _supported_T_371; // @[VAlu.scala 69:29]
+ wire _supported_T_373 = io_in_bits_3_bits_op == 7'h35; // @[VAlu.scala 71:16]
+ wire _supported_T_374 = _supported_T_372 | _supported_T_373; // @[VAlu.scala 70:30]
+ wire _supported_T_375 = io_in_bits_3_bits_op == 7'h12; // @[VAlu.scala 72:16]
+ wire _supported_T_376 = _supported_T_374 | _supported_T_375; // @[VAlu.scala 71:30]
+ wire _supported_T_377 = io_in_bits_3_bits_op == 7'h1; // @[VAlu.scala 73:16]
+ wire _supported_T_378 = _supported_T_376 | _supported_T_377; // @[VAlu.scala 72:30]
+ wire _supported_T_379 = io_in_bits_3_bits_op == 7'h3a; // @[VAlu.scala 74:16]
+ wire _supported_T_380 = _supported_T_378 | _supported_T_379; // @[VAlu.scala 73:29]
+ wire _supported_T_381 = io_in_bits_3_bits_op == 7'h3b; // @[VAlu.scala 75:16]
+ wire _supported_T_382 = _supported_T_380 | _supported_T_381; // @[VAlu.scala 74:30]
+ wire _supported_T_383 = io_in_bits_3_bits_op == 7'h10; // @[VAlu.scala 76:16]
+ wire _supported_T_384 = _supported_T_382 | _supported_T_383; // @[VAlu.scala 75:30]
+ wire _supported_T_385 = io_in_bits_3_bits_op == 7'h11; // @[VAlu.scala 77:16]
+ wire _supported_T_386 = _supported_T_384 | _supported_T_385; // @[VAlu.scala 76:29]
+ wire _supported_T_387 = io_in_bits_3_bits_op == 7'h38; // @[VAlu.scala 78:16]
+ wire _supported_T_388 = _supported_T_386 | _supported_T_387; // @[VAlu.scala 77:29]
+ wire _supported_T_389 = io_in_bits_3_bits_op == 7'h39; // @[VAlu.scala 79:16]
+ wire _supported_T_390 = _supported_T_388 | _supported_T_389; // @[VAlu.scala 78:30]
+ wire _supported_T_391 = io_in_bits_3_bits_op == 7'h8; // @[VAlu.scala 80:16]
+ wire _supported_T_392 = _supported_T_390 | _supported_T_391; // @[VAlu.scala 79:30]
+ wire _supported_T_393 = io_in_bits_3_bits_op == 7'h7; // @[VAlu.scala 81:16]
+ wire _supported_T_394 = _supported_T_392 | _supported_T_393; // @[VAlu.scala 80:30]
+ wire _supported_T_395 = io_in_bits_3_bits_op == 7'h34; // @[VAlu.scala 82:16]
+ wire _supported_T_396 = _supported_T_394 | _supported_T_395; // @[VAlu.scala 81:29]
+ wire _supported_T_397 = io_in_bits_3_bits_op == 7'h36; // @[VAlu.scala 83:16]
+ wire _supported_T_398 = _supported_T_396 | _supported_T_397; // @[VAlu.scala 82:30]
+ wire _supported_T_399 = io_in_bits_3_bits_op == 7'h9; // @[VAlu.scala 85:16]
+ wire _supported_T_400 = _supported_T_398 | _supported_T_399; // @[VAlu.scala 83:30]
+ wire _supported_T_401 = io_in_bits_3_bits_op == 7'ha; // @[VAlu.scala 86:16]
+ wire _supported_T_402 = _supported_T_400 | _supported_T_401; // @[VAlu.scala 85:28]
+ wire _supported_T_403 = io_in_bits_3_bits_op == 7'hb; // @[VAlu.scala 87:16]
+ wire _supported_T_404 = _supported_T_402 | _supported_T_403; // @[VAlu.scala 86:28]
+ wire _supported_T_405 = io_in_bits_3_bits_op == 7'hc; // @[VAlu.scala 88:16]
+ wire _supported_T_406 = _supported_T_404 | _supported_T_405; // @[VAlu.scala 87:28]
+ wire _supported_T_407 = io_in_bits_3_bits_op == 7'hd; // @[VAlu.scala 89:16]
+ wire _supported_T_408 = _supported_T_406 | _supported_T_407; // @[VAlu.scala 88:28]
+ wire _supported_T_409 = io_in_bits_3_bits_op == 7'he; // @[VAlu.scala 90:16]
+ wire _supported_T_410 = _supported_T_408 | _supported_T_409; // @[VAlu.scala 89:28]
+ wire _supported_T_411 = io_in_bits_3_bits_op == 7'h13; // @[VAlu.scala 92:16]
+ wire _supported_T_412 = _supported_T_410 | _supported_T_411; // @[VAlu.scala 90:28]
+ wire _supported_T_413 = io_in_bits_3_bits_op == 7'h19; // @[VAlu.scala 93:16]
+ wire _supported_T_414 = _supported_T_412 | _supported_T_413; // @[VAlu.scala 92:29]
+ wire _supported_T_415 = io_in_bits_3_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+ wire _supported_T_416 = _supported_T_414 | _supported_T_415; // @[VAlu.scala 93:29]
+ wire _supported_T_417 = io_in_bits_3_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+ wire _supported_T_418 = _supported_T_416 | _supported_T_417; // @[VAlu.scala 94:29]
+ wire _supported_T_419 = io_in_bits_3_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+ wire _supported_T_420 = _supported_T_418 | _supported_T_419; // @[VAlu.scala 95:30]
+ wire _supported_T_421 = io_in_bits_3_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+ wire _supported_T_422 = _supported_T_420 | _supported_T_421; // @[VAlu.scala 96:28]
+ wire _supported_T_423 = io_in_bits_3_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+ wire _supported_T_424 = _supported_T_422 | _supported_T_423; // @[VAlu.scala 97:29]
+ wire _supported_T_425 = io_in_bits_3_bits_op == 7'h21; // @[VAlu.scala 99:16]
+ wire _supported_T_426 = _supported_T_424 | _supported_T_425; // @[VAlu.scala 98:29]
+ wire _supported_T_427 = io_in_bits_3_bits_op == 7'h16; // @[VAlu.scala 100:16]
+ wire _supported_T_428 = _supported_T_426 | _supported_T_427; // @[VAlu.scala 99:32]
+ wire _supported_T_429 = io_in_bits_3_bits_op == 7'h14; // @[VAlu.scala 101:16]
+ wire _supported_T_430 = _supported_T_428 | _supported_T_429; // @[VAlu.scala 100:29]
+ wire _supported_T_431 = io_in_bits_3_bits_op == 7'h17; // @[VAlu.scala 102:16]
+ wire _supported_T_432 = _supported_T_430 | _supported_T_431; // @[VAlu.scala 101:28]
+ wire _supported_T_433 = io_in_bits_3_bits_op == 7'h18; // @[VAlu.scala 103:16]
+ wire _supported_T_434 = _supported_T_432 | _supported_T_433; // @[VAlu.scala 102:29]
+ wire _supported_T_435 = io_in_bits_3_bits_op == 7'h15; // @[VAlu.scala 104:16]
+ wire _supported_T_436 = _supported_T_434 | _supported_T_435; // @[VAlu.scala 103:29]
+ wire _supported_T_437 = io_in_bits_3_bits_op == 7'h22; // @[VAlu.scala 106:16]
+ wire _supported_T_438 = _supported_T_436 | _supported_T_437; // @[VAlu.scala 104:29]
+ wire _supported_T_439 = io_in_bits_3_bits_op == 7'h23; // @[VAlu.scala 107:16]
+ wire _supported_T_440 = _supported_T_438 | _supported_T_439; // @[VAlu.scala 106:29]
+ wire _supported_T_441 = io_in_bits_3_bits_op == 7'h24; // @[VAlu.scala 108:16]
+ wire _supported_T_442 = _supported_T_440 | _supported_T_441; // @[VAlu.scala 107:29]
+ wire _supported_T_443 = io_in_bits_3_bits_op == 7'h25; // @[VAlu.scala 109:16]
+ wire _supported_T_444 = _supported_T_442 | _supported_T_443; // @[VAlu.scala 108:29]
+ wire _supported_T_445 = io_in_bits_3_bits_op == 7'h26; // @[VAlu.scala 110:16]
+ wire _supported_T_446 = _supported_T_444 | _supported_T_445; // @[VAlu.scala 109:31]
+ wire _supported_T_447 = io_in_bits_3_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+ wire _supported_T_448 = _supported_T_446 | _supported_T_447; // @[VAlu.scala 110:31]
+ wire _supported_T_449 = io_in_bits_3_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+ wire _supported_T_450 = _supported_T_448 | _supported_T_449; // @[VAlu.scala 112:31]
+ wire _supported_T_451 = io_in_bits_3_bits_op == 7'h30; // @[VAlu.scala 114:16]
+ wire _supported_T_452 = _supported_T_450 | _supported_T_451; // @[VAlu.scala 113:32]
+ wire _supported_T_453 = io_in_bits_3_bits_op == 7'h27; // @[VAlu.scala 115:16]
+ wire _supported_T_454 = _supported_T_452 | _supported_T_453; // @[VAlu.scala 114:30]
+ wire _supported_T_455 = io_in_bits_3_bits_op == 7'h28; // @[VAlu.scala 116:16]
+ wire _supported_T_456 = _supported_T_454 | _supported_T_455; // @[VAlu.scala 115:29]
+ wire _supported_T_457 = io_in_bits_3_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+ wire _supported_T_458 = _supported_T_456 | _supported_T_457; // @[VAlu.scala 116:30]
+ wire _supported_T_459 = io_in_bits_3_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+ wire _supported_T_460 = _supported_T_458 | _supported_T_459; // @[VAlu.scala 117:30]
+ wire _supported_T_461 = io_in_bits_3_bits_op == 7'h29; // @[VAlu.scala 119:16]
+ wire _supported_T_462 = _supported_T_460 | _supported_T_461; // @[VAlu.scala 118:31]
+ wire _supported_T_463 = io_in_bits_3_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+ wire _supported_T_464 = _supported_T_462 | _supported_T_463; // @[VAlu.scala 119:30]
+ wire _supported_T_465 = io_in_bits_3_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+ wire _supported_T_466 = _supported_T_464 | _supported_T_465; // @[VAlu.scala 120:31]
+ wire _supported_T_467 = io_in_bits_3_bits_op == 7'h56; // @[VAlu.scala 123:16]
+ wire _supported_T_468 = _supported_T_466 | _supported_T_467; // @[VAlu.scala 121:30]
+ wire _supported_T_469 = io_in_bits_3_bits_op == 7'h59; // @[VAlu.scala 124:16]
+ wire _supported_T_470 = _supported_T_468 | _supported_T_469; // @[VAlu.scala 123:33]
+ wire _supported_T_471 = io_in_bits_3_bits_op == 7'h58; // @[VAlu.scala 125:16]
+ wire _supported_T_472 = _supported_T_470 | _supported_T_471; // @[VAlu.scala 124:33]
+ wire _supported_T_473 = io_in_bits_3_bits_op == 7'h5b; // @[VAlu.scala 126:16]
+ wire _supported_T_474 = _supported_T_472 | _supported_T_473; // @[VAlu.scala 125:34]
+ wire _supported_T_475 = io_in_bits_3_bits_op == 7'h5c; // @[VAlu.scala 127:16]
+ wire _supported_T_476 = _supported_T_474 | _supported_T_475; // @[VAlu.scala 126:34]
+ wire _supported_T_477 = io_in_bits_3_bits_op == 7'h5d; // @[VAlu.scala 128:16]
+ wire _supported_T_478 = _supported_T_476 | _supported_T_477; // @[VAlu.scala 127:29]
+ wire _supported_T_479 = io_in_bits_3_bits_op == 7'h5e; // @[VAlu.scala 129:16]
+ wire _supported_T_480 = _supported_T_478 | _supported_T_479; // @[VAlu.scala 128:29]
+ wire _supported_T_481 = io_in_bits_3_bits_op == 7'h5f; // @[VAlu.scala 130:16]
+ wire _supported_T_482 = _supported_T_480 | _supported_T_481; // @[VAlu.scala 129:29]
+ wire _supported_T_483 = io_in_bits_3_bits_op == 7'h60; // @[VAlu.scala 131:16]
+ wire _supported_T_484 = _supported_T_482 | _supported_T_483; // @[VAlu.scala 130:32]
+ wire _supported_T_485 = io_in_bits_3_bits_op == 7'h63; // @[VAlu.scala 133:16]
+ wire _supported_T_486 = _supported_T_484 | _supported_T_485; // @[VAlu.scala 131:29]
+ wire _supported_T_487 = io_in_bits_3_bits_op == 7'h64; // @[VAlu.scala 134:16]
+ wire supported_3 = _supported_T_486 | _supported_T_487; // @[VAlu.scala 133:32]
+ wire _T_94 = ~supported_3; // @[VAlu.scala 136:15]
+ wire _T_107 = _supported_T_485 | _supported_T_487; // @[VAlu.scala 143:34]
+ wire [1:0] sparse_3 = io_in_bits_3_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
wire [3:0] _q0ready_tag_T_1 = q0_io_out_bits_vs_tag >> q0_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 119:20]
wire q0ready_tag = _q0ready_tag_T_1[0]; // @[VCommon.scala 119:20]
wire [6:0] q0ready_idx = {q0ready_tag,q0_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
@@ -73534,13 +73553,13 @@
wire [6:0] q0ready_idx_1 = {q0ready_tag_1,q0_io_out_bits_vt_addr}; // @[Cat.scala 31:58]
wire [127:0] _q0ready_T_6 = io_vrfsb >> q0ready_idx_1; // @[VCommon.scala 122:21]
wire _q0ready_T_9 = ~q0_io_out_bits_vt_valid | ~_q0ready_T_6[0]; // @[VCommon.scala 122:15]
- wire _q0ready_T_10 = _q0ready_T_4 & _q0ready_T_9; // @[VAlu.scala 270:62]
+ wire _q0ready_T_10 = _q0ready_T_4 & _q0ready_T_9; // @[VAlu.scala 250:62]
wire [3:0] _q0ready_tag_T_5 = q0_io_out_bits_vu_tag >> q0_io_out_bits_vu_addr[1:0]; // @[VCommon.scala 119:20]
wire q0ready_tag_2 = _q0ready_tag_T_5[0]; // @[VCommon.scala 119:20]
wire [6:0] q0ready_idx_2 = {q0ready_tag_2,q0_io_out_bits_vu_addr}; // @[Cat.scala 31:58]
wire [127:0] _q0ready_T_12 = io_vrfsb >> q0ready_idx_2; // @[VCommon.scala 122:21]
wire _q0ready_T_15 = ~q0_io_out_bits_vu_valid | ~_q0ready_T_12[0]; // @[VCommon.scala 122:15]
- wire q0ready = _q0ready_T_10 & _q0ready_T_15; // @[VAlu.scala 271:62]
+ wire q0ready = _q0ready_T_10 & _q0ready_T_15; // @[VAlu.scala 251:62]
wire [3:0] _q1ready_tag_T_1 = q1_io_out_bits_vs_tag >> q1_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 119:20]
wire q1ready_tag = _q1ready_tag_T_1[0]; // @[VCommon.scala 119:20]
wire [6:0] q1ready_idx = {q1ready_tag,q1_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
@@ -73551,33 +73570,33 @@
wire [6:0] q1ready_idx_1 = {q1ready_tag_1,q1_io_out_bits_vt_addr}; // @[Cat.scala 31:58]
wire [127:0] _q1ready_T_6 = io_vrfsb >> q1ready_idx_1; // @[VCommon.scala 122:21]
wire _q1ready_T_9 = ~q1_io_out_bits_vt_valid | ~_q1ready_T_6[0]; // @[VCommon.scala 122:15]
- wire _q1ready_T_10 = _q1ready_T_4 & _q1ready_T_9; // @[VAlu.scala 274:62]
+ wire _q1ready_T_10 = _q1ready_T_4 & _q1ready_T_9; // @[VAlu.scala 254:62]
wire [3:0] _q1ready_tag_T_5 = q1_io_out_bits_vu_tag >> q1_io_out_bits_vu_addr[1:0]; // @[VCommon.scala 119:20]
wire q1ready_tag_2 = _q1ready_tag_T_5[0]; // @[VCommon.scala 119:20]
wire [6:0] q1ready_idx_2 = {q1ready_tag_2,q1_io_out_bits_vu_addr}; // @[Cat.scala 31:58]
wire [127:0] _q1ready_T_12 = io_vrfsb >> q1ready_idx_2; // @[VCommon.scala 122:21]
wire _q1ready_T_15 = ~q1_io_out_bits_vu_valid | ~_q1ready_T_12[0]; // @[VCommon.scala 122:15]
- wire q1ready = _q1ready_T_10 & _q1ready_T_15; // @[VAlu.scala 275:62]
- reg alureg; // @[VAlu.scala 283:23]
- wire _alusel_1_T_2 = ~alureg; // @[VAlu.scala 288:72]
- wire alusel_1 = io_in_bits_0_valid & ~io_in_bits_0_bits_cmdsync ? ~alureg : alureg; // @[VAlu.scala 288:19]
- wire _alusel_2_T_2 = ~alusel_1; // @[VAlu.scala 289:72]
- wire alusel_2 = io_in_bits_1_valid & ~io_in_bits_1_bits_cmdsync ? ~alusel_1 : alusel_1; // @[VAlu.scala 289:19]
- wire _alusel_3_T_2 = ~alusel_2; // @[VAlu.scala 290:72]
- wire alusel_3 = io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync ? ~alusel_2 : alusel_2; // @[VAlu.scala 290:19]
- wire _alusel_4_T_2 = ~alusel_3; // @[VAlu.scala 291:72]
- wire _GEN_1 = _T & io_in_bits_0_valid; // @[VAlu.scala 157:17]
- wire _GEN_4 = _GEN_1 & _T_3; // @[VAlu.scala 159:15]
- wire _GEN_15 = _GEN_1 & _T_14 & _T_3; // @[VAlu.scala 165:17]
- wire _GEN_41 = _T & io_in_bits_1_valid; // @[VAlu.scala 157:17]
- wire _GEN_44 = _GEN_41 & _T_3; // @[VAlu.scala 159:15]
- wire _GEN_55 = _GEN_41 & _T_45 & _T_3; // @[VAlu.scala 165:17]
- wire _GEN_81 = _T & io_in_bits_2_valid; // @[VAlu.scala 157:17]
- wire _GEN_84 = _GEN_81 & _T_3; // @[VAlu.scala 159:15]
- wire _GEN_95 = _GEN_81 & _T_76 & _T_3; // @[VAlu.scala 165:17]
- wire _GEN_121 = _T & io_in_bits_3_valid; // @[VAlu.scala 157:17]
- wire _GEN_124 = _GEN_121 & _T_3; // @[VAlu.scala 159:15]
- wire _GEN_135 = _GEN_121 & _T_107 & _T_3; // @[VAlu.scala 165:17]
+ wire q1ready = _q1ready_T_10 & _q1ready_T_15; // @[VAlu.scala 255:62]
+ reg alureg; // @[VAlu.scala 263:23]
+ wire _alusel_1_T_2 = ~alureg; // @[VAlu.scala 268:72]
+ wire alusel_1 = io_in_bits_0_valid & ~io_in_bits_0_bits_cmdsync ? ~alureg : alureg; // @[VAlu.scala 268:19]
+ wire _alusel_2_T_2 = ~alusel_1; // @[VAlu.scala 269:72]
+ wire alusel_2 = io_in_bits_1_valid & ~io_in_bits_1_bits_cmdsync ? ~alusel_1 : alusel_1; // @[VAlu.scala 269:19]
+ wire _alusel_3_T_2 = ~alusel_2; // @[VAlu.scala 270:72]
+ wire alusel_3 = io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync ? ~alusel_2 : alusel_2; // @[VAlu.scala 270:19]
+ wire _alusel_4_T_2 = ~alusel_3; // @[VAlu.scala 271:72]
+ wire _GEN_1 = _T & io_in_bits_0_valid; // @[VAlu.scala 137:17]
+ wire _GEN_4 = _GEN_1 & _T_3; // @[VAlu.scala 139:15]
+ wire _GEN_15 = _GEN_1 & _T_14 & _T_3; // @[VAlu.scala 145:17]
+ wire _GEN_41 = _T & io_in_bits_1_valid; // @[VAlu.scala 137:17]
+ wire _GEN_44 = _GEN_41 & _T_3; // @[VAlu.scala 139:15]
+ wire _GEN_55 = _GEN_41 & _T_45 & _T_3; // @[VAlu.scala 145:17]
+ wire _GEN_81 = _T & io_in_bits_2_valid; // @[VAlu.scala 137:17]
+ wire _GEN_84 = _GEN_81 & _T_3; // @[VAlu.scala 139:15]
+ wire _GEN_95 = _GEN_81 & _T_76 & _T_3; // @[VAlu.scala 145:17]
+ wire _GEN_121 = _T & io_in_bits_3_valid; // @[VAlu.scala 137:17]
+ wire _GEN_124 = _GEN_121 & _T_3; // @[VAlu.scala 139:15]
+ wire _GEN_135 = _GEN_121 & _T_107 & _T_3; // @[VAlu.scala 145:17]
VCmdq q0 ( // @[VCmdq.scala 14:11]
.clock(q0_clock),
.reset(q0_reset),
@@ -73826,7 +73845,7 @@
.io_out_bits_cmdsync(q1_io_out_bits_cmdsync),
.io_active(q1_io_active)
);
- VAluInt alu0 ( // @[VAlu.scala 341:20]
+ VAluInt alu0 ( // @[VAlu.scala 321:20]
.clock(alu0_clock),
.reset(alu0_reset),
.io_in_valid(alu0_io_in_valid),
@@ -73853,7 +73872,7 @@
.io_whint_1_valid(alu0_io_whint_1_valid),
.io_whint_1_addr(alu0_io_whint_1_addr)
);
- VAluInt_1 alu1 ( // @[VAlu.scala 375:20]
+ VAluInt_1 alu1 ( // @[VAlu.scala 355:20]
.clock(alu1_clock),
.reset(alu1_reset),
.io_in_valid(alu1_io_in_valid),
@@ -73880,285 +73899,285 @@
.io_whint_1_valid(alu1_io_whint_1_valid),
.io_whint_1_addr(alu1_io_whint_1_addr)
);
- assign io_in_ready = q0_io_in_ready & q1_io_in_ready; // @[VAlu.scala 265:33]
- assign io_active = q0_io_active | q1_io_active; // @[VAlu.scala 409:29]
- assign io_read_0_valid = q0_io_out_bits_vs_valid; // @[VAlu.scala 304:20]
- assign io_read_0_addr = q0_io_out_bits_vs_addr; // @[VAlu.scala 311:19]
- assign io_read_1_valid = q0_io_out_bits_vt_valid; // @[VAlu.scala 305:20]
- assign io_read_1_addr = q0_io_out_bits_vt_addr; // @[VAlu.scala 312:19]
- assign io_read_2_valid = q0_io_out_bits_vu_valid; // @[VAlu.scala 306:20]
- assign io_read_2_addr = q0_io_out_bits_vu_addr; // @[VAlu.scala 313:19]
- assign io_read_3_valid = q1_io_out_bits_vs_valid; // @[VAlu.scala 307:20]
- assign io_read_3_addr = q1_io_out_bits_vs_addr; // @[VAlu.scala 314:19]
- assign io_read_4_valid = q1_io_out_bits_vt_valid; // @[VAlu.scala 308:20]
- assign io_read_4_addr = q1_io_out_bits_vt_addr; // @[VAlu.scala 315:19]
- assign io_read_5_valid = q1_io_out_bits_vu_valid; // @[VAlu.scala 309:20]
- assign io_read_5_addr = q1_io_out_bits_vu_addr; // @[VAlu.scala 316:19]
- assign io_write_0_valid = alu0_io_write_0_valid; // @[VAlu.scala 359:21]
- assign io_write_0_addr = alu0_io_write_0_addr; // @[VAlu.scala 360:20]
- assign io_write_0_data = alu0_io_write_0_data; // @[VAlu.scala 361:20]
- assign io_write_1_valid = alu0_io_write_1_valid; // @[VAlu.scala 363:21]
- assign io_write_1_addr = alu0_io_write_1_addr; // @[VAlu.scala 364:20]
- assign io_write_1_data = alu0_io_write_1_data; // @[VAlu.scala 365:20]
- assign io_write_2_valid = alu1_io_write_0_valid; // @[VAlu.scala 393:21]
- assign io_write_2_addr = alu1_io_write_0_addr; // @[VAlu.scala 394:20]
- assign io_write_2_data = alu1_io_write_0_data; // @[VAlu.scala 395:20]
- assign io_write_3_valid = alu1_io_write_1_valid; // @[VAlu.scala 397:21]
- assign io_write_3_addr = alu1_io_write_1_addr; // @[VAlu.scala 398:20]
- assign io_write_3_data = alu1_io_write_1_data; // @[VAlu.scala 399:20]
- assign io_whint_0_valid = alu0_io_whint_0_valid; // @[VAlu.scala 367:21]
- assign io_whint_0_addr = alu0_io_whint_0_addr; // @[VAlu.scala 368:20]
- assign io_whint_1_valid = alu0_io_whint_1_valid; // @[VAlu.scala 370:21]
- assign io_whint_1_addr = alu0_io_whint_1_addr; // @[VAlu.scala 371:20]
- assign io_whint_2_valid = alu1_io_whint_0_valid; // @[VAlu.scala 401:21]
- assign io_whint_2_addr = alu1_io_whint_0_addr; // @[VAlu.scala 402:20]
- assign io_whint_3_valid = alu1_io_whint_1_valid; // @[VAlu.scala 404:21]
- assign io_whint_3_addr = alu1_io_whint_1_addr; // @[VAlu.scala 405:20]
- assign io_scalar_0_valid = q0_io_out_bits_sv_valid; // @[VAlu.scala 325:22]
- assign io_scalar_0_data = q0_io_out_bits_sv_data; // @[VAlu.scala 328:21]
- assign io_scalar_1_valid = q1_io_out_bits_sv_valid; // @[VAlu.scala 326:22]
- assign io_scalar_1_data = q1_io_out_bits_sv_data; // @[VAlu.scala 329:21]
+ assign io_in_ready = q0_io_in_ready & q1_io_in_ready; // @[VAlu.scala 245:33]
+ assign io_active = q0_io_active | q1_io_active; // @[VAlu.scala 389:29]
+ assign io_read_0_valid = q0_io_out_bits_vs_valid; // @[VAlu.scala 284:20]
+ assign io_read_0_addr = q0_io_out_bits_vs_addr; // @[VAlu.scala 291:19]
+ assign io_read_1_valid = q0_io_out_bits_vt_valid; // @[VAlu.scala 285:20]
+ assign io_read_1_addr = q0_io_out_bits_vt_addr; // @[VAlu.scala 292:19]
+ assign io_read_2_valid = q0_io_out_bits_vu_valid; // @[VAlu.scala 286:20]
+ assign io_read_2_addr = q0_io_out_bits_vu_addr; // @[VAlu.scala 293:19]
+ assign io_read_3_valid = q1_io_out_bits_vs_valid; // @[VAlu.scala 287:20]
+ assign io_read_3_addr = q1_io_out_bits_vs_addr; // @[VAlu.scala 294:19]
+ assign io_read_4_valid = q1_io_out_bits_vt_valid; // @[VAlu.scala 288:20]
+ assign io_read_4_addr = q1_io_out_bits_vt_addr; // @[VAlu.scala 295:19]
+ assign io_read_5_valid = q1_io_out_bits_vu_valid; // @[VAlu.scala 289:20]
+ assign io_read_5_addr = q1_io_out_bits_vu_addr; // @[VAlu.scala 296:19]
+ assign io_write_0_valid = alu0_io_write_0_valid; // @[VAlu.scala 339:21]
+ assign io_write_0_addr = alu0_io_write_0_addr; // @[VAlu.scala 340:20]
+ assign io_write_0_data = alu0_io_write_0_data; // @[VAlu.scala 341:20]
+ assign io_write_1_valid = alu0_io_write_1_valid; // @[VAlu.scala 343:21]
+ assign io_write_1_addr = alu0_io_write_1_addr; // @[VAlu.scala 344:20]
+ assign io_write_1_data = alu0_io_write_1_data; // @[VAlu.scala 345:20]
+ assign io_write_2_valid = alu1_io_write_0_valid; // @[VAlu.scala 373:21]
+ assign io_write_2_addr = alu1_io_write_0_addr; // @[VAlu.scala 374:20]
+ assign io_write_2_data = alu1_io_write_0_data; // @[VAlu.scala 375:20]
+ assign io_write_3_valid = alu1_io_write_1_valid; // @[VAlu.scala 377:21]
+ assign io_write_3_addr = alu1_io_write_1_addr; // @[VAlu.scala 378:20]
+ assign io_write_3_data = alu1_io_write_1_data; // @[VAlu.scala 379:20]
+ assign io_whint_0_valid = alu0_io_whint_0_valid; // @[VAlu.scala 347:21]
+ assign io_whint_0_addr = alu0_io_whint_0_addr; // @[VAlu.scala 348:20]
+ assign io_whint_1_valid = alu0_io_whint_1_valid; // @[VAlu.scala 350:21]
+ assign io_whint_1_addr = alu0_io_whint_1_addr; // @[VAlu.scala 351:20]
+ assign io_whint_2_valid = alu1_io_whint_0_valid; // @[VAlu.scala 381:21]
+ assign io_whint_2_addr = alu1_io_whint_0_addr; // @[VAlu.scala 382:20]
+ assign io_whint_3_valid = alu1_io_whint_1_valid; // @[VAlu.scala 384:21]
+ assign io_whint_3_addr = alu1_io_whint_1_addr; // @[VAlu.scala 385:20]
+ assign io_scalar_0_valid = q0_io_out_bits_sv_valid; // @[VAlu.scala 305:22]
+ assign io_scalar_0_data = q0_io_out_bits_sv_data; // @[VAlu.scala 308:21]
+ assign io_scalar_1_valid = q1_io_out_bits_sv_valid; // @[VAlu.scala 306:22]
+ assign io_scalar_1_data = q1_io_out_bits_sv_data; // @[VAlu.scala 309:21]
assign q0_clock = clock;
assign q0_reset = reset;
- assign q0_io_in_valid = io_in_valid & q1_io_in_ready; // @[VAlu.scala 263:33]
- assign q0_io_in_bits_0_valid = io_in_bits_0_valid & (_alusel_1_T_2 | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 298:51]
- assign q0_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_valid = io_in_bits_1_valid & (_alusel_2_T_2 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 298:51]
- assign q0_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_valid = io_in_bits_2_valid & (_alusel_3_T_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 298:51]
- assign q0_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_valid = io_in_bits_3_valid & (_alusel_4_T_2 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 298:51]
- assign q0_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 267:17]
- assign q0_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 267:17]
- assign q0_io_out_ready = q0ready & (~q0_io_out_bits_cmdsync | q1_io_out_valid & q1ready & q1_io_out_bits_cmdsync); // @[VAlu.scala 278:30]
+ assign q0_io_in_valid = io_in_valid & q1_io_in_ready; // @[VAlu.scala 243:33]
+ assign q0_io_in_bits_0_valid = io_in_bits_0_valid & (_alusel_1_T_2 | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 278:51]
+ assign q0_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_valid = io_in_bits_1_valid & (_alusel_2_T_2 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 278:51]
+ assign q0_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_valid = io_in_bits_2_valid & (_alusel_3_T_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 278:51]
+ assign q0_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_valid = io_in_bits_3_valid & (_alusel_4_T_2 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 278:51]
+ assign q0_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 247:17]
+ assign q0_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 247:17]
+ assign q0_io_out_ready = q0ready & (~q0_io_out_bits_cmdsync | q1_io_out_valid & q1ready & q1_io_out_bits_cmdsync); // @[VAlu.scala 258:30]
assign q1_clock = clock;
assign q1_reset = reset;
- assign q1_io_in_valid = io_in_valid & q0_io_in_ready; // @[VAlu.scala 264:33]
- assign q1_io_in_bits_0_valid = io_in_bits_0_valid & (alureg | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 299:51]
- assign q1_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vf_addr = io_in_bits_0_bits_vf_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vg_addr = io_in_bits_0_bits_vg_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vx_valid = io_in_bits_0_bits_vx_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vx_addr = io_in_bits_0_bits_vx_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vx_tag = io_in_bits_0_bits_vx_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vy_valid = io_in_bits_0_bits_vy_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vy_addr = io_in_bits_0_bits_vy_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vy_tag = io_in_bits_0_bits_vy_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vz_valid = io_in_bits_0_bits_vz_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vz_addr = io_in_bits_0_bits_vz_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_vz_tag = io_in_bits_0_bits_vz_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_valid = io_in_bits_1_valid & (alusel_1 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 299:51]
- assign q1_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vf_addr = io_in_bits_1_bits_vf_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vg_addr = io_in_bits_1_bits_vg_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vx_valid = io_in_bits_1_bits_vx_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vx_addr = io_in_bits_1_bits_vx_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vx_tag = io_in_bits_1_bits_vx_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vy_valid = io_in_bits_1_bits_vy_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vy_addr = io_in_bits_1_bits_vy_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vy_tag = io_in_bits_1_bits_vy_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vz_valid = io_in_bits_1_bits_vz_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vz_addr = io_in_bits_1_bits_vz_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_vz_tag = io_in_bits_1_bits_vz_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_valid = io_in_bits_2_valid & (alusel_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 299:51]
- assign q1_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vf_addr = io_in_bits_2_bits_vf_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vg_addr = io_in_bits_2_bits_vg_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vx_valid = io_in_bits_2_bits_vx_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vx_addr = io_in_bits_2_bits_vx_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vx_tag = io_in_bits_2_bits_vx_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vy_valid = io_in_bits_2_bits_vy_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vy_addr = io_in_bits_2_bits_vy_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vy_tag = io_in_bits_2_bits_vy_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vz_valid = io_in_bits_2_bits_vz_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vz_addr = io_in_bits_2_bits_vz_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_vz_tag = io_in_bits_2_bits_vz_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_valid = io_in_bits_3_valid & (alusel_3 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 299:51]
- assign q1_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vf_addr = io_in_bits_3_bits_vf_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vg_addr = io_in_bits_3_bits_vg_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vx_valid = io_in_bits_3_bits_vx_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vx_addr = io_in_bits_3_bits_vx_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vx_tag = io_in_bits_3_bits_vx_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vy_valid = io_in_bits_3_bits_vy_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vy_addr = io_in_bits_3_bits_vy_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vy_tag = io_in_bits_3_bits_vy_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vz_valid = io_in_bits_3_bits_vz_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vz_addr = io_in_bits_3_bits_vz_addr; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_vz_tag = io_in_bits_3_bits_vz_tag; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 268:17]
- assign q1_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 268:17]
- assign q1_io_out_ready = q1ready & (~q1_io_out_bits_cmdsync | q0_io_out_valid & q0ready & q0_io_out_bits_cmdsync); // @[VAlu.scala 279:30]
+ assign q1_io_in_valid = io_in_valid & q0_io_in_ready; // @[VAlu.scala 244:33]
+ assign q1_io_in_bits_0_valid = io_in_bits_0_valid & (alureg | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 279:51]
+ assign q1_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vf_addr = io_in_bits_0_bits_vf_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vg_addr = io_in_bits_0_bits_vg_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vx_valid = io_in_bits_0_bits_vx_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vx_addr = io_in_bits_0_bits_vx_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vx_tag = io_in_bits_0_bits_vx_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vy_valid = io_in_bits_0_bits_vy_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vy_addr = io_in_bits_0_bits_vy_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vy_tag = io_in_bits_0_bits_vy_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vz_valid = io_in_bits_0_bits_vz_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vz_addr = io_in_bits_0_bits_vz_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_vz_tag = io_in_bits_0_bits_vz_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_valid = io_in_bits_1_valid & (alusel_1 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 279:51]
+ assign q1_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vf_addr = io_in_bits_1_bits_vf_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vg_addr = io_in_bits_1_bits_vg_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vx_valid = io_in_bits_1_bits_vx_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vx_addr = io_in_bits_1_bits_vx_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vx_tag = io_in_bits_1_bits_vx_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vy_valid = io_in_bits_1_bits_vy_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vy_addr = io_in_bits_1_bits_vy_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vy_tag = io_in_bits_1_bits_vy_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vz_valid = io_in_bits_1_bits_vz_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vz_addr = io_in_bits_1_bits_vz_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_vz_tag = io_in_bits_1_bits_vz_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_valid = io_in_bits_2_valid & (alusel_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 279:51]
+ assign q1_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vf_addr = io_in_bits_2_bits_vf_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vg_addr = io_in_bits_2_bits_vg_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vx_valid = io_in_bits_2_bits_vx_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vx_addr = io_in_bits_2_bits_vx_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vx_tag = io_in_bits_2_bits_vx_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vy_valid = io_in_bits_2_bits_vy_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vy_addr = io_in_bits_2_bits_vy_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vy_tag = io_in_bits_2_bits_vy_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vz_valid = io_in_bits_2_bits_vz_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vz_addr = io_in_bits_2_bits_vz_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_vz_tag = io_in_bits_2_bits_vz_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_valid = io_in_bits_3_valid & (alusel_3 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 279:51]
+ assign q1_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vf_addr = io_in_bits_3_bits_vf_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vg_addr = io_in_bits_3_bits_vg_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vx_valid = io_in_bits_3_bits_vx_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vx_addr = io_in_bits_3_bits_vx_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vx_tag = io_in_bits_3_bits_vx_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vy_valid = io_in_bits_3_bits_vy_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vy_addr = io_in_bits_3_bits_vy_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vy_tag = io_in_bits_3_bits_vy_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vz_valid = io_in_bits_3_bits_vz_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vz_addr = io_in_bits_3_bits_vz_addr; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_vz_tag = io_in_bits_3_bits_vz_tag; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 248:17]
+ assign q1_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 248:17]
+ assign q1_io_out_ready = q1ready & (~q1_io_out_bits_cmdsync | q0_io_out_valid & q0ready & q0_io_out_bits_cmdsync); // @[VAlu.scala 259:30]
assign alu0_clock = clock;
assign alu0_reset = reset;
- assign alu0_io_in_valid = q0_io_out_valid & q0_io_out_ready; // @[VAlu.scala 343:39]
- assign alu0_io_in_op = q0_io_out_bits_op; // @[VAlu.scala 344:17]
- assign alu0_io_in_f2 = q0_io_out_bits_f2; // @[VAlu.scala 345:17]
- assign alu0_io_in_sz = q0_io_out_bits_sz; // @[VAlu.scala 346:17]
- assign alu0_io_in_vd_addr = q0_io_out_bits_vd_addr; // @[VAlu.scala 347:22]
- assign alu0_io_in_ve_addr = q0_io_out_bits_ve_addr; // @[VAlu.scala 348:22]
- assign alu0_io_in_sv_data = q0_io_out_bits_sv_data; // @[VAlu.scala 349:22]
- assign alu0_io_read_0_data = io_read_0_data; // @[VAlu.scala 351:24]
- assign alu0_io_read_1_data = io_read_1_data; // @[VAlu.scala 352:24]
- assign alu0_io_read_2_data = io_read_2_data; // @[VAlu.scala 353:24]
- assign alu0_io_read_3_data = io_read_3_data; // @[VAlu.scala 354:24]
- assign alu0_io_read_4_data = io_read_4_data; // @[VAlu.scala 355:24]
- assign alu0_io_read_5_data = io_read_5_data; // @[VAlu.scala 356:24]
+ assign alu0_io_in_valid = q0_io_out_valid & q0_io_out_ready; // @[VAlu.scala 323:39]
+ assign alu0_io_in_op = q0_io_out_bits_op; // @[VAlu.scala 324:17]
+ assign alu0_io_in_f2 = q0_io_out_bits_f2; // @[VAlu.scala 325:17]
+ assign alu0_io_in_sz = q0_io_out_bits_sz; // @[VAlu.scala 326:17]
+ assign alu0_io_in_vd_addr = q0_io_out_bits_vd_addr; // @[VAlu.scala 327:22]
+ assign alu0_io_in_ve_addr = q0_io_out_bits_ve_addr; // @[VAlu.scala 328:22]
+ assign alu0_io_in_sv_data = q0_io_out_bits_sv_data; // @[VAlu.scala 329:22]
+ assign alu0_io_read_0_data = io_read_0_data; // @[VAlu.scala 331:24]
+ assign alu0_io_read_1_data = io_read_1_data; // @[VAlu.scala 332:24]
+ assign alu0_io_read_2_data = io_read_2_data; // @[VAlu.scala 333:24]
+ assign alu0_io_read_3_data = io_read_3_data; // @[VAlu.scala 334:24]
+ assign alu0_io_read_4_data = io_read_4_data; // @[VAlu.scala 335:24]
+ assign alu0_io_read_5_data = io_read_5_data; // @[VAlu.scala 336:24]
assign alu1_clock = clock;
assign alu1_reset = reset;
- assign alu1_io_in_valid = q1_io_out_valid & q1_io_out_ready; // @[VAlu.scala 377:39]
- assign alu1_io_in_op = q1_io_out_bits_op; // @[VAlu.scala 378:17]
- assign alu1_io_in_f2 = q1_io_out_bits_f2; // @[VAlu.scala 379:17]
- assign alu1_io_in_sz = q1_io_out_bits_sz; // @[VAlu.scala 380:17]
- assign alu1_io_in_vd_addr = q1_io_out_bits_vd_addr; // @[VAlu.scala 381:22]
- assign alu1_io_in_ve_addr = q1_io_out_bits_ve_addr; // @[VAlu.scala 382:22]
- assign alu1_io_in_sv_data = q1_io_out_bits_sv_data; // @[VAlu.scala 383:22]
- assign alu1_io_read_0_data = io_read_3_data; // @[VAlu.scala 385:24]
- assign alu1_io_read_1_data = io_read_4_data; // @[VAlu.scala 386:24]
- assign alu1_io_read_2_data = io_read_5_data; // @[VAlu.scala 387:24]
- assign alu1_io_read_3_data = io_read_0_data; // @[VAlu.scala 388:24]
- assign alu1_io_read_4_data = io_read_1_data; // @[VAlu.scala 389:24]
- assign alu1_io_read_5_data = io_read_2_data; // @[VAlu.scala 390:24]
+ assign alu1_io_in_valid = q1_io_out_valid & q1_io_out_ready; // @[VAlu.scala 357:39]
+ assign alu1_io_in_op = q1_io_out_bits_op; // @[VAlu.scala 358:17]
+ assign alu1_io_in_f2 = q1_io_out_bits_f2; // @[VAlu.scala 359:17]
+ assign alu1_io_in_sz = q1_io_out_bits_sz; // @[VAlu.scala 360:17]
+ assign alu1_io_in_vd_addr = q1_io_out_bits_vd_addr; // @[VAlu.scala 361:22]
+ assign alu1_io_in_ve_addr = q1_io_out_bits_ve_addr; // @[VAlu.scala 362:22]
+ assign alu1_io_in_sv_data = q1_io_out_bits_sv_data; // @[VAlu.scala 363:22]
+ assign alu1_io_read_0_data = io_read_3_data; // @[VAlu.scala 365:24]
+ assign alu1_io_read_1_data = io_read_4_data; // @[VAlu.scala 366:24]
+ assign alu1_io_read_2_data = io_read_5_data; // @[VAlu.scala 367:24]
+ assign alu1_io_read_3_data = io_read_0_data; // @[VAlu.scala 368:24]
+ assign alu1_io_read_4_data = io_read_1_data; // @[VAlu.scala 369:24]
+ assign alu1_io_read_5_data = io_read_2_data; // @[VAlu.scala 370:24]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T & io_in_bits_0_valid & _T_1 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_0_bits_op); // @[VAlu.scala 157:17]
+ $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_0_bits_op); // @[VAlu.scala 137:17]
end
`ifdef PRINTF_COND
end
@@ -74169,7 +74188,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_1 & _T_3 & _T_1) begin
- $fatal; // @[VAlu.scala 159:15]
+ $fatal; // @[VAlu.scala 139:15]
end
`ifdef STOP_COND
end
@@ -74180,7 +74199,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_1 & _T_3 & _T_1) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
end
`ifdef PRINTF_COND
end
@@ -74191,7 +74210,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_4 & ~(~(io_in_bits_0_bits_vt_valid & io_in_bits_0_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 161:15]
+ $fatal; // @[VAlu.scala 141:15]
end
`ifdef STOP_COND
end
@@ -74203,8 +74222,8 @@
`endif
if (_GEN_4 & ~(~(io_in_bits_0_bits_vt_valid & io_in_bits_0_bits_sv_valid))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 161:15]
+ "Assertion failed\n at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+ ); // @[VAlu.scala 141:15]
end
`ifdef PRINTF_COND
end
@@ -74215,7 +74234,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_1 & _T_14 & _T_3 & ~(~io_in_bits_0_bits_m)) begin
- $fatal; // @[VAlu.scala 165:17]
+ $fatal; // @[VAlu.scala 145:17]
end
`ifdef STOP_COND
end
@@ -74226,7 +74245,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_1 & _T_14 & _T_3 & ~(~io_in_bits_0_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
end
`ifdef PRINTF_COND
end
@@ -74237,7 +74256,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_15 & ~(io_in_bits_0_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 166:17]
+ $fatal; // @[VAlu.scala 146:17]
end
`ifdef STOP_COND
end
@@ -74248,7 +74267,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_15 & ~(io_in_bits_0_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
end
`ifdef PRINTF_COND
end
@@ -74259,7 +74278,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_15 & ~(~io_in_bits_0_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 167:17]
+ $fatal; // @[VAlu.scala 147:17]
end
`ifdef STOP_COND
end
@@ -74271,7 +74290,7 @@
`endif
if (_GEN_15 & ~(~io_in_bits_0_bits_sv_valid)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+ "Assertion failed\n at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
end
`ifdef PRINTF_COND
end
@@ -74282,7 +74301,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_15 & ~(sparse < 2'h3)) begin
- $fatal; // @[VAlu.scala 168:17]
+ $fatal; // @[VAlu.scala 148:17]
end
`ifdef STOP_COND
end
@@ -74293,7 +74312,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_15 & ~(sparse < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
end
`ifdef PRINTF_COND
end
@@ -74304,7 +74323,7 @@
if (`PRINTF_COND) begin
`endif
if (_T & io_in_bits_1_valid & _T_32 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_1_bits_op); // @[VAlu.scala 157:17]
+ $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_1_bits_op); // @[VAlu.scala 137:17]
end
`ifdef PRINTF_COND
end
@@ -74315,7 +74334,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_41 & _T_3 & _T_32) begin
- $fatal; // @[VAlu.scala 159:15]
+ $fatal; // @[VAlu.scala 139:15]
end
`ifdef STOP_COND
end
@@ -74326,7 +74345,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_41 & _T_3 & _T_32) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
end
`ifdef PRINTF_COND
end
@@ -74337,7 +74356,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_44 & ~(~(io_in_bits_1_bits_vt_valid & io_in_bits_1_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 161:15]
+ $fatal; // @[VAlu.scala 141:15]
end
`ifdef STOP_COND
end
@@ -74349,8 +74368,8 @@
`endif
if (_GEN_44 & ~(~(io_in_bits_1_bits_vt_valid & io_in_bits_1_bits_sv_valid))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 161:15]
+ "Assertion failed\n at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+ ); // @[VAlu.scala 141:15]
end
`ifdef PRINTF_COND
end
@@ -74361,7 +74380,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_41 & _T_45 & _T_3 & ~(~io_in_bits_1_bits_m)) begin
- $fatal; // @[VAlu.scala 165:17]
+ $fatal; // @[VAlu.scala 145:17]
end
`ifdef STOP_COND
end
@@ -74372,7 +74391,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_41 & _T_45 & _T_3 & ~(~io_in_bits_1_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
end
`ifdef PRINTF_COND
end
@@ -74383,7 +74402,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_55 & ~(io_in_bits_1_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 166:17]
+ $fatal; // @[VAlu.scala 146:17]
end
`ifdef STOP_COND
end
@@ -74394,7 +74413,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_55 & ~(io_in_bits_1_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
end
`ifdef PRINTF_COND
end
@@ -74405,7 +74424,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_55 & ~(~io_in_bits_1_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 167:17]
+ $fatal; // @[VAlu.scala 147:17]
end
`ifdef STOP_COND
end
@@ -74417,7 +74436,7 @@
`endif
if (_GEN_55 & ~(~io_in_bits_1_bits_sv_valid)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+ "Assertion failed\n at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
end
`ifdef PRINTF_COND
end
@@ -74428,7 +74447,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_55 & ~(sparse_1 < 2'h3)) begin
- $fatal; // @[VAlu.scala 168:17]
+ $fatal; // @[VAlu.scala 148:17]
end
`ifdef STOP_COND
end
@@ -74439,7 +74458,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_55 & ~(sparse_1 < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
end
`ifdef PRINTF_COND
end
@@ -74450,7 +74469,7 @@
if (`PRINTF_COND) begin
`endif
if (_T & io_in_bits_2_valid & _T_63 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_2_bits_op); // @[VAlu.scala 157:17]
+ $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_2_bits_op); // @[VAlu.scala 137:17]
end
`ifdef PRINTF_COND
end
@@ -74461,7 +74480,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_3 & _T_63) begin
- $fatal; // @[VAlu.scala 159:15]
+ $fatal; // @[VAlu.scala 139:15]
end
`ifdef STOP_COND
end
@@ -74472,7 +74491,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_3 & _T_63) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
end
`ifdef PRINTF_COND
end
@@ -74483,7 +74502,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_84 & ~(~(io_in_bits_2_bits_vt_valid & io_in_bits_2_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 161:15]
+ $fatal; // @[VAlu.scala 141:15]
end
`ifdef STOP_COND
end
@@ -74495,8 +74514,8 @@
`endif
if (_GEN_84 & ~(~(io_in_bits_2_bits_vt_valid & io_in_bits_2_bits_sv_valid))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 161:15]
+ "Assertion failed\n at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+ ); // @[VAlu.scala 141:15]
end
`ifdef PRINTF_COND
end
@@ -74507,7 +74526,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_76 & _T_3 & ~(~io_in_bits_2_bits_m)) begin
- $fatal; // @[VAlu.scala 165:17]
+ $fatal; // @[VAlu.scala 145:17]
end
`ifdef STOP_COND
end
@@ -74518,7 +74537,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_76 & _T_3 & ~(~io_in_bits_2_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
end
`ifdef PRINTF_COND
end
@@ -74529,7 +74548,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_95 & ~(io_in_bits_2_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 166:17]
+ $fatal; // @[VAlu.scala 146:17]
end
`ifdef STOP_COND
end
@@ -74540,7 +74559,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & ~(io_in_bits_2_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
end
`ifdef PRINTF_COND
end
@@ -74551,7 +74570,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_95 & ~(~io_in_bits_2_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 167:17]
+ $fatal; // @[VAlu.scala 147:17]
end
`ifdef STOP_COND
end
@@ -74563,7 +74582,7 @@
`endif
if (_GEN_95 & ~(~io_in_bits_2_bits_sv_valid)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+ "Assertion failed\n at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
end
`ifdef PRINTF_COND
end
@@ -74574,7 +74593,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_95 & ~(sparse_2 < 2'h3)) begin
- $fatal; // @[VAlu.scala 168:17]
+ $fatal; // @[VAlu.scala 148:17]
end
`ifdef STOP_COND
end
@@ -74585,7 +74604,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & ~(sparse_2 < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
end
`ifdef PRINTF_COND
end
@@ -74596,7 +74615,7 @@
if (`PRINTF_COND) begin
`endif
if (_T & io_in_bits_3_valid & _T_94 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_3_bits_op); // @[VAlu.scala 157:17]
+ $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_3_bits_op); // @[VAlu.scala 137:17]
end
`ifdef PRINTF_COND
end
@@ -74607,7 +74626,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_3 & _T_94) begin
- $fatal; // @[VAlu.scala 159:15]
+ $fatal; // @[VAlu.scala 139:15]
end
`ifdef STOP_COND
end
@@ -74618,7 +74637,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_3 & _T_94) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
end
`ifdef PRINTF_COND
end
@@ -74629,7 +74648,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_124 & ~(~(io_in_bits_3_bits_vt_valid & io_in_bits_3_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 161:15]
+ $fatal; // @[VAlu.scala 141:15]
end
`ifdef STOP_COND
end
@@ -74641,8 +74660,8 @@
`endif
if (_GEN_124 & ~(~(io_in_bits_3_bits_vt_valid & io_in_bits_3_bits_sv_valid))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 161:15]
+ "Assertion failed\n at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+ ); // @[VAlu.scala 141:15]
end
`ifdef PRINTF_COND
end
@@ -74653,7 +74672,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_107 & _T_3 & ~(~io_in_bits_3_bits_m)) begin
- $fatal; // @[VAlu.scala 165:17]
+ $fatal; // @[VAlu.scala 145:17]
end
`ifdef STOP_COND
end
@@ -74664,7 +74683,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_107 & _T_3 & ~(~io_in_bits_3_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
end
`ifdef PRINTF_COND
end
@@ -74675,7 +74694,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_135 & ~(io_in_bits_3_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 166:17]
+ $fatal; // @[VAlu.scala 146:17]
end
`ifdef STOP_COND
end
@@ -74686,7 +74705,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & ~(io_in_bits_3_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
end
`ifdef PRINTF_COND
end
@@ -74697,7 +74716,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_135 & ~(~io_in_bits_3_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 167:17]
+ $fatal; // @[VAlu.scala 147:17]
end
`ifdef STOP_COND
end
@@ -74709,7 +74728,7 @@
`endif
if (_GEN_135 & ~(~io_in_bits_3_bits_sv_valid)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+ "Assertion failed\n at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
end
`ifdef PRINTF_COND
end
@@ -74720,7 +74739,7 @@
if (`STOP_COND) begin
`endif
if (_GEN_135 & ~(sparse_3 < 2'h3)) begin
- $fatal; // @[VAlu.scala 168:17]
+ $fatal; // @[VAlu.scala 148:17]
end
`ifdef STOP_COND
end
@@ -74731,7 +74750,7 @@
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & ~(sparse_3 < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+ $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
end
`ifdef PRINTF_COND
end
@@ -74739,9 +74758,9 @@
`endif // SYNTHESIS
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAlu.scala 293:37]
- alureg <= 1'h0; // @[VAlu.scala 289:19 290:19 291:19]
- end else if (_T) begin // @[VAlu.scala 283:23]
+ if (reset) begin // @[VAlu.scala 273:37]
+ alureg <= 1'h0; // @[VAlu.scala 269:19 270:19 271:19]
+ end else if (_T) begin // @[VAlu.scala 263:23]
if (io_in_bits_3_valid & ~io_in_bits_3_bits_cmdsync) begin
alureg <= ~alusel_3;
end else if (io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync) begin
@@ -85237,121 +85256,121 @@
reg value_tin_last; // @[VCmdq.scala 37:18]
reg value_m; // @[VCmdq.scala 37:18]
reg [4:0] step; // @[VCmdq.scala 42:21]
- wire _T = ~valid; // @[VLdSt.scala 119:12]
- wire _T_5 = value_tin_op == 7'h4; // @[VLdSt.scala 119:70]
- wire _T_8 = ~reset; // @[VLdSt.scala 119:11]
- wire [7:0] fmaxvlb = _T_5 ? 8'h8 : 8'h20; // @[VLdSt.scala 125:22]
- wire _outlast1_T = ~value_m; // @[VLdSt.scala 127:20]
- wire _outlast1_T_1 = step == 5'h2; // @[VLdSt.scala 127:31]
- wire outlast1 = ~value_m | step == 5'h2; // @[VLdSt.scala 127:23]
- wire outlast2 = value_m ? step == 5'he : _outlast1_T_1; // @[VLdSt.scala 128:23]
- wire outlast = _T_5 ? outlast2 : outlast1; // @[VLdSt.scala 129:22]
- wire _last1_T_1 = step == 5'h3; // @[VLdSt.scala 131:28]
- wire last1 = _outlast1_T | step == 5'h3; // @[VLdSt.scala 131:20]
- wire last2 = value_m ? step == 5'hf : _last1_T_1; // @[VLdSt.scala 132:20]
- wire last = _T_5 ? last2 : last1; // @[VLdSt.scala 133:19]
- wire _out_vd_addr_T_2 = _T_5 & step[1:0] != 2'h3; // @[VLdSt.scala 137:29]
- wire [5:0] _out_vd_addr_T_4 = value_tin_vd_addr + 6'h1; // @[VLdSt.scala 137:74]
- wire [5:0] tin_vd_addr = _T_5 & step[1:0] != 2'h3 ? value_tin_vd_addr : _out_vd_addr_T_4; // @[VLdSt.scala 137:23]
- wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VLdSt.scala 138:74]
- wire [5:0] tin_vs_addr = _out_vd_addr_T_2 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VLdSt.scala 138:23]
- wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLdSt.scala 140:27]
- wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VLdSt.scala 141:60]
- wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VLdSt.scala 141:22]
- wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VLdSt.scala 145:46]
- wire [4:0] _out_quad_T_3 = _T_5 ? _out_quad_T_2 : 5'h0; // @[VLdSt.scala 145:20]
- wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLdSt.scala 85:23]
- wire f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VLdSt.scala 86:23]
+ wire _T = ~valid; // @[VLdSt.scala 122:12]
+ wire _T_5 = value_tin_op == 7'h4; // @[VLdSt.scala 122:70]
+ wire _T_8 = ~reset; // @[VLdSt.scala 122:11]
+ wire [7:0] fmaxvlb = _T_5 ? 8'h8 : 8'h20; // @[VLdSt.scala 128:22]
+ wire _outlast1_T = ~value_m; // @[VLdSt.scala 130:20]
+ wire _outlast1_T_1 = step == 5'h2; // @[VLdSt.scala 130:31]
+ wire outlast1 = ~value_m | step == 5'h2; // @[VLdSt.scala 130:23]
+ wire outlast2 = value_m ? step == 5'he : _outlast1_T_1; // @[VLdSt.scala 131:23]
+ wire outlast = _T_5 ? outlast2 : outlast1; // @[VLdSt.scala 132:22]
+ wire _last1_T_1 = step == 5'h3; // @[VLdSt.scala 134:28]
+ wire last1 = _outlast1_T | step == 5'h3; // @[VLdSt.scala 134:20]
+ wire last2 = value_m ? step == 5'hf : _last1_T_1; // @[VLdSt.scala 135:20]
+ wire last = _T_5 ? last2 : last1; // @[VLdSt.scala 136:19]
+ wire _out_vd_addr_T_2 = _T_5 & step[1:0] != 2'h3; // @[VLdSt.scala 140:29]
+ wire [5:0] _out_vd_addr_T_4 = value_tin_vd_addr + 6'h1; // @[VLdSt.scala 140:74]
+ wire [5:0] tin_vd_addr = _T_5 & step[1:0] != 2'h3 ? value_tin_vd_addr : _out_vd_addr_T_4; // @[VLdSt.scala 140:23]
+ wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VLdSt.scala 141:74]
+ wire [5:0] tin_vs_addr = _out_vd_addr_T_2 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VLdSt.scala 141:23]
+ wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLdSt.scala 143:27]
+ wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VLdSt.scala 144:60]
+ wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VLdSt.scala 144:22]
+ wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VLdSt.scala 148:46]
+ wire [4:0] _out_quad_T_3 = _T_5 ? _out_quad_T_2 : 5'h0; // @[VLdSt.scala 148:20]
+ wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLdSt.scala 88:23]
+ wire f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VLdSt.scala 89:23]
wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_63 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_63 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_0_bits_tin_T_13 = io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 88:50]
- wire _f_io_in_bits_0_bits_tin_T_19 = io_in_bits_0_bits_op == 7'h4; // @[VLdSt.scala 89:20]
- wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+ wire _f_io_in_bits_0_bits_tin_T_13 = io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 91:50]
+ wire _f_io_in_bits_0_bits_tin_T_19 = io_in_bits_0_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+ wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+ wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+ wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
- wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_65 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
- wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VLdSt.scala 99:28]
+ wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+ wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_65 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+ wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VLdSt.scala 102:28]
wire [33:0] _f_io_in_bits_0_bits_tin_remain1_T_1 = f_io_in_bits_0_bits_tin_data > _GEN_66 ? {{26'd0},
- f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VLdSt.scala 99:22]
- wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
- wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
- wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLdSt.scala 85:23]
- wire f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VLdSt.scala 86:23]
+ f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VLdSt.scala 102:22]
+ wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+ wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
+ wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLdSt.scala 88:23]
+ wire f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VLdSt.scala 89:23]
wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_67 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_67 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_1_bits_tin_T_13 = io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 88:50]
- wire _f_io_in_bits_1_bits_tin_T_19 = io_in_bits_1_bits_op == 7'h4; // @[VLdSt.scala 89:20]
- wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+ wire _f_io_in_bits_1_bits_tin_T_13 = io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 91:50]
+ wire _f_io_in_bits_1_bits_tin_T_19 = io_in_bits_1_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+ wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+ wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+ wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
- wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_69 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
- wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VLdSt.scala 99:28]
+ wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+ wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_69 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+ wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VLdSt.scala 102:28]
wire [33:0] _f_io_in_bits_1_bits_tin_remain1_T_1 = f_io_in_bits_1_bits_tin_data > _GEN_70 ? {{26'd0},
- f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VLdSt.scala 99:22]
- wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
- wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
- wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLdSt.scala 85:23]
- wire f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VLdSt.scala 86:23]
+ f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VLdSt.scala 102:22]
+ wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+ wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
+ wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLdSt.scala 88:23]
+ wire f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VLdSt.scala 89:23]
wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_71 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_71 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_2_bits_tin_T_13 = io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 88:50]
- wire _f_io_in_bits_2_bits_tin_T_19 = io_in_bits_2_bits_op == 7'h4; // @[VLdSt.scala 89:20]
- wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+ wire _f_io_in_bits_2_bits_tin_T_13 = io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 91:50]
+ wire _f_io_in_bits_2_bits_tin_T_19 = io_in_bits_2_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+ wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_72 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_72 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+ wire [32:0] _GEN_72 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+ wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_72 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_73 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
- wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_73 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
- wire [33:0] _GEN_74 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VLdSt.scala 99:28]
+ wire [33:0] _GEN_73 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+ wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_73 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+ wire [33:0] _GEN_74 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VLdSt.scala 102:28]
wire [33:0] _f_io_in_bits_2_bits_tin_remain1_T_1 = f_io_in_bits_2_bits_tin_data > _GEN_74 ? {{26'd0},
- f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VLdSt.scala 99:22]
- wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
- wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
- wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLdSt.scala 85:23]
- wire f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VLdSt.scala 86:23]
+ f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VLdSt.scala 102:22]
+ wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+ wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
+ wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLdSt.scala 88:23]
+ wire f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VLdSt.scala 89:23]
wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
wire [1:0] _GEN_75 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_75 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_3_bits_tin_T_13 = io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 88:50]
- wire _f_io_in_bits_3_bits_tin_T_19 = io_in_bits_3_bits_op == 7'h4; // @[VLdSt.scala 89:20]
- wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+ wire _f_io_in_bits_3_bits_tin_T_13 = io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 91:50]
+ wire _f_io_in_bits_3_bits_tin_T_19 = io_in_bits_3_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+ wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 8:8]
wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
- wire [32:0] _GEN_76 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_76 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+ wire [32:0] _GEN_76 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+ wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_76 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
- wire [33:0] _GEN_77 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
- wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_77 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
- wire [33:0] _GEN_78 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VLdSt.scala 99:28]
+ wire [33:0] _GEN_77 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+ wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_77 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+ wire [33:0] _GEN_78 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VLdSt.scala 102:28]
wire [33:0] _f_io_in_bits_3_bits_tin_remain1_T_1 = f_io_in_bits_3_bits_tin_data > _GEN_78 ? {{26'd0},
- f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VLdSt.scala 99:22]
- wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
- wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
+ f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VLdSt.scala 102:22]
+ wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+ wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
wire _T_11 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
wire _T_12 = ~last; // @[VCmdq.scala 66:11]
wire _GEN_1 = ~last & outlast; // @[VCmdq.scala 66:18 68:17 74:17]
- wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VLdSt.scala 121:19 145:14]
+ wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VLdSt.scala 124:19 148:14]
wire _GEN_5 = ~last & value_tin_vs_valid; // @[VCmdq.scala 66:18 68:17 74:17]
wire _GEN_14 = ~last & value_m; // @[VCmdq.scala 66:18 69:15 75:15]
wire _GEN_16 = io_out_valid & io_out_ready ? _T_12 : valid; // @[VCmdq.scala 35:22 65:46]
@@ -86225,7 +86244,7 @@
wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
wire [63:0] _active_T_18 = _active_T_17 | active_active_11; // @[VCmdq.scala 91:24]
wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
- wire [2:0] active_active0_stepq = _T_5 ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VLdSt.scala 153:20]
+ wire [2:0] active_active0_stepq = _T_5 ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VLdSt.scala 156:20]
wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
@@ -86300,7 +86319,7 @@
; // @[Library.scala 18:8]
wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 93:68]
wire [63:0] active_active0 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 8:8]
- wire [2:0] active_active1_stepq = _T_5 ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VLdSt.scala 153:20]
+ wire [2:0] active_active1_stepq = _T_5 ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VLdSt.scala 156:20]
wire _active_active1_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
active_active1_stepq <= 3'h0; // @[VCommon.scala 91:42]
wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -86439,52 +86458,52 @@
assign f_reset = reset;
assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLdSt.scala 103:12 84:19]
- assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+ assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLdSt.scala 106:12 87:19]
+ assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
- assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
- assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
- assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_0_bits_tin_last = ~io_in_bits_0_bits_m & io_in_bits_0_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+ 'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+ assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+ assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+ assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_0_bits_tin_last = ~io_in_bits_0_bits_m & io_in_bits_0_bits_op != 7'h4; // @[VLdSt.scala 114:23]
assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLdSt.scala 103:12 84:19]
- assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+ assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLdSt.scala 106:12 87:19]
+ assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
- assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
- assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
- assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_1_bits_tin_last = ~io_in_bits_1_bits_m & io_in_bits_1_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+ 'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+ assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+ assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+ assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_1_bits_tin_last = ~io_in_bits_1_bits_m & io_in_bits_1_bits_op != 7'h4; // @[VLdSt.scala 114:23]
assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLdSt.scala 103:12 84:19]
- assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+ assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLdSt.scala 106:12 87:19]
+ assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
- assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
- assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
- assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_2_bits_tin_last = ~io_in_bits_2_bits_m & io_in_bits_2_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+ 'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+ assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+ assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+ assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_2_bits_tin_last = ~io_in_bits_2_bits_m & io_in_bits_2_bits_op != 7'h4; // @[VLdSt.scala 114:23]
assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLdSt.scala 103:12 84:19]
- assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+ assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLdSt.scala 106:12 87:19]
+ assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
- assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
- assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
- assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
- assign f_io_in_bits_3_bits_tin_last = ~io_in_bits_3_bits_m & io_in_bits_3_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+ 'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+ assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+ assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+ assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+ assign f_io_in_bits_3_bits_tin_last = ~io_in_bits_3_bits_m & io_in_bits_3_bits_op != 7'h4; // @[VLdSt.scala 114:23]
assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
assign f_io_out_ready = _T | io_out_ready & last; // @[VCmdq.scala 57:28]
always @(posedge clock) begin
@@ -86596,7 +86615,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(~valid | value_tin_op == 7'h2 | value_tin_op == 7'h3 | value_tin_op == 7'h4)) begin
- $fatal; // @[VLdSt.scala 119:11]
+ $fatal; // @[VLdSt.scala 122:11]
end
`ifdef STOP_COND
end
@@ -86608,8 +86627,8 @@
`endif
if (~reset & ~(~valid | value_tin_op == 7'h2 | value_tin_op == 7'h3 | value_tin_op == 7'h4)) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:119 assert(!valid || in.op === e.vld.U || in.op === e.vst.U || in.op === e.vstq.U)\n"
- ); // @[VLdSt.scala 119:11]
+ "Assertion failed\n at VLdSt.scala:122 assert(!valid || in.op === e.vld.U || in.op === e.vst.U || in.op === e.vstq.U)\n"
+ ); // @[VLdSt.scala 122:11]
end
`ifdef PRINTF_COND
end
@@ -86620,7 +86639,7 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 87:11]
+ $fatal; // @[VLdSt.scala 90:11]
end
`ifdef STOP_COND
end
@@ -86631,7 +86650,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
end
`ifdef PRINTF_COND
end
@@ -86643,7 +86662,7 @@
`endif
if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h3 & (io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid)))
) begin
- $fatal; // @[VLdSt.scala 88:11]
+ $fatal; // @[VLdSt.scala 91:11]
end
`ifdef STOP_COND
end
@@ -86656,8 +86675,8 @@
if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h3 & (io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:88 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 88:11]
+ "Assertion failed\n at VLdSt.scala:91 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 91:11]
end
`ifdef PRINTF_COND
end
@@ -86668,7 +86687,7 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 89:11]
+ $fatal; // @[VLdSt.scala 92:11]
end
`ifdef STOP_COND
end
@@ -86680,8 +86699,8 @@
`endif
if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_13))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 89:11]
+ "Assertion failed\n at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 92:11]
end
`ifdef PRINTF_COND
end
@@ -86693,7 +86712,7 @@
`endif
if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
) begin
- $fatal; // @[VLdSt.scala 90:11]
+ $fatal; // @[VLdSt.scala 93:11]
end
`ifdef STOP_COND
end
@@ -86706,8 +86725,8 @@
if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:90 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 90:11]
+ "Assertion failed\n at VLdSt.scala:93 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
+ ); // @[VLdSt.scala 93:11]
end
`ifdef PRINTF_COND
end
@@ -86718,7 +86737,7 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 87:11]
+ $fatal; // @[VLdSt.scala 90:11]
end
`ifdef STOP_COND
end
@@ -86729,7 +86748,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
end
`ifdef PRINTF_COND
end
@@ -86741,7 +86760,7 @@
`endif
if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h3 & (io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid)))
) begin
- $fatal; // @[VLdSt.scala 88:11]
+ $fatal; // @[VLdSt.scala 91:11]
end
`ifdef STOP_COND
end
@@ -86754,8 +86773,8 @@
if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h3 & (io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:88 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 88:11]
+ "Assertion failed\n at VLdSt.scala:91 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 91:11]
end
`ifdef PRINTF_COND
end
@@ -86766,7 +86785,7 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 89:11]
+ $fatal; // @[VLdSt.scala 92:11]
end
`ifdef STOP_COND
end
@@ -86778,8 +86797,8 @@
`endif
if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_13))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 89:11]
+ "Assertion failed\n at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 92:11]
end
`ifdef PRINTF_COND
end
@@ -86791,7 +86810,7 @@
`endif
if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
) begin
- $fatal; // @[VLdSt.scala 90:11]
+ $fatal; // @[VLdSt.scala 93:11]
end
`ifdef STOP_COND
end
@@ -86804,8 +86823,8 @@
if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:90 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 90:11]
+ "Assertion failed\n at VLdSt.scala:93 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
+ ); // @[VLdSt.scala 93:11]
end
`ifdef PRINTF_COND
end
@@ -86816,7 +86835,7 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 87:11]
+ $fatal; // @[VLdSt.scala 90:11]
end
`ifdef STOP_COND
end
@@ -86827,7 +86846,7 @@
if (`PRINTF_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
+ $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
end
`ifdef PRINTF_COND
end
@@ -86839,7 +86858,7 @@
`endif
if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h3 & (io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid)))
) begin
- $fatal; // @[VLdSt.scala 88:11]
+ $fatal; // @[VLdSt.scala 91:11]
end
`ifdef STOP_COND
end
@@ -86852,8 +86871,8 @@
if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h3 & (io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:88 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 88:11]
+ "Assertion failed\n at VLdSt.scala:91 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 91:11]
end
`ifdef PRINTF_COND
end
@@ -86864,7 +86883,7 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 89:11]
+ $fatal; // @[VLdSt.scala 92:11]
end
`ifdef STOP_COND
end
@@ -86876,8 +86895,8 @@
`endif
if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_13))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 89:11]
+ "Assertion failed\n at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 92:11]
end
`ifdef PRINTF_COND
end
@@ -86889,7 +86908,7 @@
`endif
if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
) begin
- $fatal; // @[VLdSt.scala 90:11]
+ $fatal; // @[VLdSt.scala 93:11]
end
`ifdef STOP_COND
end
@@ -86902,8 +86921,8 @@
if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:90 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 90:11]
+ "Assertion failed\n at VLdSt.scala:93 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
+ ); // @[VLdSt.scala 93:11]
end
`ifdef PRINTF_COND
end
@@ -86914,79 +86933,6 @@
if (`STOP_COND) begin
`endif
if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 87:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 88:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:88 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 88:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 89:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 89:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
- ) begin
$fatal; // @[VLdSt.scala 90:11]
end
`ifdef STOP_COND
@@ -86997,11 +86943,84 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
+ ) begin
+ $fatal; // @[VLdSt.scala 91:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
+ ) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at VLdSt.scala:91 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 91:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
+ $fatal; // @[VLdSt.scala 92:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+ ); // @[VLdSt.scala 92:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
+ ) begin
+ $fatal; // @[VLdSt.scala 93:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:90 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 90:11]
+ "Assertion failed\n at VLdSt.scala:93 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
+ ); // @[VLdSt.scala 93:11]
end
`ifdef PRINTF_COND
end
@@ -88242,88 +88261,88 @@
wire [6:0] q_io_out_ready_idx = {q_io_out_ready_tag,q_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
wire [127:0] _q_io_out_ready_T_1 = io_vrfsb >> q_io_out_ready_idx; // @[VCommon.scala 122:21]
wire _q_io_out_ready_T_4 = ~q_io_out_bits_vs_valid | ~_q_io_out_ready_T_1[0]; // @[VCommon.scala 122:15]
- wire ctrlready = ctrl_io_in_ready & (io_read_ready | ~ctrl_io_in_bits_write); // @[VLdSt.scala 206:33]
- reg rdataEn; // @[VLdSt.scala 201:24]
- reg [7:0] rdataSize; // @[VLdSt.scala 202:22]
- reg [4:0] rdataAddr; // @[VLdSt.scala 203:22]
- reg [4:0] rdataAshf; // @[VLdSt.scala 204:22]
- wire qoutEn = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 208:31]
- wire rdataEnNxt = qoutEn & ctrl_io_in_bits_write; // @[VLdSt.scala 209:27]
- wire _qmaxvlb_T = q_io_out_bits_op == 7'h4; // @[VLdSt.scala 211:38]
- wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VLdSt.scala 211:20]
- wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VLdSt.scala 212:18]
- wire [1:0] quad = q_io_out_bits_quad; // @[VLdSt.scala 216:34]
- wire [9:0] _rdataAshf_T_1 = quad * 8'h8; // @[VLdSt.scala 219:45]
- wire [31:0] _GEN_3 = {{22'd0}, _rdataAshf_T_1}; // @[VLdSt.scala 219:37]
- wire [31:0] _rdataAshf_T_3 = q_io_out_bits_addr - _GEN_3; // @[VLdSt.scala 219:37]
- wire [31:0] _GEN_1 = rdataEnNxt ? q_io_out_bits_addr : {{27'd0}, rdataAddr}; // @[VLdSt.scala 215:21 218:15 203:22]
- wire [31:0] _GEN_2 = rdataEnNxt ? _rdataAshf_T_3 : {{27'd0}, rdataAshf}; // @[VLdSt.scala 215:21 219:15 204:22]
- wire rdataWmask_0 = rdataSize > 8'h0; // @[VLdSt.scala 223:32]
- wire rdataWmask_1 = rdataSize > 8'h1; // @[VLdSt.scala 223:32]
- wire rdataWmask_2 = rdataSize > 8'h2; // @[VLdSt.scala 223:32]
- wire rdataWmask_3 = rdataSize > 8'h3; // @[VLdSt.scala 223:32]
- wire rdataWmask_4 = rdataSize > 8'h4; // @[VLdSt.scala 223:32]
- wire rdataWmask_5 = rdataSize > 8'h5; // @[VLdSt.scala 223:32]
- wire rdataWmask_6 = rdataSize > 8'h6; // @[VLdSt.scala 223:32]
- wire rdataWmask_7 = rdataSize > 8'h7; // @[VLdSt.scala 223:32]
- wire rdataWmask_8 = rdataSize > 8'h8; // @[VLdSt.scala 223:32]
- wire rdataWmask_9 = rdataSize > 8'h9; // @[VLdSt.scala 223:32]
- wire rdataWmask_10 = rdataSize > 8'ha; // @[VLdSt.scala 223:32]
- wire rdataWmask_11 = rdataSize > 8'hb; // @[VLdSt.scala 223:32]
- wire rdataWmask_12 = rdataSize > 8'hc; // @[VLdSt.scala 223:32]
- wire rdataWmask_13 = rdataSize > 8'hd; // @[VLdSt.scala 223:32]
- wire rdataWmask_14 = rdataSize > 8'he; // @[VLdSt.scala 223:32]
- wire rdataWmask_15 = rdataSize > 8'hf; // @[VLdSt.scala 223:32]
- wire rdataWmask_16 = rdataSize > 8'h10; // @[VLdSt.scala 223:32]
- wire rdataWmask_17 = rdataSize > 8'h11; // @[VLdSt.scala 223:32]
- wire rdataWmask_18 = rdataSize > 8'h12; // @[VLdSt.scala 223:32]
- wire rdataWmask_19 = rdataSize > 8'h13; // @[VLdSt.scala 223:32]
- wire rdataWmask_20 = rdataSize > 8'h14; // @[VLdSt.scala 223:32]
- wire rdataWmask_21 = rdataSize > 8'h15; // @[VLdSt.scala 223:32]
- wire rdataWmask_22 = rdataSize > 8'h16; // @[VLdSt.scala 223:32]
- wire rdataWmask_23 = rdataSize > 8'h17; // @[VLdSt.scala 223:32]
- wire rdataWmask_24 = rdataSize > 8'h18; // @[VLdSt.scala 223:32]
- wire rdataWmask_25 = rdataSize > 8'h19; // @[VLdSt.scala 223:32]
- wire rdataWmask_26 = rdataSize > 8'h1a; // @[VLdSt.scala 223:32]
- wire rdataWmask_27 = rdataSize > 8'h1b; // @[VLdSt.scala 223:32]
- wire rdataWmask_28 = rdataSize > 8'h1c; // @[VLdSt.scala 223:32]
- wire rdataWmask_29 = rdataSize > 8'h1d; // @[VLdSt.scala 223:32]
- wire rdataWmask_30 = rdataSize > 8'h1e; // @[VLdSt.scala 223:32]
- wire rdataWmask_31 = rdataSize > 8'h1f; // @[VLdSt.scala 223:32]
- wire _T_4 = ~reset; // @[VLdSt.scala 235:9]
- wire [7:0] data_io_in_bits_wdata_datain_0 = io_read_data[7:0]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_1 = io_read_data[15:8]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_2 = io_read_data[23:16]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_3 = io_read_data[31:24]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_4 = io_read_data[39:32]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_5 = io_read_data[47:40]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_6 = io_read_data[55:48]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_7 = io_read_data[63:56]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_8 = io_read_data[71:64]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_9 = io_read_data[79:72]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_10 = io_read_data[87:80]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_11 = io_read_data[95:88]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_12 = io_read_data[103:96]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_13 = io_read_data[111:104]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_14 = io_read_data[119:112]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_15 = io_read_data[127:120]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_16 = io_read_data[135:128]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_17 = io_read_data[143:136]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_18 = io_read_data[151:144]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_19 = io_read_data[159:152]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_20 = io_read_data[167:160]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_21 = io_read_data[175:168]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_22 = io_read_data[183:176]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_23 = io_read_data[191:184]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_24 = io_read_data[199:192]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_25 = io_read_data[207:200]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_26 = io_read_data[215:208]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_27 = io_read_data[223:216]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_28 = io_read_data[231:224]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_29 = io_read_data[239:232]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_30 = io_read_data[247:240]; // @[VLdSt.scala 47:24]
- wire [7:0] data_io_in_bits_wdata_datain_31 = io_read_data[255:248]; // @[VLdSt.scala 47:24]
- wire [4:0] data_io_in_bits_wdata_idx = 5'h0 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire ctrlready = ctrl_io_in_ready & (io_read_ready | ~ctrl_io_in_bits_write); // @[VLdSt.scala 209:33]
+ reg rdataEn; // @[VLdSt.scala 204:24]
+ reg [7:0] rdataSize; // @[VLdSt.scala 205:22]
+ reg [4:0] rdataAddr; // @[VLdSt.scala 206:22]
+ reg [4:0] rdataAshf; // @[VLdSt.scala 207:22]
+ wire qoutEn = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 211:31]
+ wire rdataEnNxt = qoutEn & ctrl_io_in_bits_write; // @[VLdSt.scala 212:27]
+ wire _qmaxvlb_T = q_io_out_bits_op == 7'h4; // @[VLdSt.scala 214:38]
+ wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VLdSt.scala 214:20]
+ wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VLdSt.scala 215:18]
+ wire [1:0] quad = q_io_out_bits_quad; // @[VLdSt.scala 219:34]
+ wire [9:0] _rdataAshf_T_1 = quad * 8'h8; // @[VLdSt.scala 222:45]
+ wire [31:0] _GEN_3 = {{22'd0}, _rdataAshf_T_1}; // @[VLdSt.scala 222:37]
+ wire [31:0] _rdataAshf_T_3 = q_io_out_bits_addr - _GEN_3; // @[VLdSt.scala 222:37]
+ wire [31:0] _GEN_1 = rdataEnNxt ? q_io_out_bits_addr : {{27'd0}, rdataAddr}; // @[VLdSt.scala 218:21 221:15 206:22]
+ wire [31:0] _GEN_2 = rdataEnNxt ? _rdataAshf_T_3 : {{27'd0}, rdataAshf}; // @[VLdSt.scala 218:21 222:15 207:22]
+ wire rdataWmask_0 = rdataSize > 8'h0; // @[VLdSt.scala 226:32]
+ wire rdataWmask_1 = rdataSize > 8'h1; // @[VLdSt.scala 226:32]
+ wire rdataWmask_2 = rdataSize > 8'h2; // @[VLdSt.scala 226:32]
+ wire rdataWmask_3 = rdataSize > 8'h3; // @[VLdSt.scala 226:32]
+ wire rdataWmask_4 = rdataSize > 8'h4; // @[VLdSt.scala 226:32]
+ wire rdataWmask_5 = rdataSize > 8'h5; // @[VLdSt.scala 226:32]
+ wire rdataWmask_6 = rdataSize > 8'h6; // @[VLdSt.scala 226:32]
+ wire rdataWmask_7 = rdataSize > 8'h7; // @[VLdSt.scala 226:32]
+ wire rdataWmask_8 = rdataSize > 8'h8; // @[VLdSt.scala 226:32]
+ wire rdataWmask_9 = rdataSize > 8'h9; // @[VLdSt.scala 226:32]
+ wire rdataWmask_10 = rdataSize > 8'ha; // @[VLdSt.scala 226:32]
+ wire rdataWmask_11 = rdataSize > 8'hb; // @[VLdSt.scala 226:32]
+ wire rdataWmask_12 = rdataSize > 8'hc; // @[VLdSt.scala 226:32]
+ wire rdataWmask_13 = rdataSize > 8'hd; // @[VLdSt.scala 226:32]
+ wire rdataWmask_14 = rdataSize > 8'he; // @[VLdSt.scala 226:32]
+ wire rdataWmask_15 = rdataSize > 8'hf; // @[VLdSt.scala 226:32]
+ wire rdataWmask_16 = rdataSize > 8'h10; // @[VLdSt.scala 226:32]
+ wire rdataWmask_17 = rdataSize > 8'h11; // @[VLdSt.scala 226:32]
+ wire rdataWmask_18 = rdataSize > 8'h12; // @[VLdSt.scala 226:32]
+ wire rdataWmask_19 = rdataSize > 8'h13; // @[VLdSt.scala 226:32]
+ wire rdataWmask_20 = rdataSize > 8'h14; // @[VLdSt.scala 226:32]
+ wire rdataWmask_21 = rdataSize > 8'h15; // @[VLdSt.scala 226:32]
+ wire rdataWmask_22 = rdataSize > 8'h16; // @[VLdSt.scala 226:32]
+ wire rdataWmask_23 = rdataSize > 8'h17; // @[VLdSt.scala 226:32]
+ wire rdataWmask_24 = rdataSize > 8'h18; // @[VLdSt.scala 226:32]
+ wire rdataWmask_25 = rdataSize > 8'h19; // @[VLdSt.scala 226:32]
+ wire rdataWmask_26 = rdataSize > 8'h1a; // @[VLdSt.scala 226:32]
+ wire rdataWmask_27 = rdataSize > 8'h1b; // @[VLdSt.scala 226:32]
+ wire rdataWmask_28 = rdataSize > 8'h1c; // @[VLdSt.scala 226:32]
+ wire rdataWmask_29 = rdataSize > 8'h1d; // @[VLdSt.scala 226:32]
+ wire rdataWmask_30 = rdataSize > 8'h1e; // @[VLdSt.scala 226:32]
+ wire rdataWmask_31 = rdataSize > 8'h1f; // @[VLdSt.scala 226:32]
+ wire _T_4 = ~reset; // @[VLdSt.scala 238:9]
+ wire [7:0] data_io_in_bits_wdata_datain_0 = io_read_data[7:0]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_1 = io_read_data[15:8]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_2 = io_read_data[23:16]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_3 = io_read_data[31:24]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_4 = io_read_data[39:32]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_5 = io_read_data[47:40]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_6 = io_read_data[55:48]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_7 = io_read_data[63:56]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_8 = io_read_data[71:64]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_9 = io_read_data[79:72]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_10 = io_read_data[87:80]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_11 = io_read_data[95:88]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_12 = io_read_data[103:96]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_13 = io_read_data[111:104]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_14 = io_read_data[119:112]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_15 = io_read_data[127:120]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_16 = io_read_data[135:128]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_17 = io_read_data[143:136]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_18 = io_read_data[151:144]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_19 = io_read_data[159:152]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_20 = io_read_data[167:160]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_21 = io_read_data[175:168]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_22 = io_read_data[183:176]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_23 = io_read_data[191:184]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_24 = io_read_data[199:192]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_25 = io_read_data[207:200]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_26 = io_read_data[215:208]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_27 = io_read_data[223:216]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_28 = io_read_data[231:224]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_29 = io_read_data[239:232]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_30 = io_read_data[247:240]; // @[VLdSt.scala 50:24]
+ wire [7:0] data_io_in_bits_wdata_datain_31 = io_read_data[255:248]; // @[VLdSt.scala 50:24]
+ wire [4:0] data_io_in_bits_wdata_idx = 5'h0 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_0_value__0 = 5'h0 == data_io_in_bits_wdata_idx ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_0_value__1 = 5'h1 == data_io_in_bits_wdata_idx ?
@@ -88450,7 +88469,7 @@
data_io_in_bits_wdata_dataout_0_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_0_value_5_0 = data_io_in_bits_wdata_dataout_0_value_4_0 |
data_io_in_bits_wdata_dataout_0_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_1 = 5'h1 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_1 = 5'h1 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_1_value__0 = 5'h0 == data_io_in_bits_wdata_idx_1 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_1_value__1 = 5'h1 == data_io_in_bits_wdata_idx_1 ?
@@ -88577,7 +88596,7 @@
data_io_in_bits_wdata_dataout_1_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_1_value_5_0 = data_io_in_bits_wdata_dataout_1_value_4_0 |
data_io_in_bits_wdata_dataout_1_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_2 = 5'h2 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_2 = 5'h2 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_2_value__0 = 5'h0 == data_io_in_bits_wdata_idx_2 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_2_value__1 = 5'h1 == data_io_in_bits_wdata_idx_2 ?
@@ -88704,7 +88723,7 @@
data_io_in_bits_wdata_dataout_2_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_2_value_5_0 = data_io_in_bits_wdata_dataout_2_value_4_0 |
data_io_in_bits_wdata_dataout_2_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_3 = 5'h3 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_3 = 5'h3 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_3_value__0 = 5'h0 == data_io_in_bits_wdata_idx_3 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_3_value__1 = 5'h1 == data_io_in_bits_wdata_idx_3 ?
@@ -88831,7 +88850,7 @@
data_io_in_bits_wdata_dataout_3_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_3_value_5_0 = data_io_in_bits_wdata_dataout_3_value_4_0 |
data_io_in_bits_wdata_dataout_3_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_4 = 5'h4 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_4 = 5'h4 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_4_value__0 = 5'h0 == data_io_in_bits_wdata_idx_4 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_4_value__1 = 5'h1 == data_io_in_bits_wdata_idx_4 ?
@@ -88958,7 +88977,7 @@
data_io_in_bits_wdata_dataout_4_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_4_value_5_0 = data_io_in_bits_wdata_dataout_4_value_4_0 |
data_io_in_bits_wdata_dataout_4_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_5 = 5'h5 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_5 = 5'h5 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_5_value__0 = 5'h0 == data_io_in_bits_wdata_idx_5 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_5_value__1 = 5'h1 == data_io_in_bits_wdata_idx_5 ?
@@ -89085,7 +89104,7 @@
data_io_in_bits_wdata_dataout_5_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_5_value_5_0 = data_io_in_bits_wdata_dataout_5_value_4_0 |
data_io_in_bits_wdata_dataout_5_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_6 = 5'h6 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_6 = 5'h6 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_6_value__0 = 5'h0 == data_io_in_bits_wdata_idx_6 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_6_value__1 = 5'h1 == data_io_in_bits_wdata_idx_6 ?
@@ -89212,7 +89231,7 @@
data_io_in_bits_wdata_dataout_6_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_6_value_5_0 = data_io_in_bits_wdata_dataout_6_value_4_0 |
data_io_in_bits_wdata_dataout_6_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_7 = 5'h7 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_7 = 5'h7 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_7_value__0 = 5'h0 == data_io_in_bits_wdata_idx_7 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_7_value__1 = 5'h1 == data_io_in_bits_wdata_idx_7 ?
@@ -89339,7 +89358,7 @@
data_io_in_bits_wdata_dataout_7_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_7_value_5_0 = data_io_in_bits_wdata_dataout_7_value_4_0 |
data_io_in_bits_wdata_dataout_7_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_8 = 5'h8 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_8 = 5'h8 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_8_value__0 = 5'h0 == data_io_in_bits_wdata_idx_8 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_8_value__1 = 5'h1 == data_io_in_bits_wdata_idx_8 ?
@@ -89466,7 +89485,7 @@
data_io_in_bits_wdata_dataout_8_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_8_value_5_0 = data_io_in_bits_wdata_dataout_8_value_4_0 |
data_io_in_bits_wdata_dataout_8_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_9 = 5'h9 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_9 = 5'h9 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_9_value__0 = 5'h0 == data_io_in_bits_wdata_idx_9 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_9_value__1 = 5'h1 == data_io_in_bits_wdata_idx_9 ?
@@ -89593,7 +89612,7 @@
data_io_in_bits_wdata_dataout_9_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_9_value_5_0 = data_io_in_bits_wdata_dataout_9_value_4_0 |
data_io_in_bits_wdata_dataout_9_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_10 = 5'ha - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_10 = 5'ha - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_10_value__0 = 5'h0 == data_io_in_bits_wdata_idx_10 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_10_value__1 = 5'h1 == data_io_in_bits_wdata_idx_10 ?
@@ -89720,7 +89739,7 @@
data_io_in_bits_wdata_dataout_10_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_10_value_5_0 = data_io_in_bits_wdata_dataout_10_value_4_0 |
data_io_in_bits_wdata_dataout_10_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_11 = 5'hb - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_11 = 5'hb - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_11_value__0 = 5'h0 == data_io_in_bits_wdata_idx_11 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_11_value__1 = 5'h1 == data_io_in_bits_wdata_idx_11 ?
@@ -89847,7 +89866,7 @@
data_io_in_bits_wdata_dataout_11_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_11_value_5_0 = data_io_in_bits_wdata_dataout_11_value_4_0 |
data_io_in_bits_wdata_dataout_11_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_12 = 5'hc - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_12 = 5'hc - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_12_value__0 = 5'h0 == data_io_in_bits_wdata_idx_12 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_12_value__1 = 5'h1 == data_io_in_bits_wdata_idx_12 ?
@@ -89974,7 +89993,7 @@
data_io_in_bits_wdata_dataout_12_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_12_value_5_0 = data_io_in_bits_wdata_dataout_12_value_4_0 |
data_io_in_bits_wdata_dataout_12_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_13 = 5'hd - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_13 = 5'hd - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_13_value__0 = 5'h0 == data_io_in_bits_wdata_idx_13 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_13_value__1 = 5'h1 == data_io_in_bits_wdata_idx_13 ?
@@ -90101,7 +90120,7 @@
data_io_in_bits_wdata_dataout_13_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_13_value_5_0 = data_io_in_bits_wdata_dataout_13_value_4_0 |
data_io_in_bits_wdata_dataout_13_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_14 = 5'he - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_14 = 5'he - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_14_value__0 = 5'h0 == data_io_in_bits_wdata_idx_14 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_14_value__1 = 5'h1 == data_io_in_bits_wdata_idx_14 ?
@@ -90228,7 +90247,7 @@
data_io_in_bits_wdata_dataout_14_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_14_value_5_0 = data_io_in_bits_wdata_dataout_14_value_4_0 |
data_io_in_bits_wdata_dataout_14_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_15 = 5'hf - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_15 = 5'hf - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_15_value__0 = 5'h0 == data_io_in_bits_wdata_idx_15 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_15_value__1 = 5'h1 == data_io_in_bits_wdata_idx_15 ?
@@ -90355,7 +90374,7 @@
data_io_in_bits_wdata_dataout_15_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_15_value_5_0 = data_io_in_bits_wdata_dataout_15_value_4_0 |
data_io_in_bits_wdata_dataout_15_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_16 = 5'h10 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_16 = 5'h10 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_16_value__0 = 5'h0 == data_io_in_bits_wdata_idx_16 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_16_value__1 = 5'h1 == data_io_in_bits_wdata_idx_16 ?
@@ -90482,7 +90501,7 @@
data_io_in_bits_wdata_dataout_16_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_16_value_5_0 = data_io_in_bits_wdata_dataout_16_value_4_0 |
data_io_in_bits_wdata_dataout_16_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_17 = 5'h11 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_17 = 5'h11 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_17_value__0 = 5'h0 == data_io_in_bits_wdata_idx_17 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_17_value__1 = 5'h1 == data_io_in_bits_wdata_idx_17 ?
@@ -90609,7 +90628,7 @@
data_io_in_bits_wdata_dataout_17_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_17_value_5_0 = data_io_in_bits_wdata_dataout_17_value_4_0 |
data_io_in_bits_wdata_dataout_17_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_18 = 5'h12 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_18 = 5'h12 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_18_value__0 = 5'h0 == data_io_in_bits_wdata_idx_18 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_18_value__1 = 5'h1 == data_io_in_bits_wdata_idx_18 ?
@@ -90736,7 +90755,7 @@
data_io_in_bits_wdata_dataout_18_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_18_value_5_0 = data_io_in_bits_wdata_dataout_18_value_4_0 |
data_io_in_bits_wdata_dataout_18_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_19 = 5'h13 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_19 = 5'h13 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_19_value__0 = 5'h0 == data_io_in_bits_wdata_idx_19 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_19_value__1 = 5'h1 == data_io_in_bits_wdata_idx_19 ?
@@ -90863,7 +90882,7 @@
data_io_in_bits_wdata_dataout_19_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_19_value_5_0 = data_io_in_bits_wdata_dataout_19_value_4_0 |
data_io_in_bits_wdata_dataout_19_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_20 = 5'h14 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_20 = 5'h14 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_20_value__0 = 5'h0 == data_io_in_bits_wdata_idx_20 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_20_value__1 = 5'h1 == data_io_in_bits_wdata_idx_20 ?
@@ -90990,7 +91009,7 @@
data_io_in_bits_wdata_dataout_20_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_20_value_5_0 = data_io_in_bits_wdata_dataout_20_value_4_0 |
data_io_in_bits_wdata_dataout_20_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_21 = 5'h15 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_21 = 5'h15 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_21_value__0 = 5'h0 == data_io_in_bits_wdata_idx_21 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_21_value__1 = 5'h1 == data_io_in_bits_wdata_idx_21 ?
@@ -91117,7 +91136,7 @@
data_io_in_bits_wdata_dataout_21_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_21_value_5_0 = data_io_in_bits_wdata_dataout_21_value_4_0 |
data_io_in_bits_wdata_dataout_21_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_22 = 5'h16 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_22 = 5'h16 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_22_value__0 = 5'h0 == data_io_in_bits_wdata_idx_22 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_22_value__1 = 5'h1 == data_io_in_bits_wdata_idx_22 ?
@@ -91244,7 +91263,7 @@
data_io_in_bits_wdata_dataout_22_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_22_value_5_0 = data_io_in_bits_wdata_dataout_22_value_4_0 |
data_io_in_bits_wdata_dataout_22_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_23 = 5'h17 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_23 = 5'h17 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_23_value__0 = 5'h0 == data_io_in_bits_wdata_idx_23 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_23_value__1 = 5'h1 == data_io_in_bits_wdata_idx_23 ?
@@ -91371,7 +91390,7 @@
data_io_in_bits_wdata_dataout_23_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_23_value_5_0 = data_io_in_bits_wdata_dataout_23_value_4_0 |
data_io_in_bits_wdata_dataout_23_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_24 = 5'h18 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_24 = 5'h18 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_24_value__0 = 5'h0 == data_io_in_bits_wdata_idx_24 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_24_value__1 = 5'h1 == data_io_in_bits_wdata_idx_24 ?
@@ -91498,7 +91517,7 @@
data_io_in_bits_wdata_dataout_24_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_24_value_5_0 = data_io_in_bits_wdata_dataout_24_value_4_0 |
data_io_in_bits_wdata_dataout_24_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_25 = 5'h19 - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_25 = 5'h19 - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_25_value__0 = 5'h0 == data_io_in_bits_wdata_idx_25 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_25_value__1 = 5'h1 == data_io_in_bits_wdata_idx_25 ?
@@ -91625,7 +91644,7 @@
data_io_in_bits_wdata_dataout_25_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_25_value_5_0 = data_io_in_bits_wdata_dataout_25_value_4_0 |
data_io_in_bits_wdata_dataout_25_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_26 = 5'h1a - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_26 = 5'h1a - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_26_value__0 = 5'h0 == data_io_in_bits_wdata_idx_26 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_26_value__1 = 5'h1 == data_io_in_bits_wdata_idx_26 ?
@@ -91752,7 +91771,7 @@
data_io_in_bits_wdata_dataout_26_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_26_value_5_0 = data_io_in_bits_wdata_dataout_26_value_4_0 |
data_io_in_bits_wdata_dataout_26_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_27 = 5'h1b - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_27 = 5'h1b - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_27_value__0 = 5'h0 == data_io_in_bits_wdata_idx_27 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_27_value__1 = 5'h1 == data_io_in_bits_wdata_idx_27 ?
@@ -91879,7 +91898,7 @@
data_io_in_bits_wdata_dataout_27_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_27_value_5_0 = data_io_in_bits_wdata_dataout_27_value_4_0 |
data_io_in_bits_wdata_dataout_27_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_28 = 5'h1c - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_28 = 5'h1c - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_28_value__0 = 5'h0 == data_io_in_bits_wdata_idx_28 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_28_value__1 = 5'h1 == data_io_in_bits_wdata_idx_28 ?
@@ -92006,7 +92025,7 @@
data_io_in_bits_wdata_dataout_28_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_28_value_5_0 = data_io_in_bits_wdata_dataout_28_value_4_0 |
data_io_in_bits_wdata_dataout_28_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_29 = 5'h1d - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_29 = 5'h1d - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_29_value__0 = 5'h0 == data_io_in_bits_wdata_idx_29 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_29_value__1 = 5'h1 == data_io_in_bits_wdata_idx_29 ?
@@ -92133,7 +92152,7 @@
data_io_in_bits_wdata_dataout_29_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_29_value_5_0 = data_io_in_bits_wdata_dataout_29_value_4_0 |
data_io_in_bits_wdata_dataout_29_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_30 = 5'h1e - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_30 = 5'h1e - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_30_value__0 = 5'h0 == data_io_in_bits_wdata_idx_30 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_30_value__1 = 5'h1 == data_io_in_bits_wdata_idx_30 ?
@@ -92260,7 +92279,7 @@
data_io_in_bits_wdata_dataout_30_value_3_3; // @[Library.scala 115:37]
wire [7:0] data_io_in_bits_wdata_dataout_30_value_5_0 = data_io_in_bits_wdata_dataout_30_value_4_0 |
data_io_in_bits_wdata_dataout_30_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wdata_idx_31 = 5'h1f - rdataAshf; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wdata_idx_31 = 5'h1f - rdataAshf; // @[VLdSt.scala 55:52]
wire [7:0] data_io_in_bits_wdata_dataout_31_value__0 = 5'h0 == data_io_in_bits_wdata_idx_31 ?
data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] data_io_in_bits_wdata_dataout_31_value__1 = 5'h1 == data_io_in_bits_wdata_idx_31 ?
@@ -92391,63 +92410,63 @@
data_io_in_bits_wdata_dataout_6_value_5_0,data_io_in_bits_wdata_dataout_5_value_5_0,
data_io_in_bits_wdata_dataout_4_value_5_0,data_io_in_bits_wdata_dataout_3_value_5_0,
data_io_in_bits_wdata_dataout_2_value_5_0,data_io_in_bits_wdata_dataout_1_value_5_0,
- data_io_in_bits_wdata_dataout_0_value_5_0}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wdata_dataout_0_value_5_0}; // @[VLdSt.scala 60:13]
wire [127:0] data_io_in_bits_wdata_lo = {data_io_in_bits_wdata_dataout_15_value_5_0,
data_io_in_bits_wdata_dataout_14_value_5_0,data_io_in_bits_wdata_dataout_13_value_5_0,
data_io_in_bits_wdata_dataout_12_value_5_0,data_io_in_bits_wdata_dataout_11_value_5_0,
data_io_in_bits_wdata_dataout_10_value_5_0,data_io_in_bits_wdata_dataout_9_value_5_0,
- data_io_in_bits_wdata_dataout_8_value_5_0,data_io_in_bits_wdata_lo_lo}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wdata_dataout_8_value_5_0,data_io_in_bits_wdata_lo_lo}; // @[VLdSt.scala 60:13]
wire [63:0] data_io_in_bits_wdata_hi_lo = {data_io_in_bits_wdata_dataout_23_value_5_0,
data_io_in_bits_wdata_dataout_22_value_5_0,data_io_in_bits_wdata_dataout_21_value_5_0,
data_io_in_bits_wdata_dataout_20_value_5_0,data_io_in_bits_wdata_dataout_19_value_5_0,
data_io_in_bits_wdata_dataout_18_value_5_0,data_io_in_bits_wdata_dataout_17_value_5_0,
- data_io_in_bits_wdata_dataout_16_value_5_0}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wdata_dataout_16_value_5_0}; // @[VLdSt.scala 60:13]
wire [127:0] data_io_in_bits_wdata_hi = {data_io_in_bits_wdata_dataout_31_value_5_0,
data_io_in_bits_wdata_dataout_30_value_5_0,data_io_in_bits_wdata_dataout_29_value_5_0,
data_io_in_bits_wdata_dataout_28_value_5_0,data_io_in_bits_wdata_dataout_27_value_5_0,
data_io_in_bits_wdata_dataout_26_value_5_0,data_io_in_bits_wdata_dataout_25_value_5_0,
- data_io_in_bits_wdata_dataout_24_value_5_0,data_io_in_bits_wdata_hi_lo}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wdata_dataout_24_value_5_0,data_io_in_bits_wdata_hi_lo}; // @[VLdSt.scala 60:13]
wire [7:0] data_io_in_bits_wmask_lo_lo = {rdataWmask_7,rdataWmask_6,rdataWmask_5,rdataWmask_4,rdataWmask_3,
- rdataWmask_2,rdataWmask_1,rdataWmask_0}; // @[VLdSt.scala 239:68]
+ rdataWmask_2,rdataWmask_1,rdataWmask_0}; // @[VLdSt.scala 242:68]
wire [15:0] data_io_in_bits_wmask_lo = {rdataWmask_15,rdataWmask_14,rdataWmask_13,rdataWmask_12,rdataWmask_11,
- rdataWmask_10,rdataWmask_9,rdataWmask_8,data_io_in_bits_wmask_lo_lo}; // @[VLdSt.scala 239:68]
+ rdataWmask_10,rdataWmask_9,rdataWmask_8,data_io_in_bits_wmask_lo_lo}; // @[VLdSt.scala 242:68]
wire [7:0] data_io_in_bits_wmask_hi_lo = {rdataWmask_23,rdataWmask_22,rdataWmask_21,rdataWmask_20,rdataWmask_19,
- rdataWmask_18,rdataWmask_17,rdataWmask_16}; // @[VLdSt.scala 239:68]
+ rdataWmask_18,rdataWmask_17,rdataWmask_16}; // @[VLdSt.scala 242:68]
wire [31:0] _data_io_in_bits_wmask_T = {rdataWmask_31,rdataWmask_30,rdataWmask_29,rdataWmask_28,rdataWmask_27,
- rdataWmask_26,rdataWmask_25,rdataWmask_24,data_io_in_bits_wmask_hi_lo,data_io_in_bits_wmask_lo}; // @[VLdSt.scala 239:68]
- wire data_io_in_bits_wmask_datain_0 = _data_io_in_bits_wmask_T[0]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_1 = _data_io_in_bits_wmask_T[1]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_2 = _data_io_in_bits_wmask_T[2]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_3 = _data_io_in_bits_wmask_T[3]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_4 = _data_io_in_bits_wmask_T[4]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_5 = _data_io_in_bits_wmask_T[5]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_6 = _data_io_in_bits_wmask_T[6]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_7 = _data_io_in_bits_wmask_T[7]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_8 = _data_io_in_bits_wmask_T[8]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_9 = _data_io_in_bits_wmask_T[9]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_10 = _data_io_in_bits_wmask_T[10]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_11 = _data_io_in_bits_wmask_T[11]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_12 = _data_io_in_bits_wmask_T[12]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_13 = _data_io_in_bits_wmask_T[13]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_14 = _data_io_in_bits_wmask_T[14]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_15 = _data_io_in_bits_wmask_T[15]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_16 = _data_io_in_bits_wmask_T[16]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_17 = _data_io_in_bits_wmask_T[17]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_18 = _data_io_in_bits_wmask_T[18]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_19 = _data_io_in_bits_wmask_T[19]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_20 = _data_io_in_bits_wmask_T[20]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_21 = _data_io_in_bits_wmask_T[21]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_22 = _data_io_in_bits_wmask_T[22]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_23 = _data_io_in_bits_wmask_T[23]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_24 = _data_io_in_bits_wmask_T[24]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_25 = _data_io_in_bits_wmask_T[25]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_26 = _data_io_in_bits_wmask_T[26]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_27 = _data_io_in_bits_wmask_T[27]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_28 = _data_io_in_bits_wmask_T[28]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_29 = _data_io_in_bits_wmask_T[29]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_30 = _data_io_in_bits_wmask_T[30]; // @[VLdSt.scala 47:24]
- wire data_io_in_bits_wmask_datain_31 = _data_io_in_bits_wmask_T[31]; // @[VLdSt.scala 47:24]
- wire [4:0] data_io_in_bits_wmask_idx = 5'h0 - rdataAddr; // @[VLdSt.scala 52:53]
+ rdataWmask_26,rdataWmask_25,rdataWmask_24,data_io_in_bits_wmask_hi_lo,data_io_in_bits_wmask_lo}; // @[VLdSt.scala 242:68]
+ wire data_io_in_bits_wmask_datain_0 = _data_io_in_bits_wmask_T[0]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_1 = _data_io_in_bits_wmask_T[1]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_2 = _data_io_in_bits_wmask_T[2]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_3 = _data_io_in_bits_wmask_T[3]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_4 = _data_io_in_bits_wmask_T[4]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_5 = _data_io_in_bits_wmask_T[5]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_6 = _data_io_in_bits_wmask_T[6]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_7 = _data_io_in_bits_wmask_T[7]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_8 = _data_io_in_bits_wmask_T[8]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_9 = _data_io_in_bits_wmask_T[9]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_10 = _data_io_in_bits_wmask_T[10]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_11 = _data_io_in_bits_wmask_T[11]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_12 = _data_io_in_bits_wmask_T[12]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_13 = _data_io_in_bits_wmask_T[13]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_14 = _data_io_in_bits_wmask_T[14]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_15 = _data_io_in_bits_wmask_T[15]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_16 = _data_io_in_bits_wmask_T[16]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_17 = _data_io_in_bits_wmask_T[17]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_18 = _data_io_in_bits_wmask_T[18]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_19 = _data_io_in_bits_wmask_T[19]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_20 = _data_io_in_bits_wmask_T[20]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_21 = _data_io_in_bits_wmask_T[21]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_22 = _data_io_in_bits_wmask_T[22]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_23 = _data_io_in_bits_wmask_T[23]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_24 = _data_io_in_bits_wmask_T[24]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_25 = _data_io_in_bits_wmask_T[25]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_26 = _data_io_in_bits_wmask_T[26]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_27 = _data_io_in_bits_wmask_T[27]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_28 = _data_io_in_bits_wmask_T[28]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_29 = _data_io_in_bits_wmask_T[29]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_30 = _data_io_in_bits_wmask_T[30]; // @[VLdSt.scala 50:24]
+ wire data_io_in_bits_wmask_datain_31 = _data_io_in_bits_wmask_T[31]; // @[VLdSt.scala 50:24]
+ wire [4:0] data_io_in_bits_wmask_idx = 5'h0 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_0_value__0 = 5'h0 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_0_value__1 = 5'h1 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_0_value__2 = 5'h2 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92558,7 +92577,7 @@
data_io_in_bits_wmask_dataout_0_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_0_value_5_0 = data_io_in_bits_wmask_dataout_0_value_4_0 |
data_io_in_bits_wmask_dataout_0_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_1 = 5'h1 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_1 = 5'h1 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_1_value__0 = 5'h0 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_1_value__1 = 5'h1 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_1_value__2 = 5'h2 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92675,7 +92694,7 @@
data_io_in_bits_wmask_dataout_1_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_1_value_5_0 = data_io_in_bits_wmask_dataout_1_value_4_0 |
data_io_in_bits_wmask_dataout_1_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_2 = 5'h2 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_2 = 5'h2 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_2_value__0 = 5'h0 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_2_value__1 = 5'h1 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_2_value__2 = 5'h2 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92792,7 +92811,7 @@
data_io_in_bits_wmask_dataout_2_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_2_value_5_0 = data_io_in_bits_wmask_dataout_2_value_4_0 |
data_io_in_bits_wmask_dataout_2_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_3 = 5'h3 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_3 = 5'h3 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_3_value__0 = 5'h0 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_3_value__1 = 5'h1 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_3_value__2 = 5'h2 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92909,7 +92928,7 @@
data_io_in_bits_wmask_dataout_3_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_3_value_5_0 = data_io_in_bits_wmask_dataout_3_value_4_0 |
data_io_in_bits_wmask_dataout_3_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_4 = 5'h4 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_4 = 5'h4 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_4_value__0 = 5'h0 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_4_value__1 = 5'h1 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_4_value__2 = 5'h2 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93026,7 +93045,7 @@
data_io_in_bits_wmask_dataout_4_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_4_value_5_0 = data_io_in_bits_wmask_dataout_4_value_4_0 |
data_io_in_bits_wmask_dataout_4_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_5 = 5'h5 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_5 = 5'h5 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_5_value__0 = 5'h0 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_5_value__1 = 5'h1 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_5_value__2 = 5'h2 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93143,7 +93162,7 @@
data_io_in_bits_wmask_dataout_5_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_5_value_5_0 = data_io_in_bits_wmask_dataout_5_value_4_0 |
data_io_in_bits_wmask_dataout_5_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_6 = 5'h6 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_6 = 5'h6 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_6_value__0 = 5'h0 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_6_value__1 = 5'h1 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_6_value__2 = 5'h2 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93260,7 +93279,7 @@
data_io_in_bits_wmask_dataout_6_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_6_value_5_0 = data_io_in_bits_wmask_dataout_6_value_4_0 |
data_io_in_bits_wmask_dataout_6_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_7 = 5'h7 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_7 = 5'h7 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_7_value__0 = 5'h0 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_7_value__1 = 5'h1 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_7_value__2 = 5'h2 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93377,7 +93396,7 @@
data_io_in_bits_wmask_dataout_7_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_7_value_5_0 = data_io_in_bits_wmask_dataout_7_value_4_0 |
data_io_in_bits_wmask_dataout_7_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_8 = 5'h8 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_8 = 5'h8 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_8_value__0 = 5'h0 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_8_value__1 = 5'h1 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_8_value__2 = 5'h2 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93494,7 +93513,7 @@
data_io_in_bits_wmask_dataout_8_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_8_value_5_0 = data_io_in_bits_wmask_dataout_8_value_4_0 |
data_io_in_bits_wmask_dataout_8_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_9 = 5'h9 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_9 = 5'h9 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_9_value__0 = 5'h0 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_9_value__1 = 5'h1 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_9_value__2 = 5'h2 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93611,7 +93630,7 @@
data_io_in_bits_wmask_dataout_9_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_9_value_5_0 = data_io_in_bits_wmask_dataout_9_value_4_0 |
data_io_in_bits_wmask_dataout_9_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_10 = 5'ha - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_10 = 5'ha - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_10_value__0 = 5'h0 == data_io_in_bits_wmask_idx_10 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_10_value__1 = 5'h1 == data_io_in_bits_wmask_idx_10 &
@@ -93738,7 +93757,7 @@
data_io_in_bits_wmask_dataout_10_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_10_value_5_0 = data_io_in_bits_wmask_dataout_10_value_4_0 |
data_io_in_bits_wmask_dataout_10_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_11 = 5'hb - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_11 = 5'hb - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_11_value__0 = 5'h0 == data_io_in_bits_wmask_idx_11 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_11_value__1 = 5'h1 == data_io_in_bits_wmask_idx_11 &
@@ -93865,7 +93884,7 @@
data_io_in_bits_wmask_dataout_11_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_11_value_5_0 = data_io_in_bits_wmask_dataout_11_value_4_0 |
data_io_in_bits_wmask_dataout_11_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_12 = 5'hc - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_12 = 5'hc - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_12_value__0 = 5'h0 == data_io_in_bits_wmask_idx_12 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_12_value__1 = 5'h1 == data_io_in_bits_wmask_idx_12 &
@@ -93992,7 +94011,7 @@
data_io_in_bits_wmask_dataout_12_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_12_value_5_0 = data_io_in_bits_wmask_dataout_12_value_4_0 |
data_io_in_bits_wmask_dataout_12_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_13 = 5'hd - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_13 = 5'hd - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_13_value__0 = 5'h0 == data_io_in_bits_wmask_idx_13 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_13_value__1 = 5'h1 == data_io_in_bits_wmask_idx_13 &
@@ -94119,7 +94138,7 @@
data_io_in_bits_wmask_dataout_13_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_13_value_5_0 = data_io_in_bits_wmask_dataout_13_value_4_0 |
data_io_in_bits_wmask_dataout_13_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_14 = 5'he - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_14 = 5'he - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_14_value__0 = 5'h0 == data_io_in_bits_wmask_idx_14 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_14_value__1 = 5'h1 == data_io_in_bits_wmask_idx_14 &
@@ -94246,7 +94265,7 @@
data_io_in_bits_wmask_dataout_14_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_14_value_5_0 = data_io_in_bits_wmask_dataout_14_value_4_0 |
data_io_in_bits_wmask_dataout_14_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_15 = 5'hf - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_15 = 5'hf - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_15_value__0 = 5'h0 == data_io_in_bits_wmask_idx_15 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_15_value__1 = 5'h1 == data_io_in_bits_wmask_idx_15 &
@@ -94373,7 +94392,7 @@
data_io_in_bits_wmask_dataout_15_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_15_value_5_0 = data_io_in_bits_wmask_dataout_15_value_4_0 |
data_io_in_bits_wmask_dataout_15_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_16 = 5'h10 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_16 = 5'h10 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_16_value__0 = 5'h0 == data_io_in_bits_wmask_idx_16 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_16_value__1 = 5'h1 == data_io_in_bits_wmask_idx_16 &
@@ -94500,7 +94519,7 @@
data_io_in_bits_wmask_dataout_16_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_16_value_5_0 = data_io_in_bits_wmask_dataout_16_value_4_0 |
data_io_in_bits_wmask_dataout_16_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_17 = 5'h11 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_17 = 5'h11 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_17_value__0 = 5'h0 == data_io_in_bits_wmask_idx_17 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_17_value__1 = 5'h1 == data_io_in_bits_wmask_idx_17 &
@@ -94627,7 +94646,7 @@
data_io_in_bits_wmask_dataout_17_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_17_value_5_0 = data_io_in_bits_wmask_dataout_17_value_4_0 |
data_io_in_bits_wmask_dataout_17_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_18 = 5'h12 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_18 = 5'h12 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_18_value__0 = 5'h0 == data_io_in_bits_wmask_idx_18 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_18_value__1 = 5'h1 == data_io_in_bits_wmask_idx_18 &
@@ -94754,7 +94773,7 @@
data_io_in_bits_wmask_dataout_18_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_18_value_5_0 = data_io_in_bits_wmask_dataout_18_value_4_0 |
data_io_in_bits_wmask_dataout_18_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_19 = 5'h13 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_19 = 5'h13 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_19_value__0 = 5'h0 == data_io_in_bits_wmask_idx_19 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_19_value__1 = 5'h1 == data_io_in_bits_wmask_idx_19 &
@@ -94881,7 +94900,7 @@
data_io_in_bits_wmask_dataout_19_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_19_value_5_0 = data_io_in_bits_wmask_dataout_19_value_4_0 |
data_io_in_bits_wmask_dataout_19_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_20 = 5'h14 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_20 = 5'h14 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_20_value__0 = 5'h0 == data_io_in_bits_wmask_idx_20 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_20_value__1 = 5'h1 == data_io_in_bits_wmask_idx_20 &
@@ -95008,7 +95027,7 @@
data_io_in_bits_wmask_dataout_20_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_20_value_5_0 = data_io_in_bits_wmask_dataout_20_value_4_0 |
data_io_in_bits_wmask_dataout_20_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_21 = 5'h15 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_21 = 5'h15 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_21_value__0 = 5'h0 == data_io_in_bits_wmask_idx_21 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_21_value__1 = 5'h1 == data_io_in_bits_wmask_idx_21 &
@@ -95135,7 +95154,7 @@
data_io_in_bits_wmask_dataout_21_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_21_value_5_0 = data_io_in_bits_wmask_dataout_21_value_4_0 |
data_io_in_bits_wmask_dataout_21_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_22 = 5'h16 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_22 = 5'h16 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_22_value__0 = 5'h0 == data_io_in_bits_wmask_idx_22 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_22_value__1 = 5'h1 == data_io_in_bits_wmask_idx_22 &
@@ -95262,7 +95281,7 @@
data_io_in_bits_wmask_dataout_22_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_22_value_5_0 = data_io_in_bits_wmask_dataout_22_value_4_0 |
data_io_in_bits_wmask_dataout_22_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_23 = 5'h17 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_23 = 5'h17 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_23_value__0 = 5'h0 == data_io_in_bits_wmask_idx_23 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_23_value__1 = 5'h1 == data_io_in_bits_wmask_idx_23 &
@@ -95389,7 +95408,7 @@
data_io_in_bits_wmask_dataout_23_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_23_value_5_0 = data_io_in_bits_wmask_dataout_23_value_4_0 |
data_io_in_bits_wmask_dataout_23_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_24 = 5'h18 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_24 = 5'h18 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_24_value__0 = 5'h0 == data_io_in_bits_wmask_idx_24 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_24_value__1 = 5'h1 == data_io_in_bits_wmask_idx_24 &
@@ -95516,7 +95535,7 @@
data_io_in_bits_wmask_dataout_24_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_24_value_5_0 = data_io_in_bits_wmask_dataout_24_value_4_0 |
data_io_in_bits_wmask_dataout_24_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_25 = 5'h19 - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_25 = 5'h19 - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_25_value__0 = 5'h0 == data_io_in_bits_wmask_idx_25 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_25_value__1 = 5'h1 == data_io_in_bits_wmask_idx_25 &
@@ -95643,7 +95662,7 @@
data_io_in_bits_wmask_dataout_25_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_25_value_5_0 = data_io_in_bits_wmask_dataout_25_value_4_0 |
data_io_in_bits_wmask_dataout_25_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_26 = 5'h1a - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_26 = 5'h1a - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_26_value__0 = 5'h0 == data_io_in_bits_wmask_idx_26 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_26_value__1 = 5'h1 == data_io_in_bits_wmask_idx_26 &
@@ -95770,7 +95789,7 @@
data_io_in_bits_wmask_dataout_26_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_26_value_5_0 = data_io_in_bits_wmask_dataout_26_value_4_0 |
data_io_in_bits_wmask_dataout_26_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_27 = 5'h1b - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_27 = 5'h1b - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_27_value__0 = 5'h0 == data_io_in_bits_wmask_idx_27 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_27_value__1 = 5'h1 == data_io_in_bits_wmask_idx_27 &
@@ -95897,7 +95916,7 @@
data_io_in_bits_wmask_dataout_27_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_27_value_5_0 = data_io_in_bits_wmask_dataout_27_value_4_0 |
data_io_in_bits_wmask_dataout_27_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_28 = 5'h1c - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_28 = 5'h1c - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_28_value__0 = 5'h0 == data_io_in_bits_wmask_idx_28 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_28_value__1 = 5'h1 == data_io_in_bits_wmask_idx_28 &
@@ -96024,7 +96043,7 @@
data_io_in_bits_wmask_dataout_28_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_28_value_5_0 = data_io_in_bits_wmask_dataout_28_value_4_0 |
data_io_in_bits_wmask_dataout_28_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_29 = 5'h1d - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_29 = 5'h1d - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_29_value__0 = 5'h0 == data_io_in_bits_wmask_idx_29 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_29_value__1 = 5'h1 == data_io_in_bits_wmask_idx_29 &
@@ -96151,7 +96170,7 @@
data_io_in_bits_wmask_dataout_29_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_29_value_5_0 = data_io_in_bits_wmask_dataout_29_value_4_0 |
data_io_in_bits_wmask_dataout_29_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_30 = 5'h1e - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_30 = 5'h1e - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_30_value__0 = 5'h0 == data_io_in_bits_wmask_idx_30 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_30_value__1 = 5'h1 == data_io_in_bits_wmask_idx_30 &
@@ -96278,7 +96297,7 @@
data_io_in_bits_wmask_dataout_30_value_3_3; // @[Library.scala 115:37]
wire data_io_in_bits_wmask_dataout_30_value_5_0 = data_io_in_bits_wmask_dataout_30_value_4_0 |
data_io_in_bits_wmask_dataout_30_value_4_1; // @[Library.scala 115:37]
- wire [4:0] data_io_in_bits_wmask_idx_31 = 5'h1f - rdataAddr; // @[VLdSt.scala 52:53]
+ wire [4:0] data_io_in_bits_wmask_idx_31 = 5'h1f - rdataAddr; // @[VLdSt.scala 55:52]
wire data_io_in_bits_wmask_dataout_31_value__0 = 5'h0 == data_io_in_bits_wmask_idx_31 &
data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
wire data_io_in_bits_wmask_dataout_31_value__1 = 5'h1 == data_io_in_bits_wmask_idx_31 &
@@ -96409,128 +96428,128 @@
data_io_in_bits_wmask_dataout_6_value_5_0,data_io_in_bits_wmask_dataout_5_value_5_0,
data_io_in_bits_wmask_dataout_4_value_5_0,data_io_in_bits_wmask_dataout_3_value_5_0,
data_io_in_bits_wmask_dataout_2_value_5_0,data_io_in_bits_wmask_dataout_1_value_5_0,
- data_io_in_bits_wmask_dataout_0_value_5_0}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wmask_dataout_0_value_5_0}; // @[VLdSt.scala 60:13]
wire [15:0] data_io_in_bits_wmask_lo_1 = {data_io_in_bits_wmask_dataout_15_value_5_0,
data_io_in_bits_wmask_dataout_14_value_5_0,data_io_in_bits_wmask_dataout_13_value_5_0,
data_io_in_bits_wmask_dataout_12_value_5_0,data_io_in_bits_wmask_dataout_11_value_5_0,
data_io_in_bits_wmask_dataout_10_value_5_0,data_io_in_bits_wmask_dataout_9_value_5_0,
- data_io_in_bits_wmask_dataout_8_value_5_0,data_io_in_bits_wmask_lo_lo_1}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wmask_dataout_8_value_5_0,data_io_in_bits_wmask_lo_lo_1}; // @[VLdSt.scala 60:13]
wire [7:0] data_io_in_bits_wmask_hi_lo_1 = {data_io_in_bits_wmask_dataout_23_value_5_0,
data_io_in_bits_wmask_dataout_22_value_5_0,data_io_in_bits_wmask_dataout_21_value_5_0,
data_io_in_bits_wmask_dataout_20_value_5_0,data_io_in_bits_wmask_dataout_19_value_5_0,
data_io_in_bits_wmask_dataout_18_value_5_0,data_io_in_bits_wmask_dataout_17_value_5_0,
- data_io_in_bits_wmask_dataout_16_value_5_0}; // @[VLdSt.scala 57:13]
+ data_io_in_bits_wmask_dataout_16_value_5_0}; // @[VLdSt.scala 60:13]
wire [15:0] data_io_in_bits_wmask_hi_1 = {data_io_in_bits_wmask_dataout_31_value_5_0,
data_io_in_bits_wmask_dataout_30_value_5_0,data_io_in_bits_wmask_dataout_29_value_5_0,
data_io_in_bits_wmask_dataout_28_value_5_0,data_io_in_bits_wmask_dataout_27_value_5_0,
data_io_in_bits_wmask_dataout_26_value_5_0,data_io_in_bits_wmask_dataout_25_value_5_0,
- data_io_in_bits_wmask_dataout_24_value_5_0,data_io_in_bits_wmask_hi_lo_1}; // @[VLdSt.scala 57:13]
- wire _ctrl_io_out_ready_T = ~ctrl_io_out_bits_write; // @[VLdSt.scala 242:63]
- wire _ctrl_io_out_ready_T_1 = data_io_out_valid | ~ctrl_io_out_bits_write; // @[VLdSt.scala 242:60]
- reg wdataEn; // @[VLdSt.scala 264:24]
- wire _maskb_1_T = 6'h1 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ data_io_in_bits_wmask_dataout_24_value_5_0,data_io_in_bits_wmask_hi_lo_1}; // @[VLdSt.scala 60:13]
+ wire _ctrl_io_out_ready_T = ~ctrl_io_out_bits_write; // @[VLdSt.scala 245:63]
+ wire _ctrl_io_out_ready_T_1 = data_io_out_valid | ~ctrl_io_out_bits_write; // @[VLdSt.scala 245:60]
+ reg wdataEn; // @[VLdSt.scala 267:24]
+ wire _maskb_1_T = 6'h1 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_1 = _maskb_1_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_0_T = 6'h0 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_0_T = 6'h0 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_0 = _maskb_0_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_3_T = 6'h3 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_3_T = 6'h3 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_3 = _maskb_3_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_2_T = 6'h2 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_2_T = 6'h2 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_2 = _maskb_2_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_5_T = 6'h5 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_5_T = 6'h5 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_5 = _maskb_5_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_4_T = 6'h4 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_4_T = 6'h4 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_4 = _maskb_4_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_7_T = 6'h7 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_7_T = 6'h7 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_7 = _maskb_7_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_6_T = 6'h6 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_6_T = 6'h6 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_6 = _maskb_6_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire [63:0] mask_lo_lo = {maskb_7,maskb_6,maskb_5,maskb_4,maskb_3,maskb_2,maskb_1,maskb_0}; // @[VLdSt.scala 281:20]
- wire _maskb_9_T = 6'h9 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire [63:0] mask_lo_lo = {maskb_7,maskb_6,maskb_5,maskb_4,maskb_3,maskb_2,maskb_1,maskb_0}; // @[VLdSt.scala 284:20]
+ wire _maskb_9_T = 6'h9 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_9 = _maskb_9_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_8_T = 6'h8 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_8_T = 6'h8 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_8 = _maskb_8_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_11_T = 6'hb < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_11_T = 6'hb < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_11 = _maskb_11_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_10_T = 6'ha < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_10_T = 6'ha < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_10 = _maskb_10_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_13_T = 6'hd < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_13_T = 6'hd < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_13 = _maskb_13_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_12_T = 6'hc < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_12_T = 6'hc < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_12 = _maskb_12_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_15_T = 6'hf < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_15_T = 6'hf < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_15 = _maskb_15_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_14_T = 6'he < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_14_T = 6'he < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_14 = _maskb_14_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire [127:0] mask_lo = {maskb_15,maskb_14,maskb_13,maskb_12,maskb_11,maskb_10,maskb_9,maskb_8,mask_lo_lo}; // @[VLdSt.scala 281:20]
- wire _maskb_17_T = 6'h11 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire [127:0] mask_lo = {maskb_15,maskb_14,maskb_13,maskb_12,maskb_11,maskb_10,maskb_9,maskb_8,mask_lo_lo}; // @[VLdSt.scala 284:20]
+ wire _maskb_17_T = 6'h11 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_17 = _maskb_17_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_16_T = 6'h10 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_16_T = 6'h10 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_16 = _maskb_16_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_19_T = 6'h13 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_19_T = 6'h13 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_19 = _maskb_19_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_18_T = 6'h12 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_18_T = 6'h12 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_18 = _maskb_18_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_21_T = 6'h15 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_21_T = 6'h15 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_21 = _maskb_21_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_20_T = 6'h14 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_20_T = 6'h14 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_20 = _maskb_20_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_23_T = 6'h17 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_23_T = 6'h17 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_23 = _maskb_23_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_22_T = 6'h16 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_22_T = 6'h16 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_22 = _maskb_22_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire [63:0] mask_hi_lo = {maskb_23,maskb_22,maskb_21,maskb_20,maskb_19,maskb_18,maskb_17,maskb_16}; // @[VLdSt.scala 281:20]
- wire _maskb_25_T = 6'h19 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire [63:0] mask_hi_lo = {maskb_23,maskb_22,maskb_21,maskb_20,maskb_19,maskb_18,maskb_17,maskb_16}; // @[VLdSt.scala 284:20]
+ wire _maskb_25_T = 6'h19 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_25 = _maskb_25_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_24_T = 6'h18 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_24_T = 6'h18 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_24 = _maskb_24_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_27_T = 6'h1b < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_27_T = 6'h1b < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_27 = _maskb_27_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_26_T = 6'h1a < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_26_T = 6'h1a < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_26 = _maskb_26_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_29_T = 6'h1d < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_29_T = 6'h1d < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_29 = _maskb_29_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_28_T = 6'h1c < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_28_T = 6'h1c < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_28 = _maskb_28_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_31_T = 6'h1f < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_31_T = 6'h1f < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_31 = _maskb_31_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire _maskb_30_T = 6'h1e < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+ wire _maskb_30_T = 6'h1e < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
wire [7:0] maskb_30 = _maskb_30_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
- wire [255:0] mask = {maskb_31,maskb_30,maskb_29,maskb_28,maskb_27,maskb_26,maskb_25,maskb_24,mask_hi_lo,mask_lo}; // @[VLdSt.scala 281:20]
- wire [7:0] io_write_data_datain_0 = wregd_io_out_bits[7:0]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_1 = wregd_io_out_bits[15:8]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_2 = wregd_io_out_bits[23:16]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_3 = wregd_io_out_bits[31:24]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_4 = wregd_io_out_bits[39:32]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_5 = wregd_io_out_bits[47:40]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_6 = wregd_io_out_bits[55:48]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_7 = wregd_io_out_bits[63:56]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_8 = wregd_io_out_bits[71:64]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_9 = wregd_io_out_bits[79:72]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_10 = wregd_io_out_bits[87:80]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_11 = wregd_io_out_bits[95:88]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_12 = wregd_io_out_bits[103:96]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_13 = wregd_io_out_bits[111:104]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_14 = wregd_io_out_bits[119:112]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_15 = wregd_io_out_bits[127:120]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_16 = wregd_io_out_bits[135:128]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_17 = wregd_io_out_bits[143:136]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_18 = wregd_io_out_bits[151:144]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_19 = wregd_io_out_bits[159:152]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_20 = wregd_io_out_bits[167:160]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_21 = wregd_io_out_bits[175:168]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_22 = wregd_io_out_bits[183:176]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_23 = wregd_io_out_bits[191:184]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_24 = wregd_io_out_bits[199:192]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_25 = wregd_io_out_bits[207:200]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_26 = wregd_io_out_bits[215:208]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_27 = wregd_io_out_bits[223:216]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_28 = wregd_io_out_bits[231:224]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_29 = wregd_io_out_bits[239:232]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_30 = wregd_io_out_bits[247:240]; // @[VLdSt.scala 47:24]
- wire [7:0] io_write_data_datain_31 = wregd_io_out_bits[255:248]; // @[VLdSt.scala 47:24]
- wire [4:0] io_write_data_index = wrega_io_out_bits_addr; // @[VLdSt.scala 50:21]
- wire [5:0] _io_write_data_idx_T = {{1'd0}, io_write_data_index}; // @[VLdSt.scala 52:36]
- wire [4:0] io_write_data_idx = _io_write_data_idx_T[4:0]; // @[VLdSt.scala 52:36]
+ wire [255:0] mask = {maskb_31,maskb_30,maskb_29,maskb_28,maskb_27,maskb_26,maskb_25,maskb_24,mask_hi_lo,mask_lo}; // @[VLdSt.scala 284:20]
+ wire [7:0] io_write_data_datain_0 = wregd_io_out_bits[7:0]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_1 = wregd_io_out_bits[15:8]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_2 = wregd_io_out_bits[23:16]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_3 = wregd_io_out_bits[31:24]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_4 = wregd_io_out_bits[39:32]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_5 = wregd_io_out_bits[47:40]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_6 = wregd_io_out_bits[55:48]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_7 = wregd_io_out_bits[63:56]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_8 = wregd_io_out_bits[71:64]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_9 = wregd_io_out_bits[79:72]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_10 = wregd_io_out_bits[87:80]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_11 = wregd_io_out_bits[95:88]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_12 = wregd_io_out_bits[103:96]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_13 = wregd_io_out_bits[111:104]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_14 = wregd_io_out_bits[119:112]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_15 = wregd_io_out_bits[127:120]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_16 = wregd_io_out_bits[135:128]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_17 = wregd_io_out_bits[143:136]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_18 = wregd_io_out_bits[151:144]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_19 = wregd_io_out_bits[159:152]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_20 = wregd_io_out_bits[167:160]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_21 = wregd_io_out_bits[175:168]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_22 = wregd_io_out_bits[183:176]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_23 = wregd_io_out_bits[191:184]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_24 = wregd_io_out_bits[199:192]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_25 = wregd_io_out_bits[207:200]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_26 = wregd_io_out_bits[215:208]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_27 = wregd_io_out_bits[223:216]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_28 = wregd_io_out_bits[231:224]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_29 = wregd_io_out_bits[239:232]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_30 = wregd_io_out_bits[247:240]; // @[VLdSt.scala 50:24]
+ wire [7:0] io_write_data_datain_31 = wregd_io_out_bits[255:248]; // @[VLdSt.scala 50:24]
+ wire [4:0] io_write_data_index = wrega_io_out_bits_addr; // @[VLdSt.scala 53:21]
+ wire [5:0] _io_write_data_idx_T = {{1'd0}, io_write_data_index}; // @[VLdSt.scala 55:35]
+ wire [4:0] io_write_data_idx = _io_write_data_idx_T[4:0]; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_0_value__0 = 5'h0 == io_write_data_idx ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_0_value__1 = 5'h1 == io_write_data_idx ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_0_value__2 = 5'h2 == io_write_data_idx ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96597,7 +96616,7 @@
wire [7:0] io_write_data_dataout_0_value_4_0 = io_write_data_dataout_0_value_3_0 | io_write_data_dataout_0_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_0_value_4_1 = io_write_data_dataout_0_value_3_2 | io_write_data_dataout_0_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_0_value_5_0 = io_write_data_dataout_0_value_4_0 | io_write_data_dataout_0_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_1 = 5'h1 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_1 = 5'h1 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_1_value__0 = 5'h0 == io_write_data_idx_1 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_1_value__1 = 5'h1 == io_write_data_idx_1 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_1_value__2 = 5'h2 == io_write_data_idx_1 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96664,7 +96683,7 @@
wire [7:0] io_write_data_dataout_1_value_4_0 = io_write_data_dataout_1_value_3_0 | io_write_data_dataout_1_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_1_value_4_1 = io_write_data_dataout_1_value_3_2 | io_write_data_dataout_1_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_1_value_5_0 = io_write_data_dataout_1_value_4_0 | io_write_data_dataout_1_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_2 = 5'h2 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_2 = 5'h2 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_2_value__0 = 5'h0 == io_write_data_idx_2 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_2_value__1 = 5'h1 == io_write_data_idx_2 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_2_value__2 = 5'h2 == io_write_data_idx_2 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96731,7 +96750,7 @@
wire [7:0] io_write_data_dataout_2_value_4_0 = io_write_data_dataout_2_value_3_0 | io_write_data_dataout_2_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_2_value_4_1 = io_write_data_dataout_2_value_3_2 | io_write_data_dataout_2_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_2_value_5_0 = io_write_data_dataout_2_value_4_0 | io_write_data_dataout_2_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_3 = 5'h3 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_3 = 5'h3 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_3_value__0 = 5'h0 == io_write_data_idx_3 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_3_value__1 = 5'h1 == io_write_data_idx_3 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_3_value__2 = 5'h2 == io_write_data_idx_3 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96798,7 +96817,7 @@
wire [7:0] io_write_data_dataout_3_value_4_0 = io_write_data_dataout_3_value_3_0 | io_write_data_dataout_3_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_3_value_4_1 = io_write_data_dataout_3_value_3_2 | io_write_data_dataout_3_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_3_value_5_0 = io_write_data_dataout_3_value_4_0 | io_write_data_dataout_3_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_4 = 5'h4 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_4 = 5'h4 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_4_value__0 = 5'h0 == io_write_data_idx_4 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_4_value__1 = 5'h1 == io_write_data_idx_4 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_4_value__2 = 5'h2 == io_write_data_idx_4 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96865,7 +96884,7 @@
wire [7:0] io_write_data_dataout_4_value_4_0 = io_write_data_dataout_4_value_3_0 | io_write_data_dataout_4_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_4_value_4_1 = io_write_data_dataout_4_value_3_2 | io_write_data_dataout_4_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_4_value_5_0 = io_write_data_dataout_4_value_4_0 | io_write_data_dataout_4_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_5 = 5'h5 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_5 = 5'h5 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_5_value__0 = 5'h0 == io_write_data_idx_5 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_5_value__1 = 5'h1 == io_write_data_idx_5 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_5_value__2 = 5'h2 == io_write_data_idx_5 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96932,7 +96951,7 @@
wire [7:0] io_write_data_dataout_5_value_4_0 = io_write_data_dataout_5_value_3_0 | io_write_data_dataout_5_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_5_value_4_1 = io_write_data_dataout_5_value_3_2 | io_write_data_dataout_5_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_5_value_5_0 = io_write_data_dataout_5_value_4_0 | io_write_data_dataout_5_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_6 = 5'h6 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_6 = 5'h6 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_6_value__0 = 5'h0 == io_write_data_idx_6 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_6_value__1 = 5'h1 == io_write_data_idx_6 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_6_value__2 = 5'h2 == io_write_data_idx_6 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96999,7 +97018,7 @@
wire [7:0] io_write_data_dataout_6_value_4_0 = io_write_data_dataout_6_value_3_0 | io_write_data_dataout_6_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_6_value_4_1 = io_write_data_dataout_6_value_3_2 | io_write_data_dataout_6_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_6_value_5_0 = io_write_data_dataout_6_value_4_0 | io_write_data_dataout_6_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_7 = 5'h7 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_7 = 5'h7 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_7_value__0 = 5'h0 == io_write_data_idx_7 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_7_value__1 = 5'h1 == io_write_data_idx_7 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_7_value__2 = 5'h2 == io_write_data_idx_7 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97066,7 +97085,7 @@
wire [7:0] io_write_data_dataout_7_value_4_0 = io_write_data_dataout_7_value_3_0 | io_write_data_dataout_7_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_7_value_4_1 = io_write_data_dataout_7_value_3_2 | io_write_data_dataout_7_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_7_value_5_0 = io_write_data_dataout_7_value_4_0 | io_write_data_dataout_7_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_8 = 5'h8 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_8 = 5'h8 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_8_value__0 = 5'h0 == io_write_data_idx_8 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_8_value__1 = 5'h1 == io_write_data_idx_8 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_8_value__2 = 5'h2 == io_write_data_idx_8 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97133,7 +97152,7 @@
wire [7:0] io_write_data_dataout_8_value_4_0 = io_write_data_dataout_8_value_3_0 | io_write_data_dataout_8_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_8_value_4_1 = io_write_data_dataout_8_value_3_2 | io_write_data_dataout_8_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_8_value_5_0 = io_write_data_dataout_8_value_4_0 | io_write_data_dataout_8_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_9 = 5'h9 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_9 = 5'h9 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_9_value__0 = 5'h0 == io_write_data_idx_9 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_9_value__1 = 5'h1 == io_write_data_idx_9 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_9_value__2 = 5'h2 == io_write_data_idx_9 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97200,7 +97219,7 @@
wire [7:0] io_write_data_dataout_9_value_4_0 = io_write_data_dataout_9_value_3_0 | io_write_data_dataout_9_value_3_1; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_9_value_4_1 = io_write_data_dataout_9_value_3_2 | io_write_data_dataout_9_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_9_value_5_0 = io_write_data_dataout_9_value_4_0 | io_write_data_dataout_9_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_10 = 5'ha + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_10 = 5'ha + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_10_value__0 = 5'h0 == io_write_data_idx_10 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_10_value__1 = 5'h1 == io_write_data_idx_10 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_10_value__2 = 5'h2 == io_write_data_idx_10 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97290,7 +97309,7 @@
io_write_data_dataout_10_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_10_value_5_0 = io_write_data_dataout_10_value_4_0 |
io_write_data_dataout_10_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_11 = 5'hb + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_11 = 5'hb + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_11_value__0 = 5'h0 == io_write_data_idx_11 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_11_value__1 = 5'h1 == io_write_data_idx_11 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_11_value__2 = 5'h2 == io_write_data_idx_11 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97380,7 +97399,7 @@
io_write_data_dataout_11_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_11_value_5_0 = io_write_data_dataout_11_value_4_0 |
io_write_data_dataout_11_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_12 = 5'hc + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_12 = 5'hc + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_12_value__0 = 5'h0 == io_write_data_idx_12 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_12_value__1 = 5'h1 == io_write_data_idx_12 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_12_value__2 = 5'h2 == io_write_data_idx_12 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97470,7 +97489,7 @@
io_write_data_dataout_12_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_12_value_5_0 = io_write_data_dataout_12_value_4_0 |
io_write_data_dataout_12_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_13 = 5'hd + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_13 = 5'hd + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_13_value__0 = 5'h0 == io_write_data_idx_13 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_13_value__1 = 5'h1 == io_write_data_idx_13 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_13_value__2 = 5'h2 == io_write_data_idx_13 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97560,7 +97579,7 @@
io_write_data_dataout_13_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_13_value_5_0 = io_write_data_dataout_13_value_4_0 |
io_write_data_dataout_13_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_14 = 5'he + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_14 = 5'he + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_14_value__0 = 5'h0 == io_write_data_idx_14 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_14_value__1 = 5'h1 == io_write_data_idx_14 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_14_value__2 = 5'h2 == io_write_data_idx_14 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97650,7 +97669,7 @@
io_write_data_dataout_14_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_14_value_5_0 = io_write_data_dataout_14_value_4_0 |
io_write_data_dataout_14_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_15 = 5'hf + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_15 = 5'hf + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_15_value__0 = 5'h0 == io_write_data_idx_15 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_15_value__1 = 5'h1 == io_write_data_idx_15 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_15_value__2 = 5'h2 == io_write_data_idx_15 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97740,7 +97759,7 @@
io_write_data_dataout_15_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_15_value_5_0 = io_write_data_dataout_15_value_4_0 |
io_write_data_dataout_15_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_16 = 5'h10 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_16 = 5'h10 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_16_value__0 = 5'h0 == io_write_data_idx_16 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_16_value__1 = 5'h1 == io_write_data_idx_16 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_16_value__2 = 5'h2 == io_write_data_idx_16 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97830,7 +97849,7 @@
io_write_data_dataout_16_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_16_value_5_0 = io_write_data_dataout_16_value_4_0 |
io_write_data_dataout_16_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_17 = 5'h11 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_17 = 5'h11 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_17_value__0 = 5'h0 == io_write_data_idx_17 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_17_value__1 = 5'h1 == io_write_data_idx_17 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_17_value__2 = 5'h2 == io_write_data_idx_17 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97920,7 +97939,7 @@
io_write_data_dataout_17_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_17_value_5_0 = io_write_data_dataout_17_value_4_0 |
io_write_data_dataout_17_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_18 = 5'h12 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_18 = 5'h12 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_18_value__0 = 5'h0 == io_write_data_idx_18 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_18_value__1 = 5'h1 == io_write_data_idx_18 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_18_value__2 = 5'h2 == io_write_data_idx_18 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98010,7 +98029,7 @@
io_write_data_dataout_18_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_18_value_5_0 = io_write_data_dataout_18_value_4_0 |
io_write_data_dataout_18_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_19 = 5'h13 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_19 = 5'h13 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_19_value__0 = 5'h0 == io_write_data_idx_19 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_19_value__1 = 5'h1 == io_write_data_idx_19 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_19_value__2 = 5'h2 == io_write_data_idx_19 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98100,7 +98119,7 @@
io_write_data_dataout_19_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_19_value_5_0 = io_write_data_dataout_19_value_4_0 |
io_write_data_dataout_19_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_20 = 5'h14 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_20 = 5'h14 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_20_value__0 = 5'h0 == io_write_data_idx_20 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_20_value__1 = 5'h1 == io_write_data_idx_20 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_20_value__2 = 5'h2 == io_write_data_idx_20 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98190,7 +98209,7 @@
io_write_data_dataout_20_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_20_value_5_0 = io_write_data_dataout_20_value_4_0 |
io_write_data_dataout_20_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_21 = 5'h15 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_21 = 5'h15 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_21_value__0 = 5'h0 == io_write_data_idx_21 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_21_value__1 = 5'h1 == io_write_data_idx_21 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_21_value__2 = 5'h2 == io_write_data_idx_21 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98280,7 +98299,7 @@
io_write_data_dataout_21_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_21_value_5_0 = io_write_data_dataout_21_value_4_0 |
io_write_data_dataout_21_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_22 = 5'h16 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_22 = 5'h16 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_22_value__0 = 5'h0 == io_write_data_idx_22 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_22_value__1 = 5'h1 == io_write_data_idx_22 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_22_value__2 = 5'h2 == io_write_data_idx_22 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98370,7 +98389,7 @@
io_write_data_dataout_22_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_22_value_5_0 = io_write_data_dataout_22_value_4_0 |
io_write_data_dataout_22_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_23 = 5'h17 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_23 = 5'h17 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_23_value__0 = 5'h0 == io_write_data_idx_23 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_23_value__1 = 5'h1 == io_write_data_idx_23 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_23_value__2 = 5'h2 == io_write_data_idx_23 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98460,7 +98479,7 @@
io_write_data_dataout_23_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_23_value_5_0 = io_write_data_dataout_23_value_4_0 |
io_write_data_dataout_23_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_24 = 5'h18 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_24 = 5'h18 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_24_value__0 = 5'h0 == io_write_data_idx_24 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_24_value__1 = 5'h1 == io_write_data_idx_24 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_24_value__2 = 5'h2 == io_write_data_idx_24 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98550,7 +98569,7 @@
io_write_data_dataout_24_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_24_value_5_0 = io_write_data_dataout_24_value_4_0 |
io_write_data_dataout_24_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_25 = 5'h19 + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_25 = 5'h19 + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_25_value__0 = 5'h0 == io_write_data_idx_25 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_25_value__1 = 5'h1 == io_write_data_idx_25 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_25_value__2 = 5'h2 == io_write_data_idx_25 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98640,7 +98659,7 @@
io_write_data_dataout_25_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_25_value_5_0 = io_write_data_dataout_25_value_4_0 |
io_write_data_dataout_25_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_26 = 5'h1a + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_26 = 5'h1a + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_26_value__0 = 5'h0 == io_write_data_idx_26 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_26_value__1 = 5'h1 == io_write_data_idx_26 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_26_value__2 = 5'h2 == io_write_data_idx_26 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98730,7 +98749,7 @@
io_write_data_dataout_26_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_26_value_5_0 = io_write_data_dataout_26_value_4_0 |
io_write_data_dataout_26_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_27 = 5'h1b + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_27 = 5'h1b + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_27_value__0 = 5'h0 == io_write_data_idx_27 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_27_value__1 = 5'h1 == io_write_data_idx_27 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_27_value__2 = 5'h2 == io_write_data_idx_27 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98820,7 +98839,7 @@
io_write_data_dataout_27_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_27_value_5_0 = io_write_data_dataout_27_value_4_0 |
io_write_data_dataout_27_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_28 = 5'h1c + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_28 = 5'h1c + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_28_value__0 = 5'h0 == io_write_data_idx_28 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_28_value__1 = 5'h1 == io_write_data_idx_28 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_28_value__2 = 5'h2 == io_write_data_idx_28 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98910,7 +98929,7 @@
io_write_data_dataout_28_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_28_value_5_0 = io_write_data_dataout_28_value_4_0 |
io_write_data_dataout_28_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_29 = 5'h1d + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_29 = 5'h1d + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_29_value__0 = 5'h0 == io_write_data_idx_29 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_29_value__1 = 5'h1 == io_write_data_idx_29 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_29_value__2 = 5'h2 == io_write_data_idx_29 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -99000,7 +99019,7 @@
io_write_data_dataout_29_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_29_value_5_0 = io_write_data_dataout_29_value_4_0 |
io_write_data_dataout_29_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_30 = 5'h1e + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_30 = 5'h1e + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_30_value__0 = 5'h0 == io_write_data_idx_30 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_30_value__1 = 5'h1 == io_write_data_idx_30 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_30_value__2 = 5'h2 == io_write_data_idx_30 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -99090,7 +99109,7 @@
io_write_data_dataout_30_value_3_3; // @[Library.scala 115:37]
wire [7:0] io_write_data_dataout_30_value_5_0 = io_write_data_dataout_30_value_4_0 |
io_write_data_dataout_30_value_4_1; // @[Library.scala 115:37]
- wire [4:0] io_write_data_idx_31 = 5'h1f + io_write_data_index; // @[VLdSt.scala 52:36]
+ wire [4:0] io_write_data_idx_31 = 5'h1f + io_write_data_index; // @[VLdSt.scala 55:35]
wire [7:0] io_write_data_dataout_31_value__0 = 5'h0 == io_write_data_idx_31 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_31_value__1 = 5'h1 == io_write_data_idx_31 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
wire [7:0] io_write_data_dataout_31_value__2 = 5'h2 == io_write_data_idx_31 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -99182,18 +99201,18 @@
io_write_data_dataout_31_value_4_1; // @[Library.scala 115:37]
wire [63:0] io_write_data_lo_lo = {io_write_data_dataout_7_value_5_0,io_write_data_dataout_6_value_5_0,
io_write_data_dataout_5_value_5_0,io_write_data_dataout_4_value_5_0,io_write_data_dataout_3_value_5_0,
- io_write_data_dataout_2_value_5_0,io_write_data_dataout_1_value_5_0,io_write_data_dataout_0_value_5_0}; // @[VLdSt.scala 57:13]
+ io_write_data_dataout_2_value_5_0,io_write_data_dataout_1_value_5_0,io_write_data_dataout_0_value_5_0}; // @[VLdSt.scala 60:13]
wire [127:0] io_write_data_lo = {io_write_data_dataout_15_value_5_0,io_write_data_dataout_14_value_5_0,
io_write_data_dataout_13_value_5_0,io_write_data_dataout_12_value_5_0,io_write_data_dataout_11_value_5_0,
io_write_data_dataout_10_value_5_0,io_write_data_dataout_9_value_5_0,io_write_data_dataout_8_value_5_0,
- io_write_data_lo_lo}; // @[VLdSt.scala 57:13]
+ io_write_data_lo_lo}; // @[VLdSt.scala 60:13]
wire [63:0] io_write_data_hi_lo = {io_write_data_dataout_23_value_5_0,io_write_data_dataout_22_value_5_0,
io_write_data_dataout_21_value_5_0,io_write_data_dataout_20_value_5_0,io_write_data_dataout_19_value_5_0,
- io_write_data_dataout_18_value_5_0,io_write_data_dataout_17_value_5_0,io_write_data_dataout_16_value_5_0}; // @[VLdSt.scala 57:13]
+ io_write_data_dataout_18_value_5_0,io_write_data_dataout_17_value_5_0,io_write_data_dataout_16_value_5_0}; // @[VLdSt.scala 60:13]
wire [255:0] _io_write_data_T = {io_write_data_dataout_31_value_5_0,io_write_data_dataout_30_value_5_0,
io_write_data_dataout_29_value_5_0,io_write_data_dataout_28_value_5_0,io_write_data_dataout_27_value_5_0,
io_write_data_dataout_26_value_5_0,io_write_data_dataout_25_value_5_0,io_write_data_dataout_24_value_5_0,
- io_write_data_hi_lo,io_write_data_lo}; // @[VLdSt.scala 57:13]
+ io_write_data_hi_lo,io_write_data_lo}; // @[VLdSt.scala 60:13]
VCmdq_3 q ( // @[VCmdq.scala 14:11]
.clock(q_clock),
.reset(q_reset),
@@ -99316,105 +99335,105 @@
.io_out_valid(wregd_io_out_valid),
.io_out_bits(wregd_io_out_bits)
);
- assign io_in_ready = q_io_in_ready; // @[VLdSt.scala 162:11]
- assign io_active = q_io_active; // @[VLdSt.scala 293:13]
- assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VLdSt.scala 169:35]
- assign io_read_addr = q_io_out_bits_vs_addr; // @[VLdSt.scala 171:16]
- assign io_write_valid = wrega_io_out_valid & wregd_io_out_valid; // @[VLdSt.scala 287:40]
- assign io_write_addr = wrega_io_out_bits_widx; // @[VLdSt.scala 288:17]
- assign io_write_data = _io_write_data_T & mask; // @[VLdSt.scala 289:80]
- assign io_dbus_valid = ctrl_io_out_valid & _ctrl_io_out_ready_T_1; // @[VLdSt.scala 246:38]
- assign io_dbus_write = ctrl_io_out_bits_write; // @[VLdSt.scala 247:17]
+ assign io_in_ready = q_io_in_ready; // @[VLdSt.scala 165:11]
+ assign io_active = q_io_active; // @[VLdSt.scala 296:13]
+ assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VLdSt.scala 172:35]
+ assign io_read_addr = q_io_out_bits_vs_addr; // @[VLdSt.scala 174:16]
+ assign io_write_valid = wrega_io_out_valid & wregd_io_out_valid; // @[VLdSt.scala 290:40]
+ assign io_write_addr = wrega_io_out_bits_widx; // @[VLdSt.scala 291:17]
+ assign io_write_data = _io_write_data_T & mask; // @[VLdSt.scala 292:80]
+ assign io_dbus_valid = ctrl_io_out_valid & _ctrl_io_out_ready_T_1; // @[VLdSt.scala 249:38]
+ assign io_dbus_write = ctrl_io_out_bits_write; // @[VLdSt.scala 250:17]
assign io_dbus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
assign io_dbus_adrx = {1'h0,ctrl_io_out_bits_adrx[30:0]}; // @[Cat.scala 31:58]
- assign io_dbus_size = ctrl_io_out_bits_size; // @[VLdSt.scala 250:16]
- assign io_dbus_wdata = data_io_out_bits_wdata; // @[VLdSt.scala 251:17]
- assign io_dbus_wmask = data_io_out_bits_wmask; // @[VLdSt.scala 252:17]
- assign io_last = ctrl_io_out_bits_last; // @[VLdSt.scala 258:11]
+ assign io_dbus_size = ctrl_io_out_bits_size; // @[VLdSt.scala 253:16]
+ assign io_dbus_wdata = data_io_out_bits_wdata; // @[VLdSt.scala 254:17]
+ assign io_dbus_wmask = data_io_out_bits_wmask; // @[VLdSt.scala 255:17]
+ assign io_last = ctrl_io_out_bits_last; // @[VLdSt.scala 261:11]
assign q_clock = clock;
assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 162:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLdSt.scala 162:11]
- assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VLdSt.scala 165:65]
+ assign q_io_in_valid = io_in_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 165:11]
+ assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLdSt.scala 165:11]
+ assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VLdSt.scala 168:65]
assign ctrl_clock = clock;
assign ctrl_reset = reset;
- assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 208:31]
- assign ctrl_io_in_bits_last = q_io_out_bits_last; // @[VLdSt.scala 232:25]
- assign ctrl_io_in_bits_write = q_io_out_bits_op == 7'h3 | _qmaxvlb_T; // @[VLdSt.scala 79:22]
- assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VLdSt.scala 229:25]
- assign ctrl_io_in_bits_adrx = q_io_out_bits_addr + 32'h20; // @[VLdSt.scala 230:47]
- assign ctrl_io_in_bits_size = qsize[5:0]; // @[VLdSt.scala 231:25]
- assign ctrl_io_in_bits_widx = q_io_out_bits_vd_addr; // @[VLdSt.scala 234:25]
- assign ctrl_io_out_ready = io_dbus_ready & (data_io_out_valid | ~ctrl_io_out_bits_write); // @[VLdSt.scala 242:38]
+ assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 211:31]
+ assign ctrl_io_in_bits_last = q_io_out_bits_last; // @[VLdSt.scala 235:25]
+ assign ctrl_io_in_bits_write = q_io_out_bits_op == 7'h3 | _qmaxvlb_T; // @[VLdSt.scala 82:22]
+ assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VLdSt.scala 232:25]
+ assign ctrl_io_in_bits_adrx = q_io_out_bits_addr + 32'h20; // @[VLdSt.scala 233:47]
+ assign ctrl_io_in_bits_size = qsize[5:0]; // @[VLdSt.scala 234:25]
+ assign ctrl_io_in_bits_widx = q_io_out_bits_vd_addr; // @[VLdSt.scala 237:25]
+ assign ctrl_io_out_ready = io_dbus_ready & (data_io_out_valid | ~ctrl_io_out_bits_write); // @[VLdSt.scala 245:38]
assign data_clock = clock;
assign data_reset = reset;
- assign data_io_in_valid = rdataEn; // @[VLdSt.scala 237:20]
- assign data_io_in_bits_wdata = {data_io_in_bits_wdata_hi,data_io_in_bits_wdata_lo}; // @[VLdSt.scala 57:13]
- assign data_io_in_bits_wmask = {data_io_in_bits_wmask_hi_1,data_io_in_bits_wmask_lo_1}; // @[VLdSt.scala 57:13]
- assign data_io_out_ready = io_dbus_ready & (ctrl_io_out_valid & ctrl_io_out_bits_write); // @[VLdSt.scala 243:38]
+ assign data_io_in_valid = rdataEn; // @[VLdSt.scala 240:20]
+ assign data_io_in_bits_wdata = {data_io_in_bits_wdata_hi,data_io_in_bits_wdata_lo}; // @[VLdSt.scala 60:13]
+ assign data_io_in_bits_wmask = {data_io_in_bits_wmask_hi_1,data_io_in_bits_wmask_lo_1}; // @[VLdSt.scala 60:13]
+ assign data_io_out_ready = io_dbus_ready & (ctrl_io_out_valid & ctrl_io_out_bits_write); // @[VLdSt.scala 246:38]
assign wrega_clock = clock;
assign wrega_reset = reset;
- assign wrega_io_in_valid = ctrl_io_out_valid & io_dbus_ready & _ctrl_io_out_ready_T; // @[VLdSt.scala 268:59]
- assign wrega_io_in_bits_widx = ctrl_io_out_bits_widx; // @[VLdSt.scala 269:25]
- assign wrega_io_in_bits_addr = ctrl_io_out_bits_addr[4:0]; // @[VLdSt.scala 270:25]
- assign wrega_io_in_bits_size = ctrl_io_out_bits_size; // @[VLdSt.scala 271:25]
- assign wrega_io_out_ready = wregd_io_out_valid; // @[VLdSt.scala 272:22]
+ assign wrega_io_in_valid = ctrl_io_out_valid & io_dbus_ready & _ctrl_io_out_ready_T; // @[VLdSt.scala 271:59]
+ assign wrega_io_in_bits_widx = ctrl_io_out_bits_widx; // @[VLdSt.scala 272:25]
+ assign wrega_io_in_bits_addr = ctrl_io_out_bits_addr[4:0]; // @[VLdSt.scala 273:25]
+ assign wrega_io_in_bits_size = ctrl_io_out_bits_size; // @[VLdSt.scala 274:25]
+ assign wrega_io_out_ready = wregd_io_out_valid; // @[VLdSt.scala 275:22]
assign wregd_clock = clock;
assign wregd_reset = reset;
- assign wregd_io_in_valid = wdataEn; // @[VLdSt.scala 275:21]
- assign wregd_io_in_bits = io_dbus_rdata; // @[VLdSt.scala 276:20]
- assign wregd_io_out_ready = wrega_io_out_valid; // @[VLdSt.scala 277:22]
+ assign wregd_io_in_valid = wdataEn; // @[VLdSt.scala 278:21]
+ assign wregd_io_in_bits = io_dbus_rdata; // @[VLdSt.scala 279:20]
+ assign wregd_io_out_ready = wrega_io_out_valid; // @[VLdSt.scala 280:22]
always @(posedge clock) begin
- if (rdataEnNxt) begin // @[VLdSt.scala 215:21]
- if (q_io_out_bits_remain > qmaxvlb) begin // @[VLdSt.scala 212:18]
- if (q_io_out_bits_op == 7'h4) begin // @[VLdSt.scala 211:20]
+ if (rdataEnNxt) begin // @[VLdSt.scala 218:21]
+ if (q_io_out_bits_remain > qmaxvlb) begin // @[VLdSt.scala 215:18]
+ if (q_io_out_bits_op == 7'h4) begin // @[VLdSt.scala 214:20]
rdataSize <= 8'h8;
end else begin
rdataSize <= 8'h20;
@@ -99430,7 +99449,7 @@
if (`STOP_COND) begin
`endif
if (~reset & ~(~(ctrl_io_in_valid & ~ctrl_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 235:9]
+ $fatal; // @[VLdSt.scala 238:9]
end
`ifdef STOP_COND
end
@@ -99442,7 +99461,7 @@
`endif
if (~reset & ~(~(ctrl_io_in_valid & ~ctrl_io_in_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:235 assert(!(ctrl.io.in.valid && !ctrl.io.in.ready))\n"); // @[VLdSt.scala 235:9]
+ "Assertion failed\n at VLdSt.scala:238 assert(!(ctrl.io.in.valid && !ctrl.io.in.ready))\n"); // @[VLdSt.scala 238:9]
end
`ifdef PRINTF_COND
end
@@ -99453,7 +99472,7 @@
if (`STOP_COND) begin
`endif
if (_T_4 & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 240:9]
+ $fatal; // @[VLdSt.scala 243:9]
end
`ifdef STOP_COND
end
@@ -99465,7 +99484,7 @@
`endif
if (_T_4 & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:240 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VLdSt.scala 240:9]
+ "Assertion failed\n at VLdSt.scala:243 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VLdSt.scala 243:9]
end
`ifdef PRINTF_COND
end
@@ -99476,7 +99495,7 @@
if (`STOP_COND) begin
`endif
if (_T_4 & ~(~(data_io_out_valid & ~ctrl_io_out_valid))) begin
- $fatal; // @[VLdSt.scala 244:9]
+ $fatal; // @[VLdSt.scala 247:9]
end
`ifdef STOP_COND
end
@@ -99488,7 +99507,7 @@
`endif
if (_T_4 & ~(~(data_io_out_valid & ~ctrl_io_out_valid))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:244 assert(!(data.io.out.valid && !ctrl.io.out.valid))\n"); // @[VLdSt.scala 244:9]
+ "Assertion failed\n at VLdSt.scala:247 assert(!(data.io.out.valid && !ctrl.io.out.valid))\n"); // @[VLdSt.scala 247:9]
end
`ifdef PRINTF_COND
end
@@ -99499,75 +99518,6 @@
if (`STOP_COND) begin
`endif
if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
- $fatal; // @[VLdSt.scala 253:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:253 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.addr(31)))\n"); // @[VLdSt.scala 253:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
- $fatal; // @[VLdSt.scala 254:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:254 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.adrx(31)))\n"); // @[VLdSt.scala 254:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
- $fatal; // @[VLdSt.scala 255:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:255 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"
- ); // @[VLdSt.scala 255:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
$fatal; // @[VLdSt.scala 256:9]
end
`ifdef STOP_COND
@@ -99578,9 +99528,78 @@
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
+ if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at VLdSt.scala:256 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.addr(31)))\n"); // @[VLdSt.scala 256:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
+ $fatal; // @[VLdSt.scala 257:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at VLdSt.scala:257 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.adrx(31)))\n"); // @[VLdSt.scala 257:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
+ $fatal; // @[VLdSt.scala 258:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:258 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"
+ ); // @[VLdSt.scala 258:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:256 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"
- ); // @[VLdSt.scala 256:9]
+ $fatal; // @[VLdSt.scala 259:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
+ $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:259 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"
+ ); // @[VLdSt.scala 259:9]
end
`ifdef PRINTF_COND
end
@@ -99591,7 +99610,7 @@
if (`STOP_COND) begin
`endif
if (_T_4 & ~(~(wrega_io_in_valid & ~wrega_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 273:9]
+ $fatal; // @[VLdSt.scala 276:9]
end
`ifdef STOP_COND
end
@@ -99603,7 +99622,7 @@
`endif
if (_T_4 & ~(~(wrega_io_in_valid & ~wrega_io_in_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:273 assert(!(wrega.io.in.valid && !wrega.io.in.ready))\n"); // @[VLdSt.scala 273:9]
+ "Assertion failed\n at VLdSt.scala:276 assert(!(wrega.io.in.valid && !wrega.io.in.ready))\n"); // @[VLdSt.scala 276:9]
end
`ifdef PRINTF_COND
end
@@ -99614,7 +99633,7 @@
if (`STOP_COND) begin
`endif
if (_T_4 & ~(~(wregd_io_in_valid & ~wregd_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 278:9]
+ $fatal; // @[VLdSt.scala 281:9]
end
`ifdef STOP_COND
end
@@ -99626,7 +99645,7 @@
`endif
if (_T_4 & ~(~(wregd_io_in_valid & ~wregd_io_in_ready))) begin
$fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:278 assert(!(wregd.io.in.valid && !wregd.io.in.ready))\n"); // @[VLdSt.scala 278:9]
+ "Assertion failed\n at VLdSt.scala:281 assert(!(wregd.io.in.valid && !wregd.io.in.ready))\n"); // @[VLdSt.scala 281:9]
end
`ifdef PRINTF_COND
end
@@ -99634,14 +99653,14 @@
`endif // SYNTHESIS
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLdSt.scala 209:27]
+ if (reset) begin // @[VLdSt.scala 212:27]
rdataEn <= 1'h0;
end else begin
rdataEn <= qoutEn & ctrl_io_in_bits_write;
end
end
always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLdSt.scala 266:45]
+ if (reset) begin // @[VLdSt.scala 269:45]
wdataEn <= 1'h0;
end else begin
wdataEn <= io_dbus_valid & io_dbus_ready & ~io_dbus_write;
@@ -121544,174 +121563,174 @@
wire [127:0] vdec_io_vrfsb_data; // @[VDecode.scala 9:18]
wire vdec_io_undef; // @[VDecode.scala 9:18]
wire vdec_io_nempty; // @[VDecode.scala 9:18]
- wire valu_clock; // @[VAlu.scala 29:18]
- wire valu_reset; // @[VAlu.scala 29:18]
- wire valu_io_in_ready; // @[VAlu.scala 29:18]
- wire valu_io_in_valid; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_valid; // @[VAlu.scala 29:18]
- wire [6:0] valu_io_in_bits_0_bits_op; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_0_bits_f2; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_0_bits_sz; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_m; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vd_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_ve_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vf_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vg_addr; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_vs_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vs_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_0_bits_vs_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_vt_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vt_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_0_bits_vt_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_vu_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vu_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_0_bits_vu_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_vx_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vx_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_0_bits_vx_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_vy_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vy_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_0_bits_vy_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_vz_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_0_bits_vz_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_0_bits_vz_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_sv_valid; // @[VAlu.scala 29:18]
- wire [31:0] valu_io_in_bits_0_bits_sv_data; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_0_bits_cmdsync; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_valid; // @[VAlu.scala 29:18]
- wire [6:0] valu_io_in_bits_1_bits_op; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_1_bits_f2; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_1_bits_sz; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_m; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vd_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_ve_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vf_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vg_addr; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_vs_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vs_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_1_bits_vs_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_vt_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vt_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_1_bits_vt_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_vu_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vu_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_1_bits_vu_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_vx_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vx_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_1_bits_vx_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_vy_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vy_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_1_bits_vy_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_vz_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_1_bits_vz_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_1_bits_vz_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_sv_valid; // @[VAlu.scala 29:18]
- wire [31:0] valu_io_in_bits_1_bits_sv_data; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_1_bits_cmdsync; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_valid; // @[VAlu.scala 29:18]
- wire [6:0] valu_io_in_bits_2_bits_op; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_2_bits_f2; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_2_bits_sz; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_m; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vd_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_ve_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vf_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vg_addr; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_vs_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vs_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_2_bits_vs_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_vt_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vt_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_2_bits_vt_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_vu_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vu_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_2_bits_vu_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_vx_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vx_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_2_bits_vx_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_vy_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vy_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_2_bits_vy_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_vz_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_2_bits_vz_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_2_bits_vz_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_sv_valid; // @[VAlu.scala 29:18]
- wire [31:0] valu_io_in_bits_2_bits_sv_data; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_2_bits_cmdsync; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_valid; // @[VAlu.scala 29:18]
- wire [6:0] valu_io_in_bits_3_bits_op; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_3_bits_f2; // @[VAlu.scala 29:18]
- wire [2:0] valu_io_in_bits_3_bits_sz; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_m; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vd_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_ve_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vf_addr; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vg_addr; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_vs_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vs_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_3_bits_vs_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_vt_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vt_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_3_bits_vt_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_vu_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vu_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_3_bits_vu_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_vx_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vx_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_3_bits_vx_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_vy_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vy_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_3_bits_vy_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_vz_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_in_bits_3_bits_vz_addr; // @[VAlu.scala 29:18]
- wire [3:0] valu_io_in_bits_3_bits_vz_tag; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_sv_valid; // @[VAlu.scala 29:18]
- wire [31:0] valu_io_in_bits_3_bits_sv_data; // @[VAlu.scala 29:18]
- wire valu_io_in_bits_3_bits_cmdsync; // @[VAlu.scala 29:18]
- wire [63:0] valu_io_active; // @[VAlu.scala 29:18]
- wire [127:0] valu_io_vrfsb; // @[VAlu.scala 29:18]
- wire valu_io_read_0_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_read_0_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_read_0_data; // @[VAlu.scala 29:18]
- wire valu_io_read_1_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_read_1_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_read_1_data; // @[VAlu.scala 29:18]
- wire valu_io_read_2_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_read_2_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_read_2_data; // @[VAlu.scala 29:18]
- wire valu_io_read_3_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_read_3_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_read_3_data; // @[VAlu.scala 29:18]
- wire valu_io_read_4_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_read_4_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_read_4_data; // @[VAlu.scala 29:18]
- wire valu_io_read_5_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_read_5_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_read_5_data; // @[VAlu.scala 29:18]
- wire valu_io_write_0_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_write_0_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_write_0_data; // @[VAlu.scala 29:18]
- wire valu_io_write_1_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_write_1_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_write_1_data; // @[VAlu.scala 29:18]
- wire valu_io_write_2_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_write_2_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_write_2_data; // @[VAlu.scala 29:18]
- wire valu_io_write_3_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_write_3_addr; // @[VAlu.scala 29:18]
- wire [255:0] valu_io_write_3_data; // @[VAlu.scala 29:18]
- wire valu_io_whint_0_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_whint_0_addr; // @[VAlu.scala 29:18]
- wire valu_io_whint_1_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_whint_1_addr; // @[VAlu.scala 29:18]
- wire valu_io_whint_2_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_whint_2_addr; // @[VAlu.scala 29:18]
- wire valu_io_whint_3_valid; // @[VAlu.scala 29:18]
- wire [5:0] valu_io_whint_3_addr; // @[VAlu.scala 29:18]
- wire valu_io_scalar_0_valid; // @[VAlu.scala 29:18]
- wire [31:0] valu_io_scalar_0_data; // @[VAlu.scala 29:18]
- wire valu_io_scalar_1_valid; // @[VAlu.scala 29:18]
- wire [31:0] valu_io_scalar_1_data; // @[VAlu.scala 29:18]
+ wire valu_clock; // @[VAlu.scala 9:18]
+ wire valu_reset; // @[VAlu.scala 9:18]
+ wire valu_io_in_ready; // @[VAlu.scala 9:18]
+ wire valu_io_in_valid; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_valid; // @[VAlu.scala 9:18]
+ wire [6:0] valu_io_in_bits_0_bits_op; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_0_bits_f2; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_0_bits_sz; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_m; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vd_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_ve_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vf_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vg_addr; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_vs_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vs_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_0_bits_vs_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_vt_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vt_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_0_bits_vt_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_vu_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vu_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_0_bits_vu_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_vx_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vx_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_0_bits_vx_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_vy_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vy_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_0_bits_vy_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_vz_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_0_bits_vz_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_0_bits_vz_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_sv_valid; // @[VAlu.scala 9:18]
+ wire [31:0] valu_io_in_bits_0_bits_sv_data; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_0_bits_cmdsync; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_valid; // @[VAlu.scala 9:18]
+ wire [6:0] valu_io_in_bits_1_bits_op; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_1_bits_f2; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_1_bits_sz; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_m; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vd_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_ve_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vf_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vg_addr; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_vs_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vs_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_1_bits_vs_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_vt_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vt_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_1_bits_vt_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_vu_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vu_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_1_bits_vu_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_vx_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vx_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_1_bits_vx_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_vy_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vy_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_1_bits_vy_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_vz_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_1_bits_vz_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_1_bits_vz_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_sv_valid; // @[VAlu.scala 9:18]
+ wire [31:0] valu_io_in_bits_1_bits_sv_data; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_1_bits_cmdsync; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_valid; // @[VAlu.scala 9:18]
+ wire [6:0] valu_io_in_bits_2_bits_op; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_2_bits_f2; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_2_bits_sz; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_m; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vd_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_ve_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vf_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vg_addr; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_vs_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vs_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_2_bits_vs_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_vt_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vt_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_2_bits_vt_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_vu_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vu_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_2_bits_vu_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_vx_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vx_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_2_bits_vx_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_vy_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vy_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_2_bits_vy_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_vz_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_2_bits_vz_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_2_bits_vz_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_sv_valid; // @[VAlu.scala 9:18]
+ wire [31:0] valu_io_in_bits_2_bits_sv_data; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_2_bits_cmdsync; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_valid; // @[VAlu.scala 9:18]
+ wire [6:0] valu_io_in_bits_3_bits_op; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_3_bits_f2; // @[VAlu.scala 9:18]
+ wire [2:0] valu_io_in_bits_3_bits_sz; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_m; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vd_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_ve_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vf_addr; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vg_addr; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_vs_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vs_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_3_bits_vs_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_vt_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vt_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_3_bits_vt_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_vu_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vu_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_3_bits_vu_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_vx_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vx_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_3_bits_vx_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_vy_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vy_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_3_bits_vy_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_vz_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_in_bits_3_bits_vz_addr; // @[VAlu.scala 9:18]
+ wire [3:0] valu_io_in_bits_3_bits_vz_tag; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_sv_valid; // @[VAlu.scala 9:18]
+ wire [31:0] valu_io_in_bits_3_bits_sv_data; // @[VAlu.scala 9:18]
+ wire valu_io_in_bits_3_bits_cmdsync; // @[VAlu.scala 9:18]
+ wire [63:0] valu_io_active; // @[VAlu.scala 9:18]
+ wire [127:0] valu_io_vrfsb; // @[VAlu.scala 9:18]
+ wire valu_io_read_0_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_read_0_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_read_0_data; // @[VAlu.scala 9:18]
+ wire valu_io_read_1_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_read_1_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_read_1_data; // @[VAlu.scala 9:18]
+ wire valu_io_read_2_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_read_2_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_read_2_data; // @[VAlu.scala 9:18]
+ wire valu_io_read_3_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_read_3_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_read_3_data; // @[VAlu.scala 9:18]
+ wire valu_io_read_4_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_read_4_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_read_4_data; // @[VAlu.scala 9:18]
+ wire valu_io_read_5_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_read_5_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_read_5_data; // @[VAlu.scala 9:18]
+ wire valu_io_write_0_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_write_0_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_write_0_data; // @[VAlu.scala 9:18]
+ wire valu_io_write_1_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_write_1_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_write_1_data; // @[VAlu.scala 9:18]
+ wire valu_io_write_2_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_write_2_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_write_2_data; // @[VAlu.scala 9:18]
+ wire valu_io_write_3_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_write_3_addr; // @[VAlu.scala 9:18]
+ wire [255:0] valu_io_write_3_data; // @[VAlu.scala 9:18]
+ wire valu_io_whint_0_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_whint_0_addr; // @[VAlu.scala 9:18]
+ wire valu_io_whint_1_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_whint_1_addr; // @[VAlu.scala 9:18]
+ wire valu_io_whint_2_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_whint_2_addr; // @[VAlu.scala 9:18]
+ wire valu_io_whint_3_valid; // @[VAlu.scala 9:18]
+ wire [5:0] valu_io_whint_3_addr; // @[VAlu.scala 9:18]
+ wire valu_io_scalar_0_valid; // @[VAlu.scala 9:18]
+ wire [31:0] valu_io_scalar_0_data; // @[VAlu.scala 9:18]
+ wire valu_io_scalar_1_valid; // @[VAlu.scala 9:18]
+ wire [31:0] valu_io_scalar_1_data; // @[VAlu.scala 9:18]
wire vconv_clock; // @[VConvCtrl.scala 9:18]
wire vconv_reset; // @[VConvCtrl.scala 9:18]
wire vconv_io_in_ready; // @[VConvCtrl.scala 9:18]
@@ -122327,7 +122346,7 @@
.io_undef(vdec_io_undef),
.io_nempty(vdec_io_nempty)
);
- VAlu valu ( // @[VAlu.scala 29:18]
+ VAlu valu ( // @[VAlu.scala 9:18]
.clock(valu_clock),
.reset(valu_reset),
.io_in_ready(valu_io_in_ready),
