Merge "Add chip_sw_rv_dm_ndm_reset_req_when_cpu_halted in edacloud regression suites"
diff --git a/hw/top_matcha/data/chip_testplan.hjson b/hw/top_matcha/data/chip_testplan.hjson
index 725de65..7db13e0 100644
--- a/hw/top_matcha/data/chip_testplan.hjson
+++ b/hw/top_matcha/data/chip_testplan.hjson
@@ -110,6 +110,16 @@
stage: V1
tests: ["chip_sw_gpio"]
}
+ {
+ name: chip_sw_crt_test
+ desc: '''Verify C runtime functionality.
+
+ - The SW test setup data in .bss and .data region.
+ - The SW test verify both CRT clear and copy functions.
+ '''
+ stage: V1
+ tests: ["chip_sw_crt_test"]
+ }
// SPI_DEVICE (pre-verified IP) integration tests:
{
@@ -284,6 +294,22 @@
// TBD if it can be combined with chip_sw_i2c_host_tx_rx
tests: []
}
+
+ // I2S integration tests:
+ {
+ name: chip_sw_i2s_tx_rx
+ desc: '''Verify the transmission of data over the chip's I2S interface.
+
+ - Setup I2S tx rx IRQs in plic.
+ - Create a workload and send it over I2S.
+ - Check the interrupt is received.
+ - Check the transaction is finished and the fifo is empty.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test"]
+ }
+
// USB (pre-verified IP) integration tests:
{
name: chip_sw_usb_fs_tx_rx
@@ -945,6 +971,17 @@
stage: V2
tests: ["chip_sw_smc_plic_vsi_irq"]
}
+ {
+ name: chip_sw_atomics_test
+ desc: '''Verify atomic instruction on SMC core.
+
+ - SW bringup SMC core
+ - SW config valid and invalid address.
+ - SW runs atomic instructions and verify the functionality
+ '''
+ stage: V2
+ tests: ["chip_sw_atomics_test"]
+ }
// CLKMGR tests:
{
name: chip_sw_clkmgr_idle_trans
@@ -2077,7 +2114,7 @@
- Program the smc_ctrl register to enable SMC core to boot.
'''
stage: V2
- tests: []
+ tests: ["chip_sw_smc_ctrl_test"]
}
// CAM_CTRL (pre-verified IP) integration tests:
@@ -2085,13 +2122,14 @@
name: chip_sw_cam_ctrl
desc: '''Verify that the cam_ctrl can control himax cam sensor.
+ - Program the cam_ctrl to toggle internal registers and verify the result
- Program the cam_ctrl to driver the trigger output to sensor.
- Program testbench to generate interrupt from cam_sensor, to verify if cam_ctrl
generate interrupt to host's PLIC (SMC core).
- TO-DO: test to be added.
'''
stage: V2
- tests: []
+ tests: ["chip_sw_cam_ctrl_test"]
}
// Mailbox (pre-verified IP) integration tests:
{
@@ -2147,7 +2185,7 @@
it was cleared.
'''
stage: V2
- tests: []
+ tests: ["chip_sw_dma_main_test"]
}
///////////////////////////////////////////////////////
// Security Peripherals //
@@ -3798,6 +3836,24 @@
tests: ["chip_sw_i2c_boot"]
}
{
+ // TODO(b/287644985): revise mem_test.c into smc_sram_smoke test.
+ name: chip_sw_mem_test
+ desc: '''Verify the access to all of the memory instances
+
+ - SW bring up secure core
+ - SW read/write random data in SMC ram memory region
+ - SW read/write random data in ML data memory region
+ - SW vefiry the written data matches the read data
+ '''
+ stage: V2
+ tests: ["chip_sw_mem_test"]
+ }
+
+ //////////////////
+ // CPU //
+ // RV_CORE_SMC //
+ //////////////////
+ {
name: chip_sw_boot_smc
desc: '''Verify the full SMC core image download with bootstrap signal set.
@@ -3822,6 +3878,18 @@
tests: ["chip_sw_smc_kelvin_hello_test"]
}
{
+ name: chip_sw_smc_isp_wrapper_test
+ desc: '''Verify ISP is enabled and generate data
+
+ - SW enable ISP to a simple mode.
+ - SW verify ISP status registers are updated.
+ - SW randomly read/write the memory region which is accessible by ISP.
+ - SW validate the writtne data matches the read data.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_isp_wrapper_test"]
+ }
+ {
name: chip_sw_smc_isp_simple_test_data
desc: '''Verify ISP control path and data path
@@ -3927,6 +3995,20 @@
"chip_sw_smc_page_boundary_test",
"chip_sw_smc_supervisor_mode_test",
"chip_sw_smc_virtual_memory_test"]
+
+ }
+ // SMC RV_TIMER integration tests:
+ {
+ name: chip_sw_smc_rv_timer_test
+ desc: '''Verify the timeout interrupt assertion.
+
+ - Configure the SMC RV_TIMER to generate interrupt after a set timeout.
+ - Issue a WFI to wait for the interrupt to trigger.
+ - Service the interrupt when it triggers; verify that it came from rv_timer.
+ - Verify that the interrupt triggered only after the timeout elapsed.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_rv_timer_test"]
}
{
name: chip_sw_video_pipe_smoketest
@@ -3943,17 +4025,16 @@
tests: ["chip_sw_video_pipe_smoketest"]
}
{
- name: chip_sw_run_ml_workload
- desc: '''Verify the launch ML workload at ml core at either Kelvin or Malamute.
+ name: chip_sw_smc_kelvin_run_checksum_test
+ desc: '''Verify checksum test on Kelvin core.
- - SW download ML exe binary from external QSPI Flash to ML memory.
- - SW download ML model from external QSPI Flash to ML memory.
- - SW enable both camera and ISP to grab one frame of image.
- - SW enable the ML core to run one inference and verify the result.
- workload.
+ - SW bring up both SMC and ML cores.
+ - SW write a test image onto ML DMEM.
+ - SW start Kelvin core to read image data and compute checksum.
+ - SW validate the compuated checksum matches the golden checksum.
'''
stage: V2
- tests: []
+ tests: ["chip_sw_smc_kelvin_checksum_test"]
}
]
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index be7b57b..d5a8768 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -506,6 +506,83 @@
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
{
+ name: chip_sw_atomics_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:atomics_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_cam_ctrl_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:cam_ctrl_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_crt_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:crt_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_dma_main_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:dma_main_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_mem_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:mem_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_ctrl_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:smc_ctrl_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_i2s_rx_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_i2s_rx_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_i2s_tx_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_i2s_tx_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_rv_timer_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_rv_timer_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_kelvin_checksum_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_kelvin_checksum_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_isp_wrapper_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
// Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson.
name: "chip_csr_bit_bash"
// Don't test over 200 randomly picked CSRs at a time.
@@ -1934,11 +2011,14 @@
tests: [
"chip_sw_alert_test",
"chip_sw_aon_timer_smoketest",
+ "chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_smoketest",
+ "chip_sw_crt_test",
"chip_sw_csrng_smoketest",
+ "chip_sw_dma_main_test",
"chip_sw_example_flash",
- "chip_sw_flash_ctrl_access",
"chip_sw_i2c_host_tx_rx",
+ "chip_sw_mem_test",
"chip_sw_rom_ctrl_integrity_check",
"chip_sw_rstmgr_smoketest",
"chip_sw_rstmgr_sw_req",
@@ -1946,15 +2026,19 @@
"chip_sw_rv_plic_smoketest",
"chip_sw_rv_timer_irq",
"chip_sw_smc_cam_irq_test",
+ "chip_sw_smc_ctrl_test",
"chip_sw_smc_env_test",
+ "chip_sw_smc_i2s_rx_test",
"chip_sw_smc_interrupt_boundary_test",
"chip_sw_smc_isp_wrapper_irq_test",
+ "chip_sw_smc_isp_wrapper_test",
"chip_sw_smc_isp_wrapper_tpg_64_64_test",
"chip_sw_smc_lsu_interrupt_boundary_test",
"chip_sw_smc_lsu_page_boundary_test",
"chip_sw_smc_ml_sram_smoketest",
"chip_sw_smc_ml_top_irq_test",
"chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_rv_timer_test",
"chip_sw_smc_supervisor_mode_test",
"chip_sw_smc_virtual_memory_test",
"chip_sw_spi_device_tx_rx",
@@ -1973,8 +2057,12 @@
"chip_sw_alert_handler_ping_timeout",
"chip_sw_alert_test",
"chip_sw_aon_timer_smoketest",
+ "chip_sw_atomics_test",
+ "chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_smoketest",
+ "chip_sw_crt_test",
"chip_sw_csrng_smoketest",
+ "chip_sw_dma_main_test",
"chip_sw_entropy_src_smoketest",
"chip_sw_example_flash",
"chip_sw_flash_ctrl_access",
@@ -1983,6 +2071,7 @@
"chip_sw_hmac_enc",
"chip_sw_hmac_smoketest",
"chip_sw_i2c_host_tx_rx",
+ "chip_sw_mem_test",
"chip_sw_keymgr_key_derivation",
"chip_sw_kmac_idle",
"chip_sw_kmac_smoketest",
@@ -1997,16 +2086,22 @@
"chip_sw_rv_plic_smoketest",
"chip_sw_rv_timer_irq",
"chip_sw_smc_cam_irq_test",
+ "chip_sw_smc_ctrl_test",
"chip_sw_smc_env_test",
+ "chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
"chip_sw_smc_interrupt_boundary_test",
"chip_sw_smc_isp_wrapper_irq_test",
+ "chip_sw_smc_isp_wrapper_test",
"chip_sw_smc_isp_wrapper_tpg_64_64_test",
+ "chip_sw_smc_kelvin_checksum_test",
"chip_sw_smc_kelvin_hello_test",
"chip_sw_smc_lsu_interrupt_boundary_test",
"chip_sw_smc_lsu_page_boundary_test",
"chip_sw_smc_ml_sram_smoketest",
"chip_sw_smc_ml_top_irq_test",
"chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_rv_timer_test",
"chip_sw_smc_supervisor_mode_test",
"chip_sw_smc_tlul_mailbox_test",
"chip_sw_smc_virtual_memory_test",
@@ -2026,8 +2121,12 @@
"chip_sw_alert_handler_ping_timeout",
"chip_sw_alert_test",
"chip_sw_aon_timer_smoketest",
+ "chip_sw_atomics_test",
+ "chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_smoketest",
+ "chip_sw_crt_test",
"chip_sw_csrng_smoketest",
+ "chip_sw_dma_main_test",
"chip_sw_entropy_src_smoketest",
"chip_sw_example_flash",
"chip_sw_flash_ctrl_access",
@@ -2036,6 +2135,7 @@
"chip_sw_hmac_enc",
"chip_sw_hmac_smoketest",
"chip_sw_i2c_host_tx_rx",
+ "chip_sw_mem_test",
"chip_sw_keymgr_key_derivation",
"chip_sw_kmac_idle",
"chip_sw_kmac_smoketest",
@@ -2050,16 +2150,22 @@
"chip_sw_rv_plic_smoketest",
"chip_sw_rv_timer_irq",
"chip_sw_smc_cam_irq_test",
+ "chip_sw_smc_ctrl_test",
"chip_sw_smc_env_test",
+ "chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
"chip_sw_smc_interrupt_boundary_test",
"chip_sw_smc_isp_wrapper_irq_test",
+ "chip_sw_smc_isp_wrapper_test",
"chip_sw_smc_isp_wrapper_tpg_64_64_test",
+ "chip_sw_smc_kelvin_checksum_test",
"chip_sw_smc_kelvin_hello_test",
"chip_sw_smc_lsu_interrupt_boundary_test",
"chip_sw_smc_lsu_page_boundary_test",
"chip_sw_smc_ml_sram_smoketest",
"chip_sw_smc_ml_top_irq_test",
"chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_rv_timer_test",
"chip_sw_smc_supervisor_mode_test",
"chip_sw_smc_tlul_mailbox_test",
"chip_sw_smc_virtual_memory_test",
diff --git a/sw/device/examples/hello_world/BUILD b/sw/device/examples/hello_world/BUILD
index fa9fce8..e6d7f3a 100644
--- a/sw/device/examples/hello_world/BUILD
+++ b/sw/device/examples/hello_world/BUILD
@@ -65,3 +65,25 @@
"verilator",
],
)
+
+sh_test(
+ name = "verilator_hello_world_gpio_test",
+ timeout = "long",
+ srcs = [":run_verilator_hello_world.sh"],
+ args = [
+ "$(location //hw:verilator)",
+ "$(location //sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem)",
+ "$(location :hello_world_sim_verilator_vmem)",
+ "$(location //hw/top_matcha/data:otp_img_rma)",
+ "gpio_test",
+ ],
+ data = [
+ ":hello_world_sim_verilator_vmem",
+ "//hw:verilator",
+ "//hw/top_matcha/data:otp_img_rma",
+ "//sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem",
+ ],
+ tags = [
+ "verilator",
+ ],
+)
diff --git a/sw/device/examples/hello_world/hello_world.c b/sw/device/examples/hello_world/hello_world.c
index 216178b..577e7c5 100644
--- a/sw/device/examples/hello_world/hello_world.c
+++ b/sw/device/examples/hello_world/hello_world.c
@@ -107,7 +107,11 @@
// Now have UART <-> Buttons/LEDs demo
// all LEDs off
CHECK_DIF_OK(dif_gpio_write_all(&gpio, 0x0000));
- LOG_INFO("Try out the switches on the board");
+ if (kDeviceType == kDeviceFpgaNexus) {
+ LOG_INFO("Try out the switches on the board");
+ } else if (kDeviceType == kDeviceSimVerilator) {
+ LOG_INFO("Try out the GPIO switches 28, 29, 31");
+ }
LOG_INFO("or type anything into the console window.");
LOG_INFO(
"The LEDs show the bits of the ASCII code of the last "
diff --git a/sw/device/examples/hello_world/run_verilator_hello_world.sh b/sw/device/examples/hello_world/run_verilator_hello_world.sh
index e85af45..e220a8a 100755
--- a/sw/device/examples/hello_world/run_verilator_hello_world.sh
+++ b/sw/device/examples/hello_world/run_verilator_hello_world.sh
@@ -17,7 +17,7 @@
# Run verilator interactive simulation on sw/device/examples/hello_world.
function print_usage {
- echo "Usage: run_verilator_hello_world.sh <verilator testbench> <rom binary> <flash binary> <otp binary>"
+ echo "Usage: run_verilator_hello_world.sh <verilator testbench> <rom binary> <flash binary> <otp binary> [gpio_test]"
}
if [[ $1 == "--help" ]]; then
@@ -25,7 +25,7 @@
exit 0
fi
-if [[ $# -ne 4 ]]; then
+if [[ $# -lt 4 ]]; then
print_usage
exit 1
fi
@@ -35,8 +35,16 @@
exit 1
fi
+# This cycle count is tuned so we don't need to wait too long for the test to
+# finish.
+TEST_CYCLES=700000
-TEST_CYCLES=650000
+GPIO_TEST=0
+
+if [[ $# -eq 5 ]] && [[ $5 == "gpio_test" ]]; then
+ GPIO_TEST=1
+ TEST_CYCLES=900000
+fi
VCHIP_TB=$1
ROM_BIN=$2
@@ -62,19 +70,37 @@
VERILATOR_PID=$!
-# Pipe GPIO output to a log file
-sleep 5
-cat gpio0-read | tee "${TEST_UNDECLARED_OUTPUTS_DIR}/gpio0_read.log" &
+if (( ${GPIO_TEST} == 0 )); then
+ # Pipe GPIO output to a log file
+ sleep 5
+ cat gpio0-read | tee "${TEST_UNDECLARED_OUTPUTS_DIR}/gpio0_read.log" &
-# Wait for 300s to reach the end of the hello_world initialization.
-sleep 300
-echo 'led gpio test' > "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0_device"
+ # Wait for 300s to reach the end of the hello_world initialization.
+ # Note: The value is tuned for the CICD to run. For local failing tests,
+ # consider to reduce the wait or increase the TEST_CYCLES.
+ sleep 300
+ echo 'led gpio test' > "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0_device"
-# Wait up to another 350s to complete the verilator simulation.
-timeout 350 tail --pid=${VERILATOR_PID} -f /dev/null
+ tail --pid=${VERILATOR_PID} -f /dev/null
-# Check results in GPIO and UART logs.
-cat "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0.log" | grep -q "led gpio test" || exit 1
+ # Check results in GPIO and UART logs.
+ cat "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0.log" | grep -q "led gpio test" || exit 1
-diff -q "${TEST_UNDECLARED_OUTPUTS_DIR}/gpio0_read.log" \
- "sw/device/examples/hello_world/hello_world_test_expected_gpio.txt" || exit 1
+ diff -q "${TEST_UNDECLARED_OUTPUTS_DIR}/gpio0_read.log" \
+ "sw/device/examples/hello_world/hello_world_test_expected_gpio.txt" || exit 1
+else
+ # Wait for 260s to reach the end of the hello_world initialization.
+ # Note: This value may need to tuned by the machine performance. Need to
+ # reduce the wait if the verilator simulation is fast (or increase the
+ # TEST_CYCLES variable).
+ sleep 260
+ echo 'h28 h29 h31' > gpio0-write
+
+ tail --pid=${VERILATOR_PID} -f /dev/null
+
+ # Check GPIO toggle result in the UART log
+ for switch in "9" "10" "11"; do
+ cat "${TEST_UNDECLARED_OUTPUTS_DIR}/uart0.log" | \
+ grep -q "GPIO switch #${switch} changed to 1" || exit 1
+ done
+fi
diff --git a/sw/device/tests/mem_test.c b/sw/device/tests/mem_test.c
index 43073fc..59a8f3c 100644
--- a/sw/device/tests/mem_test.c
+++ b/sw/device/tests/mem_test.c
@@ -31,8 +31,6 @@
mmio_region_t base_addr = mmio_region_from_addr(TOP_MATCHA_RAM_SMC_BASE_ADDR);
- mem_val = mmio_region_read32(base_addr, 0x0);
-
mmio_region_write32(base_addr, 0x0, 0x55aa55aa);
mem_val = mmio_region_read32(base_addr, 0x0);
CHECK(mem_val == 0x55aa55aa,
@@ -53,8 +51,6 @@
mmio_region_t ml_dmem_base_addr =
mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR);
- mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0);
-
mmio_region_write32(ml_dmem_base_addr, 0x0, 0x55aa55aa);
mmio_region_write32(ml_dmem_base_addr, 0x4, 0x12345678);
mmio_region_write32(ml_dmem_base_addr, 0x8, 0x55aa55aa);
