[dma/dv] Remove randomization constraints

Change-Id: Ibfb300f1f0dc4408888f77ec5096193c0604db02

hw/top_matcha/ip/dma/dv/dma_sim_cfg.hjson

diff --git a/hw/top_matcha/ip/dma/dv/dma_sim_cfg.hjson b/hw/top_matcha/ip/dma/dv/dma_sim_cfg.hjson
index 0d3f389..154a2b2 100644
--- a/hw/top_matcha/ip/dma/dv/dma_sim_cfg.hjson
+++ b/hw/top_matcha/ip/dma/dv/dma_sim_cfg.hjson
@@ -37,7 +37,7 @@
   sim_tops: ["dma_bind"]
 
   // Default iterations for all tests - each test entry can override this.
-  reseed: 1
+  reseed: 32
 
   // Default UVM test and seq class name.
   uvm_test: dma_base_test

hw/top_matcha/ip/dma/dv/env/dma_env_cfg.sv

diff --git a/hw/top_matcha/ip/dma/dv/env/dma_env_cfg.sv b/hw/top_matcha/ip/dma/dv/env/dma_env_cfg.sv
index 69ea0d6..64b9085 100644
--- a/hw/top_matcha/ip/dma/dv/env/dma_env_cfg.sv
+++ b/hw/top_matcha/ip/dma/dv/env/dma_env_cfg.sv
@@ -23,28 +23,12 @@
     m_reader_tl_agent_cfg.if_mode = dv_utils_pkg::Device;
     m_reader_tl_agent_cfg.is_active = 1;
     m_reader_tl_agent_cfg.device_can_rsp_on_same_cycle = 1;
-    m_reader_tl_agent_cfg.a_valid_delay_min = 0;
-    m_reader_tl_agent_cfg.a_valid_delay_max = 0;
-    m_reader_tl_agent_cfg.d_valid_delay_min = 0;
-    m_reader_tl_agent_cfg.d_valid_delay_max = 0;
-    m_reader_tl_agent_cfg.a_ready_delay_min = 0;
-    m_reader_tl_agent_cfg.a_ready_delay_max = 0;
-    m_reader_tl_agent_cfg.d_ready_delay_min = 0;
-    m_reader_tl_agent_cfg.d_ready_delay_max = 0;
 
     // create writer_tl agent config obj
     m_writer_tl_agent_cfg = tl_agent_cfg::type_id::create("m_writer_tl_agent_cfg");
     m_writer_tl_agent_cfg.if_mode = dv_utils_pkg::Device;
     m_writer_tl_agent_cfg.is_active = 1;
     m_writer_tl_agent_cfg.device_can_rsp_on_same_cycle = 1;
-    m_writer_tl_agent_cfg.a_valid_delay_min = 0;
-    m_writer_tl_agent_cfg.a_valid_delay_max = 0;
-    m_writer_tl_agent_cfg.d_valid_delay_min = 0;
-    m_writer_tl_agent_cfg.d_valid_delay_max = 0;
-    m_writer_tl_agent_cfg.a_ready_delay_min = 0;
-    m_writer_tl_agent_cfg.a_ready_delay_max = 0;
-    m_writer_tl_agent_cfg.d_ready_delay_min = 0;
-    m_writer_tl_agent_cfg.d_ready_delay_max = 0;
 
     // only support 1 outstanding TL items in tlul_adapter
     m_tl_agent_cfg.max_outstanding_req = 1;