hw/ip/dma/data/dma_testplan.hjson

// Copyright 2023 Google LLC
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "dma"
  // TODO: remove the common testplans if not applicable
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            Verify that the reader and writer perform as expected.

            Configure
            - Set up source memory with data and zero out destination memory.
            - Set reader and writer addresses, with the same length, count, and stride.
            - Disable loop mode, configure interrupts, and start both frontends.

            Check
            - Status registers read as 1 during the transfer.
            - The interrupt is raised when the transfer is complete, and the status registers
              are no longer 1.
            - Source and destination memory contain the same data.

            '''
      stage: V1
      tests: ["dma_smoke"]
    }
    {
      name: reader_stream
      desc: '''
            Configure
            - Set up reader frontend in stream mode with the writer to store to a fixed address.
            - Raise writer interrupt

            Check
            - The data written by the writer matches the data written to the reader.

      '''
      stage: V1
      tests: []
    }
    {
      name: writer_stream
      desc: '''
            Configure
            - Set up writer frontend in stream mode with the reader to fetch from a fixed address.
            - Raise writer interrupt

            Check
            - Read from the writer and confirm it's the same data fetched by the reader.
      '''
      stage: V1
      tests: []
    }
    {
      name: reader_loop
      desc: '''
            Configure
            - Read data from fixed address, configuring the control registers to not increment the
              address and continue reading for a certain number of counts, finally raising an
              interrupt.

            Check
            - Confirm the address stays fixed and valid data is fetched to the reader.
      '''
      stage: V1
      tests: []
    }
    {
      name: writer_loop
      desc: '''
            Configure
            - Write data to fixed address, configuring the control registers to not increment the
              address and continue writing for a certain number of counts, finally raising an
              interrupt.

            Check
            - Confirm the address stays fixed and valid data is written by the writer.
      '''
      stage: V1
      tests: []
    }
  ]

  covergroups: [
    {
      name: stride_cg
      desc: '''
            Cover various stride configurations in different transactions.
            '''
    }
    {
      name: interrupt_completion_cg
      desc: '''
            Confirm that data being read/written has already made it from/to memory when the
            interrupt has been raised, since the TLUL bus can arbitrate another message as
            higher priority than a DMA request.
            '''
    }
  ]
}