hw/ip/dma/data/dma.hjson

// Copyright 2023 Google LLC
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "dma",
  clocking: [{clock: "clk_i", reset: "rst_ni", primary: true}],
  bus_interfaces: [
    { protocol: "tlul", direction: "host",   name: "writer" },
    { protocol: "tlul", direction: "host",   name: "reader" },
    { protocol: "tlul", direction: "device"                 }
  ],

  // Don't create interrupt registers beginning at 0x0 in order
  // to follow IP's register map. This means that dif_dma_autogen.c was
  // manually changed to not include undefined macros that were autogen.
  no_auto_intr_regs: "true",
  interrupt_list: [
    { name: "writer_done",
      desc: "raised when the writer has completed a requested transfer. Write 1 to clear.",
    },
    { name: "reader_done",
      desc: "raised when the reader has completed a requested transfer. Write 1 to clear."
    }
  ]

  regwidth: "32",
  registers: [
      { name: "CTRL",
        desc: '''
          Control register
        ''',
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "0",
            name: "WTR_START",
            desc: '''
              Write 1 to start write frontend. This bit automatically
              resets itself to 0 if not in loop mode.
            '''
          },
          { bits: "1",
            name: "RDR_START",
            desc: '''
              Write 1 to start read frontend. This bit automatically
              resets itself to 0 if not in loop mode.
            '''
          },
          { bits: "2",
            name: "WTR_SYNC_DIS",
            desc: '''
              Write 1 to disable waiting for external writer synchronization -
              rising edge on writerSync.
            '''
          },
          { bits: "3",
            name: "RDR_SYNC_DIS",
            desc: '''
              Write 1 to disable waiting for external reader synchronization -
              rising edge on readerSync.
            '''
          },
          { bits: "4",
            name: "WTR_LOOP",
            desc: '''
              Write 1 to automatically start next write frontend transfer
              after finishing the current one.
            '''
          },
          { bits: "5",
            name: "RDR_LOOP",
            desc: '''
              Write 1 to automatically start next read frontend transfer
              after finishing the current one.
            '''
          },
        ],
        tags: [// This register will self clear when set
               "excl:CsrNonInitTests:CsrExclWrite"],
      },

      { name: "STATUS",
        desc: "Status register",
        swaccess: "ro",
        hwaccess: "hro",
        fields: [
          { bits: "0",
            name: "WTR_BUSY",
            desc: '''
              Reads as 1 when write frontend is busy transferring data.
            '''
          },
          { bits: "1",
            name: "RDR_BUSY",
            desc: '''
              Reads as 1 when write frontend is busy transferring data
            '''
          },
        ],
        tags: [
        "excl:CsrAllTests:CsrExclWrite"],
      },

      // "INTR_ENABLE" is used here instead of IP name of "INTR_MASK" to match the
      // auto-generated DIF macros with dma_reg.h.
      { name: "INTR_ENABLE",
        desc: "Interrupt enable register",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "0",
            name: "WTR_MASK",
            desc: '''
              Write 1 to enable writer interrupt.
            '''
          },
          { bits: "1",
            name: "RDR_MASK",
            desc: '''
              Write 1 to enable reader interrupt.
            '''
          },
        ],
        tags: [
        "excl:CsrAllTests:CsrExclWrite"],
      },

      // "INTR_STATE" is used here instead of IP name of "INTR_STATUS" to match the
      // auto-generated DIF macros with dma_reg.h.
      { name: "INTR_STATE",
        desc: "Interrupt status register",
        swaccess: "rw1c",
        hwaccess: "hrw",
        fields: [
          { bits: "0",
            name: "WTR_INTR",
            desc: '''
              Reads as 1 if writer interrupt has occured, write 1 to clear that interrupt.
            '''
          },
          { bits: "1",
            name: "RDR_INTR",
            desc: '''
              Reads as 1 if reader interrupt has occured, write 1 to clear that interrupt.
            '''
          },
        ],
        tags: [// This register will self clear when set
        "excl:CsrNonInitTests:CsrExclWrite"],
      },

      { name: "RDR_START_ADDR",
        desc: "Reader start address - set to 0 if reader frontend is a stream interface.",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "RDR_LENGTH",
        desc: "Reader line length (as number of reader data bus widths).",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "RDR_LINE_CNT",
        desc: "Reader line count.",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "RDR_STRIDE",
        desc: "Gap between consecutive lines (as number of reader data bus widths).",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },


      { name: "WTR_START_ADDR",
        desc: "Writer start address - set to 0 if writer frontend is a stream interface.",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "WTR_LENGTH",
        desc: "Writer line length (as number of writer data bus widths).",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "WTR_LINE_CNT",
        desc: "Writer line count.",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "WTR_STRIDE",
        desc: "Gap between consecutive lines (as number of writer data bus widths).",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "31:0",
            resval: "0",
          },
        ]
      },

      { name: "VERSION",
        desc: "Holds hardware version.",
        swaccess: "ro",
        hwaccess: "hro",
        fields: [
          { bits: "31:0",
          },
        ],
        tags: [
        "excl:CsrAllTests:CsrExclWrite"],
      },

      { name: "CONFIG_INFO",
        desc: "Holds reader, writer and control bus types.",
        swaccess: "ro",
        hwaccess: "hro",
        fields: [
          { bits: "31:0",
          },
        ]
         tags: [
        "excl:CsrAllTests:CsrExclWrite"],
     },
  ],
}