Clean up warnings in fastvdma_core
- Due to updates in the Chisel build rules, warnings are now errors.
Clean up warnings in this module.
Change-Id: I681bb20580eed9f69e08b3c71ce66d5d417a2173
diff --git a/hw/ip/dma/chisel/src/DMAConfig.scala b/hw/ip/dma/chisel/src/DMAConfig.scala
index 6d16c81..0d030b6 100644
--- a/hw/ip/dma/chisel/src/DMAConfig.scala
+++ b/hw/ip/dma/chisel/src/DMAConfig.scala
@@ -15,8 +15,6 @@
package DMAController.DMAConfig
-import chisel3._
-
object DMAConfig {
val addrWidth = 32
val readDataWidth = 32
diff --git a/hw/ip/dma/chisel/src/DMATop.scala b/hw/ip/dma/chisel/src/DMATop.scala
index 7406fbc..b1ea04d 100644
--- a/hw/ip/dma/chisel/src/DMATop.scala
+++ b/hw/ip/dma/chisel/src/DMATop.scala
@@ -24,6 +24,7 @@
import DMAController.DMAConfig._
import _root_.circt.stage.{ChiselStage,FirtoolOption}
import chisel3.stage.ChiselGeneratorAnnotation
+import scala.annotation.nowarn
class DMATop extends Module {
@@ -64,6 +65,7 @@
assert(DMAConfig.readDataWidth == DMAConfig.writeDataWidth)
}
+@nowarn
object EmitDMA extends App{
(new ChiselStage).execute(
Array("--target", "systemverilog") ++ args,
diff --git a/hw/ip/dma/chisel/src/frontend/BusBase.scala b/hw/ip/dma/chisel/src/frontend/BusBase.scala
index c679fd0..004e9cf 100644
--- a/hw/ip/dma/chisel/src/frontend/BusBase.scala
+++ b/hw/ip/dma/chisel/src/frontend/BusBase.scala
@@ -18,10 +18,8 @@
import chisel3._
import chisel3.util._
-import DMAController.Bus._
-import DMAController.CSR.{CSR, CSRBusBundle}
-import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle}
-import DMAController.DMAConfig.DMAConfig
+import DMAController.CSR.{CSRBusBundle}
+import DMAController.Worker.{XferDescBundle}
abstract class IOBus[+T] extends Module {
val io : Bundle {
diff --git a/hw/ip/dma/chisel/src/frontend/TLULCSR.scala b/hw/ip/dma/chisel/src/frontend/TLULCSR.scala
index 370e73a..2115e2d 100644
--- a/hw/ip/dma/chisel/src/frontend/TLULCSR.scala
+++ b/hw/ip/dma/chisel/src/frontend/TLULCSR.scala
@@ -15,9 +15,7 @@
package DMAController.Frontend
import DMAController.Bus._
-import DMAController.CSR.{CSR, CSRBusBundle}
-import DMAController.DMAConfig._
-import DMAController.Worker.{WorkerCSRWrapper}
+import DMAController.CSR.{CSRBusBundle}
import chisel3._
import chisel3.util._
diff --git a/hw/ip/dma/chisel/src/frontend/TLULReader.scala b/hw/ip/dma/chisel/src/frontend/TLULReader.scala
index 1230b10..5131699 100644
--- a/hw/ip/dma/chisel/src/frontend/TLULReader.scala
+++ b/hw/ip/dma/chisel/src/frontend/TLULReader.scala
@@ -15,8 +15,7 @@
package DMAController.Frontend
import DMAController.Bus._
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
+import DMAController.Worker.{XferDescBundle}
import chisel3._
import chisel3.util._
diff --git a/hw/ip/dma/chisel/src/frontend/TLULWriter.scala b/hw/ip/dma/chisel/src/frontend/TLULWriter.scala
index d025d94..5485557 100644
--- a/hw/ip/dma/chisel/src/frontend/TLULWriter.scala
+++ b/hw/ip/dma/chisel/src/frontend/TLULWriter.scala
@@ -15,8 +15,7 @@
package DMAController.Frontend
import DMAController.Bus._
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
+import DMAController.Worker.{XferDescBundle}
import chisel3._
import chisel3.util._
