hw/ip/dma/chisel/src/frontend/BusBase.scala

/*
Copyright 2024 Google LLC
Copyright (C) 2019-2022 Antmicro

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

SPDX-License-Identifier: Apache-2.0
*/

package DMAController.Frontend

import chisel3._
import chisel3.util._

import DMAController.CSR.{CSRBusBundle}
import DMAController.Worker.{XferDescBundle}

abstract class IOBus[+T] extends Module {
  val io : Bundle {
    val bus : T
    val dataIO : DecoupledIO[UInt]
    val xfer : XferDescBundle
  }
}

abstract class CSRBus [+T] extends Module {
  val io : Bundle {
    val bus : CSRBusBundle
    val ctl : T
  }
}