Bring up SMC dv tests and add them into the regression Change-Id: Id783b01038fa2c5e00c9585db2bf4219f087e8af
diff --git a/hw/top_matcha/data/chip_testplan.hjson b/hw/top_matcha/data/chip_testplan.hjson index eaed0b7..69d9de3 100644 --- a/hw/top_matcha/data/chip_testplan.hjson +++ b/hw/top_matcha/data/chip_testplan.hjson
@@ -726,6 +726,16 @@ tests: ["chip_sw_rv_timer_irq"] } { + name: chip_sw_smc_env_test + desc: '''Verify the timeout interrupt assertion. + + - Bring up both secure core and SMC core. + - Verify SMC could be terminated by writing the status register. + ''' + stage: V2 + tests: ["chip_sw_smc_env_test"] + } + { name: chip_sw_smc_timer desc: '''Verify the timeout interrupt assertion. @@ -3826,7 +3836,7 @@ - SW check back data and compare with the golden pattern. ''' stage: V2 - tests: ["chip_sw_smc_isp_simple_test_data"] + tests: ["chip_sw_smc_isp_wrapper_tpg_64_64_test"] } { name: chip_sw_smc_isp_dma_smoketest
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson index 18700ae..2469017 100644 --- a/hw/top_matcha/dv/chip_sim_cfg.hjson +++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -355,6 +355,33 @@ run_opts: ["+xbar_mode=1"] reseed: 100 } + { + name: sw_test_mode_common_with_smc + run_opts: ["+sw_build_device={sw_build_device}", + // Format SW image names (which are Bazel labels concatenated with an index + // and/or flags, see below) into output file names separated by commas to feed into + // +sw_images plusarg. For example, if the input list of SW images is + // ["//sw/device/tests/sim_dv:uart_tx_rx_test:1", + // "//sw/device/lib/testing/test_rom:test_rom:0"], then the output of this eval_cmd + // will be: "uart_tx_rx_test:1,test_rom:0". + '''+sw_images={eval_cmd} \ + reformatted_sw_images=; \ + for image in {sw_images}; do \ + reformatted_sw_images="$reformatted_sw_images `echo $image | cut -d: -f2-`"; \ + done; \ + echo $reformatted_sw_images | sed -E 's/\s+/,/g' '''] + en_run_modes: ["gen_otp_images_mode"] + } + { + name: sw_test_mode_test_rom_with_smc + sw_images: ["//sw/device/lib/testing/test_rom:test_rom:0"] + en_run_modes: ["sw_test_mode_common_with_smc"] + } + { + name: sw_test_mode_test_simple_sec + sw_images: ["//sw/device/tests:simple_sec:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom_with_smc"] + } ] // List of test specifications. @@ -381,6 +408,20 @@ // 4 milliseconds of timeout. tests: [ { + name: chip_sw_smc_isp_wrapper_tpg_64_64_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_tpg_64_64_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_simple_sec"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_env_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_env_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_simple_sec"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson. name: "chip_csr_bit_bash" // Don't test over 200 randomly picked CSRs at a time. @@ -1825,6 +1866,8 @@ "chip_sw_rstmgr_sw_rst", "chip_sw_rv_plic_smoketest", "chip_sw_rv_timer_irq", + "chip_sw_smc_env_test", + "chip_sw_smc_isp_wrapper_tpg_64_64_test", "chip_sw_spi_device_tx_rx", "chip_sw_sram_ctrl_smoketest", "chip_sw_uart_smoketest",
diff --git a/hw/top_matcha/dv/env/chip_common_pkg.sv b/hw/top_matcha/dv/env/chip_common_pkg.sv index 4a7198b..a444fae 100644 --- a/hw/top_matcha/dv/env/chip_common_pkg.sv +++ b/hw/top_matcha/dv/env/chip_common_pkg.sv
@@ -21,9 +21,13 @@ // SW constants - use unmapped address space with at least 32 bytes. parameter bit [top_pkg::TL_AW-1:0] SW_DV_START_ADDR = tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX_SEC__CFG + rv_core_ibex_reg_pkg::RV_CORE_IBEX_DV_SIM_WINDOW_OFFSET; + parameter bit [top_pkg::TL_AW-1:0] SW_DV_SMC_START_ADDR = tl_smc_pkg::ADDR_SPACE_RV_CORE_IBEX_SMC__CFG + + rv_core_ibex_reg_pkg::RV_CORE_IBEX_DV_SIM_WINDOW_OFFSET; parameter bit [top_pkg::TL_AW-1:0] SW_DV_TEST_STATUS_ADDR = SW_DV_START_ADDR + 0; parameter bit [top_pkg::TL_AW-1:0] SW_DV_LOG_ADDR = SW_DV_START_ADDR + 4; + parameter bit [top_pkg::TL_AW-1:0] SW_DV_SMC_TEST_STATUS_ADDR = SW_DV_SMC_START_ADDR + 0; + parameter bit [top_pkg::TL_AW-1:0] SW_DV_SMC_LOG_ADDR = SW_DV_SMC_START_ADDR + 4; parameter uint ROM_CONSOLE_UART = 0;
diff --git a/hw/top_matcha/dv/env/chip_env.sv b/hw/top_matcha/dv/env/chip_env.sv index df2b3f9..b3e787b 100644 --- a/hw/top_matcha/dv/env/chip_env.sv +++ b/hw/top_matcha/dv/env/chip_env.sv
@@ -56,12 +56,20 @@ if (!uvm_config_db#(sw_logger_vif)::get(this, "", "sw_logger_vif", cfg.sw_logger_vif)) begin `uvm_fatal(`gfn, "failed to get sw_logger_vif from uvm_config_db") end + if (!uvm_config_db#(sw_logger_vif)::get(this, "", "sw_smc_logger_vif", cfg.sw_smc_logger_vif)) begin + `uvm_fatal(`gfn, "failed to get sw_smc_logger_vif from uvm_config_db") + end if (!uvm_config_db#(virtual sw_test_status_if)::get( this, "", "sw_test_status_vif", cfg.sw_test_status_vif )) begin `uvm_fatal(`gfn, "failed to get sw_test_status_vif from uvm_config_db") end + if (!uvm_config_db#(virtual sw_test_status_if)::get( + this, "", "sw_smc_test_status_vif", cfg.sw_smc_test_status_vif + )) begin + `uvm_fatal(`gfn, "failed to get sw_smc_test_status_vif from uvm_config_db") + end // get the handle to the ast supply interface. if (!uvm_config_db#(virtual ast_supply_if)::get(
diff --git a/hw/top_matcha/dv/env/chip_env_cfg.sv b/hw/top_matcha/dv/env/chip_env_cfg.sv index 12c947d..6f630a7 100644 --- a/hw/top_matcha/dv/env/chip_env_cfg.sv +++ b/hw/top_matcha/dv/env/chip_env_cfg.sv
@@ -71,11 +71,13 @@ otp_type_e use_otp_image = OtpTypeLcStRma; string otp_images[otp_type_e]; - uint sw_test_timeout_ns = 12_000_000; // 12ms - sw_logger_vif sw_logger_vif; - sw_test_status_vif sw_test_status_vif; - ast_supply_vif ast_supply_vif; - ast_ext_clk_vif ast_ext_clk_vif; + uint sw_test_timeout_ns = 12_000_000; // 12ms + sw_logger_vif sw_logger_vif; + sw_test_status_vif sw_test_status_vif; + sw_smc_logger_vif sw_smc_logger_vif; + sw_smc_test_status_vif sw_smc_test_status_vif; + ast_supply_vif ast_supply_vif; + ast_ext_clk_vif ast_ext_clk_vif; // Number of RAM tiles for each RAM instance. uint num_ram_main_tiles; @@ -425,7 +427,7 @@ end end else if (i == SwTypeOtp) begin otp_images[OtpTypeCustom] = $sformatf("%0s.24.vmem", sw_images[i]); - end else if (i == SwTypeDebug) begin + end else if (i == SwTypeDebug || i == SwTypeSmc) begin sw_images[i] = $sformatf("%0s_%0s", sw_images[i], sw_build_device); end end
diff --git a/hw/top_matcha/dv/env/chip_env_pkg.sv b/hw/top_matcha/dv/env/chip_env_pkg.sv index 6b361fd..874577e 100644 --- a/hw/top_matcha/dv/env/chip_env_pkg.sv +++ b/hw/top_matcha/dv/env/chip_env_pkg.sv
@@ -47,6 +47,7 @@ import pwm_monitor_pkg::*; import pwm_reg_pkg::NOutputs; import tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX_SEC__CFG; + import tl_smc_pkg::ADDR_SPACE_RV_CORE_IBEX_SMC__CFG; import rv_core_ibex_reg_pkg::RV_CORE_IBEX_DV_SIM_WINDOW_OFFSET; import i2c_agent_pkg::*; import pattgen_agent_pkg::*; @@ -67,6 +68,8 @@ typedef virtual sw_logger_if sw_logger_vif; typedef virtual sw_test_status_if sw_test_status_vif; + typedef virtual sw_logger_if sw_smc_logger_vif; + typedef virtual sw_test_status_if sw_smc_test_status_vif; typedef virtual ast_supply_if ast_supply_vif; typedef virtual ast_ext_clk_if ast_ext_clk_vif; @@ -88,7 +91,8 @@ Otp, RamMain[16], RamRet[16], - Rom + Rom, + Smc_ram } chip_mem_e; // On OpenTitan, we deal with 4 types of SW - ROM, the main test, the OTBN test and the OTP image. @@ -99,7 +103,8 @@ SwTypeTestSlotB = 2, // Ibex SW - test SW in (flash) slot B. SwTypeOtbn = 3, // Otbn SW SwTypeOtp = 4, // Customized OTP image - SwTypeDebug = 5 // Debug SW - injected into SRAM. + SwTypeDebug = 5, // Debug SW - injected into SRAM. + SwTypeSmc = 6 // SMC SW } sw_type_e; // Our dvsim.py configuration always generates five base OTP images (in various lifecycle states)
diff --git a/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv index ea12936..f2cc535 100644 --- a/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv +++ b/hw/top_matcha/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -53,6 +53,7 @@ `uvm_info(`gfn, "Starting cpu_init", UVM_MEDIUM) // Initialize the sw logger interface. + // SEC foreach (cfg.sw_images[i]) begin if (i inside {SwTypeRom, SwTypeDebug, SwTypeTestSlotA, SwTypeTestSlotB}) begin cfg.sw_logger_vif.add_sw_log_db(cfg.sw_images[i]); @@ -61,9 +62,19 @@ cfg.sw_logger_vif.sw_log_addr = SW_DV_LOG_ADDR; cfg.sw_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file; cfg.sw_logger_vif.ready(); + // SMC + foreach (cfg.sw_images[i]) begin + if (i inside {SwTypeSmc}) begin + cfg.sw_smc_logger_vif.add_sw_log_db(cfg.sw_images[i]); + end + end + cfg.sw_smc_logger_vif.sw_log_addr = SW_DV_SMC_LOG_ADDR; + cfg.sw_smc_logger_vif.write_sw_logs_to_file = cfg.write_sw_logs_to_file; + cfg.sw_smc_logger_vif.ready(); // Initialize the sw test status. - cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR; + cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR; + cfg.sw_smc_test_status_vif.sw_test_status_addr = SW_DV_SMC_TEST_STATUS_ADDR; `uvm_info(`gfn, "Initializing SRAMs", UVM_MEDIUM) @@ -113,6 +124,11 @@ cfg.mem_bkdr_util_h[FlashBank1Data].load_mem_from_file( {cfg.sw_images[SwTypeTestSlotB], ".64.scr.vmem"}); end + // SMC RAM sw imsage load + if (cfg.sw_images.exists(SwTypeSmc)) begin + cfg.mem_bkdr_util_h[Smc_ram].load_mem_from_file( + {cfg.sw_images[SwTypeSmc], ".32.vmem"}); + end config_jitter(); @@ -226,7 +242,7 @@ fork begin: isolation_thread fork - wait (cfg.sw_test_status_vif.sw_test_done); + wait (cfg.sw_test_status_vif.sw_test_done || cfg.sw_smc_test_status_vif.sw_test_done); #(cfg.sw_test_timeout_ns * 1ns); join_any disable fork; @@ -237,15 +253,28 @@ // Print pass / fail message to the log. virtual function void log_sw_test_status(); - case (cfg.sw_test_status_vif.sw_test_status) - SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW) - SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!") - default: begin - // If the SW test has not reached the passed / failed state, then it timed out. - `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n", - cfg.sw_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns)) - end - endcase + if(cfg.sw_test_status_vif.sw_test_done) begin + case (cfg.sw_test_status_vif.sw_test_status) + SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW) + SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!") + default: begin + // If the SW test has not reached the passed / failed state, then it timed out. + `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n", + cfg.sw_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns)) + end + endcase + end + if(cfg.sw_smc_test_status_vif.sw_test_done) begin + case (cfg.sw_smc_test_status_vif.sw_test_status) + SwTestStatusPassed: `uvm_info(`gfn, "SW TEST PASSED!", UVM_LOW) + SwTestStatusFailed: `uvm_error(`gfn, "SW TEST FAILED!") + default: begin + // If the SW test has not reached the passed / failed state, then it timed out. + `uvm_error(`gfn, $sformatf("SW TEST TIMED OUT. STATE: %0s, TIMEOUT = %0d ns\n", + cfg.sw_smc_test_status_vif.sw_test_status.name(), cfg.sw_test_timeout_ns)) + end + endcase + end endfunction // Configure the provided spi_agent_cfg to use flash mode, and add the
diff --git a/hw/top_matcha/dv/tb/chip_hier_macros.svh b/hw/top_matcha/dv/tb/chip_hier_macros.svh index 6265b5d..233bf05 100644 --- a/hw/top_matcha/dv/tb/chip_hier_macros.svh +++ b/hw/top_matcha/dv/tb/chip_hier_macros.svh
@@ -64,3 +64,4 @@ `define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB `define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB `define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB +`define SMC_RAM_HIER `CHIP_HIER.u_ram1p_ram_smc.u_mem.`MEM_ARRAY_SUB
diff --git a/hw/top_matcha/dv/tb/tb.sv b/hw/top_matcha/dv/tb/tb.sv index 539c2f7..77cb5c5 100644 --- a/hw/top_matcha/dv/tb/tb.sv +++ b/hw/top_matcha/dv/tb/tb.sv
@@ -186,6 +186,50 @@ .* ); + // Connect the SMC SRAM directly inside rv_core_smc. + `define SIM_SMC_SRAM_IF u_sim_smc_sram.u_sim_sram_if + // Instantiate & connect the simulation SRAM inside the SMC CPU (rv_core_ibex) using forces. + bit stub_smc; + initial begin + void'($value$plusargs("stub_smc_core=%0b", stub_smc)); + end + + bit en_sim_smc_sram = 1'b1; + wire sel_sim_smc_sram = !stub_smc & en_sim_smc_sram; + + sim_sram u_sim_smc_sram ( + .clk_i (sel_sim_smc_sram ? `SMC_CPU_HIER.clk_i : 1'b0), + .rst_ni (`SMC_CPU_HIER.rst_ni), + .tl_in_i (tlul_pkg::tl_h2d_t'(`SMC_CPU_HIER.u_tlul_req_buf.out_o)), + .tl_in_o (), + .tl_out_o (), + .tl_out_i () + ); + + initial begin + void'($value$plusargs("en_sim_smc_sram=%0b", en_sim_smc_sram)); + if (!stub_smc && en_sim_smc_sram) begin + `SIM_SMC_SRAM_IF.start_addr = SW_DV_SMC_START_ADDR; + force `SMC_CPU_HIER.u_tlul_rsp_buf.in_i = u_sim_smc_sram.tl_in_o; + end + end + + // Bind the SW test status interface directly to the sim SRAM interface. + bind `SIM_SMC_SRAM_IF sw_test_status_if u_sw_smc_test_status_if ( + .addr (tl_h2d.a_address), + .data (tl_h2d.a_data[15:0]), + .fetch_en (dut.chip_if.pwrmgr_cpu_fetch_en), + .* + ); + + // Bind the SW logger interface directly to the sim SRAM interface. + bind `SIM_SMC_SRAM_IF sw_logger_if u_sw_smc_logger_if ( + .addr (tl_h2d.a_address), + .data (tl_h2d.a_data), + .* + ); + + initial begin // IO Interfaces uvm_config_db#(virtual chip_if)::set(null, "*.env", "chip_vif", dut.chip_if); @@ -193,8 +237,12 @@ // SW logger and test status interfaces. uvm_config_db#(virtual sw_test_status_if)::set( null, "*.env", "sw_test_status_vif", `SIM_SRAM_IF.u_sw_test_status_if); + uvm_config_db#(virtual sw_test_status_if)::set( + null, "*.env", "sw_smc_test_status_vif", `SIM_SMC_SRAM_IF.u_sw_smc_test_status_if); uvm_config_db#(virtual sw_logger_if)::set( null, "*.env", "sw_logger_vif", `SIM_SRAM_IF.u_sw_logger_if); + uvm_config_db#(virtual sw_logger_if)::set( + null, "*.env", "sw_smc_logger_vif", `SIM_SMC_SRAM_IF.u_sw_smc_logger_if); // AST supply interface. uvm_config_db#(virtual ast_supply_if)::set( @@ -334,6 +382,16 @@ .system_base_addr (top_matcha_pkg::TOP_MATCHA_RAM_RET_AON_BASE_ADDR)); `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamRet0], `RAM_RET_MEM_HIER) + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for SMC_RAM", UVM_MEDIUM) + m_mem_bkdr_util[Smc_ram] = new( + .name ("mem_bkdr_util[Smc_ram]"), + .path (`DV_STRINGIFY(`SMC_RAM_HIER)), + .depth ($size(`SMC_RAM_HIER)), + .n_bits($bits(`SMC_RAM_HIER)), + .err_detection_scheme(mem_bkdr_util_pkg::ErrDetectionNone), + .system_base_addr (top_matcha_pkg::TOP_MATCHA_RAM_SMC_BASE_ADDR)); + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Smc_ram], `SMC_RAM_HIER) + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for ROM", UVM_MEDIUM) m_mem_bkdr_util[Rom] = new( .name ("mem_bkdr_util[Rom]"),
diff --git a/rules/matcha.bzl b/rules/matcha.bzl index 71a430d..87b4594 100644 --- a/rules/matcha.bzl +++ b/rules/matcha.bzl
@@ -38,6 +38,11 @@ "smc": "//sw/device/lib/arch:smc_sim_verilator", } +DV_CORE_TARGETS = { + "secure_core": "@lowrisc_opentitan//sw/device/lib/arch:sim_dv", + "smc": "//sw/device/lib/arch:smc_sim_dv", +} + NEXUS_CORE_TARGETS = { "secure_core": "//sw/device/lib/arch:sc_fpga_nexus", "smc": "//sw/device/lib/arch:smc_fpga_nexus", @@ -50,7 +55,7 @@ def device_deps(core): per_device_deps = { "sim_verilator": [VERILATOR_CORE_TARGETS.get(core)], - "sim_dv": ["@lowrisc_opentitan//sw/device/lib/arch:sim_dv"], + "sim_dv": [DV_CORE_TARGETS.get(core)], "fpga_nexus": [NEXUS_CORE_TARGETS.get(core)], } return per_device_deps
diff --git a/sw/device/lib/arch/BUILD b/sw/device/lib/arch/BUILD index 172ae85..373534e 100644 --- a/sw/device/lib/arch/BUILD +++ b/sw/device/lib/arch/BUILD
@@ -11,6 +11,14 @@ ) cc_library( + name = "smc_sim_dv", + srcs = ["device_smc_sim_dv.c"], + deps = [ + ":device", + ], +) + +cc_library( name = "smc_sim_verilator", srcs = ["device_smc_sim_verilator.c"], deps = [
diff --git a/sw/device/lib/arch/device_smc_sim_dv.c b/sw/device/lib/arch/device_smc_sim_dv.c new file mode 100644 index 0000000..ef7c4ac --- /dev/null +++ b/sw/device/lib/arch/device_smc_sim_dv.c
@@ -0,0 +1,49 @@ +// Copyright 2022 Google LLC. +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include <assert.h> +#include <stdbool.h> + +#include "sw/device/lib/arch/device.h" + +/** + * @file + * @brief Device-specific symbol definitions for the DV device. + */ + +const device_type_t kDeviceType = kDeviceSimDV; + +const uint64_t kClockFreqCpuMhz = 100; + +const uint64_t kClockFreqCpuHz = kClockFreqCpuMhz * 1000 * 1000; + +uint64_t to_cpu_cycles(uint64_t usec) { return usec * kClockFreqCpuMhz; } + +const uint64_t kClockFreqHiSpeedPeripheralHz = 96 * 1000 * 1000; // 96MHz + +const uint64_t kClockFreqPeripheralHz = 24 * 1000 * 1000; // 24MHz + +const uint64_t kClockFreqUsbHz = 48 * 1000 * 1000; // 48MHz + +const uint64_t kClockFreqAonHz = 200 * 1000; // 200kHz + +const uint64_t kUartBaudrate = 1 * 1000 * 1000; // 1Mbps + +const uint32_t kUartNCOValue = + CALCULATE_UART_NCO(kUartBaudrate, kClockFreqPeripheralHz); + +const uint32_t kUartTxFifoCpuCycles = + CALCULATE_UART_TX_FIFO_CPU_CYCLES(kUartBaudrate, kClockFreqCpuHz); + +const uint32_t kAstCheckPollCpuCycles = + CALCULATE_AST_CHECK_POLL_CPU_CYCLES(kClockFreqCpuHz); + +const uintptr_t kDeviceTestStatusAddress = 0x54030080; + +const uintptr_t kDeviceLogBypassUartAddress = 0x54030084; + +const bool kJitterEnabled = false; + +void device_fpga_version_print(void) {}