I2S Cleanup - Removed innacurate content from dv files. Reference history for original content. - Documentation updated from template text to accurate description of I2S - Added ASSERT missing and ASSERT_KNOWN to i2s.sv Change-Id: Ia482fe2798a8b073a90e8a1fb8ee5aabab43a155
diff --git a/hw/top_matcha/ip/i2s/data/i2s.hjson b/hw/top_matcha/ip/i2s/data/i2s.hjson index c24f629..405e6c0 100644 --- a/hw/top_matcha/ip/i2s/data/i2s.hjson +++ b/hw/top_matcha/ip/i2s/data/i2s.hjson
@@ -55,12 +55,12 @@ } { bits: "24:18", name: "NCO_RX", - desc: "SCLK / BCLK Clock divide control TX. CLK_divided = clk_audio/(2*(2*NCO_RX))." + desc: "SCLK / BCLK Clock divide control TX. CLK_divided = clk_audio/(2*NCO_RX)." resval: "1" } { bits: "31:25", name: "NCO_TX", - desc: "SCLK / BCLK Clock divide control RX. CLK_divided = clk_audio/(2*(2*NCO_TX))." + desc: "SCLK / BCLK Clock divide control RX. CLK_divided = clk_audio/(2*NCO_TX)." resval: "1" } ]
diff --git a/hw/top_matcha/ip/i2s/doc/_index.md b/hw/top_matcha/ip/i2s/doc/_index.md index 57eff71..8bb20fd 100644 --- a/hw/top_matcha/ip/i2s/doc/_index.md +++ b/hw/top_matcha/ip/i2s/doc/_index.md
@@ -1,8 +1,7 @@ ---- -title: "I2S HWIP Technical Specification" ---- +# I2S HWIP Technical Specification -# Overview + +## Overview This document specifies I2S hardware IP functionality. This module conforms to the @@ -11,449 +10,216 @@ top level system. -## Features +### Features -- 2-pin full duplex external interface -- 8-bit data word, optional even or odd parity bit per byte +- Concurrent RX & TX supported +- 16-bit per channel sample data - 1 stop bit -- 32 x 8b RX buffer -- 32 x 8b TX buffer -- Programmable baud rate -- Interrupt for transmit empty, receive overflow, frame error, parity error, break error, receive - timeout +- 32 x 32b RX buffer (left channel: 31:16 right channel 15:0) +- 32 x 32b TX buffer (left channel: 31:16 right channel 15:0) +- Programmable clock divider +- Interrupt for transmit empty, transmit watermark, receive overflow, recive + watermark -## Description +### Description -The I2S module is a serial-to-parallel receive (RX) and parallel-to-serial -(TX) full duplex design intended to communicate to an outside device, typically -for basic terminal-style communication. It is programmed to run at a particular -baud rate and contains only a transmit and receive signal to the outside world, -i.e. no synchronizing clock. The programmable baud rate guarantees to be met up -to 1Mbps. +The I2S module is an audio RX and TX module. It +supports simultaneous audio RX and TX at 16bits per L/R channel. +Clock divide for RX and TX can be independently set. RX has a fixed 16 clock +cycle oversampling and TX has no oversampling. Both I2S RX and I2S TX +operate in host mode only. -## Compatibility +### Compatibility -The OpenTitan I2S is feature compatible to a specific implementation in [Chromium EC](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/chip/g/i2s.c). -Additional features such as parity have been added. +I2S has been tested to work with the following peripherals. +- RX: SPH0645LM4H mic using adafruit breakout board +- TX: MAX98357A amplifier using adafruit breakout board -# Theory of Operations +## Theory of Operation -## Block Diagram +### Block Diagram - + -## Hardware Interfaces +### Design Details -{{< incGenFromIpDesc "../data/i2s.hjson" "hwcfg" >}} +#### Serial interface (both directions) -## Design Details +The TX/RX serial lines are low when idle. While enabled RX and/or TX will +operate at their respective frequencies regardless of data provided until they +are disabled. There is no error checking on the data received in hardware. -### Serial interface (both directions) +#### Transmission -The TX/RX serial lines are high when idle. Data starts with a START bit (high -idle state deasserts, **1**-->**0**) followed by 8 data bits. The least -significant bit is sent first. If the parity feature is turned on then an odd or -even parity bit follows after the data bits. Finally a STOP (**1**) bit -completes one byte of data transfer. +A write to {{< regref "WDATA" >}} enqueues a data word into the 32 word deep write FIFO. The TX +module dequeues the word from the FIFO and shifts it bit by bit out to the I2S +TX pin on positive edges of the I2S clock. -{{< wavejson >}} -{ - signal: [ - { name: 'Baud Clock', wave: 'p............' }, - { name: 'tx', wave: '10333333331..', data: [ "lsb", "", "", "", "", "", "", "msb" ] }, - { name: 'Baud Clock', wave: 'p............' }, - { name: 'tx (w/ parity)', wave: '103333333341.', data: [ "lsb", "", "", "", "", "", "", "msb", "par" ] }, - ], - head: { - text: 'Serial Transmission Frame', - }, - foot: { - text: 'start bit ("0") at cycle -1, stop bit ("1") at cycle 8, or after parity bit', - tock: -2 - }, - foot: { - text: [ - 'tspan', - ['tspan', 'start bit '], - ['tspan', {class:'info h4'}, '0'], - ['tspan', ' at cycle -1, stop bit '], - ['tspan', {class:'info h4'}, '1'], - ['tspan', ' at cycle 8, or at cycle 9 after parity bit'], - ], - tock: -2, - } -} -{{< /wavejson >}} +If TX is not enabled, DATA written to the FIFO will be queued until TX is enabled. -### Transmission +When the FIFO is below watermark level, a TX FIFO water mark interrupt will be raised. +Watermark is interrupt is a level interrupt and will only be cleared once the condition is no longer met. -A write to {{< regref "WDATA" >}} enqueues a data byte into the 32 byte deep write FIFO, which -triggers the transmit module to start I2S TX serial data transfer. The TX -module dequeues the byte from the FIFO and shifts it bit by bit out to the I2S -TX pin on positive edges of the baud clock. - -If TX is not enabled, written DATA into FIFO will be stacked up and sent out -when TX is enabled. - -When the FIFO becomes empty as part of transmittion, a TX FIFO empty interrupt will be raised. -This is separate from the TX FIFO water mark interrupt. +Raising of the separate TX FIFO empty interrupt while TX is enabled indicates +an empty FIFO at which point TX will output all zeros. This condition is likely +to create audible artifacts if copying data into the FIFO doesn't keep up with +the TX rate and while streaming audio. -### Reception +#### Reception -The RX module oversamples the RX input pin at 16x the requested -baud clock. When the input is detected low the receiver will check -half a bit-time later (i.e. 8 cycles of the oversample clock) that the -line is still low before detecting the START bit. If the line has -returned high the glitch is ignored. After it detects the START bit, -the RX module samples at the center of each bit-time and gathers -incoming serial bits into a charcter buffer. If the STOP bit is -detected as high and the optional partity bit is correct the data byte -is pushed into a 32 byte deep RX FIFO. The data can be read out by -reading {{< regref "RDATA" >}} register. +When RX is enabled data is clocked in on falling edge of the I2S clock. +The data can be read out by reading {{< regref "RDATA" >}} register which returns the entire 32 bit sample +that includes left data (31:16) and right data (15:0) of the sample. -This behaviour of the receiver can be used to compute the approximate -baud clock frequency error that can be tolerated between the -transmitter at the other end of the cable and the receiver. The -initial sample point is aligned with the center of the START bit. The -receiver will then sample every 16 cycles of the 16 x baud clock, the -diagram below shows the number of ticks after the centering that each -bit is captured. Because of the frequency difference between the -transmiter and receiver the actual sample point will drift compared to -the ideal center of the bit. In order to correctly receive the STOP -bit it must be sampled between the "early" and "late" points shown -on the diagram, which are half a bit-time or 8 ticks of the 16x baud -clock before or after the center. If the transmitter is considered -"ideal" then the local clock must thus differ by no more than plus or -minus 8 ticks in 144 or aproximately +/- 5.5%. If parity is enabled -the stop bit will be a bit time later, so this becomes 8/160 or about -+/- 5%. +This IP is designed for a microphone that requires 64bit oversampling. That is a total of +64 clock cycles are required to receive one sample of audio data. For this I2S IP that is +32 bits including both left and right channel data. -{{< wavejson >}} -{ - signal: [ - { name: 'Sample', wave: '', node: '..P............', period: "2" }, - {}, - { name: 'rx', - wave: '1.0.3.3.3.3.3.3.3.3.1.0.3', - node: '...A................C.D..', - cdata: [ "idle", "start", "+16", "+32", "+48", "+64", "+80", - "+96", "+112", "+128", "+144", "next start" ] }, - ], - "edge" : ["P-|>A center", "P-|>C early", "P-|>D late"], - head: { - text: 'Receiver sampling window', - }, -} -{{< /wavejson >}} +#### Setting the I2S Frequency -In practice, the transmitter and receiver will both differ from the -ideal baud rate. Since the worst case difference for reception is 5%, -the i2s can be expected to work if both sides are within +/- 2.5% of -the ideal baud rate. +The I2S clock divider is set via the {{< regref "CTRL.NCO_RX" >}} or {{< regref "CTRL.NCO_TX" >}} +register fields for RX and TX respectively. This should be +set using the equation below, where `f_clkin` is the input audio clock frequency, and `f_sclk` is the desired rx or tx clock rate. Note sclk and bclk are +typically used interchangeably in I2S device documentation. -### Setting the baud rate +For RX -The baud rate is set by writing to the {{< regref "CTRL.NCO" >}} register field. This should be -set using the equation below, where `f_pclk` is the system clock frequency -provided to the I2S, and `f_baud` is the desired baud rate (in bits per second). +$$ f\_{sclk} = {f\_{clkin} \over { 2 \times NCO\_{RX}}} $$ -$$ NCO = 16 \times {{2^{$bits(NCO)} \times f\_{baud}} \over {f\_{pclk}}} $$ +For TX -The formula above depends on the NCO CSR width. -The logic creates a x16 tick when the NCO counter overflows. -So, the computed baud rate from NCO value is below. +$$ f\_{sclk} = {f\_{clkin} \over { 2 \times NCO\_{TX}}} $$ -$$ f\_{baud} = {{1 \over 16} \times {NCO \over {2^{$bits(NCO)}}} \times {f\_{pclk}}} $$ - -Note that the NCO result from the above formula can be a fraction but -the NCO register only accepts an integer value. This will create an -error if the baud rate is not divisible by the fixed clock frequency. As -discussed in the previous section the error rate between the receiver -and remote transmitter should be lower than `8 / 144` to latch a -correct character value when parity is not used and lower than `8 / -160` when parity is used. In the expectation that the device the other -side of the line behaves similarly, this requires each side have a -baud rate that is matched to within +/- 2.5% of the ideal baud -rate. The contribution to this error if NCO is rounded down to an -integer (which will make the actual baud rate always lower or equal to -the requested rate) can be computed from: - -$$ Error = {{(NCO - INT(NCO))} \over {NCO}} percent $$ - -In this case if the resulting value of NCO is greater than $$ {1 \over -0.025} = 40 $$ then this will always be less than the 2.5% error -target. - -For NCO less than 40 the error in baud rate may or may not be -acceptable and should be carefully checked and rounding to the nearest -integer may achieve better results. If the computed value is close to -an integer so that the error in the target range then the baud rate -can be supported, however if it is too far off an integer then the -baud rate cannot be supported. This check is needed when - -$$ {{baud} < {{40 * f\_{pclk}} \over {2^{$bits(NCO)+4}}}} \qquad OR \qquad -{{f\_{pclk}} > {{{2^{$bits(NCO)+4}} * {baud}} \over {40}}} $$ - -Using rounded frequencies and common baud rates, this implies that -care is needed for 9600 baud and below if the system clock is under -250MHz, with 4800 baud and below if the system clock is under 125MHz, -2400 baud and below if the system clock us under 63MHz, and 1200 baud -and below if the system clock is under 32MHz. - - -### Interrupts +#### Interrupts I2S module has a few interrupts including general data flow interrupts and unexpected event interrupts. -#### tx_watermark / rx_watermark -If the TX FIFO level becomes smaller than the TX water mark level (configurable via {{< regref "FIFO_CTRL.RXILVL" >}} and {{< regref "FIFO_CTRL.TXILVL" >}}), the `tx_watermark` interrupt is raised to inform SW. -If the RX FIFO level becomes greater than or equal to RX water mark level (configurable via {{< regref "FIFO_CTRL.RXILVL" >}} and {{< regref "FIFO_CTRL.TXILVL" >}}), the `rx_watermark` interrupt is raised to inform SW. +##### tx_watermark / rx_watermark +Note that the water mark interrupts remain asserted until the event is cleared by filling or emptying the FIFO beyond the interrupt level in the case of TX and RX watermarks respectively. -Note that the watermark interrupts are edge triggered events. -This means the interrupt only triggers when the condition transitions from untrue->true. -This is especially important in the tx_watermark case. -When the TX FIFO is empty, it by default satisifies all the watermark conditions. -In order for the interrupt to trigger then, it is required that software initiates a write burst that is greater than the programmed watermark value. +If the TX FIFO level becomes smaller than the TX water mark level (configurable via {{< regref "FIFO_CTRL.TXILVL" >}}), the `tx_watermark` interrupt is raised to inform SW. +If the RX FIFO level becomes greater than or equal to RX water mark level (configurable via {{< regref "FIFO_CTRL.RXILVL" >}}), the `rx_watermark` interrupt is raised to inform SW. -For example, assume TX watermark is programmed to be less than 4 bytes, and software programs one byte at a time, waits for it to finish transmitting, before supplying the next byte. -Under these conditions, the TX watermark interrupt will never trigger because the size of the FIFO never exceeds the watermark level. - - -#### tx_empty +##### tx_empty If TX FIFO becomes empty as part of transmit, the interrupt `tx_empty` is asserted. The transmitted contents may be garbage at this point as old FIFO contents will likely be transmitted. -#### rx_overflow +##### rx_overflow If RX FIFO receives an additional write request when its FIFO is full, -the interrupt `rx_overflow` is asserted and the character is dropped. +the interrupt `rx_overflow` is asserted and the sample is dropped. In +most circumstances this condition is undesireable as it will distort the audio. -#### rx_break_err -The `rx_break_err` interrupt is triggered if a break condition has -been detected. A break condition is defined as the RX pin being -continuously low for more than a programmable number of -character-times (via {{< regref "CTRL.RXBLVL" >}}, either 2, 4, 8, or 16). A -character time is 10 bit-times if parity is disabled (START + 8 data + -STOP) or 11 bit-times if parity is enabled (START + 8 data + parity + -STOP). If the I2S is connected to an external connector this would -typically indicate the cable has been disconnected (or there is a -break in the wire). If the I2S is connected to another part on the -same board it would typically indicate the other part has reset or -rebooted. (If the open connector or resetting peer part causes the RX -input to not be actively driven, then a pulldown resistor is needed to -ensure a break and a pullup resistor will ensure the line looks idle -and no break is generated.) Note that only one interrupt is generated -per break -- the line must return high for at least half a bit-time -before an additional break interrupt is generated. The current break -status can be read from the {{< regref "STATUS.BREAK" >}} bit. If STATUS.BREAK is set -but {{< regref "INTR_STATE.BREAK" >}} is clear then the line break has already caused -an interrupt that has been cleared but the line break is still going -on. If {{< regref "STATUS.BREAK" >}} is clear but {{< regref "INTR_STATE.BREAK" >}} is set then -there has been a line break for which software has not cleared the -interrupt but the line is now back to normal. +## Programmers Guide -#### rx_frame_err -The `rx_frame_err` interrupt is triggered if the RX module receives the `START` -bit (**0**) and a series of data bits but did not detect the `STOP` bit -(**1**). This can happen because of noise affecting the line or if the -transmitter clock is fast or slow compared to the receiver. In a real frame -error the stop bit will be present just at an incorrect time so the line will -continue to signal both high and low. The start of a line break (described -above) matches a frame error with all data bits zero and one frame error -interrupt will be raised. If the line stays zero until the break error occurs, -the frame error will be set at every char-time. Frame errors will continue to -be reported after a break error. - -{{< wavejson >}} -{ - signal: [ - { name: 'Baud Clock', wave: 'p............' }, - { name: 'rx', wave: '10333333330..', data: [ "lsb", "", "", "", "", "", "", "msb" ] }, - {}, - { name: 'intr_rx_frame_err', wave: '0..........1.'}, - ], - head: { - text: 'Serial Receive with Framing Error', - }, - foot: { - text: [ - 'tspan', - ['tspan', 'start bit '], - ['tspan', {class:'info h4'}, '0'], - ['tspan', ' at cycle -1, stop bit '], - ['tspan', {class:'error h4'}, '1'], - ['tspan', ' missing at cycle 8'], - ], - tock: -2, - } -} -{{< /wavejson >}} - -The effects of the line being low for certain periods are summarized -in the table: - -|Line low (bit-times) | Frame Err? | Break? | Comment | -|---------------------|------------|--------|---------| -|<10 | If STOP=0 | No | Normal operation | -|10 (with parity) | No | No | Normal zero data with STOP=1 | -|10 (no parity) | Yes | No | Frame error since STOP=0 | -|11 - RXBLVL*char | Yes | No | Break less than detect level | -|\>RXBLVL*char | Yes | Once | Frame error signalled at every char-time, break at RXBLVL char-times| - -#### rx_timeout -The `rx_timeout` interrupt is triggered when the RX FIFO has data sitting in it -without software reading it for a programmable number of bit times (using the -baud rate clock as reference, programmable via {{< regref "TIMEOUT_CTRL" >}}). This is used to -alert software that it has data still waiting in the FIFO that has not been -handled yet. The timeout counter is reset whenever the FIFO depth is changed or -an `rx_timeout` event occurs. If the RX FIFO is full and new character is -received, it won't reset the timeout value. The software is responsible for -keeping the RX FIFO in the level below the watermark. The actual timeout time -can vary based on the reset of the timeout timer and the start of the -transaction. For instance, if the software resets the timeout timer by reading a -character from the RX FIFO and right after it there is a baud clock tick and the -start of a new RX transaction from the host, the timeout time is reduced by 1 -and half baud clock periods. - -#### rx_partity_err -The `rx_parity_err` interrupt is triggered if parity is enabled and -the RX parity bit does not match the expected polarity as programmed -in {{< regref "CTRL.PARITY_ODD" >}}. - -# Programmers Guide - -## Initialization +### Initialization The following code snippet demonstrates initializing the I2S to a programmable -baud rate, clearing the RX and TX FIFO, setting up the FIFOs for interrupt -levels, and enabling some interrupts. The NCO register controls the baud rate, -and should be set using the equation below, where `f_pclk` is the fixed clock -frequency and `f_baud` is the baud rate in bits per second. The I2S uses the -primary clock `clk_i` as a clock source. +frequency, clearing the RX and TX FIFO, setting up the FIFOs for interrupt +levels, and enabling some interrupts. The NCO_RX or NCO_TX register controls the +RX or TX frequencies respectively, and should be set using the equation below, +where `f_clkin` is the fixed audio clock frequency and `f_sclk` is the desired +RX or TX clock rate. The I2S uses the audio clock `clk_i` as a clock source. -$$ NCO = {{2^{20} * f\_{baud}} \over {f\_{pclk}}} $$ - -Note that the NCO result from the above formula can be a fraction but -the NCO register only accepts an integer value. See the the -[Reception](#reception) and [Setting the baud -rate](#setting-the-baud-rate) sections for more discussion of the -baud rate error target and when care is needed. - -Also note that because the baud rate is multiplied by 2^20 care is -needed not to overflow 32-bit registers. Baud rates can easily be more -than 12 bits. The code below is careful to force 64-bit -arithmetic. (Even if the complier is pre-computing constants there can -be unexpected overflow). +$$ f\_{sclk} = {f\_{clkin} \over { 2 \times NCO}} $$ ```cpp -#define CLK_FIXED_FREQ_HZ (50ULL * 1000 * 1000) +void i2s_init(unsigned int clkin, unsigned int sclk_tx, unsigned int sclk_rx) { + uint32_t i2s_ctrl_nco_tx = clkin / (2 * sclk_tx); + uint32_t i2s_ctrl_nco_rx = clkin / (2 * sclk_rx); -void i2s_init(unsigned int baud) { - // nco = 2^20 * baud / fclk. Assume NCO width is 16bit. - uint64_t i2s_ctrl_nco = ((uint64_t)baud << 20) / CLK_FIXED_FREQ_HZ; - REG32(I2S_CTRL(0)) = - ((i2s_ctrl_nco & I2S_CTRL_NCO_MASK) << I2S_CTRL_NCO_OFFSET) | - (1 << I2S_CTRL_TX) | - (1 << I2S_CTRL_RX); + // Configure clock dividers. + *I2S_CTRL_REG = + (i2s_ctrl_nco_rx & I2S_CTRL_NCO_RX_MASK) << I2S_CTRL_NCO_RX_OFFSET | + (i2s_ctrl_nco_tx & I2S_CTRL_NCO_TX_MASK) << I2S_CTRL_NCO_TX_OFFSET; - // clear FIFOs and set up to interrupt on any RX, half-full TX + // Configure the fifos with a watermark level of 4 entries, and reset them. *I2S_FIFO_CTRL_REG = - I2S_FIFO_CTRL_RXRST | // clear both FIFOs - I2S_FIFO_CTRL_TXRST | - (I2S_FIFO_CTRL_RXILVL_RXFULL_1 <<3) | // intr on RX 1 character - (I2S_FIFO_CTRL_TXILVL_TXFULL_16<<5) ; // intr on TX 16 character + (I2S_FIFO_CTRL_TXILVL_VALUE_TXLVL4 << I2S_FIFO_CTRL_TXILVL_MASK) << I2S_FIFO_CTRL_TXILVL_OFFSET | + (I2S_FIFO_CTRL_RXILVL_VALUE_RXLVL4 << I2S_FIFO_CTRL_RXILVL_MASK) << I2S_FIFO_CTRL_RXILVL_OFFSET | + (1 << I2S_FIFO_CTRL_TXRST_MASK) << I2S_FIFO_CTRL_TXRST_OFFSET | + (1 << I2S_FIFO_CTRL_RXRST_MASK) << I2S_FIFO_CTRL_RXRST_OFFSET; - // enable only RX, overflow, and error interrupts + // Enable TX and RX watermark interrupts. *I2S_INTR_ENABLE_REG = - I2S_INTR_ENABLE_RX_WATERMARK_MASK | - I2S_INTR_ENABLE_TX_OVERFLOW_MASK | - I2S_INTR_ENABLE_RX_OVERFLOW_MASK | - I2S_INTR_ENABLE_RX_FRAME_ERR_MASK | - I2S_INTR_ENABLE_RX_PARITY_ERR_MASK; - - // at the processor level, the I2S interrupts should also be enabled + (1 << I2S_INTR_ENABLE_TX_WATERMARK_BIT) | (1 << I2S_INTR_ENABLE_RX_WATERMARK_BIT); } ``` -## Common Examples +### Common Examples -The following code shows the steps to transmit a string of characters. +The following code shows the steps to transmit an audio sample. ```cpp int i2s_tx_rdy() { - return ((*I2S_FIFO_STATUS_REG & I2S_FIFO_STATUS_TXLVL_MASK) == 32) ? 0 : 1; + return ((*I2S_STATUS_REG & I2S_STATUS_TXFULL_BIT)) ? 0 : 1; } -void i2s_send_char(char val) { +void i2s_send_sample(int16_t left, int16_t right) { + int32_t val = ((left << 16) & 0xFFFF0000) | (right & 0xFFFF); while(!i2s_tx_rdy()) {} *I2S_WDATA_REG = val; } - -void i2s_send_str(char *str) { - while(*str != '\0') { - i2s_send_char(*str++); -} ``` -Do the following to receive a character, with -1 returned if RX is empty. +Do the following to receive a sample, with -1 returned if RX is empty. ```cpp int i2s_rx_empty() { - return ((*I2S_FIFO_STATUS_REG & I2S_FIFO_STATUS_RXLVL_MASK) == - (0 << I2S_FIFO_STATUS_RXLVL_LSB)) ? 1 : 0; + return ((*I2S_STATUS_REG & (1 << I2S_STATUS_RXEMPTY_BIT)) == ? 1 : 0; } -int i2s_rcv_char() { +int i2s_rcv_sample() { if(i2s_rx_empty()) return -1; return *I2S_RDATA_REG; } ``` -## Interrupt Handling +### Interrupt Handling The code below shows one example of how to handle all I2S interrupts in one service routine. ```cpp void i2s_interrupt_routine() { - volatile uint32 intr_state = *I2S_INTR_STATE_REG; - uint32 intr_state_mask = 0; - char i2s_ch; - uint32 intr_enable_reg; + volatile uint32_t intr_state = *I2S_INTR_STATE_REG; + uint32_t intr_state_mask = 0; + uint32_t i2s_sample; + uint32_t intr_enable_reg; // Turn off Interrupt Enable intr_enable_reg = *I2S_INTR_ENABLE_REG; - *I2S_INTR_ENABLE_REG = intr_enable_reg & 0xFFFFFF00; // Clr bits 7:0 + *I2S_INTR_ENABLE_REG = intr_enable_reg & 0xFFFFFFF0; // Clr bits 3:0 - if (intr_state & I2S_INTR_STATE_RX_PARITY_ERR_MASK) { + if (intr_state & (1 << I2S_INTR_STATE_TX_WATERMARK_BIT)) { // Do something ... // Store Int mask - intr_state_mask |= I2S_INTR_STATE_RX_PARITY_ERR_MASK; + intr_state_mask |= (1 << I2S_INTR_STATE_TX_WATERMARK_BIT); } - - if (intr_state & I2S_INTR_STATE_RX_BREAK_ERR_MASK) { + if (intr_state & (1 << I2S_INTR_STATE_TX_EMPTY_BIT)) { // Do something ... // Store Int mask - intr_state_mask |= I2S_INTR_STATE_RX_BREAK_ERR_MASK; + intr_state_mask |= (1 << I2S_INTR_STATE_TX_EMPTY_BIT); + } + if (intr_state & (1 << I2S_INTR_STATE_RX_OVERFLOW_BIT)) { + // Do something ... + + // Store Int mask + intr_state_mask |= (1 << I2S_INTR_STATE_RX_OVERFLOW_BIT); } - // .. Frame Error - - // TX/RX Overflow Error - - // RX Int - if (intr_state & I2S_INTR_STATE_RX_WATERMARK_MASK) { + if (intr_state & (1 << I2S_INTR_STATE_RX_WATERMARK_MASK)) { while(1) { - i2s_ch = i2s_rcv_char(); - if (i2s_ch == 0xff) break; - i2s_buf.append(i2s_ch); + i2s_sample = i2s_rcv_sample(); + if (i2s_ch == 0xFFFFFFFF) break; + i2s_buf.append(i2s_sample); } // Store Int mask - intr_state_mask |= I2S_INTR_STATE_RX_WATERMARK_MASK; + intr_state_mask |= (1 << I2S_INTR_STATE_RX_WATERMARK_BIT); } // Clear Interrupt State @@ -463,26 +229,3 @@ *I2S_INTR_ENABLE_REG = intr_enable_reg; } ``` - -One use of the `rx_timeout` interrupt is when the {{< regref "FIFO_CTRL.RXILVL" >}} -is set greater than one, so an interrupt is only fired when the fifo -is full to a certain level. If the remote device sends fewer than the -watermark number of characters before stopping sending (for example it -is waiting an acknowledgement) then the usual `rx_watermark` interrupt -would not be raised. In this case an `rx_timeout` would generate an -interrupt that allows the host to read these additional characters. The -`rx_timeout` can be selected based on the worst latency experienced by a -character. The worst case latency experienced by a character will happen -if characters happen to arrive just slower than the timeout: the second -character arrives just before the timeout for the first (resetting the -timer), the third just before the timeout from the second etc. In this -case the host will eventually get a watermark interrupt, this will happen -`((RXILVL - 1)*timeout)` after the first character was received. - -## Device Interface Functions (DIFs) - -{{< dif_listing "sw/device/lib/dif/dif_i2s.h" >}} - -## Register Table - -{{< incGenFromIpDesc "../data/i2s.hjson" "registers" >}}
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diff --git a/hw/top_matcha/ip/i2s/doc/checklist.md b/hw/top_matcha/ip/i2s/doc/checklist.md index 534388d..8c91da8 100644 --- a/hw/top_matcha/ip/i2s/doc/checklist.md +++ b/hw/top_matcha/ip/i2s/doc/checklist.md
@@ -14,15 +14,15 @@ Type | Item | Resolution | Note/Collaterals --------------|--------------------------------|-------------|------------------ -Documentation | [SPEC_COMPLETE][] | Done | [I2S Spec](../) -Documentation | [CSR_DEFINED][] | Done | -RTL | [CLKRST_CONNECTED][] | Done | -RTL | [IP_TOP][] | Done | -RTL | [IP_INSTANTIABLE][] | Done | -RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A | -RTL | [FUNC_IMPLEMENTED][] | Done | -RTL | [ASSERT_KNOWN_ADDED][] | Done | -Code Quality | [LINT_SETUP][] | Done | +Documentation | [SPEC_COMPLETE][] | Not Started | [I2S Spec](../) +Documentation | [CSR_DEFINED][] | Not Started | +RTL | [CLKRST_CONNECTED][] | Not Started | +RTL | [IP_TOP][] | Not Started | +RTL | [IP_INSTANTIABLE][] | Not Started | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started | +RTL | [FUNC_IMPLEMENTED][] | Not Started | +RTL | [ASSERT_KNOWN_ADDED][] | Not Started | +Code Quality | [LINT_SETUP][] | - | [SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}} @@ -43,24 +43,24 @@ Type | Item | Resolution | Note/Collaterals --------------|---------------------------|-------------|------------------ -Documentation | [NEW_FEATURES][] | N/A | -Documentation | [BLOCK_DIAGRAM][] | N/A | -Documentation | [DOC_INTERFACE][] | Done | -Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. -Documentation | [MISSING_FUNC][] | N/A | -Documentation | [FEATURE_FROZEN][] | Done | -RTL | [FEATURE_COMPLETE][] | Done | -RTL | [PORT_FROZEN][] | Done | -RTL | [ARCHITECTURE_FROZEN][] | Done | -RTL | [REVIEW_TODO][] | Done | -RTL | [STYLE_X][] | Done | -RTL | [CDC_SYNCMACRO][] | N/A | -Code Quality | [LINT_PASS][] | Done | -Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. -Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. -Code Quality | [AREA_CHECK][] | Done | Area check done (on FPGA) -Code Quality | [TIMING_CHECK][] | Done | Fmax 50MHz on NexysVideo -Security | [SEC_CM_DOCUMENTED][] | N/A | +Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [BLOCK_DIAGRAM][] | Not Started | +Documentation | [DOC_INTERFACE][] | Not Started | +Documentation | [DOC_INTEGRATION_GUIDE][] | Not Started | +Documentation | [MISSING_FUNC][] | Not Started | +Documentation | [FEATURE_FROZEN][] | Not Started | +RTL | [FEATURE_COMPLETE][] | Not Started | +RTL | [PORT_FROZEN][] | Not Started | +RTL | [ARCHITECTURE_FROZEN][] | Not Started | +RTL | [REVIEW_TODO][] | Not Started | +RTL | [STYLE_X][] | Not Started | +RTL | [CDC_SYNCMACRO][] | Not Started | +Code Quality | [LINT_PASS][] | Not Started | +Code Quality | [CDC_SETUP][] | Not Started | +Code Quality | [RDC_SETUP][] | Not Started | +Code Quality | [AREA_CHECK][] | Not Started | +Code Quality | [TIMING_CHECK][] | Not Started | +Security | [SEC_CM_DOCUMENTED][] | Not Started | [NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}} [BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}} @@ -85,13 +85,13 @@ Type | Item | Resolution | Note/Collaterals --------------|------------------------------|-------------|------------------ -Security | [SEC_CM_ASSETS_LISTED][] | Done | -Security | [SEC_CM_IMPLEMENTED][] | Done | -Security | [SEC_CM_RND_CNST][] | N/A | -Security | [SEC_CM_NON_RESET_FLOPS][] | N/A | -Security | [SEC_CM_SHADOW_REGS][] | N/A | -Security | [SEC_CM_RTL_REVIEWED][] | N/A | -Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM. +Security | [SEC_CM_ASSETS_LISTED][] | Not Started | +Security | [SEC_CM_IMPLEMENTED][] | Not Started | +Security | [SEC_CM_RND_CNST][] | Not Started | +Security | [SEC_CM_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_CM_SHADOW_REGS][] | Not Started | +Security | [SEC_CM_RTL_REVIEWED][] | Not Started | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started | [SEC_CM_ASSETS_LISTED]: {{<relref "/doc/project/checklist.md#sec_cm_assets_listed" >}} [SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}} @@ -105,19 +105,19 @@ Type | Item | Resolution | Note/Collaterals --------------|-------------------------|-------------|------------------ -Documentation | [NEW_FEATURES_D3][] | N/A | -RTL | [TODO_COMPLETE][] | Done | -Code Quality | [LINT_COMPLETE][] | Done | -Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff -Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff -Review | [REVIEW_RTL][] | Done | -Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff -Review | [REVIEW_SW_CHANGE][] | Done | by awill@ -Review | [REVIEW_SW_ERRATA][] | Done | -Security | [SEC_NON_RESET_FLOPS][] | N/A | -Security | [SEC_SHADOW_REGS][] | N/A | -Review | Reviewer(s) | Done | eunchan@ jeoong@ weicai@ awill@ -Review | Signoff date | Done | 2022-06-16 +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Security | [SEC_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_SHADOW_REGS][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | [NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}} [TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}} @@ -135,28 +135,28 @@ Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ -Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [I2S DV document]({{<relref "dv/index.md" >}}) -Documentation | [TESTPLAN_COMPLETED][] | Done | [I2S Testplan]({{<relref "dv/index.md#testplan" >}}) -Testbench | [TB_TOP_CREATED][] | Done | -Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | -Testbench | [SIM_TB_ENV_CREATED][] | Done | -Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | -Testbench | [CSR_CHECK_GEN_AUTOMATED][] | waived | Revisit later. Tool setup in progress. -Testbench | [TB_GEN_AUTOMATED][] | N/A | -Tests | [SIM_SMOKE_TEST_PASSING][] | Done | -Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | -Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | -Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | -Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | Exception (implemented in local) -Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | Exception (implemented in local) -Regression | [FPV_REGRESSION_SETUP][] | N/A | -Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | -Code Quality | [TB_LINT_SETUP][] | Done | -Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Except for IP module -Review | [DESIGN_SPEC_REVIEWED][] | Done | -Review | [TESTPLAN_REVIEWED][] | Done | -Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug) -Review | [V2_CHECKLIST_SCOPED][] | Done | +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [I2S DV document]({{<relref "dv/index.md" >}}) +Documentation | [TESTPLAN_COMPLETED][] | Not Started | [I2S Testplan]({{<relref "dv/index.md#testplan" >}}) +Testbench | [TB_TOP_CREATED][] | Not Started | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | +Testbench | [SIM_TB_ENV_CREATED][] | Not Started | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | +Testbench | [TB_GEN_AUTOMATED][] | Not Started | +Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Code Quality | [TB_LINT_SETUP][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | +Review | [V2_CHECKLIST_SCOPED][] | Not Started | [DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}} [TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan_completed" >}} @@ -185,26 +185,26 @@ Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------------|-------------|------------------ -Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | N/A | -Documentation | [DV_DOC_COMPLETED][] | Done | +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | +Documentation | [DV_DOC_COMPLETED][] | Not Started | Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started | -Testbench | [ALL_INTERFACES_EXERCISED][] | Done | -Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | -Testbench | [SIM_TB_ENV_COMPLETED][] | Done | -Tests | [SIM_ALL_TESTS_PASSING][] | Done | -Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | -Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | -Tests | [SIM_FW_SIMULATED][] | N/A | -Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | -Coverage | [SIM_CODE_COVERAGE_V2][] | Done | -Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | -Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | -Coverage | [FPV_COI_COVERAGE_V2][] | N/A | -Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | -Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | -Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A | +Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | +Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | +Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | +Tests | [SIM_FW_SIMULATED][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | +Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | +Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | -Review | [V3_CHECKLIST_SCOPED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Not Started | [DESIGN_DELTAS_CAPTURED_V2]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v2" >}} [DV_DOC_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_completed" >}} @@ -247,21 +247,21 @@ Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------|-------------|------------------ -Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | N/A | -Tests | [X_PROP_ANALYSIS_COMPLETED][] | Waived | Revisit later. Tool setup in progress -Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | N/A | -Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Done | -Coverage | [SIM_CODE_COVERAGE_AT_100][] | Done |[common_cov_excl.el][], [i2s_cov_excl.el][] -Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Done | -Coverage | [FPV_CODE_COVERAGE_AT_100][] | N/A | -Coverage | [FPV_COI_COVERAGE_AT_100][] | N/A | -Code Quality | [ALL_TODOS_RESOLVED][] | Done | -Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Done | +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | Code Quality | [TB_LINT_COMPLETE][] | Not Started | -Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | N/A | -Issues | [NO_ISSUES_PENDING][] | Done | -Review | Reviewer(s) | Done | @eunchan @sjgitty @sriyerg -Review | Signoff date | Done | 2019-11-01 +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | [DESIGN_DELTAS_CAPTURED_V3]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v3" >}} [X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/project/checklist.md#x_prop_analysis_completed" >}} @@ -276,6 +276,3 @@ [TB_LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#tb_lint_complete" >}} [PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v3" >}} [NO_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_issues_pending" >}} - -[common_cov_excl.el]:https://github.com/lowRISC/opentitan/blob/master/hw/dv/tools/vcs/common_cov_excl.el -[i2s_cov_excl.el]: https://github.com/lowRISC/opentitan/blob/04bb36e0ae1430262b048d400102b0fed43377ac/hw/ip/i2s/dv/cov/i2s_cov_excl.el
diff --git a/hw/top_matcha/ip/i2s/doc/dv/index.md b/hw/top_matcha/ip/i2s/doc/dv/index.md index f4dbff3..2a7b4dc 100644 --- a/hw/top_matcha/ip/i2s/doc/dv/index.md +++ b/hw/top_matcha/ip/i2s/doc/dv/index.md
@@ -11,93 +11,6 @@ * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "hw" >}}) - * [HW development stages]({{< relref "doc/project/development_stages.md" >}}) -* [Simulation results](https://reports.opentitan.org/hw/ip/i2s/dv/latest/results.html) - -## Design features -For detailed information on I2S design features, please see the [I2S design specification]({{< relref ".." >}}). - -## Testbench architecture -I2S testbench has been constructed based on the -[CIP testbench architecture]({{< relref "hw/dv/sv/cip_lib/doc" >}}). - -### Block diagram - - -### Top level testbench -Top level testbench is located at `hw/ip/i2s/dv/tb/tb.sv`. It instantiates the I2S DUT module `hw/ip/i2s/rtl/i2s.sv`. -In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: -* [Clock and reset interface]({{< relref "hw/dv/sv/common_ifs" >}}) -* [TileLink host interface]({{< relref "hw/dv/sv/tl_agent/doc" >}}) -* I2S IOs -* Interrupts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})) - -### Common DV utility components -The following utilities provide generic helper tasks and functions to perform activities that are common across the project: -* [common_ifs]({{< relref "hw/dv/sv/common_ifs" >}}) -* [dv_utils_pkg]({{< relref "hw/dv/sv/dv_utils/doc" >}}) -* [csr_utils_pkg]({{< relref "hw/dv/sv/csr_utils/doc" >}}) - -### Global types & methods -All common types and methods defined at the package level can be found in -`i2s_env_pkg`. Some of them in use are: -```systemverilog -parameter uint I2S_FIFO_DEPTH = 32; -``` - -### TL_agent -I2S instantiates (already handled in CIP base env) [tl_agent]({{< relref "hw/dv/sv/tl_agent/doc" >}}) -which provides the ability to drive and independently monitor random traffic via -TL host interface into I2S device. - -### I2S agent -[I2S agent]({{< relref "hw/dv/sv/usb20_agent/doc" >}}) is used to drive and monitor I2S items, which also provides basic coverage on -data, parity, baud rate etc. -These baud rates are supported: 9600, 115200, 230400, 1Mbps(1048576), 2Mbps(2097152) - -### UVM RAL Model -The I2S RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/doc" >}}) FuseSoC generator script automatically when the simulation is at the build stage. - -It can be created manually by invoking [`regtool`]({{< relref "util/reggen/doc" >}}): - -### Stimulus strategy -#### Test sequences -All test sequences reside in `hw/ip/i2s/dv/env/seq_lib`. -The `i2s_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. -All test sequences are extended from `i2s_base_vseq`. -It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. -Some of the most commonly used tasks / functions are as follows: -* i2s_init: Configure i2s control and fifo related csr with random values -* send_tx_byte: Program one TX byte to enable DUT to send a TX byte to I2S interface -* send_rx_byte: Drive a RX byte to DUT through I2S interface - -#### Functional coverage -To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. -The following covergroups have been developed to prove that the test intent has been adequately met: -* common covergroup for interrupts `hw/dv/sv/cip_lib/cip_base_env_cov.sv`: Cover interrupt value, interrupt enable, intr_test, interrup pin -* i2s_cg in i2s_agent_cov `hw/dv/sv/i2s_agent/i2s_agent_cov.sv`: Cover direction, i2s data, en_parity, odd_parity and baud rate -* fifo_level_cg `hw/ip/i2s/dv/env/i2s_env_cov.sv`: Cover all fifo level with fifo reset for both TX and RX - -### Self-checking strategy -#### Scoreboard -The `i2s_scoreboard` is primarily used for end to end checking. -It creates the following analysis fifos to retrieve the data monitored by corresponding interface agents: -* tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provides transaction items at the end of address channel and - data channel respectively -* i2s_tx_fifo, i2s_rx_fifo: These 2 fifos provides I2S TX and RX item when its transfer completes - -#### Assertions -* TLUL assertions: The `tb/i2s_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance. -* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. - -## Building and running tests -We are using our in-house developed [regression tool]({{< relref "hw/dv/tools/doc" >}}) for building and running our tests and regressions. -Please take a look at the link for detailed information on the usage, capabilities, features and known issues. -Here's how to run a smoke test: -```console -$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/i2s/dv/i2s_sim_cfg.hjson -i i2s_smoke -``` - -## Testplan -{{< incGenFromIpDesc "../../data/i2s_testplan.hjson" "testplan" >}} +- I2S DV not yet implemented. File structure based off UART left as placeholder +- Reference file history for original content with all instances of uart +replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/cov/i2s_cov_excl.el b/hw/top_matcha/ip/i2s/dv/cov/i2s_cov_excl.el index b6d384c..d103b8b 100644 --- a/hw/top_matcha/ip/i2s/dv/cov/i2s_cov_excl.el +++ b/hw/top_matcha/ip/i2s/dv/cov/i2s_cov_excl.el
@@ -13,6 +13,9 @@ // See the License for the specific language governing permissions and // limitations under the License. +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s + // Coverage exclusion file for i2s ANNOTATION: "[UNR] default branch" CHECKSUM: "2856317324 3065048585"
diff --git a/hw/top_matcha/ip/i2s/dv/env/i2s_env.sv b/hw/top_matcha/ip/i2s/dv/env/i2s_env.sv index 5f8c5fa..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/i2s_env.sv +++ b/hw/top_matcha/ip/i2s/dv/env/i2s_env.sv
@@ -13,34 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_env extends cip_base_env #(.CFG_T (i2s_env_cfg), - .COV_T (i2s_env_cov), - .VIRTUAL_SEQUENCER_T (i2s_virtual_sequencer), - .SCOREBOARD_T (i2s_scoreboard)); - `uvm_component_utils(i2s_env) - - i2s_agent m_i2s_agent; - - `uvm_component_new - - function void build_phase(uvm_phase phase); - super.build_phase(phase); - - m_i2s_agent = i2s_agent::type_id::create("m_i2s_agent", this); - uvm_config_db#(i2s_agent_cfg)::set(this, "m_i2s_agent*", "cfg", cfg.m_i2s_agent_cfg); - cfg.m_i2s_agent_cfg.en_cov = cfg.en_cov; - endfunction - - function void connect_phase(uvm_phase phase); - super.connect_phase(phase); - if (cfg.en_scb) begin - m_i2s_agent.monitor.tx_analysis_port.connect(scoreboard.i2s_tx_fifo.analysis_export); - m_i2s_agent.monitor.rx_analysis_port.connect(scoreboard.i2s_rx_fifo.analysis_export); - end - if (cfg.m_i2s_agent_cfg.is_active) begin - virtual_sequencer.i2s_sequencer_h = m_i2s_agent.sequencer; - end - endfunction - -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/i2s_env_cfg.sv b/hw/top_matcha/ip/i2s/dv/env/i2s_env_cfg.sv index 947e3c6..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/i2s_env_cfg.sv +++ b/hw/top_matcha/ip/i2s/dv/env/i2s_env_cfg.sv
@@ -13,42 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_env_cfg extends cip_base_env_cfg #(.RAL_T(i2s_reg_block)); - - // ext component cfgs - rand i2s_agent_cfg m_i2s_agent_cfg; - // during break error, DUT will trigger additional frame/parity errors, which mon doesn't catch - // disable parity/frame check in this period - bit disable_scb_rx_parity_check; - bit disable_scb_rx_frame_check; - - `uvm_object_utils_begin(i2s_env_cfg) - `uvm_field_object(m_i2s_agent_cfg, UVM_DEFAULT) - `uvm_object_utils_end - - `uvm_object_new - - virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1); - list_of_alerts = i2s_env_pkg::LIST_OF_ALERTS; - super.initialize(csr_base_addr); - // create i2s agent config obj - m_i2s_agent_cfg = i2s_agent_cfg::type_id::create("m_i2s_agent_cfg"); - // set num_interrupts & num_alerts which will be used to create coverage and more - num_interrupts = ral.intr_state.get_n_used_bits(); - // only support 1 outstanding TL item - m_tl_agent_cfg.max_outstanding_req = 1; - endfunction - - // i2s doesn't have reset pin. When reset occurs/clears, - // need to call reset function in i2s_agent_cfg - virtual function void reset_asserted(); - super.reset_asserted(); - m_i2s_agent_cfg.reset_asserted(); - endfunction - - virtual function void reset_deasserted(); - super.reset_deasserted(); - m_i2s_agent_cfg.reset_deasserted(); - endfunction -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/i2s_env_cov.sv b/hw/top_matcha/ip/i2s/dv/env/i2s_env_cov.sv index 06aa882..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/i2s_env_cov.sv +++ b/hw/top_matcha/ip/i2s/dv/env/i2s_env_cov.sv
@@ -13,36 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_env_cov extends cip_base_env_cov #(.CFG_T(i2s_env_cfg)); - `uvm_component_utils(i2s_env_cov) - - covergroup fifo_level_cg with function sample(i2s_dir_e dir, int lvl, bit rst); - cp_dir: coverpoint dir; - cp_lvl: coverpoint lvl { - bins all_levels[] = {[0:I2S_FIFO_DEPTH]}; - } - cp_rst: coverpoint rst; - cross cp_dir, cp_lvl, cp_rst; - endgroup - - // Cover all combinations of 2 different clocks - covergroup baud_rate_w_core_clk_cg with function sample(baud_rate_e baud_rate, - int clk_freq); - cp_baud_rate: coverpoint baud_rate; - cp_clk_freq: coverpoint clk_freq { - bins freqs[] = {24, 25, 48, 50, 100}; - } - cross cp_baud_rate, cp_clk_freq { - ignore_bins unsupported = binsof(cp_baud_rate) intersect {BaudRate1p5Mbps} && - binsof(cp_clk_freq) intersect {24}; - } - endgroup - - function new(string name, uvm_component parent); - super.new(name, parent); - fifo_level_cg = new(); - baud_rate_w_core_clk_cg = new(); - endfunction : new - -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/i2s_env_pkg.sv b/hw/top_matcha/ip/i2s/dv/env/i2s_env_pkg.sv index b8984ea..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/i2s_env_pkg.sv +++ b/hw/top_matcha/ip/i2s/dv/env/i2s_env_pkg.sv
@@ -13,107 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -package i2s_env_pkg; - // dep packages - import uvm_pkg::*; - import top_pkg::*; - import dv_utils_pkg::*; - import csr_utils_pkg::*; - import tl_agent_pkg::*; - import i2s_agent_pkg::*; - import dv_lib_pkg::*; - import dv_base_reg_pkg::*; - import cip_base_pkg::*; - import i2s_ral_pkg::*; - - // macro includes - `include "uvm_macros.svh" - `include "dv_macros.svh" - - // local types - parameter uint I2S_FIFO_DEPTH = 32; - // alerts - parameter uint NUM_ALERTS = 1; - parameter string LIST_OF_ALERTS[] = {"fatal_fault"}; - - typedef enum int { - TxWatermark = 0, - RxWatermark = 1, - TxEmpty = 2, - RxOverflow = 3, - RxFrameErr = 4, - RxBreakErr = 5, - RxTimeout = 6, - RxParityErr = 7, - NumUartIntr = 8 - } i2s_intr_e; - - // get the number of bytes that triggers watermark interrupt - function automatic int get_watermark_bytes_by_level(int lvl, i2s_dir_e dir); - case(lvl) - 0: return dir == UartTx ? 2 : 1; - 1: return 4; - 2: return 8; - 3: return 16; - 4: return 30; - default: begin - `uvm_fatal("i2s_env_pkg::get_watermark_bytes_by_level", - $sformatf("invalid watermark level value - %0d", lvl)) - end - endcase - endfunction - - // get the number of bytes that triggers break interrupt - function automatic int get_break_bytes_by_level(int lvl); - case(lvl) - 0: return 2; - 1: return 4; - 2: return 8; - 3: return 16; - default: begin - `uvm_fatal("i2s_env_pkg::get_break_bytes_by_level", - $sformatf("invalid break level value - %0d", lvl)) - end - endcase - endfunction - - // nco = 16*(2 ** nco_width) * freq_baud / freq_core, and truncate the factional number - // if i2s baud rate is 1500_000 and IO is 24Mhz, NCO is 'h1_0000, which is over the NCO width - // use NCO = 'hffff for this case since the error is tolerable. Refer to #4263 - `define CALC_NCO(baud_rate, nco_width, clk_freq_mhz) \ - (baud_rate == BaudRate1p5Mbps && clk_freq_mhz == 24) ? 16'hffff : \ - (longint'(baud_rate) * (2**(nco_width+4))) / (clk_freq_mhz * 1000_000) - - // calculate the nco - function automatic int get_nco(baud_rate_e baud_rate, int clk_freq_mhz, int nco_width); - int nco; - nco = `CALC_NCO(baud_rate, nco_width, clk_freq_mhz); - if (nco >= (2 ** nco_width)) begin - `uvm_fatal("i2s_agent_pkg::get_nco", $sformatf( - {"nco (%0d) can't bigger than (2 ** %0d) - 1, it's only %0d bits ", - "baud_rate = %0d, clk_freq_mhz = %0d"}, - nco, nco_width, nco_width, baud_rate, clk_freq_mhz)) - end - return nco; - endfunction - - // TX finishes the item at the beginning of last cycle and update reg value - // in the last 2 cycles, need to avoid driving and checking - `define TX_IGNORED_PERIOD {1, 2} - // RX finishes the item at the middle of last cycle and update reg value - // in the last cycle, need to avoid driving and checking - `define RX_IGNORED_PERIOD {1} - - // package sources - `include "i2s_env_cfg.sv" - `include "i2s_env_cov.sv" - `include "i2s_virtual_sequencer.sv" - `include "i2s_scoreboard.sv" - `include "i2s_env.sv" - `include "i2s_vseq_list.sv" - - `undef CALC_NCO - `undef TX_IGNORED_PERIOD - `undef RX_IGNORED_PERIOD -endpackage +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/i2s_scoreboard.sv b/hw/top_matcha/ip/i2s/dv/env/i2s_scoreboard.sv index 7c02e88..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/i2s_scoreboard.sv +++ b/hw/top_matcha/ip/i2s/dv/env/i2s_scoreboard.sv
@@ -13,538 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_scoreboard extends cip_base_scoreboard #(.CFG_T(i2s_env_cfg), - .RAL_T(i2s_reg_block), - .COV_T(i2s_env_cov)); - `uvm_component_utils(i2s_scoreboard) - - virtual i2s_if i2s_vif; - - // local variables - local bit tx_enabled; - local bit rx_enabled; - local int i2s_tx_clk_pulses; - local int i2s_rx_clk_pulses; - - // expected values - local bit tx_full_exp, rx_full_exp, tx_empty_exp, rx_empty_exp, tx_idle_exp, rx_idle_exp; - local int txlvl_exp, rxlvl_exp; - local bit [NumUartIntr-1:0] intr_exp; - local bit [7:0] rdata_exp; - // store tx/rx_q at TL address phase - local int tx_q_size_at_addr_phase, rx_q_size_at_addr_phase; - local bit [NumUartIntr-1:0] intr_exp_at_addr_phase; - - // non sticky interrupts are edge-triggered - // set it when interrupt is triggered, clear it when interrupt condition is no longer true - local bit tx_watermark_triggered = 1; - local bit rx_watermark_triggered = 0; - - // TLM fifos to pick up the packets - uvm_tlm_analysis_fifo #(i2s_item) i2s_tx_fifo; - uvm_tlm_analysis_fifo #(i2s_item) i2s_rx_fifo; - - // local queues to hold incoming packets pending comparison - i2s_item tx_q[$]; - // when item is removed from fifo and being sent on I2S tx interface, store it in this queue - i2s_item tx_processing_item_q[$]; - i2s_item rx_q[$]; - - // it takes 3 cycles to move item from fifo to process, which delays reg status change - // and it also takes 3 cycles to trigger tx matermark interrupt - parameter uint NUM_CLK_DLY_TO_UPDATE_TX_WATERMARK = 3; - - `uvm_component_new - - function void build_phase(uvm_phase phase); - super.build_phase(phase); - i2s_tx_fifo = new("i2s_tx_fifo", this); - i2s_rx_fifo = new("i2s_rx_fifo", this); - endfunction - - function void connect_phase(uvm_phase phase); - super.connect_phase(phase); - i2s_vif = cfg.m_i2s_agent_cfg.vif; - endfunction - - task run_phase(uvm_phase phase); - super.run_phase(phase); - fork - process_i2s_tx_fifo(); - process_i2s_rx_fifo(); - join_none - endtask - - virtual task process_i2s_tx_fifo(); - i2s_item act_item, exp_item; - forever begin - i2s_tx_fifo.get(act_item); - - `uvm_info(`gfn, $sformatf("received i2s tx item:\n%0s", act_item.sprint()), UVM_HIGH) - `DV_CHECK_EQ(tx_processing_item_q.size(), 1) - exp_item = tx_processing_item_q.pop_front(); - // move item from fifo to process - if (tx_q.size > 0) begin - tx_processing_item_q.push_back(tx_q.pop_front()); - `uvm_info(`gfn, $sformatf("After drop one item, new tx_q size: %0d", tx_q.size), UVM_HIGH) - end - compare(act_item, exp_item, "TX"); - // after an item is sent, check to see if size dipped below watermark - predict_tx_watermark_intr(); - - if (tx_q.size() == 0 && tx_processing_item_q.size() == 0) begin - intr_exp[TxEmpty] = 1; - end - end - endtask - - virtual task process_i2s_rx_fifo(); - i2s_item item; - forever begin - i2s_rx_fifo.get(item); - `uvm_info(`gfn, $sformatf("received i2s rx item:\n%0s", item.sprint()), UVM_HIGH) - - if (rx_enabled) begin - bit parity = `GET_PARITY(item.data, ral.ctrl.parity_odd.get_mirrored_value()); - bit parity_err = ral.ctrl.parity_en.get_mirrored_value() && parity != item.parity; - - if (parity_err) begin - intr_exp[RxParityErr] = 1; - `uvm_info(`gfn, $sformatf("dropped i2s rx item due to partiy err:\n%0s", - item.sprint()), UVM_HIGH) - end - if (!item.stop_bit) begin - intr_exp[RxFrameErr] = 1; - `uvm_info(`gfn, $sformatf("dropped i2s rx item due to frame err:\n%0s", - item.sprint()), UVM_HIGH) - end - if (!parity_err && item.stop_bit == 1) begin // no parity/frame error - if (rx_q.size < I2S_FIFO_DEPTH) begin - rx_q.push_back(item); - predict_rx_watermark_intr(); - end - else begin - intr_exp[RxOverflow] = 1; - `uvm_info(`gfn, $sformatf("dropped i2s rx item due to overflow:\n%0s", - item.sprint()), UVM_HIGH) - end - end // no parity/frame error - end // if (rx_enabled) - end // forever - endtask - - // when interrupt is non-sticky, interrupt will be triggered once unless it exits interrupt - // condition - virtual function bit get_non_sticky_interrupt(bit cur_intr, bit new_intr, ref bit triggered); - bit final_intr = cur_intr || (new_intr & ~triggered); - if (!new_intr) triggered = 0; - else if (final_intr) triggered = 1; - - return final_intr; - endfunction - - virtual function void predict_tx_watermark_intr(uint tx_q_size = tx_q.size); - uint watermark = get_watermark_bytes_by_level(ral.fifo_ctrl.txilvl.get_mirrored_value(), - UartTx); - intr_exp[TxWatermark] = get_non_sticky_interrupt(.cur_intr(intr_exp[TxWatermark]), - .new_intr(tx_q_size < watermark), - .triggered(tx_watermark_triggered)); - endfunction - - virtual function void predict_rx_watermark_intr(uint rx_q_size = rx_q.size); - uint watermark = get_watermark_bytes_by_level(ral.fifo_ctrl.rxilvl.get_mirrored_value(), - UartRx); - intr_exp[RxWatermark] = get_non_sticky_interrupt( - .cur_intr(intr_exp[RxWatermark]), - .new_intr(rx_q_size >= watermark && rx_enabled), - .triggered(rx_watermark_triggered)); - endfunction - - // we don't model i2s cycle-acurrately, ignore checking when item is just/almost finished - function bit is_in_ignored_period(i2s_dir_e dir); - case (dir) - UartTx: return i2s_tx_clk_pulses inside `TX_IGNORED_PERIOD; - UartRx: return i2s_rx_clk_pulses inside `RX_IGNORED_PERIOD; - endcase - endfunction - - virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); - uvm_reg csr; - bit do_read_check = 1'b1; - bit write = item.is_write(); - uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); - - // if access was to a valid csr, get the csr handle - if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin - csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); - `DV_CHECK_NE_FATAL(csr, null) - end else begin - `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) - end - - if (channel == AddrChannel) begin - // if incoming access is a write to a valid csr, then make updates right away - if (write) begin - void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); - end - - // need to store i2s_tx/tx_clk_pulses earlier to predict reg value correctly - i2s_tx_clk_pulses = i2s_vif.i2s_tx_clk_pulses; - i2s_rx_clk_pulses = i2s_vif.i2s_rx_clk_pulses; - // save fifo level at address phase - tx_q_size_at_addr_phase = tx_q.size; - rx_q_size_at_addr_phase = rx_q.size; - end - - // process the csr req - // for write, update local variable and fifo at address phase - // for read, update predication at address phase and compare at data phase - case (csr.get_name()) - "ctrl": begin - if (write && channel == AddrChannel) begin - if (cfg.en_cov) begin - cov.baud_rate_w_core_clk_cg.sample(cfg.m_i2s_agent_cfg.baud_rate, cfg.clk_freq_mhz); - end - - tx_enabled = ral.ctrl.tx.get_mirrored_value(); - rx_enabled = ral.ctrl.rx.get_mirrored_value(); - - if ((tx_q.size > 0 || tx_processing_item_q.size > 0) && tx_enabled) begin - if (tx_q.size > 0 && tx_processing_item_q.size == 0) begin - tx_processing_item_q.push_back(tx_q.pop_front()); - fork begin - int loc_tx_q_size = tx_q.size(); - cfg.clk_rst_vif.wait_n_clks(NUM_CLK_DLY_TO_UPDATE_TX_WATERMARK); - predict_tx_watermark_intr(loc_tx_q_size); - end join_none - end - end - end - end - "wdata": begin - // if tx is enabled, push exp tx data to q - if (write && channel == AddrChannel) begin - i2s_item tx_item = i2s_item::type_id::create("tx_item"); - - tx_item.data = item.a_data; - if (tx_q.size() < I2S_FIFO_DEPTH) begin - tx_q.push_back(tx_item); - `uvm_info(`gfn, $sformatf("After push one item, tx_q size: %0d", tx_q.size), UVM_HIGH) - end else begin - `uvm_info(`gfn, $sformatf( - "Drop tx item: %0h, tx_q size: %0d, i2s_tx_clk_pulses: %0d", - csr.get_mirrored_value(), tx_q.size(), i2s_tx_clk_pulses), UVM_MEDIUM) - end - fork begin - int loc_tx_q_size = tx_q.size(); - // remove 1 when it's abort to be popped for transfer - if (tx_enabled && tx_processing_item_q.size == 0 && tx_q.size > 0) loc_tx_q_size--; - // use negedge to avoid race condition - cfg.clk_rst_vif.wait_n_clks(NUM_CLK_DLY_TO_UPDATE_TX_WATERMARK); - if (ral.ctrl.slpbk.get_mirrored_value()) begin - // if sys loopback is on, tx item isn't sent to i2s pin but rx fifo - i2s_item tx_item = tx_q.pop_front(); - if (rx_enabled && (rx_q.size < I2S_FIFO_DEPTH)) begin - rx_q.push_back(tx_item); - predict_rx_watermark_intr(); - end - end else if (tx_enabled && tx_processing_item_q.size == 0 && tx_q.size > 0) begin - tx_processing_item_q.push_back(tx_q.pop_front()); - end - predict_tx_watermark_intr(loc_tx_q_size); - end join_none - end // write && channel == AddrChannel - end - "fifo_ctrl": begin - if (write && channel == AddrChannel) begin - // these fields are WO - bit txrst_val = bit'(get_field_val(ral.fifo_ctrl.txrst, item.a_data)); - bit rxrst_val = bit'(get_field_val(ral.fifo_ctrl.rxrst, item.a_data)); - if (txrst_val) begin - if (tx_enabled && tx_q.size > 0 && tx_processing_item_q.size == 0) begin - // keep the 1st item in the queue, as it's being sent - tx_processing_item_q.push_back(tx_q.pop_front()); - end - tx_q.delete(); - void'(ral.fifo_ctrl.txrst.predict(.value(0), .kind(UVM_PREDICT_WRITE))); - if (cfg.en_cov) begin - cov.fifo_level_cg.sample(.dir(UartTx), - .lvl(ral.fifo_status.txlvl.get_mirrored_value()), - .rst(1)); - end - end - if (rxrst_val) begin - rx_q.delete(); - void'(ral.fifo_ctrl.rxrst.predict(.value(0), .kind(UVM_PREDICT_WRITE))); - if (cfg.en_cov) begin - cov.fifo_level_cg.sample(.dir(UartRx), - .lvl(ral.fifo_status.rxlvl.get_mirrored_value()), - .rst(1)); - end - end - // recalculate watermark when RXILVL/TXILVL is updated - predict_rx_watermark_intr(); - fork begin - int loc_tx_q_size = tx_q.size(); - if (txrst_val) cfg.clk_rst_vif.wait_n_clks(NUM_CLK_DLY_TO_UPDATE_TX_WATERMARK); - predict_tx_watermark_intr(loc_tx_q_size); - end join_none - end // write && channel == AddrChannel - end - "intr_test": begin - if (write && channel == AddrChannel) begin - bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); - intr_exp |= item.a_data; - if (cfg.en_cov) begin - foreach (intr_exp[i]) begin - cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_exp[i]); - end - end - end - end - "status": begin - if (!write) begin // read - case (channel) - AddrChannel: begin // predict at address phase - tx_full_exp = tx_q.size >= I2S_FIFO_DEPTH; - tx_empty_exp = tx_q.size == 0; - tx_idle_exp = tx_q.size == 0 && tx_processing_item_q.size == 0; - rx_full_exp = rx_q.size == I2S_FIFO_DEPTH; - rx_empty_exp = rx_q.size == 0; - rx_idle_exp = (i2s_rx_clk_pulses == 0) || !rx_enabled; - end - DataChannel: begin // check at data phase - int i2s_bits; - - do_read_check = 1'b0; - // don't check it in system loopback mode. Since no pin activity, hard to predict - // status value, check it in seq - if (ral.ctrl.slpbk.get_mirrored_value()) return; - - i2s_bits = 10 + ral.ctrl.parity_en.get_mirrored_value(); - - // ignore corner case when item is about to complete, also fifo is changing from - // full to not full and it's at ignored period - if (!(tx_enabled && tx_q_size_at_addr_phase == I2S_FIFO_DEPTH - && is_in_ignored_period(UartTx))) begin - `DV_CHECK_EQ(get_field_val(ral.status.txfull, item.d_data), tx_full_exp, $sformatf( - "check tx_full fail: tx_en = %0d, tx_q.size = %0d, i2s_tx_clk_pulses = %0d", - tx_enabled, tx_q_size_at_addr_phase, i2s_tx_clk_pulses)) - end - if (!(rx_enabled && is_in_ignored_period(UartRx) && - rx_q_size_at_addr_phase inside {I2S_FIFO_DEPTH - 1, I2S_FIFO_DEPTH})) begin - `DV_CHECK_EQ(get_field_val(ral.status.rxfull, item.d_data), rx_full_exp, $sformatf( - "check rx_full fail: rx_en = %0d, rx_q.size = %0d, i2s_rx_clk_pulses = %0d", - rx_enabled, rx_q_size_at_addr_phase, i2s_rx_clk_pulses)) - end - - // when tx_q.size = 1 and it's at last 2 cycles, can't predict if txempty is set - if (!(tx_enabled && tx_q_size_at_addr_phase inside {0, 1} - && is_in_ignored_period(UartTx))) begin - `DV_CHECK_EQ(get_field_val(ral.status.txempty, item.d_data), tx_empty_exp, - $sformatf("check tx_empty fail: i2s_tx_clk_pulses = %0d, tx_q.size = %0d", - i2s_tx_clk_pulses, tx_q_size_at_addr_phase)) - end - if (!(rx_q_size_at_addr_phase inside {0, 1} && is_in_ignored_period(UartRx))) begin - `DV_CHECK_EQ(get_field_val(ral.status.rxempty, item.d_data), rx_empty_exp, - $sformatf("check rx_empty fail: i2s_rx_clk_pulses = %0d, rx_q.size = %0d", - i2s_rx_clk_pulses, rx_q_size_at_addr_phase)) - end - - // don't check when it's last item at last 2 cycles - if (!(tx_q_size_at_addr_phase == 0 && is_in_ignored_period(UartTx))) begin - `DV_CHECK_EQ(get_field_val(ral.status.txidle, item.d_data), tx_idle_exp, $sformatf( - "check tx_idle fail: tx_en = %0d, tx_q.size = %0d, i2s_tx_clk_pulses = %0d", - tx_enabled, tx_q_size_at_addr_phase, i2s_tx_clk_pulses)) - end - // rx_idle_exp will be clear/set during START/STOP bit, - // but we don't use exactly same clk as DUT - // check rx_idle==1 when i2s_rx_clk_pulses>0, rx_idle==0 when i2s_rx_clk_pulses==0 - // ignore checking when i2s_rx_clk_pulses==1 or i2s_rx_clk_pulses==i2s_bits - if (!(i2s_rx_clk_pulses inside {1, i2s_bits}) || !rx_enabled) begin - `DV_CHECK_EQ(get_field_val(ral.status.rxidle, item.d_data), rx_idle_exp, $sformatf( - "check rx_idle fail: rx_en = %0d, i2s_rx_clk_pulses = %0d", - rx_enabled, i2s_rx_clk_pulses)) - end - end - endcase - end // if (!write) - end // status - "intr_state": begin - if (write && channel == AddrChannel) begin // write & address phase - bit[TL_DW-1:0] intr_wdata = item.a_data; - fork begin - bit [NumUartIntr-1:0] pre_intr = intr_exp; - // add 1 cycle delay to avoid race condition when fifo changing and interrupt clearing - // occur simultaneously - cfg.clk_rst_vif.wait_clks(1); - intr_exp &= ~intr_wdata; - end join_none - end else if (!write && channel == AddrChannel) begin // read & addr phase - intr_exp_at_addr_phase = intr_exp; - end else if (!write && channel == DataChannel) begin // read & data phase - i2s_intr_e intr; - bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); - do_read_check = 1'b0; - foreach (intr_exp[i]) begin - intr = i2s_intr_e'(i); // cast to enum to get interrupt name - if (cfg.en_cov) begin - cov.intr_cg.sample(intr, intr_en[intr], intr_exp[intr]); - cov.intr_pins_cg.sample(intr, cfg.intr_vif.pins[intr]); - end - // don't check it when it's in ignored period - if (intr inside {TxWatermark, TxEmpty}) begin // TX interrupts - if (is_in_ignored_period(UartTx)) continue; - end else begin // RX interrupts - // RxTimeout, RxBreakErr is checked in seq - if (intr inside {RxTimeout, RxBreakErr} || is_in_ignored_period(UartRx) || - (cfg.disable_scb_rx_parity_check && intr == RxParityErr) || - (cfg.disable_scb_rx_frame_check && intr == RxFrameErr) - ) begin - continue; - end - end - `DV_CHECK_EQ(item.d_data[i], intr_exp_at_addr_phase[i], - $sformatf("Interrupt: %0s", intr.name)); - `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & intr_exp[i]), - $sformatf("Interrupt_pin: %0s", intr.name)); - end - end // read & data phase - end - "rdata": begin - if (!write) begin // read only - // rdata is removed from fifo after addr phase - if (channel == AddrChannel) begin - if (rx_q.size() > 0) begin - i2s_item rx_q_item = rx_q.pop_front(); - rdata_exp = rx_q_item.data; - predict_rx_watermark_intr(); - end else begin - do_read_check = 1'b0; - `uvm_error(`gfn, "unexpected read when fifo is empty") - end // rx_q.size() == 0 - end else begin //DataChannel - void'(csr.predict(.value(rdata_exp), .kind(UVM_PREDICT_READ))); - end // channel == DataChannel - end // !write - end - "fifo_status": begin - if (!write) begin - case (channel) - AddrChannel: begin // predict at address phase - txlvl_exp = tx_q.size() > I2S_FIFO_DEPTH ? I2S_FIFO_DEPTH : tx_q.size(); - rxlvl_exp = rx_q.size(); - end - DataChannel: begin // check at data phase - bit [5:0] txlvl_act, rxlvl_act; - - void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); - txlvl_act = ral.fifo_status.txlvl.get_mirrored_value(); - rxlvl_act = ral.fifo_status.rxlvl.get_mirrored_value(); - - if (txlvl_act == txlvl_exp) begin - // match, do nothing - end else if (tx_enabled && is_in_ignored_period(UartTx) && - absolute(txlvl_act - txlvl_exp) == 1) begin - // allow +/-1 difference as txlvl is reduced when previous item is in stop phase - // match, do nothing - end else begin - `uvm_error(`gfn, $sformatf("txlvl mismatch exp: %0d (+/-1), act: %0d,\ - clk_pulses: %0d", txlvl_exp, txlvl_act, i2s_tx_clk_pulses)) - end - - if (rxlvl_act == rxlvl_exp) begin - // match, do nothing - end else if (rx_enabled && is_in_ignored_period(UartRx) - && absolute(rxlvl_act - rxlvl_exp) == 1) begin - // allow +/-1 difference as rxlvl is reduced when previous item is in stop phase - // match, do nothing - end else begin - `uvm_error(`gfn, $sformatf("rxlvl mismatch exp: %0d (+/-1), act: %0d,\ - clk_pulses: %0d", rxlvl_exp, rxlvl_act, i2s_rx_clk_pulses)) - end - do_read_check = 1'b0; - - if (cfg.en_cov) begin - cov.fifo_level_cg.sample(.dir(UartTx), .lvl(txlvl_act), .rst(0)); - cov.fifo_level_cg.sample(.dir(UartRx), .lvl(rxlvl_act), .rst(0)); - end - end - endcase - end - end - "val": begin - if (!write && channel == DataChannel) begin - // rx oversampled val, check in test - do_read_check = 1'b0; - end - end - "ovrd", "intr_enable", "timeout_ctrl", "alert_test": begin - // no special handling is needed - end - default: begin - `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) - end - endcase - - // On reads, if do_read_check, is set, then check mirrored_value against item.d_data - if (!write && channel == DataChannel) begin - if (do_read_check) begin - `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, - $sformatf("reg name: %0s", csr.get_full_name())) - end - void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); - end - endtask - - function void compare(i2s_item act, i2s_item exp, string dir = "TX"); - if (!act.compare(exp)) begin - `uvm_error(`gfn, $sformatf("%s item mismatch!\nexp:\n%0s\nobs:\n%0s", - dir, exp.sprint(), act.sprint())) - end - else begin - `uvm_info(`gfn, $sformatf("%s item match!\nexp:\n%0s\nobs:\n%0s", - dir, exp.sprint(), act.sprint()), UVM_HIGH) - end - endfunction - - virtual function void reset(string kind = "HARD"); - super.reset(kind); - // reset the ral model and local fifos and queues - i2s_tx_fifo.flush(); - i2s_rx_fifo.flush(); - tx_q.delete(); - tx_processing_item_q.delete(); - rx_q.delete(); - // reset local variables - i2s_tx_clk_pulses = 0; - i2s_rx_clk_pulses = 0; - tx_q_size_at_addr_phase = 0; - rx_q_size_at_addr_phase = 0; - tx_watermark_triggered = 1; - rx_watermark_triggered = 0; - tx_enabled = ral.ctrl.tx.get_reset(); - rx_enabled = ral.ctrl.rx.get_reset(); - tx_full_exp = ral.status.txfull.get_reset(); - rx_full_exp = ral.status.rxfull.get_reset(); - tx_empty_exp = ral.status.txempty.get_reset(); - rx_empty_exp = ral.status.rxempty.get_reset(); - tx_idle_exp = ral.status.txidle.get_reset(); - rx_idle_exp = ral.status.rxidle.get_reset(); - txlvl_exp = ral.fifo_status.txlvl.get_reset(); - rxlvl_exp = ral.fifo_status.rxlvl.get_reset(); - intr_exp = ral.intr_state.get_reset(); - rdata_exp = ral.rdata.get_reset(); - endfunction - - function void check_phase(uvm_phase phase); - super.check_phase(phase); - `DV_EOT_PRINT_TLM_FIFO_CONTENTS(i2s_item, i2s_tx_fifo) - `DV_EOT_PRINT_TLM_FIFO_CONTENTS(i2s_item, i2s_rx_fifo) - `DV_EOT_PRINT_Q_CONTENTS(i2s_item, tx_q) - `DV_EOT_PRINT_Q_CONTENTS(i2s_item, tx_processing_item_q) - `DV_EOT_PRINT_Q_CONTENTS(i2s_item, rx_q) - endfunction - -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/i2s_virtual_sequencer.sv b/hw/top_matcha/ip/i2s/dv/env/i2s_virtual_sequencer.sv index df9eaa2..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/i2s_virtual_sequencer.sv +++ b/hw/top_matcha/ip/i2s/dv/env/i2s_virtual_sequencer.sv
@@ -13,13 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_virtual_sequencer extends cip_base_virtual_sequencer #(.CFG_T(i2s_env_cfg), - .COV_T(i2s_env_cov)); - `uvm_component_utils(i2s_virtual_sequencer) - - i2s_sequencer i2s_sequencer_h; - - `uvm_component_new - -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_base_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_base_vseq.sv index 6bf41b7..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_base_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_base_vseq.sv
@@ -13,285 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_base_vseq extends cip_base_vseq #(.CFG_T (i2s_env_cfg), - .RAL_T (i2s_reg_block), - .COV_T (i2s_env_cov), - .VIRTUAL_SEQUENCER_T (i2s_virtual_sequencer)); - `uvm_object_utils(i2s_base_vseq) - - // variables for dut initialization - rand baud_rate_e baud_rate; // set baud rate - rand bit en_tx; // enable tx - rand bit en_rx; // enable rx - rand bit en_parity; // enable parity - rand bit odd_parity; // enable odd parity - rand bit en_noise_filter; // enable noise filter - - // glitch control - rand uint i2s_period_glitch_pct; - - // enable interrupts - rand bit [NumUartIntr-1:0] en_intr; - - // random delays to access fifo/intr, may be controlled in extended seq - rand uint dly_to_access_fifo; - - // various knobs to enable certain routines - bit do_interrupt = 1'b1; - - constraint i2s_period_glitch_pct_c { - i2s_period_glitch_pct inside {[0:10]}; - } - - constraint baud_rate_c { - // when the i2s frequency is very close to core freq, disable noise filter and glitch, - // otherwise, not enough timing margin to predict status correctly in scb - if (baud_rate == BaudRate1p5Mbps && p_sequencer.cfg.clk_freq_mhz < 48) { - en_noise_filter == 0; - i2s_period_glitch_pct == 0; - } - // constrain nco not over nco.get_n_bits - `CALC_NCO(baud_rate, p_sequencer.cfg.ral.ctrl.nco.get_n_bits(), - p_sequencer.cfg.clk_freq_mhz) < 2 ** p_sequencer.cfg.ral.ctrl.nco.get_n_bits(); - } - - constraint dly_to_access_fifo_c { - // i2s clk is slow, up to 2 ** 16 (65_536) slower than pclk - // 1_000_000 is about 1.5 * 65_536 - dly_to_access_fifo dist { - 0 :/ 1, - [1 :100] :/ 1, - [101 :10_000] :/ 8, - [10_001 :1_000_000] :/ 1 - }; - } - - `uvm_object_new - - virtual task dut_shutdown(); - super.dut_shutdown(); - // wait for tx and rx operations to complete - `uvm_info(`gfn, "waiting for idle", UVM_HIGH) - cfg.m_i2s_agent_cfg.vif.wait_for_idle(); - `uvm_info(`gfn, "done waiting for idle", UVM_HIGH) - endtask - - // setup basic i2s features - virtual task i2s_init(); - int nco = get_nco(baud_rate, cfg.clk_freq_mhz, ral.ctrl.nco.get_n_bits()); - - // we skip writting some CSRs at the last 1-2 i2s cycles, when baud rate is 1.5Mbps, i2s - // cycle is small, need to reduce the TL delay, so that the write doesn't happen at the - // ignore period - if (baud_rate == BaudRate1p5Mbps && p_sequencer.cfg.clk_freq_mhz < 48) begin - if (cfg.m_tl_agent_cfg.d_ready_delay_max > 5) cfg.m_tl_agent_cfg.d_ready_delay_max = 5; - end - - cfg.m_i2s_agent_cfg.set_i2s_period_glitch_pct(i2s_period_glitch_pct); - - // cfg i2s agent to set the baud rate & parity - cfg.m_i2s_agent_cfg.set_baud_rate(baud_rate); - cfg.m_i2s_agent_cfg.set_parity(en_parity, odd_parity); - ral.ctrl.tx.set(en_tx); - ral.ctrl.rx.set(en_rx); - ral.ctrl.nf.set(en_noise_filter); - ral.ctrl.parity_en.set(en_parity); - ral.ctrl.parity_odd.set(odd_parity); - if (do_interrupt) `DV_CHECK_RANDOMIZE_FATAL(ral.ctrl.rxblvl) - ral.ctrl.nco.set(nco); - csr_update(ral.ctrl); - - if (do_interrupt) begin - ral.intr_enable.set(en_intr); - csr_update(ral.intr_enable); - - // from spec - timeout value may be reduced by 1.5 clock periods at some corner cases - // need >= char time + 2, so that receiving next character can reset the counter - // before timer is expired - `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.timeout_ctrl.val, - value inside {[10 + en_parity + 2 : 100]};) - `DV_CHECK_RANDOMIZE_FATAL(ral.timeout_ctrl.en) - csr_update(ral.timeout_ctrl); - - `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.fifo_ctrl.rxilvl, - value <= 4;) - `DV_CHECK_RANDOMIZE_FATAL(ral.fifo_ctrl.txilvl) - csr_update(ral.fifo_ctrl); - end - endtask - - // clear fifos - virtual task clear_fifos(bit clear_tx_fifo, bit clear_rx_fifo); - ral.fifo_ctrl.rxrst.set(clear_rx_fifo); - ral.fifo_ctrl.txrst.set(clear_tx_fifo); - csr_update(ral.fifo_ctrl); - endtask - - // set i2s parity for the dut and the agent - virtual task set_parity(bit en_parity, bit odd_parity); - // cfg i2s dut - ral.ctrl.parity_en.set(en_parity); - ral.ctrl.parity_odd.set(odd_parity); - csr_update(ral.ctrl); - // cfg i2s agent - cfg.m_i2s_agent_cfg.set_parity(en_parity, odd_parity); - endtask - - // set i2s baud rate for the dut and the agent - virtual task set_baud_rate(baud_rate_e baud_rate); - int nco = get_nco(baud_rate, cfg.clk_freq_mhz, ral.ctrl.nco.get_n_bits()); - ral.ctrl.nco.set(nco); - csr_update(ral.ctrl); - // cfg i2s agent - cfg.m_i2s_agent_cfg.set_baud_rate(baud_rate); - endtask - - virtual task spinwait_txidle(); - if (ral.ctrl.tx.get_mirrored_value()) begin - // use a very big timeout as it takes long time to flush all the items - csr_spinwait(.ptr(ral.status.txidle), .exp_data(1'b1), .timeout_ns(40_000_000), - .spinwait_delay_ns($urandom_range(0, 1000))); - end - endtask - - virtual task spinwait_rxidle(); - if (ral.ctrl.rx.get_mirrored_value()) begin - csr_spinwait(.ptr(ral.status.rxidle), .exp_data(1'b1), - .spinwait_delay_ns($urandom_range(0, 1000))); - end - endtask - - // task to send a byte of data out of dut - virtual task send_tx_byte(byte data); - csr_wr(.ptr(ral.wdata), .value(data)); - endtask - - // task to send a byte of data into dut, can override it to test error cases - virtual task send_rx_byte(byte data); - drive_rx_error_byte(.parity_err(0), .frame_err(0), .data(data)); - endtask - - // drive rx byte with parity_err or frame_err, data is random - virtual task drive_rx_error_byte(bit parity_err, bit frame_err, byte data = $urandom); - i2s_seq send_rx_seq; - `uvm_create_on(send_rx_seq, p_sequencer.i2s_sequencer_h); - `DV_CHECK_RANDOMIZE_WITH_FATAL(send_rx_seq, - data == local::data; - parity_err == local::parity_err; - frame_err == local::frame_err; - ) - `uvm_send(send_rx_seq) - endtask : drive_rx_error_byte - - // task to check if byte received is what was sent by the agent - virtual task chk_rx_byte(logic [7:0] exp_data); - bit [TL_DW-1:0] rdata; - csr_rd(.ptr(ral.rdata), .value(rdata)); - // do check but only if rx is enabled - if (ral.ctrl.rx.get_mirrored_value()) begin - if (!cfg.under_reset) `DV_CHECK_EQ(rdata, exp_data) - end - endtask - - // task to read all the rx bytes - virtual task read_all_rx_bytes(); - bit [TL_DW-1:0] rdata, fifo_status; - - csr_rd(.ptr(ral.fifo_status), .value(fifo_status)); - repeat (get_field_val(ral.fifo_status.rxlvl, fifo_status)) begin - wait_ignored_period_and_read_rdata(rdata); - end - - csr_rd(.ptr(ral.fifo_status), .value(fifo_status)); - - `uvm_info(`gfn, "read_all_rx_bytes is done", UVM_HIGH) - endtask : read_all_rx_bytes - - // override this function to control RX fifo level - virtual task rand_read_rx_byte(uint weight_to_skip); - bit [TL_DW-1:0] rdata, fifo_status; - int rxlvl; - - randcase - 1: begin // read & check one byte - csr_rd(.ptr(ral.fifo_status), .value(fifo_status)); - rxlvl = get_field_val(ral.fifo_status.rxlvl, fifo_status); - if(rxlvl > 0) begin - wait_ignored_period_and_read_rdata(rdata); - end - end - 1: begin // read & check some bytes - csr_rd(.ptr(ral.fifo_status), .value(fifo_status)); - rxlvl = get_field_val(ral.fifo_status.rxlvl, fifo_status); - if(rxlvl > 0) begin - repeat ($urandom_range(1, rxlvl)) wait_ignored_period_and_read_rdata(rdata); - end - end - 1: begin // read & check all rx bytes - read_all_rx_bytes(); - end - weight_to_skip: begin - end - endcase - endtask : rand_read_rx_byte - - // read rx data from CSR rdata, but wait until it's not in igored period - virtual task wait_ignored_period_and_read_rdata(ref bit [TL_DW-1:0] rdata); - wait_when_in_ignored_period(.rx(1)); - csr_rd(.ptr(ral.rdata), .value(rdata)); - endtask - - // task to wait for all rx bytes to be sent - virtual task wait_for_all_tx_bytes(); - bit [TL_DW-1:0] fifo_status, status; - - if (ral.ctrl.tx.get_mirrored_value()) begin - do begin - if (cfg.under_reset) break; - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_fifo) - cfg.clk_rst_vif.wait_clks(dly_to_access_fifo); - csr_rd(.ptr(ral.fifo_status), .value(fifo_status)); - csr_rd(.ptr(ral.status), .value(status)); - end while (get_field_val(ral.fifo_status.txlvl, fifo_status) > 0 || - get_field_val(ral.status.txidle, status) == 0); - end - - `uvm_info(`gfn, "wait_for_all_tx_bytes is done", UVM_HIGH) - endtask : wait_for_all_tx_bytes - - // task to wait for tx fifo not full - virtual task wait_for_tx_fifo_not_full(); - bit [TL_DW-1:0] status; - - if (ral.ctrl.tx.get_mirrored_value()) begin - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_fifo) - csr_spinwait(.ptr(ral.status.txfull), .exp_data(1'b0), - .spinwait_delay_ns(dly_to_access_fifo)); - end - - `uvm_info(`gfn, "wait_for_tx_fifo_not_full is done", UVM_HIGH) - endtask : wait_for_tx_fifo_not_full - - // task to wait for rx fifo not full, will be overriden in overflow test - virtual task wait_for_rx_fifo_not_full(); - if (ral.ctrl.rx.get_mirrored_value()) begin - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_fifo) - csr_spinwait(.ptr(ral.status.rxfull), .exp_data(1'b0), - .spinwait_delay_ns(dly_to_access_fifo), - .timeout_ns(50_000_000)); // use longer timeout as i2s freq is low - end - `uvm_info(`gfn, "wait_for_rx_fifo_not_full is done", UVM_HIGH) - endtask : wait_for_rx_fifo_not_full - - // in some corner cases, we can't drive when the i2s item is almost done - // wait for this period to pass - virtual task wait_when_in_ignored_period(bit tx = 0, bit rx = 0); - wait (!( - (tx && cfg.m_i2s_agent_cfg.vif.i2s_tx_clk_pulses inside `TX_IGNORED_PERIOD) || - (rx && cfg.m_i2s_agent_cfg.vif.i2s_rx_clk_pulses inside `RX_IGNORED_PERIOD) - )); - `uvm_info(`gfn, "wait_when_in_ignored_period is done", UVM_HIGH) - endtask : wait_when_in_ignored_period - -endclass : i2s_base_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_common_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_common_vseq.sv index 1587d10..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_common_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_common_vseq.sv
@@ -13,17 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_common_vseq extends i2s_base_vseq; - `uvm_object_utils(i2s_common_vseq) - - constraint num_trans_c { - num_trans inside {[1:2]}; - } - `uvm_object_new - - virtual task body(); - run_common_vseq_wrapper(num_trans); - endtask : body - -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_full_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_full_vseq.sv index e5fdfd1..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_full_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_full_vseq.sv
@@ -13,51 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_fifo_full_vseq extends i2s_tx_rx_vseq; - `uvm_object_utils(i2s_fifo_full_vseq) - - constraint num_trans_c { - num_trans inside {[5:10]}; - } - - constraint num_tx_bytes_c { - num_tx_bytes dist { - [0:1] :/ 2, - [2:32] :/ 2, - [33:100] :/ 2 - }; - } - - constraint num_rx_bytes_c { - num_rx_bytes dist { - [0:1] :/ 2, - [2:32] :/ 2, - [33:100] :/ 2 - }; - } - - constraint dly_to_next_trans_c { - dly_to_next_trans dist { - 0 :/ 30, // more back2back transaction - [1:100] :/ 5, - [100:10000] :/ 2 - }; - } - - constraint wait_for_idle_c { - // fifo is 32 depth, wait/not_wait = 1/40, higher change to have fifo full - wait_for_idle dist { - 1 :/ 1, - 0 :/ 40 - }; - } - - constraint weight_to_skip_rx_read_c { - // 3: read, 50: skip - weight_to_skip_rx_read == 50; - } - - `uvm_object_new - -endclass : i2s_fifo_full_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_overflow_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_overflow_vseq.sv index e7e2c8e..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_overflow_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_overflow_vseq.sv
@@ -13,18 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_fifo_overflow_vseq extends i2s_fifo_full_vseq; - `uvm_object_utils(i2s_fifo_overflow_vseq) - - `uvm_object_new - - // don't wait for fifo not full - virtual task wait_for_tx_fifo_not_full(); - endtask : wait_for_tx_fifo_not_full - - // don't wait for fifo not full - virtual task wait_for_rx_fifo_not_full(); - endtask : wait_for_rx_fifo_not_full - -endclass : i2s_fifo_overflow_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_reset_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_reset_vseq.sv index 234c789..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_reset_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_fifo_reset_vseq.sv
@@ -13,46 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_fifo_reset_vseq extends i2s_fifo_overflow_vseq; - `uvm_object_utils(i2s_fifo_reset_vseq) - - `uvm_object_new - - virtual task process_remaining_data(); - bit do_clear_tx_fifo; - bit do_clear_rx_fifo; - - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(do_clear_tx_fifo, - do_clear_tx_fifo dist {0 :/ 1, 1 :/ 4};) - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(do_clear_rx_fifo, - do_clear_rx_fifo dist {0 :/ 1, 1 :/ 4};) - - fork - begin - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_fifo) - cfg.clk_rst_vif.wait_clks(dly_to_access_fifo); - // can't predict if the item is clear or not, when reset fifo at almost done period - wait_when_in_ignored_period(.tx(do_clear_tx_fifo), .rx(do_clear_rx_fifo)); - clear_fifos(.clear_tx_fifo(do_clear_tx_fifo), .clear_rx_fifo(do_clear_rx_fifo)); - end - begin - if (!do_clear_tx_fifo) begin - wait_for_all_tx_bytes(); - end else begin - spinwait_txidle(); - end - end - begin - if (!do_clear_rx_fifo) begin - read_all_rx_bytes(); - end else begin - spinwait_rxidle(); - end - end - join - - dut_shutdown(); - endtask : process_remaining_data - -endclass : i2s_fifo_reset_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_intr_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_intr_vseq.sv index 6861c6f..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_intr_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_intr_vseq.sv
@@ -13,320 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// simply trigger each interrupt one by one and check interrupt pin & reg in the seq -class i2s_intr_vseq extends i2s_base_vseq; - `uvm_object_utils(i2s_intr_vseq) - - constraint num_trans_c { - num_trans inside {[1:5]}; - } - - // make interrupt easy to predict - lower the freq so that there is enough time to read status - // and check - constraint baud_rate_extra_c { - baud_rate <= BaudRate230400; - } - - `uvm_object_new - - task body(); - i2s_intr_e i2s_intr; - // will inject parity/stop error in this case - cfg.m_i2s_agent_cfg.en_rx_checks = 0; - for (int i = 1; i <= num_trans; i++) begin - `DV_CHECK_RANDOMIZE_FATAL(this) - i2s_init(); - - repeat (NumUartIntr) begin - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(i2s_intr, - i2s_intr != NumUartIntr;) - `uvm_info(`gfn, $sformatf("\nTesting %0s", i2s_intr.name), UVM_LOW) - drive_and_check_one_intr(i2s_intr); - - // quickly clear all intr & fifo, make sure no leftover for next iteration - clear_fifos(.clear_tx_fifo(1), .clear_rx_fifo(1)); - // tx may have unfinished transaction - spinwait_txidle(); - dut_shutdown(); - csr_wr(.ptr(ral.intr_state), .value('hff)); - end - `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) - end - endtask : body - - task drive_and_check_one_intr(i2s_intr_e i2s_intr); - int tx_fifo_max_size; - uint bit_num_per_trans; - - // 1 start + 8 data + 1 parity (if enabled) + 1 stop - bit_num_per_trans = 10 + cfg.m_i2s_agent_cfg.en_parity; - - case (i2s_intr) - TxWatermark: begin - int level = ral.fifo_ctrl.txilvl.get_mirrored_value(); - int watermark_bytes = get_watermark_bytes_by_level(level, UartTx); - if (!en_tx) return; - // when tx is enabled, one extra item is in the data path - // when watermark_bytes==1, watermark interrupt is triggered before item is processed - if (en_tx && watermark_bytes > 1) watermark_bytes += 1; - drive_tx_bytes(.num_bytes(watermark_bytes - 1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - drive_tx_bytes(.num_bytes(1)); - // wait until it drops below watermark - csr_spinwait(.ptr(ral.fifo_status.txlvl), - .exp_data(get_watermark_bytes_by_level(level, UartTx)), - .compare_op(CompareOpLt)); - check_one_intr(.i2s_intr(i2s_intr), .exp(1)); - cfg.m_i2s_agent_cfg.vif.wait_for_tx_idle(); - // check interrupt is non-sticky - csr_wr(.ptr(ral.intr_state), .value(1 << i2s_intr)); - drive_tx_bytes(.num_bytes(watermark_bytes - 1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - cfg.m_i2s_agent_cfg.vif.wait_for_tx_idle(); - end - - RxWatermark: begin - int level = ral.fifo_ctrl.rxilvl.get_mirrored_value(); - int watermark_bytes = get_watermark_bytes_by_level(level, UartRx); - drive_rx_bytes(.num_bytes(watermark_bytes - 1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - drive_rx_bytes(.num_bytes(1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(en_rx)); - // check interrupt is non-sticky - csr_wr(.ptr(ral.intr_state), .value(1 << i2s_intr)); - drive_rx_bytes(.num_bytes(1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - end - - TxEmpty: begin - if (en_tx) begin - // when tx is enabled, one extra item is in the data path, total is I2S_FIFO_DEPTH + 1 - drive_tx_bytes(.num_bytes($urandom_range(1, I2S_FIFO_DEPTH + 1))); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - spinwait_txidle(); - check_one_intr(.i2s_intr(i2s_intr), .exp(1)); - // check interrupt is non-sticky - csr_wr(.ptr(ral.intr_state), .value(1 << i2s_intr)); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - end - end - - RxOverflow: begin - drive_rx_bytes(.num_bytes(I2S_FIFO_DEPTH)); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - drive_rx_bytes(.num_bytes(1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(en_rx)); - end - - RxFrameErr: begin - drive_rx_error_byte(.parity_err(0), .frame_err(1)); - check_one_intr(.i2s_intr(i2s_intr), .exp(en_rx)); - sync_up_rx_from_frame_err(bit_num_per_trans); - end - - // Follow this table from spec to verify RxBreakErr - // Line low(bit-times) Frame Err? Break? Comment - // <10 If STOP=0 No Normal operation - // 10 (with parity) No No Normal zero data with STOP=1 - // 10 (no parity) Yes No Frame error since STOP=0 - // 11 - RXBLVL*char Yes No Break less than detect level - // >RXBLVL*char Yes Once Frame signalled at every char-times, - // break at RXBLVL char-times - RxBreakErr: begin - bit [NumUartIntr-1:0] exp_intr_state; - int level = ral.ctrl.rxblvl.get_mirrored_value(); - int break_bytes = get_break_bytes_by_level(level); - - // drive one good rx char to reset DUT break cnt (allzero_cnt) - drive_rx_bytes(.num_bytes(1)); - // clear rx fifo and interrupts triggered by above driving - clear_fifos(.clear_tx_fifo(0), .clear_rx_fifo(1)); - csr_wr(.ptr(ral.intr_state), .value('hff)); - - fork - begin - drive_rx_all_0s(); - end - begin - // < 10 cycles 0s, expect no interrupt - wait_for_baud_clock_cycles(9); - // check interrupt reg & pin but not affect timing of driving i2s RX - nonblocking_check_all_intr(.exp(0), .do_clear(0)); - // 10th cycle - wait_for_baud_clock_cycles(1); - exp_intr_state[RxFrameErr] = ~en_parity & en_rx; - nonblocking_check_all_intr(.exp(exp_intr_state), .do_clear(0)); - // 11th cycle - wait_for_baud_clock_cycles(1); - exp_intr_state[RxParityErr] = en_parity & en_rx & `GET_PARITY(0, odd_parity); - exp_intr_state[RxFrameErr] = en_rx; - nonblocking_check_all_intr(.exp(exp_intr_state), .do_clear(1)); - end - join - - // disable parity & frame err check in scb, as mon can't handle line breaking - // check them in seq - cfg.disable_scb_rx_parity_check = 1; - cfg.disable_scb_rx_frame_check = 1; - - // from 11 to RXBLVL * char - 1 - if (break_bytes > 2) begin // avoid negetive value - wait_for_baud_clock_cycles(bit_num_per_trans * (break_bytes - 1) - 11); - nonblocking_check_all_intr(.exp(exp_intr_state), .do_clear(1)); - end - // RXBLVL * char - wait_for_baud_clock_cycles(bit_num_per_trans); - exp_intr_state[RxBreakErr] = en_rx; - nonblocking_check_all_intr(.exp(exp_intr_state), .do_clear(1)); - - // RXBLVL * char * 2 - wait_for_baud_clock_cycles(bit_num_per_trans * break_bytes); - // check break intr doesn't occur again - exp_intr_state[RxBreakErr] = 0; - nonblocking_check_all_intr(.exp(exp_intr_state)); - - sync_up_rx_from_frame_err(bit_num_per_trans); - cfg.disable_scb_rx_parity_check = 0; - cfg.disable_scb_rx_frame_check = 0; - end - - RxTimeout: begin - bit [TL_DW-1:0] rdata; - uint num_bytes = $urandom_range(1, I2S_FIFO_DEPTH); - uint timeout_val = ral.timeout_ctrl.val.get_mirrored_value(); - bit en_timeout = ral.timeout_ctrl.en.get_mirrored_value(); - drive_rx_bytes(num_bytes); - // wait for timeout_val-1 cycles, timeout shouldn't occur - // wait for one more cycle, timeout occurs - // timeout event will repeat if SW only clears the interrupt but not read the fifo - wait_for_baud_clock_cycles(timeout_val - 1); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - wait_for_baud_clock_cycles(2); - check_one_intr(.i2s_intr(i2s_intr), .exp(en_rx & en_timeout)); - csr_wr(.ptr(ral.intr_state), .value('hff)); - // expect timeout again since no fifo activity - wait_for_baud_clock_cycles(timeout_val); - check_one_intr(.i2s_intr(i2s_intr), .exp(en_rx & en_timeout)); - csr_wr(.ptr(ral.intr_state), .value('hff)); - - if (!en_rx) return; - // reset timeout timer by issuing a rdata read - csr_rd(.ptr(ral.rdata), .value(rdata)); - - // wait for timeout_val-2 cycles (it's about to timeout) and then - // read or drive one i2s RX item to reset timeout cnt. More fifo read, less fifo write - // Repeat until fifo is empty. Timeout should never occur - forever begin - bit [TL_DW-1:0] status; - bit rxfull; - randcase - 3: begin // read RX fifo - csr_rd(.ptr(ral.status), .value(status)); - if (get_field_val(ral.status.rxempty, status)) begin - break; - end - // use -2 to have higher tolerance to avoid timeout - wait_for_baud_clock_cycles(timeout_val - 2); - csr_rd(.ptr(ral.rdata), .value(rdata)); - end - 1: begin // drive one RX item (fifo write) - // use -2 to have higher tolerance to avoid timeout - int cycles = timeout_val - bit_num_per_trans - 2; - wait_for_baud_clock_cycles(cycles > 0 ? cycles : 0); - csr_rd(.ptr(ral.status.rxfull), .value(rxfull)); - // it won't reset timeout timer if receiving a rx item when fifo is full - if (rxfull) csr_rd(.ptr(ral.rdata), .value(rdata)); - else drive_rx_bytes(.num_bytes(1)); - end - endcase - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - end - - // no rx timeout if no data in rx fifo - wait_for_baud_clock_cycles(timeout_val * 2); - check_one_intr(.i2s_intr(i2s_intr), .exp(0)); - end - - RxParityErr: begin - drive_rx_error_byte(.parity_err(1), .frame_err(0)); - check_one_intr(.i2s_intr(i2s_intr), .exp(en_rx & en_parity)); - end - endcase - endtask : drive_and_check_one_intr - - // only check one interrupt state and pin - task check_one_intr(i2s_intr_e i2s_intr, bit exp); - bit [TL_DW-1:0] act_intr_state; - bit exp_pin; - - csr_rd(.ptr(ral.intr_state), .value(act_intr_state)); - if (!cfg.under_reset) `DV_CHECK_EQ(act_intr_state[i2s_intr], exp) - exp_pin = exp & en_intr[i2s_intr]; - if (!cfg.under_reset) `DV_CHECK_EQ(cfg.intr_vif.pins[i2s_intr], exp_pin, $sformatf( - "i2s_intr name/val: %0s/%0d, en_intr: %0h", i2s_intr.name, i2s_intr, en_intr)) - endtask : check_one_intr - - // check all interrupt state and pin - task check_all_intr(bit [NumUartIntr-1:0] exp, bit do_clear = 0); - bit [NumUartIntr-1:0] act_intr_state; - bit [NumUartIntr-1:0] exp_pin; - - csr_rd(.ptr(ral.intr_state), .value(act_intr_state)); - if (!cfg.under_reset) `DV_CHECK_EQ(act_intr_state, exp) - exp_pin = exp & en_intr; - if (!cfg.under_reset) `DV_CHECK_EQ(cfg.intr_vif.pins[NumUartIntr-1:0], exp_pin, $sformatf( - "i2s_intr val: %0h, en_intr: %0h", exp, en_intr)) - - if (do_clear) begin - csr_wr(.ptr(ral.intr_state), .value(exp)); - end - endtask : check_all_intr - - task nonblocking_check_all_intr(bit [NumUartIntr-1:0] exp, bit do_clear = 0); - fork - check_all_intr(exp, do_clear); - join_none - endtask : nonblocking_check_all_intr - - // drive all 0s to verify break error - task drive_rx_all_0s(); - i2s_seq send_rx_seq; - `uvm_create_on(send_rx_seq, p_sequencer.i2s_sequencer_h); - `DV_CHECK_RANDOMIZE_WITH_FATAL(send_rx_seq, - data == 0; - parity == 0; - frame_err == 1; - ) - `uvm_send(send_rx_seq) - endtask - - // drive all 1s for sync up with design after frame error - task sync_up_rx_from_frame_err(uint cycles_per_trans); - cfg.m_i2s_agent_cfg.vif.i2s_rx = 1; - wait_for_baud_clock_cycles(cycles_per_trans); - endtask - - task wait_for_baud_clock_cycles(uint cycles); - #(cfg.m_i2s_agent_cfg.vif.i2s_clk_period_ns * cycles); - endtask - - task drive_tx_bytes(int num_bytes); - repeat (num_bytes) begin - byte tx_byte; - `DV_CHECK_STD_RANDOMIZE_FATAL(tx_byte) - send_tx_byte(.data(tx_byte)); - end - // wait for 1 cycle to allow interrupt triggered - cfg.clk_rst_vif.wait_clks(1); - endtask : drive_tx_bytes - - task drive_rx_bytes(int num_bytes); - repeat (num_bytes) begin - byte rx_byte; - `DV_CHECK_STD_RANDOMIZE_FATAL(rx_byte) - send_rx_byte(.data(rx_byte)); - end - endtask : drive_rx_bytes - -endclass : i2s_intr_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_long_xfer_wo_dly_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_long_xfer_wo_dly_vseq.sv index dd710cf..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_long_xfer_wo_dly_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_long_xfer_wo_dly_vseq.sv
@@ -13,52 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// transfer large amount of data without delay between each transaction, in order to test clock -// offset is not over 1/4 of the period -class i2s_long_xfer_wo_dly_vseq extends i2s_fifo_full_vseq; - `uvm_object_utils(i2s_long_xfer_wo_dly_vseq) - - `uvm_object_new - - constraint num_tx_bytes_c { - num_tx_bytes dist { - [101:1000] :/ 1 - }; - } - - constraint num_rx_bytes_c { - num_rx_bytes dist { - [101:1000] :/ 1 - }; - } - - constraint dly_to_access_fifo_c { - dly_to_access_fifo < 100; - } - - constraint dly_to_next_trans_c { - dly_to_next_trans == 0; - } - - constraint wait_for_idle_c { - wait_for_idle == 0; - } - - constraint weight_to_skip_rx_read_c { - // 3: read, 1: skip - weight_to_skip_rx_read == 1; - } - - constraint dly_to_rx_read_c { - dly_to_rx_read < 100; - } - - // lower the freq as design freq isn't precise and agent has precise freq. - // The delay in this test is small and running too fast will accumulate the diff, which may lead - // to mis-aligned cycle - constraint baud_rate_extra_c { - baud_rate > BaudRate230400; - } - -endclass : i2s_long_xfer_wo_dly_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_loopback_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_loopback_vseq.sv index 4a44506..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_loopback_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_loopback_vseq.sv
@@ -13,106 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// test 2 kinds of loopback -// 1. system loopback, any outgoing bits to TX are received through RX -// 2. Line loopback, incoming bits (on RX) are forwarded to TX -class i2s_loopback_vseq extends i2s_tx_rx_vseq; - `uvm_object_utils(i2s_loopback_vseq) - - constraint en_tx_c { - en_tx == 1; - } - - constraint en_rx_c { - en_rx == 1; - } - - `uvm_object_new - - task body(); - for (int i = 1; i <= num_trans; i++) begin - `DV_CHECK_RANDOMIZE_FATAL(this) - i2s_init(); - - randcase - 1: drive_system_loopback(); - 1: drive_line_loopback(); - endcase - `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) - end - endtask : body - - virtual task drive_system_loopback(); - byte unsigned tx_byte; - `uvm_info(`gfn, "Start system loopback", UVM_HIGH) - - ral.ctrl.slpbk.set(1); - csr_update(ral.ctrl); - - `DV_CHECK_STD_RANDOMIZE_FATAL(tx_byte) - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_next_trans) - cfg.clk_rst_vif.wait_clks(dly_to_next_trans); - - // drive tx data and expect to receive it rx fifo - send_tx_byte(tx_byte); - // wait for loopback to complete - spinwait_txidle(); - spinwait_rxidle(); - csr_rd_check(.ptr(ral.rdata), .compare_value(tx_byte)); - // clear TxEmpty interrupt - csr_wr(.ptr(ral.intr_state), .value(1 << TxEmpty)); - // check status is default value - csr_rd_check(.ptr(ral.status), .compare_value(ral.status.get_reset())); - - ral.ctrl.slpbk.set(0); - csr_update(ral.ctrl); - endtask - - // when line loopback is enabled, RX data will be wired to TX w/o any synchronizer - // drive RX with random data and random delay, and check same value at TX - virtual task drive_line_loopback(); - `uvm_info(`gfn, "Start line loopback", UVM_HIGH) - - ral.ctrl.llpbk.set(1); - csr_update(ral.ctrl); - - // disable monitor, as it can't handle these random data - cfg.m_i2s_agent_cfg.en_tx_monitor = 0; - cfg.m_i2s_agent_cfg.en_rx_monitor = 0; - fork - begin // isolation_fork - fork - // drive RX with random data and random delay - repeat ($urandom_range(100, 1000)) begin - cfg.m_i2s_agent_cfg.vif.i2s_rx = $urandom_range(0, 1); - `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(dly_to_next_trans, - dly_to_next_trans > 0;) - #(dly_to_next_trans * 1ns); - end - // RX has same value as TX without any synchronizer in the data path - forever begin - @(cfg.m_i2s_agent_cfg.vif.i2s_tx || cfg.m_i2s_agent_cfg.vif.i2s_rx); - #1ps; // avoid race condition - if (!cfg.under_reset) begin - `DV_CHECK_EQ(cfg.m_i2s_agent_cfg.vif.i2s_tx, cfg.m_i2s_agent_cfg.vif.i2s_rx) - end - end - join_any - disable fork; - end // isolation_fork - join - - cfg.m_i2s_agent_cfg.vif.i2s_rx = 1; // back to default value - cfg.m_i2s_agent_cfg.en_tx_monitor = 1; - cfg.m_i2s_agent_cfg.en_rx_monitor = 1; - - // if noise filter is on, need 3 cycles delay to make sure internal rx value is 1, otherwise, - // unexpected value (0) may be propagated to RX datapath - if (en_noise_filter) cfg.clk_rst_vif.wait_clks(3); - - ral.ctrl.llpbk.set(0); - csr_update(ral.ctrl); - endtask - -endclass : i2s_loopback_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_noise_filter_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_noise_filter_vseq.sv index d336b65..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_noise_filter_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_noise_filter_vseq.sv
@@ -13,33 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// test small glitch that can be filtered when noise filter is enabled -class i2s_noise_filter_vseq extends i2s_tx_rx_vseq; - `uvm_object_utils(i2s_noise_filter_vseq) - - `uvm_object_new - - // add noise before sending rx byte - // check rxidle should be high after adding noise - virtual task send_rx_byte(byte data); - int core_clk_period_ps = cfg.clk_rst_vif.clk_period_ps; - - // monitor doesn't filter glitch less than 1 core cycle, need to disable it - cfg.m_i2s_agent_cfg.en_rx_monitor = 0; - if (en_noise_filter) begin - // i2s clk is much slower than core clk - // need large number to check if the glitch has no impact to i2s - repeat ($urandom_range(1, 10_000)) begin - cfg.m_i2s_agent_cfg.vif.drive_i2s_rx_glitch( - .max_glitch_ps(core_clk_period_ps), // 1 core clk - // need 3 core clk cycles to push out the glitch before next drive - .stable_ps_after_glitch(core_clk_period_ps * 3)); - end - csr_rd_check(.ptr(ral.status.rxidle), .compare_value(1)); - end - cfg.m_i2s_agent_cfg.en_rx_monitor = 1; - super.send_rx_byte(data); - endtask - -endclass : i2s_noise_filter_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_perf_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_perf_vseq.sv index 6229299..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_perf_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_perf_vseq.sv
@@ -13,35 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// performance test with 0 delay to access fifo, less delay to access interrupts -class i2s_perf_vseq extends i2s_fifo_full_vseq; - `uvm_object_utils(i2s_perf_vseq) - - `uvm_object_new - - constraint dly_to_access_fifo_c { - dly_to_access_fifo == 0; - } - - constraint dly_to_next_trans_c { - dly_to_next_trans == 0; - } - - constraint wait_for_idle_c { - wait_for_idle == 0; - } - - constraint dly_to_rx_read_c { - dly_to_rx_read == 0; - } - - constraint dly_to_access_intr_c { - dly_to_access_intr dist { - 0 :/ 5, - [1 :100] :/ 4, - [101 :10_000] :/ 1 - }; - } - -endclass : i2s_perf_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_oversample_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_oversample_vseq.sv index 3e9ad0f..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_oversample_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_oversample_vseq.sv
@@ -13,94 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// test reg i2s.VAL -// 1. find the center of oversampled clock -// 2. drive 16 bits on RX pin based on 16x oversampled clk, then check the reg value -class i2s_rx_oversample_vseq extends i2s_tx_rx_vseq; - `uvm_object_utils(i2s_rx_oversample_vseq) - uint num_bits; - - constraint en_rx_c { - en_rx == 1; - } - - // lower the freq so that there is enough time to read rx oversmapled value and check - constraint baud_rate_extra_c { - baud_rate <= BaudRate115200; - } - - `uvm_object_new - - task body(); - int i2s_xfer_bits; - num_bits = ral.val.rx.get_n_bits(); - cfg.m_i2s_agent_cfg.en_rx_monitor = 0; - for (int i = 1; i <= num_trans; i++) begin - `DV_CHECK_RANDOMIZE_FATAL(this) - i2s_init(); - - find_oversampled_clk_center(); - // don't use big number here, the way TB measures cycle isn't the same as DUT - // need to re-sync again after cerntain cycles - repeat ($urandom_range(1, 3)) begin - drive_rx_oversampled_val(); - end - `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) - end - - // wait for a full i2s transaction time to flush out the remaining rx transaction - i2s_xfer_bits = NUM_I2S_XFER_BITS_WO_PARITY + cfg.m_i2s_agent_cfg.en_parity; - #(cfg.m_i2s_agent_cfg.vif.i2s_clk_period_ns * i2s_xfer_bits); - - cfg.m_i2s_agent_cfg.en_rx_monitor = 1; - clear_fifos(.clear_rx_fifo(1), .clear_tx_fifo(0)); - // clear all interrupts as the driving of rx value in seq may trigger interrupt that scb - // doesn't expect - csr_wr(.ptr(ral.intr_state), .value('1)); - endtask : body - - // find the center of oversampled clk - // 1. drive all 0s/1s and keep reading reg for the pattern w/o any delay - // 2. after find the pattern, flip pattern[0] and keep polling reg for 0x0001/0xfffe - // 3. after find it, then we know we're close to the edge of the clk - // 4. Delay 0.4 * oversample_clk_period to get to the center of the clk - virtual task find_oversampled_clk_center(); - bit [TL_DW-1:0] pattern; - `uvm_info(`gfn, "finding oversample clk center", UVM_HIGH) - randcase - 1: pattern = (1 << num_bits) - 1; // all 1s - 1: pattern = 0; - endcase - // drive constant value and find all 1s/0s pattern - cfg.m_i2s_agent_cfg.vif.i2s_rx = pattern[0]; - csr_spinwait(.ptr(ral.val.rx), .exp_data(pattern)); - // flip a bit and find the clk edge - pattern[0] = ~pattern[0]; - cfg.m_i2s_agent_cfg.vif.i2s_rx = pattern[0]; - csr_spinwait(.ptr(ral.val.rx), .exp_data(pattern)); - // move 0.4 clk into the clk center, as previous reg read consume some cycles - #(get_oversampled_baud_clk_period_ns() *1ns * 0.4); - endtask - - // drive N bits on RX pin based on oversampled clk, then check the reg value - virtual task drive_rx_oversampled_val(); - bit [TL_DW-1:0] data; - `uvm_info(`gfn, "Start drive rx oversampled value", UVM_HIGH) - - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(data, - data <= ((1 << num_bits) - 1);) - // Most recent bit is bit 0 - for (int i = num_bits - 1; i >= 0; i--) begin - cfg.m_i2s_agent_cfg.vif.i2s_rx = data[i]; - #(get_oversampled_baud_clk_period_ns() * 1ns); - end - cfg.m_i2s_agent_cfg.vif.i2s_rx = 1; // back to default value - csr_rd_check(.ptr(ral.val.rx), .compare_value(data), .blocking(0)); - endtask - - virtual function real get_oversampled_baud_clk_period_ns(); - return cfg.m_i2s_agent_cfg.vif.i2s_clk_period_ns / num_bits; - endfunction - -endclass : i2s_rx_oversample_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_parity_err_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_parity_err_vseq.sv index 612eb9f..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_parity_err_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_parity_err_vseq.sv
@@ -13,20 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// test rx parity error -// cross rx/tx watermark/overflow with parity error in this seq -class i2s_rx_parity_err_vseq extends i2s_fifo_overflow_vseq; - `uvm_object_utils(i2s_rx_parity_err_vseq) - - `uvm_object_new - - virtual task send_rx_byte(byte data); - cfg.m_i2s_agent_cfg.en_rx_checks = 0; // disable rx checks in monitor - drive_rx_error_byte(.parity_err($urandom_range(0, 9) == 0), // 10% - .frame_err (0), - .data (data)); - cfg.m_i2s_agent_cfg.en_rx_checks = 1; - endtask - -endclass : i2s_rx_parity_err_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_start_bit_filter_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_start_bit_filter_vseq.sv index 756e2ff..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_start_bit_filter_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_rx_start_bit_filter_vseq.sv
@@ -13,39 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// test start bit length < 0.5 will be ignored -class i2s_rx_start_bit_filter_vseq extends i2s_smoke_vseq; - `uvm_object_utils(i2s_rx_start_bit_filter_vseq) - - `uvm_object_new - - // add noise before sending rx byte - // when start bit is detected, design will check it again after 0.5 i2s clock - // if it's not low, consider it as glitch and ignore it - virtual task send_rx_byte(byte data); - uint64 i2s_clk_period_ps = cfg.m_i2s_agent_cfg.vif.i2s_clk_period_ns * 1000; - - // monitor doesn't have start bit filter, need to disable it while driving filtered start bit - cfg.m_i2s_agent_cfg.en_rx_monitor = 0; - repeat ($urandom_range(10, 100)) begin - // drive 0 for up to 0.4 i2s clk and 1 for 0.8 clk. Design samples start bit (0) first, - // after 0.5 clk, design will sample 1 and should drop this start bit - // need stable period > 0.5, use 0.8 clk to have enough margin - cfg.m_i2s_agent_cfg.vif.drive_i2s_rx_glitch( - .max_glitch_ps(i2s_clk_period_ps * 0.4), - .stable_ps_after_glitch(i2s_clk_period_ps * 0.8)); - end - cfg.m_i2s_agent_cfg.en_rx_monitor = 1; - csr_rd_check(.ptr(ral.status.rxidle), .compare_value(1)); - - super.send_rx_byte(data); - endtask - - // disable txidle check as it will also read rxidle which value is unexpected - // during the long start bit glitch, rxidle will be low. mon/scb isn't supported - // for checking this glitch for rxidle. Check it in test instead. - virtual task spinwait_txidle(); - endtask - -endclass : i2s_rx_start_bit_filter_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_smoke_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_smoke_vseq.sv index 140d838..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_smoke_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_smoke_vseq.sv
@@ -13,69 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// simple smoke test with both en_tx and en_rx on -// process one item at a time for TX and RX -class i2s_smoke_vseq extends i2s_tx_rx_vseq; - `uvm_object_utils(i2s_smoke_vseq) - - constraint num_trans_c { - num_trans == 2; - } - - constraint num_tx_bytes_c { - num_tx_bytes == 5; - } - - constraint num_rx_bytes_c { - num_rx_bytes == 5; - } - - constraint en_tx_c { - en_tx == 1; - } - - constraint en_rx_c { - en_rx == 1; - } - - `uvm_object_new - - task body(); - do_interrupt = 0; - super.body(); - endtask : body - - // program one Tx item in register and wait for it to complete before send another one - virtual task process_tx(); - for (int j = 1; j <= num_tx_bytes; j++) begin - byte tx_byte; - - wait_when_in_ignored_period(.tx(1)); - `DV_CHECK_STD_RANDOMIZE_FATAL(tx_byte) - send_tx_byte(tx_byte); - // if no delay in TL-UL trans, DUT takes 1 more cycle to update status reg - cfg.clk_rst_vif.wait_clks(1); - spinwait_txidle(); - end - endtask : process_tx - - // sequencally send one Rx byte, then immediately read from register and check it - virtual task process_rx(); - for (int j = 1; j <= num_rx_bytes; j++) begin - byte rx_byte; - bit [TL_DW-1:0] dut_rdata; - - `DV_CHECK_STD_RANDOMIZE_FATAL(rx_byte) - send_rx_byte(rx_byte); - spinwait_rxidle(); - csr_rd(.ptr(ral.rdata), .value(dut_rdata)); - if (!cfg.under_reset) `DV_CHECK_EQ(rx_byte, dut_rdata) - end - endtask : process_rx - - virtual task process_remaining_data(); - dut_shutdown(); - endtask : process_remaining_data - -endclass : i2s_smoke_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_stress_all_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_stress_all_vseq.sv index f4ecb55..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_stress_all_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_stress_all_vseq.sv
@@ -13,57 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// combine all i2s seqs (except below seqs) in one seq to run sequentially -// 1. csr seq, which requires scb to be disabled -// 2. i2s_rx_oversample_vseq, which requires zero_delays as it's very timing sensitive -class i2s_stress_all_vseq extends i2s_base_vseq; - `uvm_object_utils(i2s_stress_all_vseq) - - `uvm_object_new - - constraint num_trans_c { - num_trans inside {[3:6]}; - } - - task body(); - string seq_names[] = {"i2s_smoke_vseq", - "i2s_tx_rx_vseq", - "i2s_fifo_full_vseq", - "i2s_fifo_overflow_vseq", - "i2s_fifo_reset_vseq", - "i2s_common_vseq", // for intr_test - "i2s_intr_vseq", - "i2s_noise_filter_vseq", - "i2s_rx_start_bit_filter_vseq", - "i2s_rx_parity_err_vseq", - "i2s_tx_ovrd_vseq", - "i2s_perf_vseq", - "i2s_long_xfer_wo_dly_vseq", - "i2s_loopback_vseq"}; - for (int i = 1; i <= num_trans; i++) begin - uvm_sequence seq; - i2s_base_vseq i2s_vseq; - uint seq_idx = $urandom_range(0, seq_names.size - 1); - - seq = create_seq_by_name(seq_names[seq_idx]); - `downcast(i2s_vseq, seq) - - // if upper seq disables do_apply_reset for this seq, then can't issue reset - // as upper seq may drive reset - if (do_apply_reset) i2s_vseq.do_apply_reset = $urandom_range(0, 1); - else i2s_vseq.do_apply_reset = 0; - - i2s_vseq.set_sequencer(p_sequencer); - `DV_CHECK_RANDOMIZE_FATAL(i2s_vseq) - if (seq_names[seq_idx] == "i2s_common_vseq") begin - i2s_common_vseq common_vseq; - `downcast(common_vseq, i2s_vseq); - common_vseq.common_seq_type = "intr_test"; - end - - i2s_vseq.start(p_sequencer); - end - endtask : body - -endclass +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_ovrd_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_ovrd_vseq.sv index 48de57d..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_ovrd_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_ovrd_vseq.sv
@@ -13,42 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -// test TX override feature through i2s.OVRD and check the pin -class i2s_tx_ovrd_vseq extends i2s_smoke_vseq; - `uvm_object_utils(i2s_tx_ovrd_vseq) - - `uvm_object_new - - // add orvd test on tx and make sure no side-effect on rx - virtual task send_tx_byte(byte data); - bit en_ovrd; - bit txval; - bit exp; - - // add 1 i2s clk to make sure previous i2s TX transfer is done completedly - #(cfg.m_i2s_agent_cfg.vif.i2s_clk_period_ns * 1ns); - - // disable monitor as monitor can't handle this - cfg.m_i2s_agent_cfg.en_tx_monitor = 0; - repeat ($urandom_range(1, 5)) begin - `DV_CHECK_STD_RANDOMIZE_FATAL(en_ovrd) - `DV_CHECK_STD_RANDOMIZE_FATAL(txval) - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_next_trans) - - if (en_ovrd) exp = txval; - else exp = 1; - csr_wr(.ptr(ral.ovrd), .value({txval, en_ovrd})); - cfg.clk_rst_vif.wait_clks(1); - if (!cfg.under_reset) `DV_CHECK_EQ(cfg.m_i2s_agent_cfg.vif.i2s_tx, exp) - cfg.clk_rst_vif.wait_clks(dly_to_next_trans); - end - // disable ovrd - csr_wr(.ptr(ral.ovrd), .value(0)); - cfg.clk_rst_vif.wait_clks(1); - cfg.m_i2s_agent_cfg.en_tx_monitor = 1; - - super.send_tx_byte(data); - endtask - -endclass : i2s_tx_ovrd_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_rx_vseq.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_rx_vseq.sv index 2e3a2f9..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_rx_vseq.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_tx_rx_vseq.sv
@@ -13,227 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_tx_rx_vseq extends i2s_base_vseq; - `uvm_object_utils(i2s_tx_rx_vseq) - - rand uint num_tx_bytes; - rand uint num_rx_bytes; - rand uint dly_to_next_trans; - rand uint dly_to_access_intr; - rand bit wait_for_idle; - rand uint weight_to_skip_rx_read; - rand uint dly_to_rx_read; - - - constraint num_trans_c { - num_trans inside {[1:20]}; - } - - constraint num_tx_bytes_c { - num_tx_bytes dist { - 1 :/ 2, - [2:10] :/ 5, - [11:15] :/ 5, - [16:20] :/ 2 - }; - } - - constraint num_rx_bytes_c { - num_rx_bytes dist { - 1 :/ 2, - [2:10] :/ 5, - [11:15] :/ 5, - [16:20] :/ 2 - }; - } - - constraint dly_to_next_trans_c { - dly_to_next_trans dist { - 0 :/ 5, // more back2back transaction - [1:100] :/ 5, - [100:10000] :/ 2 - }; - } - - constraint dly_to_access_intr_c { - dly_to_access_intr dist { - 0 :/ 1, - [1 :100] :/ 5, - [101 :10_000] :/ 3, - [10_001 :1_000_000] :/ 1 - }; - } - - constraint wait_for_idle_c { - wait_for_idle dist { - 1 :/ 1, - 0 :/ 10 - }; - } - - constraint weight_to_skip_rx_read_c { - // 3: read, 7: skip - weight_to_skip_rx_read == 7; - } - - constraint dly_to_rx_read_c { - dly_to_rx_read dist {0 :/ 1, - [1:100] :/ 1, - [100:10000] :/ 2}; - } - - `uvm_object_new - - - task pre_start(); - super.pre_start(); - num_trans.rand_mode(0); - // dly to send a_valid is controlled in i2s vseq level. Don't add additional delay in tl - // driver as it may make tl happens at ignore period - cfg.m_tl_agent_cfg.a_valid_delay_min = 0; - cfg.m_tl_agent_cfg.a_valid_delay_max = 0; - endtask - - task body(); - fork - begin - while (do_interrupt) process_interrupts(); - end - begin - // repeat test sequencing upto 50 times - for (int i = 1; i <= num_trans; i++) begin - // start each new run by randomizing dut parameters - `DV_CHECK_RANDOMIZE_FATAL(this) - - i2s_init(); - - `uvm_info(`gfn, $sformatf("starting run %0d/%0d", i, num_trans), UVM_MEDIUM) - fork - begin - `uvm_info(`gfn, $sformatf("begin sending %0d tx bytes", num_tx_bytes), UVM_MEDIUM) - process_tx(); - `uvm_info(`gfn, $sformatf("done sending %0d tx bytes", num_tx_bytes), UVM_HIGH) - end - begin - `uvm_info(`gfn, $sformatf("begin sending %0d rx bytes", num_rx_bytes), UVM_MEDIUM) - process_rx(); - `uvm_info(`gfn, $sformatf("done sending %0d rx bytes", num_rx_bytes), UVM_HIGH) - end - join - - process_remaining_data(); - `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) - end - do_interrupt = 0; // to end thread process_interrupts gracefully - end - join - endtask : body - - task post_start(); - bit [TL_DW-1:0] intr_status; - // dut_shutdown is must for each iteration, it's called in body - do_dut_shutdown = 0; - // need to clear fifo when tx is disabled as data isn't sent out - if (ral.ctrl.tx.get_mirrored_value() == 0) begin - clear_fifos(.clear_tx_fifo(1), .clear_rx_fifo(0)); - // wait for 1 cycle to allow tx_empty occur and be cleared later at super.post_start() - cfg.clk_rst_vif.wait_clks(1); - end - super.post_start(); - endtask - - // read interrupts and randomly clear interrupts if set - task process_interrupts(); - bit [TL_DW-1:0] intr_status, clear_intr; - bit clear_rx_intr, clear_tx_intr; - - // avoid zero delay loop during reset - wait(!cfg.under_reset); - // read interrupt - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_intr) - cfg.clk_rst_vif.wait_clks(dly_to_access_intr); - csr_rd(.ptr(ral.intr_state), .value(intr_status)); - - // clear interrupt, randomly clear the interrupt that is set, and - // don't clear the interrupt which isn't set - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(clear_intr, - foreach (clear_intr[i]) { - clear_intr[i] -> intr_status[i] == 1; - }) - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_intr) - cfg.clk_rst_vif.wait_clks(dly_to_access_intr); - - // for fifo interrupt, parity/frame error, don't clear it at ignored period - // as it hasn't been checked - clear_tx_intr = clear_intr[TxWatermark] | clear_intr[TxWatermark] | clear_intr[TxEmpty]; - clear_rx_intr = clear_intr[RxWatermark] | clear_intr[RxOverflow] | clear_intr[RxFrameErr] | - clear_intr[RxParityErr]; - wait_when_in_ignored_period(clear_tx_intr, clear_rx_intr); - csr_wr(.ptr(ral.intr_state), .value(clear_intr)); - endtask - - virtual task process_tx(); - for (int j = 1; j <= num_tx_bytes; j++) begin - byte tx_byte; - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_next_trans) - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(wait_for_idle) - - cfg.clk_rst_vif.wait_clks(dly_to_next_trans); - wait_for_tx_fifo_not_full(); - wait_when_in_ignored_period(.tx(1)); - `DV_CHECK_STD_RANDOMIZE_FATAL(tx_byte) - send_tx_byte(tx_byte); - if (wait_for_idle) spinwait_txidle(); - end - endtask : process_tx - - // control RX data from both sides independently - // 1. i2s device - // 2. register - virtual task process_rx(); - bit send_rx_done = 0; - fork - begin // drive from i2s RX interface - for (int j = 1; j <= num_rx_bytes; j++) begin - byte rx_byte; - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_next_trans) - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(wait_for_idle) - `DV_CHECK_STD_RANDOMIZE_FATAL(rx_byte) - - cfg.clk_rst_vif.wait_clks(dly_to_next_trans); - wait_for_rx_fifo_not_full(); - send_rx_byte(rx_byte); - if (wait_for_idle) spinwait_rxidle(); - end - send_rx_done = 1; // to end reading RX thread - end - begin // read RX data through register - while (!send_rx_done && !cfg.under_reset) begin - // csr read is much faster than i2s transfer, use bigger delay - `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_rx_read) - cfg.clk_rst_vif.wait_clks(dly_to_rx_read); - rand_read_rx_byte(weight_to_skip_rx_read); - end - end - join - endtask : process_rx - - virtual task process_remaining_data(); - - fork - begin // TX - wait_for_all_tx_bytes(); - // tx fifo is empty but still need to wait for last tx item to be flushed out - cfg.m_i2s_agent_cfg.vif.wait_for_tx_idle(); - end - begin // RX - // wait for last rx item to be completed before read all of them - cfg.m_i2s_agent_cfg.vif.wait_for_rx_idle(); - read_all_rx_bytes(); - end - join - - endtask : process_remaining_data - -endclass : i2s_tx_rx_vseq +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_vseq_list.sv b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_vseq_list.sv index 67b4817..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_vseq_list.sv +++ b/hw/top_matcha/ip/i2s/dv/env/seq_lib/i2s_vseq_list.sv
@@ -13,21 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -`include "i2s_base_vseq.sv" -`include "i2s_tx_rx_vseq.sv" -`include "i2s_smoke_vseq.sv" -`include "i2s_common_vseq.sv" -`include "i2s_fifo_full_vseq.sv" -`include "i2s_fifo_overflow_vseq.sv" -`include "i2s_fifo_reset_vseq.sv" -`include "i2s_rx_oversample_vseq.sv" -`include "i2s_intr_vseq.sv" -`include "i2s_noise_filter_vseq.sv" -`include "i2s_tx_ovrd_vseq.sv" -`include "i2s_rx_start_bit_filter_vseq.sv" -`include "i2s_rx_parity_err_vseq.sv" -`include "i2s_loopback_vseq.sv" -`include "i2s_perf_vseq.sv" -`include "i2s_long_xfer_wo_dly_vseq.sv" -`include "i2s_stress_all_vseq.sv" +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/i2s_sim_cfg.hjson b/hw/top_matcha/ip/i2s/dv/i2s_sim_cfg.hjson index 5251b52..4703ccd 100644 --- a/hw/top_matcha/ip/i2s/dv/i2s_sim_cfg.hjson +++ b/hw/top_matcha/ip/i2s/dv/i2s_sim_cfg.hjson
@@ -1,143 +1,9 @@ // Copyright lowRISC contributors. +// Copyright 2023 Google LLC +// // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ - // Name of the sim cfg - typically same as the name of the DUT. - name: i2s - // Top level dut name (sv module). - dut: i2s +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s - // Top level testbench name (sv module). - tb: tb - - // Simulator used to sign off this block - tool: vcs - - // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:dv:i2s_sim:0.1 - - // Testplan hjson file. - testplan: "{proj_root}/hw/ip/i2s/data/i2s_testplan.hjson" - - // RAL spec - used to generate the RAL model. - ral_spec: "{proj_root}/hw/ip/i2s/data/i2s.hjson" - - // Import additional common sim cfg files. - import_cfgs: [// Project wide common sim cfg file - "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", - // Common CIP test lists - "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] - - // Add additional tops for simulation. - sim_tops: ["i2s_bind", "sec_cm_prim_onehot_check_bind"] - - // Default iterations for all tests - each test entry can override this. - reseed: 50 - - // Default UVM test and seq class name. - uvm_test: i2s_base_test - uvm_test_seq: i2s_base_vseq - - // Add I2S specific exclusion files. - vcs_cov_excl_files: ["{proj_root}/hw/ip/i2s/dv/cov/i2s_cov_excl.el"] - - // List of test specifications. - tests: [ - { - name: i2s_smoke - uvm_test_seq: i2s_smoke_vseq - } - - { - name: i2s_tx_rx - uvm_test_seq: i2s_tx_rx_vseq - } - - { - name: i2s_fifo_full - uvm_test_seq: i2s_fifo_full_vseq - } - - { - name: i2s_fifo_overflow - uvm_test_seq: i2s_fifo_overflow_vseq - } - - { - name: i2s_fifo_reset - // need more seeds to cover i2s_env_cov::fifo_level_cg - reseed: 300 - uvm_test_seq: i2s_fifo_reset_vseq - } - - { - name: i2s_rx_oversample - uvm_test_seq: i2s_rx_oversample_vseq - run_opts: ["+zero_delays=1"] - } - - { - name: i2s_intr - uvm_test_seq: i2s_intr_vseq - // 3ms - run_opts: ["+test_timeout_ns=3000000000"] - } - - { - name: i2s_noise_filter - uvm_test_seq: i2s_noise_filter_vseq - } - - { - name: i2s_rx_start_bit_filter - uvm_test_seq: i2s_rx_start_bit_filter_vseq - } - - { - name: i2s_rx_parity_err - uvm_test_seq: i2s_rx_parity_err_vseq - } - - { - name: i2s_tx_ovrd - uvm_test_seq: i2s_tx_ovrd_vseq - } - - { - name: i2s_loopback - uvm_test_seq: i2s_loopback_vseq - } - - { - name: i2s_perf - uvm_test_seq: i2s_perf_vseq - run_opts: ["+zero_delays=1"] - } - - { - name: i2s_long_xfer_wo_dly - uvm_test_seq: i2s_long_xfer_wo_dly_vseq - run_opts: ["+zero_delays=1"] - } - - { - name: i2s_stress_all_with_rand_reset - // need more seeds to cover i2s_agent_cov::i2s_reset_cg - reseed: 100 - } - ] - - // List of regressions. - regressions: [ - { - name: smoke - tests: ["i2s_smoke"] - } - ] -}
diff --git a/hw/top_matcha/ip/i2s/dv/sva/i2s_bind.sv b/hw/top_matcha/ip/i2s/dv/sva/i2s_bind.sv index 4cb66d1..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/sva/i2s_bind.sv +++ b/hw/top_matcha/ip/i2s/dv/sva/i2s_bind.sv
@@ -13,23 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -module i2s_bind; - - bind i2s tlul_assert #( - .EndpointType("Device") - ) tlul_assert_device ( - .clk_i, - .rst_ni, - .h2d (tl_i), - .d2h (tl_o) - ); - - bind i2s i2s_csr_assert_fpv i2s_csr_assert ( - .clk_i, - .rst_ni, - .h2d (tl_i), - .d2h (tl_o) -); - -endmodule +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/tb/tb.sv b/hw/top_matcha/ip/i2s/dv/tb/tb.sv index fc9157e..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/tb/tb.sv +++ b/hw/top_matcha/ip/i2s/dv/tb/tb.sv
@@ -13,202 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. -// -module tb; - // dep packages - import uvm_pkg::*; - import dv_utils_pkg::*; - import tl_agent_pkg::*; - import i2s_env_pkg::*; - import i2s_test_pkg::*; - - // macro includes - `include "uvm_macros.svh" - `include "dv_macros.svh" - - wire clk, rst_n; - wire devmode; - wire intr_tx_watermark; - wire intr_rx_watermark; - wire intr_tx_empty; - wire intr_rx_overflow; - wire intr_rx_timeout; - wire i2s_rx, i2s_tx, i2s_tx_en; - wire [NUM_MAX_INTERRUPTS-1:0] interrupts; - - // interfaces - clk_rst_if clk_rst_if(.clk, .rst_n); - pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts); - pins_if #(1) devmode_if(devmode); - tl_if tl_if(.clk, .rst_n); - i2s_if i2s_if(); - - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // // //MY TEST - // // localparam STIMULUS_BYTES = 200; - // // reg stim_storage [STIMULUS_BYTES-1:0]; - - // // parameter RST_DURATION = 50; //ns - // // parameter CLK_PERIOD = 20; //ns - - // parameter STIMULUS_DATA_COUNT = 10; - // parameter DATA_WIDTH = 16; - - // // Inputs - // reg rst_i; - // reg sdat_i; - - // // Outputs - // wire [15:0] data_o; - // wire lr_chnl_o; - // wire write_o; - wire sclk_o; - wire wsel_o; - - // // Received data - // reg [15:0] data_rx [0:1]; - - // // Transmitted data - // reg [15:0] data_tx [0:STIMULUS_DATA_COUNT-1]; - // integer indx_tx; - // integer indx_bit_tx; - - // //IP should operate at SCLK frequency. Pass in as clock. - // //SCLK frequency = 16bits * 16ks/s - // //SCLK divider = base_clk / SCLK frequency - // //SCLK divider = 10M/(16*16*10e3) = 3.90 (approx=4) - // reg [1:0] sclk_divider; - // sclk_tick = clk; - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - `DV_ALERT_IF_CONNECT - - // dut - i2s dut ( - .clk_i (clk ), - .rst_ni (rst_n ), - - .tl_i (tl_if.h2d ), - .tl_o (tl_if.d2h ), - - .alert_rx_i (alert_rx ), - .alert_tx_o (alert_tx ), - - .cio_sd_i (clk ), - .cio_sclk_o (sclk_o ), - .cio_sclk_en_o ( ), - .cio_ws_o (wsel_o ), - .cio_ws_en_o ( ), - - .intr_tx_watermark_o (intr_tx_watermark ), - .intr_rx_watermark_o (intr_rx_watermark ), - .intr_tx_empty_o (intr_tx_empty ), - .intr_rx_overflow_o (intr_rx_overflow ), - .intr_rx_timeout_o (intr_rx_timeout ), - ); - - assign interrupts[TxWatermark] = intr_tx_watermark; - assign interrupts[RxWatermark] = intr_rx_watermark; - assign interrupts[TxEmpty] = intr_tx_empty; - assign interrupts[RxOverflow] = intr_rx_overflow; - assign interrupts[RxTimeout] = intr_rx_timeout; - - assign i2s_rx = i2s_if.i2s_rx; - assign i2s_if.i2s_tx = i2s_tx; - - initial begin - // drive clk and rst_n from clk_if - clk_rst_if.set_active(); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// `timescale 1ns / 100ps -// // `include "i2s_top_rx.v" - - - -// // // Instantiate the Unit Under Test (UUT) -// // i2s_top_rx uut -// // ( -// // .clk_i(clk_i), -// // .rst_i(rst_i), -// // .data_o(data_o), -// // .lr_chnl_o(lr_chnl_o), -// // .write_o(write_o), -// // .sclk_o(sclk_o), -// // .wsel_o(wsel_o), -// // .sdat_i(sdat_i) -// // ); - -// // // Main oscillator -// // initial begin : clk_generator -// // clk_i = 1'b0; -// // #(RST_DURATION); -// // forever begin -// // clk_i = #(CLK_PERIOD/2) ~clk_i; -// // end -// // end - -// // I2S transmitter -// initial begin : transmitter -// // $dumpfile("i2s_top_rx_tb.vcd"); -// // $dumpvars(0, i2s_top_rx_tb); -// read_from_file; -// // for (int i = 0; i < STIMULUS_DATA_COUNT; i=i+1) -// // begin -// // [15:0] data_tx [i] = i; -// // end -// indx_tx = 0; -// indx_bit_tx = 15; -// sdat_i = 1'b0; -// sclk_divider = 2'b0; -// #(RST_DURATION); -// forever begin -// @(negedge(clk)) begin -// if (indx_tx < STIMULUS_DATA_COUNT) begin -// sdat_i = data_tx[indx_tx][indx_bit_tx]; -// if (indx_bit_tx > 0) begin -// indx_bit_tx = indx_bit_tx - 1; -// end -// else begin -// $display("tx: %h", data_tx[indx_tx]); -// indx_tx = indx_tx + 1; -// indx_bit_tx = 15; -// end -// end -// else begin -// $stop; -// end -// end -// end -// end - -// task read_from_file; -// integer stimulus_file; -// integer i; -// begin -// for (i=0; ; i=i+1) -// if (i<16) -// data_tx[i] = i; -// else -// data_tx[i] = 0; -// // $readmemh("stimulus/stimulus_file.txt", data_tx); -// end -// endtask - - -// endmodule -///////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); - // uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); - // uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if); - // uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); - // uvm_config_db#(virtual i2s_if)::set(null, "*.env.m_i2s_agent*", "vif", i2s_if); - // $timeformat(-12, 0, " ps", 12); - run_test(); - end - - // we expect the output enable to be always 1 - `ASSERT(UartTxEnTiedTo1_A, i2s_tx_en, clk, !rst_n) - -endmodule +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/tests/i2s_base_test.sv b/hw/top_matcha/ip/i2s/dv/tests/i2s_base_test.sv index f9400ae..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/tests/i2s_base_test.sv +++ b/hw/top_matcha/ip/i2s/dv/tests/i2s_base_test.sv
@@ -13,16 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -class i2s_base_test extends cip_base_test #(.ENV_T(i2s_env), .CFG_T(i2s_env_cfg)); - `uvm_component_utils(i2s_base_test) - `uvm_component_new - - virtual function void build_phase(uvm_phase phase); - max_quit_count = 50; - test_timeout_ns = 600_000_000; // 600ms - super.build_phase(phase); - endfunction : build_phase - -endclass : i2s_base_test - +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/dv/tests/i2s_test_pkg.sv b/hw/top_matcha/ip/i2s/dv/tests/i2s_test_pkg.sv index 603c27d..4b3bb8f 100644 --- a/hw/top_matcha/ip/i2s/dv/tests/i2s_test_pkg.sv +++ b/hw/top_matcha/ip/i2s/dv/tests/i2s_test_pkg.sv
@@ -13,21 +13,5 @@ // See the License for the specific language governing permissions and // limitations under the License. - -package i2s_test_pkg; - // dep packages - import uvm_pkg::*; - import cip_base_pkg::*; - import i2s_env_pkg::*; - - // macro includes - `include "uvm_macros.svh" - `include "dv_macros.svh" - - // local types - - // functions - - // package sources - `include "i2s_base_test.sv" -endpackage +// I2S DV not yet implemented. File structure based off UART left as placeholder +// Reference file history for original content with all instances of uart replaced with i2s
diff --git a/hw/top_matcha/ip/i2s/rtl/i2s.sv b/hw/top_matcha/ip/i2s/rtl/i2s.sv index 8cb9f5f..3042a48 100644 --- a/hw/top_matcha/ip/i2s/rtl/i2s.sv +++ b/hw/top_matcha/ip/i2s/rtl/i2s.sv
@@ -88,7 +88,7 @@ .intr_rx_overflow_o ); - // always enable the driving oc sclk and ws TODO: add transmit data + // always enable the driving sclk, ws, and tx serial data assign cio_rx_ws_en_o = 1'b1; assign cio_rx_sclk_en_o = 1'b1; assign cio_tx_sd_en_o = 1'b1; @@ -96,4 +96,19 @@ assign cio_tx_sclk_en_o = 1'b1; // Assert Known for outputs TODO: set up asserts (see uart.sv in opentitan) + `ASSERT(RxWsIsOne_A, cio_rx_ws_en_o === 1'b1) + `ASSERT(RxSclkIsOne_A, cio_rx_sclk_en_o === 1'b1) + `ASSERT(TxSdIsOne_A, cio_tx_sd_en_o === 1'b1) + `ASSERT(TxWsIsOne_A, cio_tx_ws_en_o === 1'b1) + `ASSERT(TxSclkIsOne_A, cio_tx_sclk_en_o === 1'b1) + + // Assert Known for alerts -- No alerts + + // Assert Known for interrupts + `ASSERT_KNOWN(TxWatermarkKnown_A, intr_tx_watermark_o) + `ASSERT_KNOWN(RxWatermarkKnown_A, intr_rx_watermark_o) + `ASSERT_KNOWN(TxEmptyKnown_A, intr_tx_empty_o) + `ASSERT_KNOWN(RxOverflowKnown_A, intr_rx_overflow_o) + + endmodule
