[dma/hw] Use [a/d]_ready in transaction FSM HDL change: https://spacebeaker-review.git.corp.google.com/c/shodan/experimental-hw/+/42909 -Passes DMA DV smoketest with removal of randomization constraints Fix: 292296605 Change-Id: I8bfb71a09a0b5ea3b3f3ee17c0de2a9b8295e756
diff --git a/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v b/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v index 8153fae..b80cc53 100644 --- a/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v +++ b/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v
@@ -1,3 +1,4 @@ +// SHA: c87e9e12d69cd8e0e93b12625af866c37e4c707b module TLULCSRTL_TL_TL( // @[:@3.2] input clock, // @[:@4.4] input reset, // @[:@5.4] @@ -13,6 +14,7 @@ output [9:0] io_ctl_d_source, // @[:@6.4] output [31:0] io_ctl_d_data, // @[:@6.4] output io_ctl_d_valid, // @[:@6.4] + input io_ctl_d_ready, // @[:@6.4] output [3:0] io_bus_addr, // @[:@6.4] output [31:0] io_bus_dataOut, // @[:@6.4] input [31:0] io_bus_dataIn, // @[:@6.4] @@ -23,78 +25,86 @@ reg [31:0] _RAND_0; reg [31:0] addr; // @[TLULCSR.scala 36:21:@13.4] reg [31:0] _RAND_1; - reg [9:0] source_id; // @[TLULCSR.scala 37:26:@14.4] + reg [31:0] wdata; // @[TLULCSR.scala 37:22:@14.4] reg [31:0] _RAND_2; - reg [1:0] size; // @[TLULCSR.scala 38:21:@15.4] + reg [9:0] sourceId; // @[TLULCSR.scala 38:25:@15.4] reg [31:0] _RAND_3; - wire _T_128; // @[Conditional.scala 37:30:@53.4] - wire [3:0] _T_132; // @[TLULCSR.scala 69:31:@58.6] - wire _T_136; // @[TLULCSR.scala 74:30:@63.8] - wire _T_138; // @[TLULCSR.scala 77:36:@70.10] - wire _T_139; // @[TLULCSR.scala 78:36:@71.10] - wire _T_140; // @[TLULCSR.scala 77:53:@72.10] - wire [31:0] _GEN_0; // @[TLULCSR.scala 78:57:@73.10] - wire [1:0] _GEN_1; // @[TLULCSR.scala 78:57:@73.10] - wire [1:0] _GEN_3; // @[TLULCSR.scala 74:44:@64.8] - wire [3:0] _GEN_4; // @[TLULCSR.scala 74:44:@64.8] - wire [31:0] _GEN_5; // @[TLULCSR.scala 74:44:@64.8] - wire _GEN_6; // @[TLULCSR.scala 74:44:@64.8] - wire [1:0] _GEN_7; // @[TLULCSR.scala 70:28:@60.6] - wire [9:0] _GEN_8; // @[TLULCSR.scala 70:28:@60.6] - wire [1:0] _GEN_9; // @[TLULCSR.scala 70:28:@60.6] - wire [3:0] _GEN_10; // @[TLULCSR.scala 70:28:@60.6] - wire [31:0] _GEN_11; // @[TLULCSR.scala 70:28:@60.6] - wire _GEN_12; // @[TLULCSR.scala 70:28:@60.6] - wire _T_143; // @[Conditional.scala 37:30:@82.6] - wire _T_145; // @[Conditional.scala 37:30:@89.8] - wire [1:0] _GEN_13; // @[Conditional.scala 39:67:@90.8] - wire [1:0] _GEN_16; // @[Conditional.scala 39:67:@83.6] - wire _GEN_18; // @[Conditional.scala 39:67:@83.6] - wire [31:0] _GEN_22; // @[Conditional.scala 40:58:@54.4] - wire [1:0] _GEN_23; // @[Conditional.scala 40:58:@54.4] - wire [9:0] _GEN_24; // @[Conditional.scala 40:58:@54.4] - wire [1:0] _GEN_25; // @[Conditional.scala 40:58:@54.4] - wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@54.4] - wire rsp; // @[Conditional.scala 40:58:@54.4] - assign _T_128 = 2'h0 == state; // @[Conditional.scala 37:30:@53.4] - assign _T_132 = io_ctl_a_address[5:2]; // @[TLULCSR.scala 69:31:@58.6] - assign _T_136 = io_ctl_a_opcode == 3'h4; // @[TLULCSR.scala 74:30:@63.8] - assign _T_138 = io_ctl_a_opcode == 3'h0; // @[TLULCSR.scala 77:36:@70.10] - assign _T_139 = io_ctl_a_opcode == 3'h1; // @[TLULCSR.scala 78:36:@71.10] - assign _T_140 = _T_138 | _T_139; // @[TLULCSR.scala 77:53:@72.10] - assign _GEN_0 = _T_140 ? {{28'd0}, _T_132} : addr; // @[TLULCSR.scala 78:57:@73.10] - assign _GEN_1 = _T_140 ? 2'h2 : state; // @[TLULCSR.scala 78:57:@73.10] - assign _GEN_3 = _T_136 ? 2'h1 : _GEN_1; // @[TLULCSR.scala 74:44:@64.8] - assign _GEN_4 = _T_136 ? _T_132 : _T_132; // @[TLULCSR.scala 74:44:@64.8] - assign _GEN_5 = _T_136 ? addr : _GEN_0; // @[TLULCSR.scala 74:44:@64.8] - assign _GEN_6 = _T_136 ? 1'h0 : _T_140; // @[TLULCSR.scala 74:44:@64.8] - assign _GEN_7 = io_ctl_a_valid ? io_ctl_a_size : size; // @[TLULCSR.scala 70:28:@60.6] - assign _GEN_8 = io_ctl_a_valid ? io_ctl_a_source : source_id; // @[TLULCSR.scala 70:28:@60.6] - assign _GEN_9 = io_ctl_a_valid ? _GEN_3 : state; // @[TLULCSR.scala 70:28:@60.6] - assign _GEN_10 = io_ctl_a_valid ? _GEN_4 : _T_132; // @[TLULCSR.scala 70:28:@60.6] - assign _GEN_11 = io_ctl_a_valid ? _GEN_5 : addr; // @[TLULCSR.scala 70:28:@60.6] - assign _GEN_12 = io_ctl_a_valid ? _GEN_6 : 1'h0; // @[TLULCSR.scala 70:28:@60.6] - assign _T_143 = 2'h1 == state; // @[Conditional.scala 37:30:@82.6] - assign _T_145 = 2'h2 == state; // @[Conditional.scala 37:30:@89.8] - assign _GEN_13 = _T_145 ? 2'h0 : state; // @[Conditional.scala 39:67:@90.8] - assign _GEN_16 = _T_143 ? 2'h0 : _GEN_13; // @[Conditional.scala 39:67:@83.6] - assign _GEN_18 = _T_143 ? 1'h1 : _T_145; // @[Conditional.scala 39:67:@83.6] - assign _GEN_22 = _T_128 ? {{28'd0}, _GEN_10} : addr; // @[Conditional.scala 40:58:@54.4] - assign _GEN_23 = _T_128 ? _GEN_7 : size; // @[Conditional.scala 40:58:@54.4] - assign _GEN_24 = _T_128 ? _GEN_8 : source_id; // @[Conditional.scala 40:58:@54.4] - assign _GEN_25 = _T_128 ? _GEN_9 : _GEN_16; // @[Conditional.scala 40:58:@54.4] - assign _GEN_26 = _T_128 ? _GEN_11 : addr; // @[Conditional.scala 40:58:@54.4] - assign rsp = _T_128 ? 1'h0 : _T_143; // @[Conditional.scala 40:58:@54.4] - assign io_ctl_a_ready = 2'h0 == state; // @[TLULCSR.scala 42:12:@29.4 TLULCSR.scala 66:22:@55.6] - assign io_ctl_d_opcode = {{2'd0}, rsp}; // @[TLULCSR.scala 46:19:@40.4] - assign io_ctl_d_size = size; // @[TLULCSR.scala 49:17:@43.4] - assign io_ctl_d_source = source_id; // @[TLULCSR.scala 52:19:@46.4] - assign io_ctl_d_data = io_bus_dataIn; // @[TLULCSR.scala 45:17:@39.4] - assign io_ctl_d_valid = _T_128 ? 1'h0 : _GEN_18; // @[TLULCSR.scala 47:18:@41.4] - assign io_bus_addr = _GEN_26[3:0]; // @[TLULCSR.scala 56:15:@48.4 TLULCSR.scala 80:23:@75.12] - assign io_bus_dataOut = io_ctl_a_data; // @[TLULCSR.scala 57:18:@49.4] - assign io_bus_write = _T_128 ? _GEN_12 : 1'h0; // @[TLULCSR.scala 61:16:@50.4] - assign io_bus_read = state == 2'h1; // @[TLULCSR.scala 62:15:@52.4] + reg [1:0] size; // @[TLULCSR.scala 39:21:@16.4] + reg [31:0] _RAND_4; + wire _T_130; // @[Conditional.scala 37:30:@54.4] + wire [3:0] _T_134; // @[TLULCSR.scala 68:31:@59.6] + wire _T_138; // @[TLULCSR.scala 73:30:@64.8] + wire _T_140; // @[TLULCSR.scala 76:36:@71.10] + wire _T_141; // @[TLULCSR.scala 77:36:@72.10] + wire _T_142; // @[TLULCSR.scala 76:53:@73.10] + wire [3:0] _GEN_0; // @[TLULCSR.scala 77:57:@74.10] + wire [31:0] _GEN_1; // @[TLULCSR.scala 77:57:@74.10] + wire [1:0] _GEN_2; // @[TLULCSR.scala 77:57:@74.10] + wire [1:0] _GEN_3; // @[TLULCSR.scala 73:44:@65.8] + wire [3:0] _GEN_4; // @[TLULCSR.scala 73:44:@65.8] + wire [31:0] _GEN_5; // @[TLULCSR.scala 73:44:@65.8] + wire [1:0] _GEN_6; // @[TLULCSR.scala 69:28:@61.6] + wire [9:0] _GEN_7; // @[TLULCSR.scala 69:28:@61.6] + wire [1:0] _GEN_8; // @[TLULCSR.scala 69:28:@61.6] + wire [3:0] _GEN_9; // @[TLULCSR.scala 69:28:@61.6] + wire [31:0] _GEN_10; // @[TLULCSR.scala 69:28:@61.6] + wire _T_144; // @[Conditional.scala 37:30:@83.6] + wire [1:0] _GEN_11; // @[TLULCSR.scala 88:28:@88.8] + wire _T_146; // @[Conditional.scala 37:30:@93.8] + wire [1:0] _GEN_13; // @[TLULCSR.scala 96:28:@98.10] + wire [1:0] _GEN_14; // @[Conditional.scala 39:67:@94.8] + wire _GEN_17; // @[Conditional.scala 39:67:@94.8] + wire [1:0] _GEN_18; // @[Conditional.scala 39:67:@84.6] + wire _GEN_20; // @[Conditional.scala 39:67:@84.6] + wire _GEN_21; // @[Conditional.scala 39:67:@84.6] + wire [31:0] _GEN_25; // @[Conditional.scala 40:58:@55.4] + wire [1:0] _GEN_26; // @[Conditional.scala 40:58:@55.4] + wire [9:0] _GEN_27; // @[Conditional.scala 40:58:@55.4] + wire [1:0] _GEN_28; // @[Conditional.scala 40:58:@55.4] + wire [31:0] _GEN_29; // @[Conditional.scala 40:58:@55.4] + wire rsp; // @[Conditional.scala 40:58:@55.4] + assign _T_130 = 2'h0 == state; // @[Conditional.scala 37:30:@54.4] + assign _T_134 = io_ctl_a_address[5:2]; // @[TLULCSR.scala 68:31:@59.6] + assign _T_138 = io_ctl_a_opcode == 3'h4; // @[TLULCSR.scala 73:30:@64.8] + assign _T_140 = io_ctl_a_opcode == 3'h0; // @[TLULCSR.scala 76:36:@71.10] + assign _T_141 = io_ctl_a_opcode == 3'h1; // @[TLULCSR.scala 77:36:@72.10] + assign _T_142 = _T_140 | _T_141; // @[TLULCSR.scala 76:53:@73.10] + assign _GEN_0 = _T_142 ? _T_134 : _T_134; // @[TLULCSR.scala 77:57:@74.10] + assign _GEN_1 = _T_142 ? io_ctl_a_data : wdata; // @[TLULCSR.scala 77:57:@74.10] + assign _GEN_2 = _T_142 ? 2'h2 : state; // @[TLULCSR.scala 77:57:@74.10] + assign _GEN_3 = _T_138 ? 2'h1 : _GEN_2; // @[TLULCSR.scala 73:44:@65.8] + assign _GEN_4 = _T_138 ? _T_134 : _GEN_0; // @[TLULCSR.scala 73:44:@65.8] + assign _GEN_5 = _T_138 ? wdata : _GEN_1; // @[TLULCSR.scala 73:44:@65.8] + assign _GEN_6 = io_ctl_a_valid ? io_ctl_a_size : size; // @[TLULCSR.scala 69:28:@61.6] + assign _GEN_7 = io_ctl_a_valid ? io_ctl_a_source : sourceId; // @[TLULCSR.scala 69:28:@61.6] + assign _GEN_8 = io_ctl_a_valid ? _GEN_3 : state; // @[TLULCSR.scala 69:28:@61.6] + assign _GEN_9 = io_ctl_a_valid ? _GEN_4 : _T_134; // @[TLULCSR.scala 69:28:@61.6] + assign _GEN_10 = io_ctl_a_valid ? _GEN_5 : wdata; // @[TLULCSR.scala 69:28:@61.6] + assign _T_144 = 2'h1 == state; // @[Conditional.scala 37:30:@83.6] + assign _GEN_11 = io_ctl_d_ready ? 2'h0 : 2'h1; // @[TLULCSR.scala 88:28:@88.8] + assign _T_146 = 2'h2 == state; // @[Conditional.scala 37:30:@93.8] + assign _GEN_13 = io_ctl_d_ready ? 2'h0 : 2'h2; // @[TLULCSR.scala 96:28:@98.10] + assign _GEN_14 = _T_146 ? _GEN_13 : state; // @[Conditional.scala 39:67:@94.8] + assign _GEN_17 = _T_146 ? io_ctl_d_ready : 1'h0; // @[Conditional.scala 39:67:@94.8] + assign _GEN_18 = _T_144 ? _GEN_11 : _GEN_14; // @[Conditional.scala 39:67:@84.6] + assign _GEN_20 = _T_144 ? 1'h1 : _T_146; // @[Conditional.scala 39:67:@84.6] + assign _GEN_21 = _T_144 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67:@84.6] + assign _GEN_25 = _T_130 ? {{28'd0}, _GEN_9} : addr; // @[Conditional.scala 40:58:@55.4] + assign _GEN_26 = _T_130 ? _GEN_6 : size; // @[Conditional.scala 40:58:@55.4] + assign _GEN_27 = _T_130 ? _GEN_7 : sourceId; // @[Conditional.scala 40:58:@55.4] + assign _GEN_28 = _T_130 ? _GEN_8 : _GEN_18; // @[Conditional.scala 40:58:@55.4] + assign _GEN_29 = _T_130 ? _GEN_10 : wdata; // @[Conditional.scala 40:58:@55.4] + assign rsp = _T_130 ? 1'h0 : _T_144; // @[Conditional.scala 40:58:@55.4] + assign io_ctl_a_ready = 2'h0 == state; // @[TLULCSR.scala 43:12:@30.4 TLULCSR.scala 65:22:@56.6] + assign io_ctl_d_opcode = {{2'd0}, rsp}; // @[TLULCSR.scala 47:19:@41.4] + assign io_ctl_d_size = size; // @[TLULCSR.scala 50:17:@44.4] + assign io_ctl_d_source = sourceId; // @[TLULCSR.scala 53:19:@47.4] + assign io_ctl_d_data = io_bus_dataIn; // @[TLULCSR.scala 46:17:@40.4] + assign io_ctl_d_valid = _T_130 ? 1'h0 : _GEN_20; // @[TLULCSR.scala 48:18:@42.4] + assign io_bus_addr = addr[3:0]; // @[TLULCSR.scala 57:15:@49.4] + assign io_bus_dataOut = wdata; // @[TLULCSR.scala 58:18:@50.4] + assign io_bus_write = _T_130 ? 1'h0 : _GEN_21; // @[TLULCSR.scala 60:16:@51.4] + assign io_bus_read = state == 2'h1; // @[TLULCSR.scala 61:15:@53.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -129,11 +139,15 @@ `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_2 = {1{`RANDOM}}; - source_id = _RAND_2[9:0]; + wdata = _RAND_2[31:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; - size = _RAND_3[1:0]; + sourceId = _RAND_3[9:0]; + `endif // RANDOMIZE_REG_INIT + `ifdef RANDOMIZE_REG_INIT + _RAND_4 = {1{`RANDOM}}; + size = _RAND_4[1:0]; `endif // RANDOMIZE_REG_INIT end `endif // RANDOMIZE @@ -141,22 +155,30 @@ if (reset) begin state <= 2'h0; end else begin - if (_T_128) begin + if (_T_130) begin if (io_ctl_a_valid) begin - if (_T_136) begin + if (_T_138) begin state <= 2'h1; end else begin - if (_T_140) begin + if (_T_142) begin state <= 2'h2; end end end end else begin - if (_T_143) begin - state <= 2'h0; - end else begin - if (_T_145) begin + if (_T_144) begin + if (io_ctl_d_ready) begin state <= 2'h0; + end else begin + state <= 2'h1; + end + end else begin + if (_T_146) begin + if (io_ctl_d_ready) begin + state <= 2'h0; + end else begin + state <= 2'h2; + end end end end @@ -164,23 +186,36 @@ if (reset) begin addr <= 32'h0; end else begin - if (_T_128) begin - addr <= {{28'd0}, _GEN_10}; + if (_T_130) begin + addr <= {{28'd0}, _GEN_9}; end end if (reset) begin - source_id <= 10'h0; + wdata <= 32'h0; end else begin - if (_T_128) begin + if (_T_130) begin if (io_ctl_a_valid) begin - source_id <= io_ctl_a_source; + if (!(_T_138)) begin + if (_T_142) begin + wdata <= io_ctl_a_data; + end + end + end + end + end + if (reset) begin + sourceId <= 10'h0; + end else begin + if (_T_130) begin + if (io_ctl_a_valid) begin + sourceId <= io_ctl_a_source; end end end if (reset) begin size <= 2'h0; end else begin - if (_T_128) begin + if (_T_130) begin if (io_ctl_a_valid) begin size <= io_ctl_a_size; end @@ -188,88 +223,133 @@ end end endmodule -module TLULReaderTL_TL_TL( // @[:@96.2] - input clock, // @[:@97.4] - input reset, // @[:@98.4] - output [31:0] io_bus_a_address, // @[:@99.4] - output io_bus_a_valid, // @[:@99.4] - input [31:0] io_bus_d_data, // @[:@99.4] - input io_bus_d_valid, // @[:@99.4] - output io_bus_d_ready, // @[:@99.4] - input io_dataIO_ready, // @[:@99.4] - output io_dataIO_valid, // @[:@99.4] - output [31:0] io_dataIO_bits, // @[:@99.4] - output io_xfer_done, // @[:@99.4] - input [31:0] io_xfer_address, // @[:@99.4] - input [31:0] io_xfer_length, // @[:@99.4] - input io_xfer_valid // @[:@99.4] +module TLULReaderTL_TL_TL( // @[:@104.2] + input clock, // @[:@105.4] + input reset, // @[:@106.4] + output [31:0] io_bus_a_address, // @[:@107.4] + output io_bus_a_valid, // @[:@107.4] + input io_bus_a_ready, // @[:@107.4] + input [31:0] io_bus_d_data, // @[:@107.4] + input io_bus_d_valid, // @[:@107.4] + output io_bus_d_ready, // @[:@107.4] + input io_dataIO_ready, // @[:@107.4] + output io_dataIO_valid, // @[:@107.4] + output [31:0] io_dataIO_bits, // @[:@107.4] + output io_xfer_done, // @[:@107.4] + input [31:0] io_xfer_address, // @[:@107.4] + input [31:0] io_xfer_length, // @[:@107.4] + input io_xfer_valid // @[:@107.4] ); - reg state; // @[TLULReader.scala 32:22:@101.4] + reg [1:0] state; // @[TLULReader.scala 32:22:@109.4] reg [31:0] _RAND_0; - reg [31:0] xferCnt; // @[TLULReader.scala 34:24:@102.4] + reg [31:0] xferCnt; // @[TLULReader.scala 34:24:@110.4] reg [31:0] _RAND_1; - reg [31:0] addr; // @[TLULReader.scala 35:21:@103.4] + reg [31:0] addr; // @[TLULReader.scala 35:21:@111.4] reg [31:0] _RAND_2; - reg done; // @[TLULReader.scala 36:21:@104.4] + reg valid; // @[TLULReader.scala 36:22:@112.4] reg [31:0] _RAND_3; - wire _T_103; // @[TLULReader.scala 38:31:@105.4] - wire xfer; // @[TLULReader.scala 38:39:@106.4] - wire ready; // @[TLULReader.scala 39:29:@109.4] - wire _T_148; // @[Conditional.scala 37:30:@147.4] - wire _GEN_0; // @[TLULReader.scala 66:27:@152.6] - wire [31:0] _GEN_1; // @[TLULReader.scala 66:27:@152.6] - wire [31:0] _GEN_2; // @[TLULReader.scala 66:27:@152.6] - wire _T_154; // @[TLULReader.scala 73:20:@161.8] - wire _GEN_3; // @[TLULReader.scala 73:28:@162.8] - wire _GEN_4; // @[TLULReader.scala 73:28:@162.8] - wire _GEN_5; // @[TLULReader.scala 73:28:@162.8] - wire _GEN_6; // @[Conditional.scala 39:67:@160.6] - wire _GEN_7; // @[Conditional.scala 39:67:@160.6] - wire _GEN_8; // @[Conditional.scala 39:67:@160.6] - wire _GEN_9; // @[Conditional.scala 40:58:@148.4] - wire _GEN_12; // @[Conditional.scala 40:58:@148.4] - wire [31:0] _GEN_13; // @[Conditional.scala 40:58:@148.4] - wire [31:0] _GEN_14; // @[Conditional.scala 40:58:@148.4] - wire _T_159; // @[TLULReader.scala 82:24:@171.4] - wire [32:0] _T_161; // @[TLULReader.scala 83:18:@173.6] - wire [31:0] _T_162; // @[TLULReader.scala 83:18:@174.6] - wire [32:0] _T_164; // @[TLULReader.scala 84:24:@176.6] - wire [32:0] _T_165; // @[TLULReader.scala 84:24:@177.6] - wire [31:0] _T_166; // @[TLULReader.scala 84:24:@178.6] - wire [31:0] _GEN_15; // @[TLULReader.scala 82:33:@172.4] - wire [31:0] _GEN_16; // @[TLULReader.scala 82:33:@172.4] - assign _T_103 = xferCnt != 32'h0; // @[TLULReader.scala 38:31:@105.4] - assign xfer = _T_103 & io_dataIO_ready; // @[TLULReader.scala 38:39:@106.4] - assign ready = xfer & io_bus_d_valid; // @[TLULReader.scala 39:29:@109.4] - assign _T_148 = 1'h0 == state; // @[Conditional.scala 37:30:@147.4] - assign _GEN_0 = io_xfer_valid ? 1'h1 : state; // @[TLULReader.scala 66:27:@152.6] - assign _GEN_1 = io_xfer_valid ? io_xfer_length : xferCnt; // @[TLULReader.scala 66:27:@152.6] - assign _GEN_2 = io_xfer_valid ? io_xfer_address : addr; // @[TLULReader.scala 66:27:@152.6] - assign _T_154 = xferCnt == 32'h0; // @[TLULReader.scala 73:20:@161.8] - assign _GEN_3 = _T_154 ? 1'h0 : state; // @[TLULReader.scala 73:28:@162.8] - assign _GEN_4 = _T_154 ? 1'h1 : done; // @[TLULReader.scala 73:28:@162.8] - assign _GEN_5 = _T_154 ? 1'h0 : 1'h1; // @[TLULReader.scala 73:28:@162.8] - assign _GEN_6 = state ? _GEN_3 : state; // @[Conditional.scala 39:67:@160.6] - assign _GEN_7 = state ? _GEN_4 : done; // @[Conditional.scala 39:67:@160.6] - assign _GEN_8 = state ? _GEN_5 : 1'h0; // @[Conditional.scala 39:67:@160.6] - assign _GEN_9 = _T_148 ? 1'h0 : _GEN_7; // @[Conditional.scala 40:58:@148.4] - assign _GEN_12 = _T_148 ? _GEN_0 : _GEN_6; // @[Conditional.scala 40:58:@148.4] - assign _GEN_13 = _T_148 ? _GEN_1 : xferCnt; // @[Conditional.scala 40:58:@148.4] - assign _GEN_14 = _T_148 ? _GEN_2 : addr; // @[Conditional.scala 40:58:@148.4] - assign _T_159 = _T_103 & ready; // @[TLULReader.scala 82:24:@171.4] - assign _T_161 = addr + 32'h4; // @[TLULReader.scala 83:18:@173.6] - assign _T_162 = addr + 32'h4; // @[TLULReader.scala 83:18:@174.6] - assign _T_164 = xferCnt - 32'h1; // @[TLULReader.scala 84:24:@176.6] - assign _T_165 = $unsigned(_T_164); // @[TLULReader.scala 84:24:@177.6] - assign _T_166 = _T_165[31:0]; // @[TLULReader.scala 84:24:@178.6] - assign _GEN_15 = _T_159 ? _T_162 : _GEN_14; // @[TLULReader.scala 82:33:@172.4] - assign _GEN_16 = _T_159 ? _T_166 : _GEN_13; // @[TLULReader.scala 82:33:@172.4] - assign io_bus_a_address = addr; // @[TLULReader.scala 55:20:@143.4] - assign io_bus_a_valid = _T_148 ? 1'h0 : _GEN_8; // @[TLULReader.scala 48:18:@137.4] - assign io_bus_d_ready = 1'h0 == state; // @[TLULReader.scala 42:12:@125.4 TLULReader.scala 64:22:@150.6] - assign io_dataIO_valid = xfer & io_bus_d_valid; // @[TLULReader.scala 46:19:@136.4] - assign io_dataIO_bits = io_bus_d_data; // @[TLULReader.scala 45:18:@135.4] - assign io_xfer_done = done; // @[TLULReader.scala 59:16:@146.4] + wire xfer; // @[TLULReader.scala 40:39:@117.4] + wire _T_146; // @[Conditional.scala 37:30:@153.4] + wire [1:0] _GEN_1; // @[TLULReader.scala 67:18:@159.6] + wire [31:0] _GEN_2; // @[TLULReader.scala 67:18:@159.6] + wire [31:0] _GEN_3; // @[TLULReader.scala 67:18:@159.6] + wire _T_152; // @[Conditional.scala 37:30:@167.6] + wire _T_158; // @[TLULReader.scala 82:22:@175.10] + wire [32:0] _T_160; // @[TLULReader.scala 83:24:@177.12] + wire [31:0] _T_161; // @[TLULReader.scala 83:24:@178.12] + wire [32:0] _T_163; // @[TLULReader.scala 84:30:@180.12] + wire [32:0] _T_164; // @[TLULReader.scala 84:30:@181.12] + wire [31:0] _T_165; // @[TLULReader.scala 84:30:@182.12] + wire [31:0] _GEN_4; // @[TLULReader.scala 82:31:@176.10] + wire [31:0] _GEN_5; // @[TLULReader.scala 82:31:@176.10] + wire _T_168; // @[TLULReader.scala 91:24:@187.12] + wire [1:0] _GEN_6; // @[TLULReader.scala 91:33:@188.12] + wire _GEN_8; // @[TLULReader.scala 91:33:@188.12] + wire [1:0] _GEN_10; // @[TLULReader.scala 88:30:@185.10] + wire _GEN_11; // @[TLULReader.scala 88:30:@185.10] + wire _GEN_12; // @[TLULReader.scala 88:30:@185.10] + wire _GEN_14; // @[TLULReader.scala 77:28:@171.8] + wire [1:0] _GEN_15; // @[TLULReader.scala 77:28:@171.8] + wire [31:0] _GEN_16; // @[TLULReader.scala 77:28:@171.8] + wire [31:0] _GEN_17; // @[TLULReader.scala 77:28:@171.8] + wire _GEN_18; // @[TLULReader.scala 77:28:@171.8] + wire _GEN_19; // @[TLULReader.scala 77:28:@171.8] + wire _T_171; // @[Conditional.scala 37:30:@200.8] + wire _T_178; // @[TLULReader.scala 108:22:@208.12] + wire [1:0] _GEN_20; // @[TLULReader.scala 108:31:@209.12] + wire _GEN_22; // @[TLULReader.scala 108:31:@209.12] + wire [1:0] _GEN_24; // @[TLULReader.scala 105:28:@205.10] + wire _GEN_25; // @[TLULReader.scala 105:28:@205.10] + wire _GEN_26; // @[TLULReader.scala 105:28:@205.10] + wire _GEN_27; // @[Conditional.scala 39:67:@201.8] + wire _GEN_28; // @[Conditional.scala 39:67:@201.8] + wire [1:0] _GEN_30; // @[Conditional.scala 39:67:@201.8] + wire _GEN_31; // @[Conditional.scala 39:67:@201.8] + wire _GEN_32; // @[Conditional.scala 39:67:@168.6] + wire _GEN_33; // @[Conditional.scala 39:67:@168.6] + wire _GEN_34; // @[Conditional.scala 39:67:@168.6] + wire [1:0] _GEN_35; // @[Conditional.scala 39:67:@168.6] + wire [31:0] _GEN_36; // @[Conditional.scala 39:67:@168.6] + wire [31:0] _GEN_37; // @[Conditional.scala 39:67:@168.6] + wire _GEN_38; // @[Conditional.scala 39:67:@168.6] + wire _GEN_39; // @[Conditional.scala 40:58:@154.4] + wire [1:0] _GEN_43; // @[Conditional.scala 40:58:@154.4] + wire [31:0] _GEN_44; // @[Conditional.scala 40:58:@154.4] + wire [31:0] _GEN_45; // @[Conditional.scala 40:58:@154.4] + assign xfer = io_dataIO_ready & io_xfer_valid; // @[TLULReader.scala 40:39:@117.4] + assign _T_146 = 2'h0 == state; // @[Conditional.scala 37:30:@153.4] + assign _GEN_1 = xfer ? 2'h1 : state; // @[TLULReader.scala 67:18:@159.6] + assign _GEN_2 = xfer ? io_xfer_length : xferCnt; // @[TLULReader.scala 67:18:@159.6] + assign _GEN_3 = xfer ? io_xfer_address : addr; // @[TLULReader.scala 67:18:@159.6] + assign _T_152 = 2'h1 == state; // @[Conditional.scala 37:30:@167.6] + assign _T_158 = xferCnt != 32'h0; // @[TLULReader.scala 82:22:@175.10] + assign _T_160 = addr + 32'h4; // @[TLULReader.scala 83:24:@177.12] + assign _T_161 = addr + 32'h4; // @[TLULReader.scala 83:24:@178.12] + assign _T_163 = xferCnt - 32'h1; // @[TLULReader.scala 84:30:@180.12] + assign _T_164 = $unsigned(_T_163); // @[TLULReader.scala 84:30:@181.12] + assign _T_165 = _T_164[31:0]; // @[TLULReader.scala 84:30:@182.12] + assign _GEN_4 = _T_158 ? _T_161 : addr; // @[TLULReader.scala 82:31:@176.10] + assign _GEN_5 = _T_158 ? _T_165 : xferCnt; // @[TLULReader.scala 82:31:@176.10] + assign _T_168 = xferCnt == 32'h1; // @[TLULReader.scala 91:24:@187.12] + assign _GEN_6 = _T_168 ? 2'h0 : 2'h1; // @[TLULReader.scala 91:33:@188.12] + assign _GEN_8 = _T_168 ? 1'h0 : 1'h1; // @[TLULReader.scala 91:33:@188.12] + assign _GEN_10 = io_bus_d_valid ? _GEN_6 : 2'h2; // @[TLULReader.scala 88:30:@185.10] + assign _GEN_11 = io_bus_d_valid ? _T_168 : 1'h0; // @[TLULReader.scala 88:30:@185.10] + assign _GEN_12 = io_bus_d_valid ? _GEN_8 : 1'h0; // @[TLULReader.scala 88:30:@185.10] + assign _GEN_14 = io_bus_a_ready ? _GEN_12 : valid; // @[TLULReader.scala 77:28:@171.8] + assign _GEN_15 = io_bus_a_ready ? _GEN_10 : state; // @[TLULReader.scala 77:28:@171.8] + assign _GEN_16 = io_bus_a_ready ? _GEN_4 : addr; // @[TLULReader.scala 77:28:@171.8] + assign _GEN_17 = io_bus_a_ready ? _GEN_5 : xferCnt; // @[TLULReader.scala 77:28:@171.8] + assign _GEN_18 = io_bus_a_ready ? io_bus_d_valid : 1'h0; // @[TLULReader.scala 77:28:@171.8] + assign _GEN_19 = io_bus_a_ready ? _GEN_11 : 1'h0; // @[TLULReader.scala 77:28:@171.8] + assign _T_171 = 2'h2 == state; // @[Conditional.scala 37:30:@200.8] + assign _T_178 = xferCnt == 32'h0; // @[TLULReader.scala 108:22:@208.12] + assign _GEN_20 = _T_178 ? 2'h0 : 2'h1; // @[TLULReader.scala 108:31:@209.12] + assign _GEN_22 = _T_178 ? 1'h0 : 1'h1; // @[TLULReader.scala 108:31:@209.12] + assign _GEN_24 = io_bus_d_valid ? _GEN_20 : state; // @[TLULReader.scala 105:28:@205.10] + assign _GEN_25 = io_bus_d_valid ? _T_178 : 1'h0; // @[TLULReader.scala 105:28:@205.10] + assign _GEN_26 = io_bus_d_valid ? _GEN_22 : 1'h0; // @[TLULReader.scala 105:28:@205.10] + assign _GEN_27 = _T_171 ? _GEN_26 : valid; // @[Conditional.scala 39:67:@201.8] + assign _GEN_28 = _T_171 ? io_bus_d_valid : 1'h0; // @[Conditional.scala 39:67:@201.8] + assign _GEN_30 = _T_171 ? _GEN_24 : state; // @[Conditional.scala 39:67:@201.8] + assign _GEN_31 = _T_171 ? _GEN_25 : 1'h0; // @[Conditional.scala 39:67:@201.8] + assign _GEN_32 = _T_152 ? io_bus_a_ready : _T_171; // @[Conditional.scala 39:67:@168.6] + assign _GEN_33 = _T_152 ? _GEN_18 : _GEN_28; // @[Conditional.scala 39:67:@168.6] + assign _GEN_34 = _T_152 ? _GEN_14 : _GEN_27; // @[Conditional.scala 39:67:@168.6] + assign _GEN_35 = _T_152 ? _GEN_15 : _GEN_30; // @[Conditional.scala 39:67:@168.6] + assign _GEN_36 = _T_152 ? _GEN_16 : addr; // @[Conditional.scala 39:67:@168.6] + assign _GEN_37 = _T_152 ? _GEN_17 : xferCnt; // @[Conditional.scala 39:67:@168.6] + assign _GEN_38 = _T_152 ? _GEN_19 : _GEN_31; // @[Conditional.scala 39:67:@168.6] + assign _GEN_39 = _T_146 ? xfer : _GEN_34; // @[Conditional.scala 40:58:@154.4] + assign _GEN_43 = _T_146 ? _GEN_1 : _GEN_35; // @[Conditional.scala 40:58:@154.4] + assign _GEN_44 = _T_146 ? _GEN_2 : _GEN_37; // @[Conditional.scala 40:58:@154.4] + assign _GEN_45 = _T_146 ? _GEN_3 : _GEN_36; // @[Conditional.scala 40:58:@154.4] + assign io_bus_a_address = addr; // @[TLULReader.scala 55:20:@149.4] + assign io_bus_a_valid = valid; // @[TLULReader.scala 48:18:@143.4] + assign io_bus_d_ready = _T_146 ? 1'h0 : _GEN_32; // @[TLULReader.scala 42:12:@131.4 TLULReader.scala 64:22:@156.6 TLULReader.scala 75:22:@169.8 TLULReader.scala 78:24:@172.10 TLULReader.scala 104:22:@204.10 TLULReader.scala 106:24:@206.12] + assign io_dataIO_valid = _T_146 ? 1'h0 : _GEN_33; // @[TLULReader.scala 46:19:@142.4] + assign io_dataIO_bits = io_bus_d_data; // @[TLULReader.scala 45:18:@141.4] + assign io_xfer_done = _T_146 ? 1'h0 : _GEN_38; // @[TLULReader.scala 59:16:@152.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -296,7 +376,7 @@ `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - state = _RAND_0[0:0]; + state = _RAND_0[1:0]; `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; @@ -308,22 +388,40 @@ `endif // RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT _RAND_3 = {1{`RANDOM}}; - done = _RAND_3[0:0]; + valid = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT end `endif // RANDOMIZE always @(posedge clock) begin if (reset) begin - state <= 1'h0; + state <= 2'h0; end else begin - if (_T_148) begin - if (io_xfer_valid) begin - state <= 1'h1; + if (_T_146) begin + if (xfer) begin + state <= 2'h1; end end else begin - if (state) begin - if (_T_154) begin - state <= 1'h0; + if (_T_152) begin + if (io_bus_a_ready) begin + if (io_bus_d_valid) begin + if (_T_168) begin + state <= 2'h0; + end else begin + state <= 2'h1; + end + end else begin + state <= 2'h2; + end + end + end else begin + if (_T_171) begin + if (io_bus_d_valid) begin + if (_T_178) begin + state <= 2'h0; + end else begin + state <= 2'h1; + end + end end end end @@ -331,12 +429,16 @@ if (reset) begin xferCnt <= 32'h0; end else begin - if (_T_159) begin - xferCnt <= _T_166; + if (_T_146) begin + if (xfer) begin + xferCnt <= io_xfer_length; + end end else begin - if (_T_148) begin - if (io_xfer_valid) begin - xferCnt <= io_xfer_length; + if (_T_152) begin + if (io_bus_a_ready) begin + if (_T_158) begin + xferCnt <= _T_165; + end end end end @@ -344,523 +446,663 @@ if (reset) begin addr <= 32'h0; end else begin - if (_T_159) begin - addr <= _T_162; + if (_T_146) begin + if (xfer) begin + addr <= io_xfer_address; + end end else begin - if (_T_148) begin - if (io_xfer_valid) begin - addr <= io_xfer_address; + if (_T_152) begin + if (io_bus_a_ready) begin + if (_T_158) begin + addr <= _T_161; + end end end end end if (reset) begin - done <= 1'h0; + valid <= 1'h0; end else begin - if (_T_148) begin - done <= 1'h0; + if (_T_146) begin + valid <= xfer; end else begin - if (state) begin - if (_T_154) begin - done <= 1'h1; + if (_T_152) begin + if (io_bus_a_ready) begin + if (io_bus_d_valid) begin + if (_T_168) begin + valid <= 1'h0; + end else begin + valid <= 1'h1; + end + end else begin + valid <= 1'h0; + end + end + end else begin + if (_T_171) begin + if (io_bus_d_valid) begin + if (_T_178) begin + valid <= 1'h0; + end else begin + valid <= 1'h1; + end + end else begin + valid <= 1'h0; + end end end end end end endmodule -module TLULWriterTL_TL_TL( // @[:@182.2] - input clock, // @[:@183.4] - input reset, // @[:@184.4] - output [31:0] io_bus_a_address, // @[:@185.4] - output [31:0] io_bus_a_data, // @[:@185.4] - output io_bus_a_valid, // @[:@185.4] - input io_bus_d_valid, // @[:@185.4] - output io_bus_d_ready, // @[:@185.4] - output io_dataIO_ready, // @[:@185.4] - input io_dataIO_valid, // @[:@185.4] - input [31:0] io_dataIO_bits, // @[:@185.4] - output io_xfer_done, // @[:@185.4] - input [31:0] io_xfer_address, // @[:@185.4] - input [31:0] io_xfer_length, // @[:@185.4] - input io_xfer_valid // @[:@185.4] +module TLULWriterTL_TL_TL( // @[:@220.2] + input clock, // @[:@221.4] + input reset, // @[:@222.4] + output [31:0] io_bus_a_address, // @[:@223.4] + output [31:0] io_bus_a_data, // @[:@223.4] + output io_bus_a_valid, // @[:@223.4] + input io_bus_a_ready, // @[:@223.4] + input io_bus_d_valid, // @[:@223.4] + output io_bus_d_ready, // @[:@223.4] + output io_dataIO_ready, // @[:@223.4] + input io_dataIO_valid, // @[:@223.4] + input [31:0] io_dataIO_bits, // @[:@223.4] + output io_xfer_done, // @[:@223.4] + input [31:0] io_xfer_address, // @[:@223.4] + input [31:0] io_xfer_length, // @[:@223.4] + input io_xfer_valid // @[:@223.4] ); - reg state; // @[TLULWriter.scala 32:22:@187.4] + reg [1:0] state; // @[TLULWriter.scala 32:22:@225.4] reg [31:0] _RAND_0; - reg [31:0] xferCnt; // @[TLULWriter.scala 34:24:@188.4] + reg [31:0] xferCnt; // @[TLULWriter.scala 34:24:@226.4] reg [31:0] _RAND_1; - reg [31:0] addr; // @[TLULWriter.scala 35:21:@189.4] + reg [31:0] addr; // @[TLULWriter.scala 35:21:@227.4] reg [31:0] _RAND_2; - reg done; // @[TLULWriter.scala 36:21:@190.4] + reg addrValid; // @[TLULWriter.scala 36:26:@228.4] reg [31:0] _RAND_3; - wire _T_109; // @[TLULWriter.scala 38:31:@191.4] - wire xfer; // @[TLULWriter.scala 38:39:@192.4] - wire ready; // @[TLULWriter.scala 39:29:@195.4] - wire _T_153; // @[Conditional.scala 37:30:@232.4] - wire _GEN_0; // @[TLULWriter.scala 66:27:@237.6] - wire [31:0] _GEN_1; // @[TLULWriter.scala 66:27:@237.6] - wire [31:0] _GEN_2; // @[TLULWriter.scala 66:27:@237.6] - wire _T_159; // @[TLULWriter.scala 73:20:@246.8] - wire _GEN_3; // @[TLULWriter.scala 73:28:@247.8] - wire _GEN_4; // @[TLULWriter.scala 73:28:@247.8] - wire _GEN_5; // @[TLULWriter.scala 73:28:@247.8] - wire _GEN_6; // @[Conditional.scala 39:67:@245.6] - wire _GEN_7; // @[Conditional.scala 39:67:@245.6] - wire _GEN_8; // @[Conditional.scala 39:67:@245.6] - wire _GEN_9; // @[Conditional.scala 40:58:@233.4] - wire _GEN_12; // @[Conditional.scala 40:58:@233.4] - wire [31:0] _GEN_13; // @[Conditional.scala 40:58:@233.4] - wire [31:0] _GEN_14; // @[Conditional.scala 40:58:@233.4] - wire _T_164; // @[TLULWriter.scala 82:24:@256.4] - wire [32:0] _T_166; // @[TLULWriter.scala 83:18:@258.6] - wire [31:0] _T_167; // @[TLULWriter.scala 83:18:@259.6] - wire [32:0] _T_169; // @[TLULWriter.scala 84:24:@261.6] - wire [32:0] _T_170; // @[TLULWriter.scala 84:24:@262.6] - wire [31:0] _T_171; // @[TLULWriter.scala 84:24:@263.6] - wire [31:0] _GEN_15; // @[TLULWriter.scala 82:33:@257.4] - wire [31:0] _GEN_16; // @[TLULWriter.scala 82:33:@257.4] - assign _T_109 = xferCnt != 32'h0; // @[TLULWriter.scala 38:31:@191.4] - assign xfer = _T_109 & io_dataIO_valid; // @[TLULWriter.scala 38:39:@192.4] - assign ready = xfer & io_bus_d_valid; // @[TLULWriter.scala 39:29:@195.4] - assign _T_153 = 1'h0 == state; // @[Conditional.scala 37:30:@232.4] - assign _GEN_0 = io_xfer_valid ? 1'h1 : state; // @[TLULWriter.scala 66:27:@237.6] - assign _GEN_1 = io_xfer_valid ? io_xfer_length : xferCnt; // @[TLULWriter.scala 66:27:@237.6] - assign _GEN_2 = io_xfer_valid ? io_xfer_address : addr; // @[TLULWriter.scala 66:27:@237.6] - assign _T_159 = xferCnt == 32'h0; // @[TLULWriter.scala 73:20:@246.8] - assign _GEN_3 = _T_159 ? 1'h0 : state; // @[TLULWriter.scala 73:28:@247.8] - assign _GEN_4 = _T_159 ? 1'h1 : done; // @[TLULWriter.scala 73:28:@247.8] - assign _GEN_5 = _T_159 ? 1'h0 : 1'h1; // @[TLULWriter.scala 73:28:@247.8] - assign _GEN_6 = state ? _GEN_3 : state; // @[Conditional.scala 39:67:@245.6] - assign _GEN_7 = state ? _GEN_4 : done; // @[Conditional.scala 39:67:@245.6] - assign _GEN_8 = state ? _GEN_5 : 1'h0; // @[Conditional.scala 39:67:@245.6] - assign _GEN_9 = _T_153 ? 1'h0 : _GEN_7; // @[Conditional.scala 40:58:@233.4] - assign _GEN_12 = _T_153 ? _GEN_0 : _GEN_6; // @[Conditional.scala 40:58:@233.4] - assign _GEN_13 = _T_153 ? _GEN_1 : xferCnt; // @[Conditional.scala 40:58:@233.4] - assign _GEN_14 = _T_153 ? _GEN_2 : addr; // @[Conditional.scala 40:58:@233.4] - assign _T_164 = _T_109 & ready; // @[TLULWriter.scala 82:24:@256.4] - assign _T_166 = addr + 32'h4; // @[TLULWriter.scala 83:18:@258.6] - assign _T_167 = addr + 32'h4; // @[TLULWriter.scala 83:18:@259.6] - assign _T_169 = xferCnt - 32'h1; // @[TLULWriter.scala 84:24:@261.6] - assign _T_170 = $unsigned(_T_169); // @[TLULWriter.scala 84:24:@262.6] - assign _T_171 = _T_170[31:0]; // @[TLULWriter.scala 84:24:@263.6] - assign _GEN_15 = _T_164 ? _T_167 : _GEN_14; // @[TLULWriter.scala 82:33:@257.4] - assign _GEN_16 = _T_164 ? _T_171 : _GEN_13; // @[TLULWriter.scala 82:33:@257.4] - assign io_bus_a_address = addr; // @[TLULWriter.scala 55:20:@228.4] - assign io_bus_a_data = io_dataIO_bits; // @[TLULWriter.scala 48:17:@223.4] - assign io_bus_a_valid = _T_153 ? 1'h0 : _GEN_8; // @[TLULWriter.scala 47:18:@222.4] - assign io_bus_d_ready = 1'h0 == state; // @[TLULWriter.scala 42:12:@211.4 TLULWriter.scala 64:22:@235.6] - assign io_dataIO_ready = xfer & io_bus_d_valid; // @[TLULWriter.scala 45:19:@221.4] - assign io_xfer_done = done; // @[TLULWriter.scala 59:16:@231.4] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE - integer initvar; - initial begin - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - #0.002 begin end - `endif - `ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - state = _RAND_0[0:0]; - `endif // RANDOMIZE_REG_INIT - `ifdef RANDOMIZE_REG_INIT - _RAND_1 = {1{`RANDOM}}; - xferCnt = _RAND_1[31:0]; - `endif // RANDOMIZE_REG_INIT - `ifdef RANDOMIZE_REG_INIT - _RAND_2 = {1{`RANDOM}}; - addr = _RAND_2[31:0]; - `endif // RANDOMIZE_REG_INIT - `ifdef RANDOMIZE_REG_INIT - _RAND_3 = {1{`RANDOM}}; - done = _RAND_3[0:0]; - `endif // RANDOMIZE_REG_INIT - end -`endif // RANDOMIZE - always @(posedge clock) begin - if (reset) begin - state <= 1'h0; - end else begin - if (_T_153) begin - if (io_xfer_valid) begin - state <= 1'h1; - end - end else begin - if (state) begin - if (_T_159) begin - state <= 1'h0; - end - end - end - end - if (reset) begin - xferCnt <= 32'h0; - end else begin - if (_T_164) begin - xferCnt <= _T_171; - end else begin - if (_T_153) begin - if (io_xfer_valid) begin - xferCnt <= io_xfer_length; - end - end - end - end - if (reset) begin - addr <= 32'h0; - end else begin - if (_T_164) begin - addr <= _T_167; - end else begin - if (_T_153) begin - if (io_xfer_valid) begin - addr <= io_xfer_address; - end - end - end - end - if (reset) begin - done <= 1'h0; - end else begin - if (_T_153) begin - done <= 1'h0; - end else begin - if (state) begin - if (_T_159) begin - done <= 1'h1; - end - end - end - end - end -endmodule -module CSRTL_TL_TL( // @[:@267.2] - output [31:0] io_csr_0_dataOut, // @[:@270.4] - output io_csr_0_dataWrite, // @[:@270.4] - input [31:0] io_csr_0_dataIn, // @[:@270.4] - input [31:0] io_csr_1_dataIn, // @[:@270.4] - output [31:0] io_csr_2_dataOut, // @[:@270.4] - output io_csr_2_dataWrite, // @[:@270.4] - input [31:0] io_csr_2_dataIn, // @[:@270.4] - output [31:0] io_csr_3_dataOut, // @[:@270.4] - output io_csr_3_dataWrite, // @[:@270.4] - input [31:0] io_csr_3_dataIn, // @[:@270.4] - output [31:0] io_csr_4_dataOut, // @[:@270.4] - output io_csr_4_dataWrite, // @[:@270.4] - input [31:0] io_csr_4_dataIn, // @[:@270.4] - output [31:0] io_csr_5_dataOut, // @[:@270.4] - output io_csr_5_dataWrite, // @[:@270.4] - input [31:0] io_csr_5_dataIn, // @[:@270.4] - output [31:0] io_csr_6_dataOut, // @[:@270.4] - output io_csr_6_dataWrite, // @[:@270.4] - input [31:0] io_csr_6_dataIn, // @[:@270.4] - output [31:0] io_csr_7_dataOut, // @[:@270.4] - output io_csr_7_dataWrite, // @[:@270.4] - input [31:0] io_csr_7_dataIn, // @[:@270.4] - output [31:0] io_csr_8_dataOut, // @[:@270.4] - output io_csr_8_dataWrite, // @[:@270.4] - input [31:0] io_csr_8_dataIn, // @[:@270.4] - output [31:0] io_csr_9_dataOut, // @[:@270.4] - output io_csr_9_dataWrite, // @[:@270.4] - input [31:0] io_csr_9_dataIn, // @[:@270.4] - output [31:0] io_csr_10_dataOut, // @[:@270.4] - output io_csr_10_dataWrite, // @[:@270.4] - input [31:0] io_csr_10_dataIn, // @[:@270.4] - output [31:0] io_csr_11_dataOut, // @[:@270.4] - output io_csr_11_dataWrite, // @[:@270.4] - input [31:0] io_csr_11_dataIn, // @[:@270.4] - input [31:0] io_csr_12_dataIn, // @[:@270.4] - input [31:0] io_csr_13_dataIn, // @[:@270.4] - output [31:0] io_csr_14_dataOut, // @[:@270.4] - output io_csr_14_dataWrite, // @[:@270.4] - input [31:0] io_csr_14_dataIn, // @[:@270.4] - output [31:0] io_csr_15_dataOut, // @[:@270.4] - output io_csr_15_dataWrite, // @[:@270.4] - input [31:0] io_csr_15_dataIn, // @[:@270.4] - input [3:0] io_bus_addr, // @[:@270.4] - input [31:0] io_bus_dataOut, // @[:@270.4] - output [31:0] io_bus_dataIn, // @[:@270.4] - input io_bus_write, // @[:@270.4] - input io_bus_read // @[:@270.4] -); - wire _T_178; // @[CSR.scala 32:22:@275.4] - wire _T_179; // @[CSR.scala 32:30:@276.4] - wire [31:0] _GEN_0; // @[CSR.scala 32:45:@277.4] - wire _T_184; // @[CSR.scala 39:30:@285.4] - wire _T_189; // @[CSR.scala 32:22:@294.4] - wire _T_190; // @[CSR.scala 32:30:@295.4] - wire [31:0] _GEN_4; // @[CSR.scala 32:45:@296.4] - wire _T_200; // @[CSR.scala 32:22:@313.4] - wire _T_201; // @[CSR.scala 32:30:@314.4] - wire [31:0] _GEN_8; // @[CSR.scala 32:45:@315.4] - wire _T_206; // @[CSR.scala 39:30:@323.4] - wire _T_211; // @[CSR.scala 32:22:@332.4] - wire _T_212; // @[CSR.scala 32:30:@333.4] - wire [31:0] _GEN_12; // @[CSR.scala 32:45:@334.4] - wire _T_217; // @[CSR.scala 39:30:@342.4] - wire _T_222; // @[CSR.scala 32:22:@351.4] - wire _T_223; // @[CSR.scala 32:30:@352.4] - wire [31:0] _GEN_16; // @[CSR.scala 32:45:@353.4] - wire _T_228; // @[CSR.scala 39:30:@361.4] - wire _T_233; // @[CSR.scala 32:22:@370.4] - wire _T_234; // @[CSR.scala 32:30:@371.4] - wire [31:0] _GEN_20; // @[CSR.scala 32:45:@372.4] - wire _T_239; // @[CSR.scala 39:30:@380.4] - wire _T_244; // @[CSR.scala 32:22:@389.4] - wire _T_245; // @[CSR.scala 32:30:@390.4] - wire [31:0] _GEN_24; // @[CSR.scala 32:45:@391.4] - wire _T_250; // @[CSR.scala 39:30:@399.4] - wire _T_255; // @[CSR.scala 32:22:@408.4] - wire _T_256; // @[CSR.scala 32:30:@409.4] - wire [31:0] _GEN_28; // @[CSR.scala 32:45:@410.4] - wire _T_261; // @[CSR.scala 39:30:@418.4] - wire _T_266; // @[CSR.scala 32:22:@427.4] - wire _T_267; // @[CSR.scala 32:30:@428.4] - wire [31:0] _GEN_32; // @[CSR.scala 32:45:@429.4] - wire _T_272; // @[CSR.scala 39:30:@437.4] - wire _T_277; // @[CSR.scala 32:22:@446.4] - wire _T_278; // @[CSR.scala 32:30:@447.4] - wire [31:0] _GEN_36; // @[CSR.scala 32:45:@448.4] - wire _T_283; // @[CSR.scala 39:30:@456.4] - wire _T_288; // @[CSR.scala 32:22:@465.4] - wire _T_289; // @[CSR.scala 32:30:@466.4] - wire [31:0] _GEN_40; // @[CSR.scala 32:45:@467.4] - wire _T_294; // @[CSR.scala 39:30:@475.4] - wire _T_299; // @[CSR.scala 32:22:@484.4] - wire _T_300; // @[CSR.scala 32:30:@485.4] - wire [31:0] _GEN_44; // @[CSR.scala 32:45:@486.4] - wire _T_305; // @[CSR.scala 39:30:@494.4] - wire _T_310; // @[CSR.scala 32:22:@503.4] - wire _T_311; // @[CSR.scala 32:30:@504.4] - wire [31:0] _GEN_48; // @[CSR.scala 32:45:@505.4] - wire _T_321; // @[CSR.scala 32:22:@522.4] - wire _T_322; // @[CSR.scala 32:30:@523.4] - wire [31:0] _GEN_52; // @[CSR.scala 32:45:@524.4] - wire _T_332; // @[CSR.scala 32:22:@541.4] - wire _T_333; // @[CSR.scala 32:30:@542.4] - wire [31:0] _GEN_56; // @[CSR.scala 32:45:@543.4] - wire _T_338; // @[CSR.scala 39:30:@551.4] - wire _T_343; // @[CSR.scala 32:22:@560.4] - wire _T_344; // @[CSR.scala 32:30:@561.4] - wire _T_349; // @[CSR.scala 39:30:@570.4] - assign _T_178 = io_bus_addr == 4'h0; // @[CSR.scala 32:22:@275.4] - assign _T_179 = _T_178 & io_bus_read; // @[CSR.scala 32:30:@276.4] - assign _GEN_0 = _T_179 ? io_csr_0_dataIn : 32'h0; // @[CSR.scala 32:45:@277.4] - assign _T_184 = _T_178 & io_bus_write; // @[CSR.scala 39:30:@285.4] - assign _T_189 = io_bus_addr == 4'h1; // @[CSR.scala 32:22:@294.4] - assign _T_190 = _T_189 & io_bus_read; // @[CSR.scala 32:30:@295.4] - assign _GEN_4 = _T_190 ? io_csr_1_dataIn : _GEN_0; // @[CSR.scala 32:45:@296.4] - assign _T_200 = io_bus_addr == 4'h2; // @[CSR.scala 32:22:@313.4] - assign _T_201 = _T_200 & io_bus_read; // @[CSR.scala 32:30:@314.4] - assign _GEN_8 = _T_201 ? io_csr_2_dataIn : _GEN_4; // @[CSR.scala 32:45:@315.4] - assign _T_206 = _T_200 & io_bus_write; // @[CSR.scala 39:30:@323.4] - assign _T_211 = io_bus_addr == 4'h3; // @[CSR.scala 32:22:@332.4] - assign _T_212 = _T_211 & io_bus_read; // @[CSR.scala 32:30:@333.4] - assign _GEN_12 = _T_212 ? io_csr_3_dataIn : _GEN_8; // @[CSR.scala 32:45:@334.4] - assign _T_217 = _T_211 & io_bus_write; // @[CSR.scala 39:30:@342.4] - assign _T_222 = io_bus_addr == 4'h4; // @[CSR.scala 32:22:@351.4] - assign _T_223 = _T_222 & io_bus_read; // @[CSR.scala 32:30:@352.4] - assign _GEN_16 = _T_223 ? io_csr_4_dataIn : _GEN_12; // @[CSR.scala 32:45:@353.4] - assign _T_228 = _T_222 & io_bus_write; // @[CSR.scala 39:30:@361.4] - assign _T_233 = io_bus_addr == 4'h5; // @[CSR.scala 32:22:@370.4] - assign _T_234 = _T_233 & io_bus_read; // @[CSR.scala 32:30:@371.4] - assign _GEN_20 = _T_234 ? io_csr_5_dataIn : _GEN_16; // @[CSR.scala 32:45:@372.4] - assign _T_239 = _T_233 & io_bus_write; // @[CSR.scala 39:30:@380.4] - assign _T_244 = io_bus_addr == 4'h6; // @[CSR.scala 32:22:@389.4] - assign _T_245 = _T_244 & io_bus_read; // @[CSR.scala 32:30:@390.4] - assign _GEN_24 = _T_245 ? io_csr_6_dataIn : _GEN_20; // @[CSR.scala 32:45:@391.4] - assign _T_250 = _T_244 & io_bus_write; // @[CSR.scala 39:30:@399.4] - assign _T_255 = io_bus_addr == 4'h7; // @[CSR.scala 32:22:@408.4] - assign _T_256 = _T_255 & io_bus_read; // @[CSR.scala 32:30:@409.4] - assign _GEN_28 = _T_256 ? io_csr_7_dataIn : _GEN_24; // @[CSR.scala 32:45:@410.4] - assign _T_261 = _T_255 & io_bus_write; // @[CSR.scala 39:30:@418.4] - assign _T_266 = io_bus_addr == 4'h8; // @[CSR.scala 32:22:@427.4] - assign _T_267 = _T_266 & io_bus_read; // @[CSR.scala 32:30:@428.4] - assign _GEN_32 = _T_267 ? io_csr_8_dataIn : _GEN_28; // @[CSR.scala 32:45:@429.4] - assign _T_272 = _T_266 & io_bus_write; // @[CSR.scala 39:30:@437.4] - assign _T_277 = io_bus_addr == 4'h9; // @[CSR.scala 32:22:@446.4] - assign _T_278 = _T_277 & io_bus_read; // @[CSR.scala 32:30:@447.4] - assign _GEN_36 = _T_278 ? io_csr_9_dataIn : _GEN_32; // @[CSR.scala 32:45:@448.4] - assign _T_283 = _T_277 & io_bus_write; // @[CSR.scala 39:30:@456.4] - assign _T_288 = io_bus_addr == 4'ha; // @[CSR.scala 32:22:@465.4] - assign _T_289 = _T_288 & io_bus_read; // @[CSR.scala 32:30:@466.4] - assign _GEN_40 = _T_289 ? io_csr_10_dataIn : _GEN_36; // @[CSR.scala 32:45:@467.4] - assign _T_294 = _T_288 & io_bus_write; // @[CSR.scala 39:30:@475.4] - assign _T_299 = io_bus_addr == 4'hb; // @[CSR.scala 32:22:@484.4] - assign _T_300 = _T_299 & io_bus_read; // @[CSR.scala 32:30:@485.4] - assign _GEN_44 = _T_300 ? io_csr_11_dataIn : _GEN_40; // @[CSR.scala 32:45:@486.4] - assign _T_305 = _T_299 & io_bus_write; // @[CSR.scala 39:30:@494.4] - assign _T_310 = io_bus_addr == 4'hc; // @[CSR.scala 32:22:@503.4] - assign _T_311 = _T_310 & io_bus_read; // @[CSR.scala 32:30:@504.4] - assign _GEN_48 = _T_311 ? io_csr_12_dataIn : _GEN_44; // @[CSR.scala 32:45:@505.4] - assign _T_321 = io_bus_addr == 4'hd; // @[CSR.scala 32:22:@522.4] - assign _T_322 = _T_321 & io_bus_read; // @[CSR.scala 32:30:@523.4] - assign _GEN_52 = _T_322 ? io_csr_13_dataIn : _GEN_48; // @[CSR.scala 32:45:@524.4] - assign _T_332 = io_bus_addr == 4'he; // @[CSR.scala 32:22:@541.4] - assign _T_333 = _T_332 & io_bus_read; // @[CSR.scala 32:30:@542.4] - assign _GEN_56 = _T_333 ? io_csr_14_dataIn : _GEN_52; // @[CSR.scala 32:45:@543.4] - assign _T_338 = _T_332 & io_bus_write; // @[CSR.scala 39:30:@551.4] - assign _T_343 = io_bus_addr == 4'hf; // @[CSR.scala 32:22:@560.4] - assign _T_344 = _T_343 & io_bus_read; // @[CSR.scala 32:30:@561.4] - assign _T_349 = _T_343 & io_bus_write; // @[CSR.scala 39:30:@570.4] - assign io_csr_0_dataOut = _T_184 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@287.6 CSR.scala 44:25:@292.6] - assign io_csr_0_dataWrite = _T_178 & io_bus_write; // @[CSR.scala 41:27:@288.6 CSR.scala 43:27:@291.6] - assign io_csr_2_dataOut = _T_206 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@325.6 CSR.scala 44:25:@330.6] - assign io_csr_2_dataWrite = _T_200 & io_bus_write; // @[CSR.scala 41:27:@326.6 CSR.scala 43:27:@329.6] - assign io_csr_3_dataOut = _T_217 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@344.6 CSR.scala 44:25:@349.6] - assign io_csr_3_dataWrite = _T_211 & io_bus_write; // @[CSR.scala 41:27:@345.6 CSR.scala 43:27:@348.6] - assign io_csr_4_dataOut = _T_228 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@363.6 CSR.scala 44:25:@368.6] - assign io_csr_4_dataWrite = _T_222 & io_bus_write; // @[CSR.scala 41:27:@364.6 CSR.scala 43:27:@367.6] - assign io_csr_5_dataOut = _T_239 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@382.6 CSR.scala 44:25:@387.6] - assign io_csr_5_dataWrite = _T_233 & io_bus_write; // @[CSR.scala 41:27:@383.6 CSR.scala 43:27:@386.6] - assign io_csr_6_dataOut = _T_250 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@401.6 CSR.scala 44:25:@406.6] - assign io_csr_6_dataWrite = _T_244 & io_bus_write; // @[CSR.scala 41:27:@402.6 CSR.scala 43:27:@405.6] - assign io_csr_7_dataOut = _T_261 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@420.6 CSR.scala 44:25:@425.6] - assign io_csr_7_dataWrite = _T_255 & io_bus_write; // @[CSR.scala 41:27:@421.6 CSR.scala 43:27:@424.6] - assign io_csr_8_dataOut = _T_272 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@439.6 CSR.scala 44:25:@444.6] - assign io_csr_8_dataWrite = _T_266 & io_bus_write; // @[CSR.scala 41:27:@440.6 CSR.scala 43:27:@443.6] - assign io_csr_9_dataOut = _T_283 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@458.6 CSR.scala 44:25:@463.6] - assign io_csr_9_dataWrite = _T_277 & io_bus_write; // @[CSR.scala 41:27:@459.6 CSR.scala 43:27:@462.6] - assign io_csr_10_dataOut = _T_294 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@477.6 CSR.scala 44:25:@482.6] - assign io_csr_10_dataWrite = _T_288 & io_bus_write; // @[CSR.scala 41:27:@478.6 CSR.scala 43:27:@481.6] - assign io_csr_11_dataOut = _T_305 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@496.6 CSR.scala 44:25:@501.6] - assign io_csr_11_dataWrite = _T_299 & io_bus_write; // @[CSR.scala 41:27:@497.6 CSR.scala 43:27:@500.6] - assign io_csr_14_dataOut = _T_338 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@553.6 CSR.scala 44:25:@558.6] - assign io_csr_14_dataWrite = _T_332 & io_bus_write; // @[CSR.scala 41:27:@554.6 CSR.scala 43:27:@557.6] - assign io_csr_15_dataOut = _T_349 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@572.6 CSR.scala 44:25:@577.6] - assign io_csr_15_dataWrite = _T_343 & io_bus_write; // @[CSR.scala 41:27:@573.6 CSR.scala 43:27:@576.6] - assign io_bus_dataIn = _T_344 ? io_csr_15_dataIn : _GEN_56; // @[CSR.scala 29:17:@274.4] -endmodule -module AddressGeneratorTL_TL_TL( // @[:@580.2] - input clock, // @[:@581.4] - input reset, // @[:@582.4] - input io_ctl_start, // @[:@583.4] - output io_ctl_busy, // @[:@583.4] - input [31:0] io_ctl_startAddress, // @[:@583.4] - input [31:0] io_ctl_lineLength, // @[:@583.4] - input [31:0] io_ctl_lineCount, // @[:@583.4] - input [31:0] io_ctl_lineGap, // @[:@583.4] - input io_xfer_done, // @[:@583.4] - output [31:0] io_xfer_address, // @[:@583.4] - output [31:0] io_xfer_length, // @[:@583.4] - output io_xfer_valid // @[:@583.4] -); - reg [1:0] state; // @[AddressGenerator.scala 29:22:@585.4] - reg [31:0] _RAND_0; - reg [31:0] lineCount; // @[AddressGenerator.scala 31:26:@586.4] - reg [31:0] _RAND_1; - reg [31:0] lineGap; // @[AddressGenerator.scala 32:24:@587.4] - reg [31:0] _RAND_2; - reg [31:0] address_o; // @[AddressGenerator.scala 34:26:@588.4] - reg [31:0] _RAND_3; - reg [31:0] address_i; // @[AddressGenerator.scala 35:26:@589.4] + reg valid; // @[TLULWriter.scala 37:22:@229.4] reg [31:0] _RAND_4; - reg [31:0] length_o; // @[AddressGenerator.scala 36:25:@590.4] + wire _T_151; // @[Conditional.scala 37:30:@266.4] + wire _GEN_0; // @[TLULWriter.scala 70:27:@272.6] + wire _T_157; // @[TLULWriter.scala 74:28:@275.6] + wire [1:0] _GEN_2; // @[TLULWriter.scala 74:42:@276.6] + wire [31:0] _GEN_3; // @[TLULWriter.scala 74:42:@276.6] + wire [31:0] _GEN_4; // @[TLULWriter.scala 74:42:@276.6] + wire _GEN_5; // @[TLULWriter.scala 74:42:@276.6] + wire _T_160; // @[Conditional.scala 37:30:@285.6] + wire _T_166; // @[TLULWriter.scala 90:22:@293.10] + wire [32:0] _T_168; // @[TLULWriter.scala 91:24:@295.12] + wire [31:0] _T_169; // @[TLULWriter.scala 91:24:@296.12] + wire [32:0] _T_171; // @[TLULWriter.scala 92:30:@298.12] + wire [32:0] _T_172; // @[TLULWriter.scala 92:30:@299.12] + wire [31:0] _T_173; // @[TLULWriter.scala 92:30:@300.12] + wire [31:0] _GEN_6; // @[TLULWriter.scala 90:31:@294.10] + wire [31:0] _GEN_7; // @[TLULWriter.scala 90:31:@294.10] + wire _T_176; // @[TLULWriter.scala 99:24:@305.12] + wire [1:0] _GEN_8; // @[TLULWriter.scala 99:33:@306.12] + wire _GEN_10; // @[TLULWriter.scala 99:33:@306.12] + wire [1:0] _GEN_12; // @[TLULWriter.scala 96:30:@303.10] + wire _GEN_13; // @[TLULWriter.scala 96:30:@303.10] + wire _GEN_14; // @[TLULWriter.scala 96:30:@303.10] + wire _GEN_16; // @[TLULWriter.scala 85:28:@289.8] + wire [1:0] _GEN_17; // @[TLULWriter.scala 85:28:@289.8] + wire [31:0] _GEN_18; // @[TLULWriter.scala 85:28:@289.8] + wire [31:0] _GEN_19; // @[TLULWriter.scala 85:28:@289.8] + wire _GEN_20; // @[TLULWriter.scala 85:28:@289.8] + wire _GEN_21; // @[TLULWriter.scala 85:28:@289.8] + wire _T_179; // @[Conditional.scala 37:30:@318.8] + wire _T_185; // @[TLULWriter.scala 115:22:@325.12] + wire [1:0] _GEN_22; // @[TLULWriter.scala 115:31:@326.12] + wire _GEN_24; // @[TLULWriter.scala 115:31:@326.12] + wire [1:0] _GEN_25; // @[TLULWriter.scala 113:28:@323.10] + wire _GEN_26; // @[TLULWriter.scala 113:28:@323.10] + wire _GEN_27; // @[TLULWriter.scala 113:28:@323.10] + wire _GEN_28; // @[Conditional.scala 39:67:@319.8] + wire _GEN_29; // @[Conditional.scala 39:67:@319.8] + wire [1:0] _GEN_31; // @[Conditional.scala 39:67:@319.8] + wire _GEN_32; // @[Conditional.scala 39:67:@319.8] + wire _GEN_33; // @[Conditional.scala 39:67:@286.6] + wire _GEN_34; // @[Conditional.scala 39:67:@286.6] + wire _GEN_35; // @[Conditional.scala 39:67:@286.6] + wire [1:0] _GEN_36; // @[Conditional.scala 39:67:@286.6] + wire [31:0] _GEN_37; // @[Conditional.scala 39:67:@286.6] + wire [31:0] _GEN_38; // @[Conditional.scala 39:67:@286.6] + wire _GEN_39; // @[Conditional.scala 39:67:@286.6] + wire _GEN_40; // @[Conditional.scala 40:58:@267.4] + wire _GEN_44; // @[Conditional.scala 40:58:@267.4] + wire [1:0] _GEN_45; // @[Conditional.scala 40:58:@267.4] + wire [31:0] _GEN_46; // @[Conditional.scala 40:58:@267.4] + wire [31:0] _GEN_47; // @[Conditional.scala 40:58:@267.4] + assign _T_151 = 2'h0 == state; // @[Conditional.scala 37:30:@266.4] + assign _GEN_0 = io_xfer_valid ? 1'h1 : addrValid; // @[TLULWriter.scala 70:27:@272.6] + assign _T_157 = io_dataIO_valid & addrValid; // @[TLULWriter.scala 74:28:@275.6] + assign _GEN_2 = _T_157 ? 2'h1 : state; // @[TLULWriter.scala 74:42:@276.6] + assign _GEN_3 = _T_157 ? io_xfer_length : xferCnt; // @[TLULWriter.scala 74:42:@276.6] + assign _GEN_4 = _T_157 ? io_xfer_address : addr; // @[TLULWriter.scala 74:42:@276.6] + assign _GEN_5 = _T_157 ? 1'h0 : _GEN_0; // @[TLULWriter.scala 74:42:@276.6] + assign _T_160 = 2'h1 == state; // @[Conditional.scala 37:30:@285.6] + assign _T_166 = xferCnt != 32'h0; // @[TLULWriter.scala 90:22:@293.10] + assign _T_168 = addr + 32'h4; // @[TLULWriter.scala 91:24:@295.12] + assign _T_169 = addr + 32'h4; // @[TLULWriter.scala 91:24:@296.12] + assign _T_171 = xferCnt - 32'h1; // @[TLULWriter.scala 92:30:@298.12] + assign _T_172 = $unsigned(_T_171); // @[TLULWriter.scala 92:30:@299.12] + assign _T_173 = _T_172[31:0]; // @[TLULWriter.scala 92:30:@300.12] + assign _GEN_6 = _T_166 ? _T_169 : addr; // @[TLULWriter.scala 90:31:@294.10] + assign _GEN_7 = _T_166 ? _T_173 : xferCnt; // @[TLULWriter.scala 90:31:@294.10] + assign _T_176 = xferCnt == 32'h1; // @[TLULWriter.scala 99:24:@305.12] + assign _GEN_8 = _T_176 ? 2'h0 : 2'h1; // @[TLULWriter.scala 99:33:@306.12] + assign _GEN_10 = _T_176 ? 1'h0 : 1'h1; // @[TLULWriter.scala 99:33:@306.12] + assign _GEN_12 = io_bus_d_valid ? _GEN_8 : 2'h2; // @[TLULWriter.scala 96:30:@303.10] + assign _GEN_13 = io_bus_d_valid ? _T_176 : 1'h0; // @[TLULWriter.scala 96:30:@303.10] + assign _GEN_14 = io_bus_d_valid ? _GEN_10 : 1'h0; // @[TLULWriter.scala 96:30:@303.10] + assign _GEN_16 = io_bus_a_ready ? _GEN_14 : valid; // @[TLULWriter.scala 85:28:@289.8] + assign _GEN_17 = io_bus_a_ready ? _GEN_12 : state; // @[TLULWriter.scala 85:28:@289.8] + assign _GEN_18 = io_bus_a_ready ? _GEN_6 : addr; // @[TLULWriter.scala 85:28:@289.8] + assign _GEN_19 = io_bus_a_ready ? _GEN_7 : xferCnt; // @[TLULWriter.scala 85:28:@289.8] + assign _GEN_20 = io_bus_a_ready ? io_bus_d_valid : 1'h0; // @[TLULWriter.scala 85:28:@289.8] + assign _GEN_21 = io_bus_a_ready ? _GEN_13 : 1'h0; // @[TLULWriter.scala 85:28:@289.8] + assign _T_179 = 2'h2 == state; // @[Conditional.scala 37:30:@318.8] + assign _T_185 = xferCnt == 32'h0; // @[TLULWriter.scala 115:22:@325.12] + assign _GEN_22 = _T_185 ? 2'h0 : 2'h1; // @[TLULWriter.scala 115:31:@326.12] + assign _GEN_24 = _T_185 ? 1'h0 : 1'h1; // @[TLULWriter.scala 115:31:@326.12] + assign _GEN_25 = io_bus_d_valid ? _GEN_22 : state; // @[TLULWriter.scala 113:28:@323.10] + assign _GEN_26 = io_bus_d_valid ? _T_185 : 1'h0; // @[TLULWriter.scala 113:28:@323.10] + assign _GEN_27 = io_bus_d_valid ? _GEN_24 : 1'h0; // @[TLULWriter.scala 113:28:@323.10] + assign _GEN_28 = _T_179 ? _GEN_27 : valid; // @[Conditional.scala 39:67:@319.8] + assign _GEN_29 = _T_179 ? io_bus_d_valid : 1'h0; // @[Conditional.scala 39:67:@319.8] + assign _GEN_31 = _T_179 ? _GEN_25 : state; // @[Conditional.scala 39:67:@319.8] + assign _GEN_32 = _T_179 ? _GEN_26 : 1'h0; // @[Conditional.scala 39:67:@319.8] + assign _GEN_33 = _T_160 ? io_bus_a_ready : _T_179; // @[Conditional.scala 39:67:@286.6] + assign _GEN_34 = _T_160 ? _GEN_20 : _GEN_29; // @[Conditional.scala 39:67:@286.6] + assign _GEN_35 = _T_160 ? _GEN_16 : _GEN_28; // @[Conditional.scala 39:67:@286.6] + assign _GEN_36 = _T_160 ? _GEN_17 : _GEN_31; // @[Conditional.scala 39:67:@286.6] + assign _GEN_37 = _T_160 ? _GEN_18 : addr; // @[Conditional.scala 39:67:@286.6] + assign _GEN_38 = _T_160 ? _GEN_19 : xferCnt; // @[Conditional.scala 39:67:@286.6] + assign _GEN_39 = _T_160 ? _GEN_21 : _GEN_32; // @[Conditional.scala 39:67:@286.6] + assign _GEN_40 = _T_151 ? _T_157 : _GEN_35; // @[Conditional.scala 40:58:@267.4] + assign _GEN_44 = _T_151 ? _GEN_5 : addrValid; // @[Conditional.scala 40:58:@267.4] + assign _GEN_45 = _T_151 ? _GEN_2 : _GEN_36; // @[Conditional.scala 40:58:@267.4] + assign _GEN_46 = _T_151 ? _GEN_3 : _GEN_38; // @[Conditional.scala 40:58:@267.4] + assign _GEN_47 = _T_151 ? _GEN_4 : _GEN_37; // @[Conditional.scala 40:58:@267.4] + assign io_bus_a_address = addr; // @[TLULWriter.scala 55:20:@262.4] + assign io_bus_a_data = io_dataIO_bits; // @[TLULWriter.scala 48:17:@257.4] + assign io_bus_a_valid = valid; // @[TLULWriter.scala 47:18:@256.4] + assign io_bus_d_ready = _T_151 ? 1'h0 : _GEN_33; // @[TLULWriter.scala 42:12:@245.4 TLULWriter.scala 64:22:@269.6 TLULWriter.scala 83:22:@287.8 TLULWriter.scala 86:24:@290.10 TLULWriter.scala 112:22:@322.10] + assign io_dataIO_ready = _T_151 ? 1'h0 : _GEN_34; // @[TLULWriter.scala 45:19:@255.4] + assign io_xfer_done = _T_151 ? 1'h0 : _GEN_39; // @[TLULWriter.scala 59:16:@265.4] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE + integer initvar; + initial begin + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + #0.002 begin end + `endif + `ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[1:0]; + `endif // RANDOMIZE_REG_INIT + `ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + xferCnt = _RAND_1[31:0]; + `endif // RANDOMIZE_REG_INIT + `ifdef RANDOMIZE_REG_INIT + _RAND_2 = {1{`RANDOM}}; + addr = _RAND_2[31:0]; + `endif // RANDOMIZE_REG_INIT + `ifdef RANDOMIZE_REG_INIT + _RAND_3 = {1{`RANDOM}}; + addrValid = _RAND_3[0:0]; + `endif // RANDOMIZE_REG_INIT + `ifdef RANDOMIZE_REG_INIT + _RAND_4 = {1{`RANDOM}}; + valid = _RAND_4[0:0]; + `endif // RANDOMIZE_REG_INIT + end +`endif // RANDOMIZE + always @(posedge clock) begin + if (reset) begin + state <= 2'h0; + end else begin + if (_T_151) begin + if (_T_157) begin + state <= 2'h1; + end + end else begin + if (_T_160) begin + if (io_bus_a_ready) begin + if (io_bus_d_valid) begin + if (_T_176) begin + state <= 2'h0; + end else begin + state <= 2'h1; + end + end else begin + state <= 2'h2; + end + end + end else begin + if (_T_179) begin + if (io_bus_d_valid) begin + if (_T_185) begin + state <= 2'h0; + end else begin + state <= 2'h1; + end + end + end + end + end + end + if (reset) begin + xferCnt <= 32'h0; + end else begin + if (_T_151) begin + if (_T_157) begin + xferCnt <= io_xfer_length; + end + end else begin + if (_T_160) begin + if (io_bus_a_ready) begin + if (_T_166) begin + xferCnt <= _T_173; + end + end + end + end + end + if (reset) begin + addr <= 32'h0; + end else begin + if (_T_151) begin + if (_T_157) begin + addr <= io_xfer_address; + end + end else begin + if (_T_160) begin + if (io_bus_a_ready) begin + if (_T_166) begin + addr <= _T_169; + end + end + end + end + end + if (reset) begin + addrValid <= 1'h0; + end else begin + if (_T_151) begin + if (_T_157) begin + addrValid <= 1'h0; + end else begin + if (io_xfer_valid) begin + addrValid <= 1'h1; + end + end + end + end + if (reset) begin + valid <= 1'h0; + end else begin + if (_T_151) begin + valid <= _T_157; + end else begin + if (_T_160) begin + if (io_bus_a_ready) begin + if (io_bus_d_valid) begin + if (_T_176) begin + valid <= 1'h0; + end else begin + valid <= 1'h1; + end + end else begin + valid <= 1'h0; + end + end + end else begin + if (_T_179) begin + if (io_bus_d_valid) begin + if (_T_185) begin + valid <= 1'h0; + end else begin + valid <= 1'h1; + end + end else begin + valid <= 1'h0; + end + end + end + end + end + end +endmodule +module CSRTL_TL_TL( // @[:@337.2] + output [31:0] io_csr_0_dataOut, // @[:@340.4] + output io_csr_0_dataWrite, // @[:@340.4] + input [31:0] io_csr_0_dataIn, // @[:@340.4] + input [31:0] io_csr_1_dataIn, // @[:@340.4] + output [31:0] io_csr_2_dataOut, // @[:@340.4] + output io_csr_2_dataWrite, // @[:@340.4] + input [31:0] io_csr_2_dataIn, // @[:@340.4] + output [31:0] io_csr_3_dataOut, // @[:@340.4] + output io_csr_3_dataWrite, // @[:@340.4] + input [31:0] io_csr_3_dataIn, // @[:@340.4] + output [31:0] io_csr_4_dataOut, // @[:@340.4] + output io_csr_4_dataWrite, // @[:@340.4] + input [31:0] io_csr_4_dataIn, // @[:@340.4] + output [31:0] io_csr_5_dataOut, // @[:@340.4] + output io_csr_5_dataWrite, // @[:@340.4] + input [31:0] io_csr_5_dataIn, // @[:@340.4] + output [31:0] io_csr_6_dataOut, // @[:@340.4] + output io_csr_6_dataWrite, // @[:@340.4] + input [31:0] io_csr_6_dataIn, // @[:@340.4] + output [31:0] io_csr_7_dataOut, // @[:@340.4] + output io_csr_7_dataWrite, // @[:@340.4] + input [31:0] io_csr_7_dataIn, // @[:@340.4] + output [31:0] io_csr_8_dataOut, // @[:@340.4] + output io_csr_8_dataWrite, // @[:@340.4] + input [31:0] io_csr_8_dataIn, // @[:@340.4] + output [31:0] io_csr_9_dataOut, // @[:@340.4] + output io_csr_9_dataWrite, // @[:@340.4] + input [31:0] io_csr_9_dataIn, // @[:@340.4] + output [31:0] io_csr_10_dataOut, // @[:@340.4] + output io_csr_10_dataWrite, // @[:@340.4] + input [31:0] io_csr_10_dataIn, // @[:@340.4] + output [31:0] io_csr_11_dataOut, // @[:@340.4] + output io_csr_11_dataWrite, // @[:@340.4] + input [31:0] io_csr_11_dataIn, // @[:@340.4] + input [31:0] io_csr_12_dataIn, // @[:@340.4] + input [31:0] io_csr_13_dataIn, // @[:@340.4] + output [31:0] io_csr_14_dataOut, // @[:@340.4] + output io_csr_14_dataWrite, // @[:@340.4] + input [31:0] io_csr_14_dataIn, // @[:@340.4] + output [31:0] io_csr_15_dataOut, // @[:@340.4] + output io_csr_15_dataWrite, // @[:@340.4] + input [31:0] io_csr_15_dataIn, // @[:@340.4] + input [3:0] io_bus_addr, // @[:@340.4] + input [31:0] io_bus_dataOut, // @[:@340.4] + output [31:0] io_bus_dataIn, // @[:@340.4] + input io_bus_write, // @[:@340.4] + input io_bus_read // @[:@340.4] +); + wire _T_178; // @[CSR.scala 32:22:@345.4] + wire _T_179; // @[CSR.scala 32:30:@346.4] + wire [31:0] _GEN_0; // @[CSR.scala 32:45:@347.4] + wire _T_184; // @[CSR.scala 39:30:@355.4] + wire _T_189; // @[CSR.scala 32:22:@364.4] + wire _T_190; // @[CSR.scala 32:30:@365.4] + wire [31:0] _GEN_4; // @[CSR.scala 32:45:@366.4] + wire _T_200; // @[CSR.scala 32:22:@383.4] + wire _T_201; // @[CSR.scala 32:30:@384.4] + wire [31:0] _GEN_8; // @[CSR.scala 32:45:@385.4] + wire _T_206; // @[CSR.scala 39:30:@393.4] + wire _T_211; // @[CSR.scala 32:22:@402.4] + wire _T_212; // @[CSR.scala 32:30:@403.4] + wire [31:0] _GEN_12; // @[CSR.scala 32:45:@404.4] + wire _T_217; // @[CSR.scala 39:30:@412.4] + wire _T_222; // @[CSR.scala 32:22:@421.4] + wire _T_223; // @[CSR.scala 32:30:@422.4] + wire [31:0] _GEN_16; // @[CSR.scala 32:45:@423.4] + wire _T_228; // @[CSR.scala 39:30:@431.4] + wire _T_233; // @[CSR.scala 32:22:@440.4] + wire _T_234; // @[CSR.scala 32:30:@441.4] + wire [31:0] _GEN_20; // @[CSR.scala 32:45:@442.4] + wire _T_239; // @[CSR.scala 39:30:@450.4] + wire _T_244; // @[CSR.scala 32:22:@459.4] + wire _T_245; // @[CSR.scala 32:30:@460.4] + wire [31:0] _GEN_24; // @[CSR.scala 32:45:@461.4] + wire _T_250; // @[CSR.scala 39:30:@469.4] + wire _T_255; // @[CSR.scala 32:22:@478.4] + wire _T_256; // @[CSR.scala 32:30:@479.4] + wire [31:0] _GEN_28; // @[CSR.scala 32:45:@480.4] + wire _T_261; // @[CSR.scala 39:30:@488.4] + wire _T_266; // @[CSR.scala 32:22:@497.4] + wire _T_267; // @[CSR.scala 32:30:@498.4] + wire [31:0] _GEN_32; // @[CSR.scala 32:45:@499.4] + wire _T_272; // @[CSR.scala 39:30:@507.4] + wire _T_277; // @[CSR.scala 32:22:@516.4] + wire _T_278; // @[CSR.scala 32:30:@517.4] + wire [31:0] _GEN_36; // @[CSR.scala 32:45:@518.4] + wire _T_283; // @[CSR.scala 39:30:@526.4] + wire _T_288; // @[CSR.scala 32:22:@535.4] + wire _T_289; // @[CSR.scala 32:30:@536.4] + wire [31:0] _GEN_40; // @[CSR.scala 32:45:@537.4] + wire _T_294; // @[CSR.scala 39:30:@545.4] + wire _T_299; // @[CSR.scala 32:22:@554.4] + wire _T_300; // @[CSR.scala 32:30:@555.4] + wire [31:0] _GEN_44; // @[CSR.scala 32:45:@556.4] + wire _T_305; // @[CSR.scala 39:30:@564.4] + wire _T_310; // @[CSR.scala 32:22:@573.4] + wire _T_311; // @[CSR.scala 32:30:@574.4] + wire [31:0] _GEN_48; // @[CSR.scala 32:45:@575.4] + wire _T_321; // @[CSR.scala 32:22:@592.4] + wire _T_322; // @[CSR.scala 32:30:@593.4] + wire [31:0] _GEN_52; // @[CSR.scala 32:45:@594.4] + wire _T_332; // @[CSR.scala 32:22:@611.4] + wire _T_333; // @[CSR.scala 32:30:@612.4] + wire [31:0] _GEN_56; // @[CSR.scala 32:45:@613.4] + wire _T_338; // @[CSR.scala 39:30:@621.4] + wire _T_343; // @[CSR.scala 32:22:@630.4] + wire _T_344; // @[CSR.scala 32:30:@631.4] + wire _T_349; // @[CSR.scala 39:30:@640.4] + assign _T_178 = io_bus_addr == 4'h0; // @[CSR.scala 32:22:@345.4] + assign _T_179 = _T_178 & io_bus_read; // @[CSR.scala 32:30:@346.4] + assign _GEN_0 = _T_179 ? io_csr_0_dataIn : 32'h0; // @[CSR.scala 32:45:@347.4] + assign _T_184 = _T_178 & io_bus_write; // @[CSR.scala 39:30:@355.4] + assign _T_189 = io_bus_addr == 4'h1; // @[CSR.scala 32:22:@364.4] + assign _T_190 = _T_189 & io_bus_read; // @[CSR.scala 32:30:@365.4] + assign _GEN_4 = _T_190 ? io_csr_1_dataIn : _GEN_0; // @[CSR.scala 32:45:@366.4] + assign _T_200 = io_bus_addr == 4'h2; // @[CSR.scala 32:22:@383.4] + assign _T_201 = _T_200 & io_bus_read; // @[CSR.scala 32:30:@384.4] + assign _GEN_8 = _T_201 ? io_csr_2_dataIn : _GEN_4; // @[CSR.scala 32:45:@385.4] + assign _T_206 = _T_200 & io_bus_write; // @[CSR.scala 39:30:@393.4] + assign _T_211 = io_bus_addr == 4'h3; // @[CSR.scala 32:22:@402.4] + assign _T_212 = _T_211 & io_bus_read; // @[CSR.scala 32:30:@403.4] + assign _GEN_12 = _T_212 ? io_csr_3_dataIn : _GEN_8; // @[CSR.scala 32:45:@404.4] + assign _T_217 = _T_211 & io_bus_write; // @[CSR.scala 39:30:@412.4] + assign _T_222 = io_bus_addr == 4'h4; // @[CSR.scala 32:22:@421.4] + assign _T_223 = _T_222 & io_bus_read; // @[CSR.scala 32:30:@422.4] + assign _GEN_16 = _T_223 ? io_csr_4_dataIn : _GEN_12; // @[CSR.scala 32:45:@423.4] + assign _T_228 = _T_222 & io_bus_write; // @[CSR.scala 39:30:@431.4] + assign _T_233 = io_bus_addr == 4'h5; // @[CSR.scala 32:22:@440.4] + assign _T_234 = _T_233 & io_bus_read; // @[CSR.scala 32:30:@441.4] + assign _GEN_20 = _T_234 ? io_csr_5_dataIn : _GEN_16; // @[CSR.scala 32:45:@442.4] + assign _T_239 = _T_233 & io_bus_write; // @[CSR.scala 39:30:@450.4] + assign _T_244 = io_bus_addr == 4'h6; // @[CSR.scala 32:22:@459.4] + assign _T_245 = _T_244 & io_bus_read; // @[CSR.scala 32:30:@460.4] + assign _GEN_24 = _T_245 ? io_csr_6_dataIn : _GEN_20; // @[CSR.scala 32:45:@461.4] + assign _T_250 = _T_244 & io_bus_write; // @[CSR.scala 39:30:@469.4] + assign _T_255 = io_bus_addr == 4'h7; // @[CSR.scala 32:22:@478.4] + assign _T_256 = _T_255 & io_bus_read; // @[CSR.scala 32:30:@479.4] + assign _GEN_28 = _T_256 ? io_csr_7_dataIn : _GEN_24; // @[CSR.scala 32:45:@480.4] + assign _T_261 = _T_255 & io_bus_write; // @[CSR.scala 39:30:@488.4] + assign _T_266 = io_bus_addr == 4'h8; // @[CSR.scala 32:22:@497.4] + assign _T_267 = _T_266 & io_bus_read; // @[CSR.scala 32:30:@498.4] + assign _GEN_32 = _T_267 ? io_csr_8_dataIn : _GEN_28; // @[CSR.scala 32:45:@499.4] + assign _T_272 = _T_266 & io_bus_write; // @[CSR.scala 39:30:@507.4] + assign _T_277 = io_bus_addr == 4'h9; // @[CSR.scala 32:22:@516.4] + assign _T_278 = _T_277 & io_bus_read; // @[CSR.scala 32:30:@517.4] + assign _GEN_36 = _T_278 ? io_csr_9_dataIn : _GEN_32; // @[CSR.scala 32:45:@518.4] + assign _T_283 = _T_277 & io_bus_write; // @[CSR.scala 39:30:@526.4] + assign _T_288 = io_bus_addr == 4'ha; // @[CSR.scala 32:22:@535.4] + assign _T_289 = _T_288 & io_bus_read; // @[CSR.scala 32:30:@536.4] + assign _GEN_40 = _T_289 ? io_csr_10_dataIn : _GEN_36; // @[CSR.scala 32:45:@537.4] + assign _T_294 = _T_288 & io_bus_write; // @[CSR.scala 39:30:@545.4] + assign _T_299 = io_bus_addr == 4'hb; // @[CSR.scala 32:22:@554.4] + assign _T_300 = _T_299 & io_bus_read; // @[CSR.scala 32:30:@555.4] + assign _GEN_44 = _T_300 ? io_csr_11_dataIn : _GEN_40; // @[CSR.scala 32:45:@556.4] + assign _T_305 = _T_299 & io_bus_write; // @[CSR.scala 39:30:@564.4] + assign _T_310 = io_bus_addr == 4'hc; // @[CSR.scala 32:22:@573.4] + assign _T_311 = _T_310 & io_bus_read; // @[CSR.scala 32:30:@574.4] + assign _GEN_48 = _T_311 ? io_csr_12_dataIn : _GEN_44; // @[CSR.scala 32:45:@575.4] + assign _T_321 = io_bus_addr == 4'hd; // @[CSR.scala 32:22:@592.4] + assign _T_322 = _T_321 & io_bus_read; // @[CSR.scala 32:30:@593.4] + assign _GEN_52 = _T_322 ? io_csr_13_dataIn : _GEN_48; // @[CSR.scala 32:45:@594.4] + assign _T_332 = io_bus_addr == 4'he; // @[CSR.scala 32:22:@611.4] + assign _T_333 = _T_332 & io_bus_read; // @[CSR.scala 32:30:@612.4] + assign _GEN_56 = _T_333 ? io_csr_14_dataIn : _GEN_52; // @[CSR.scala 32:45:@613.4] + assign _T_338 = _T_332 & io_bus_write; // @[CSR.scala 39:30:@621.4] + assign _T_343 = io_bus_addr == 4'hf; // @[CSR.scala 32:22:@630.4] + assign _T_344 = _T_343 & io_bus_read; // @[CSR.scala 32:30:@631.4] + assign _T_349 = _T_343 & io_bus_write; // @[CSR.scala 39:30:@640.4] + assign io_csr_0_dataOut = _T_184 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@357.6 CSR.scala 44:25:@362.6] + assign io_csr_0_dataWrite = _T_178 & io_bus_write; // @[CSR.scala 41:27:@358.6 CSR.scala 43:27:@361.6] + assign io_csr_2_dataOut = _T_206 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@395.6 CSR.scala 44:25:@400.6] + assign io_csr_2_dataWrite = _T_200 & io_bus_write; // @[CSR.scala 41:27:@396.6 CSR.scala 43:27:@399.6] + assign io_csr_3_dataOut = _T_217 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@414.6 CSR.scala 44:25:@419.6] + assign io_csr_3_dataWrite = _T_211 & io_bus_write; // @[CSR.scala 41:27:@415.6 CSR.scala 43:27:@418.6] + assign io_csr_4_dataOut = _T_228 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@433.6 CSR.scala 44:25:@438.6] + assign io_csr_4_dataWrite = _T_222 & io_bus_write; // @[CSR.scala 41:27:@434.6 CSR.scala 43:27:@437.6] + assign io_csr_5_dataOut = _T_239 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@452.6 CSR.scala 44:25:@457.6] + assign io_csr_5_dataWrite = _T_233 & io_bus_write; // @[CSR.scala 41:27:@453.6 CSR.scala 43:27:@456.6] + assign io_csr_6_dataOut = _T_250 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@471.6 CSR.scala 44:25:@476.6] + assign io_csr_6_dataWrite = _T_244 & io_bus_write; // @[CSR.scala 41:27:@472.6 CSR.scala 43:27:@475.6] + assign io_csr_7_dataOut = _T_261 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@490.6 CSR.scala 44:25:@495.6] + assign io_csr_7_dataWrite = _T_255 & io_bus_write; // @[CSR.scala 41:27:@491.6 CSR.scala 43:27:@494.6] + assign io_csr_8_dataOut = _T_272 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@509.6 CSR.scala 44:25:@514.6] + assign io_csr_8_dataWrite = _T_266 & io_bus_write; // @[CSR.scala 41:27:@510.6 CSR.scala 43:27:@513.6] + assign io_csr_9_dataOut = _T_283 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@528.6 CSR.scala 44:25:@533.6] + assign io_csr_9_dataWrite = _T_277 & io_bus_write; // @[CSR.scala 41:27:@529.6 CSR.scala 43:27:@532.6] + assign io_csr_10_dataOut = _T_294 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@547.6 CSR.scala 44:25:@552.6] + assign io_csr_10_dataWrite = _T_288 & io_bus_write; // @[CSR.scala 41:27:@548.6 CSR.scala 43:27:@551.6] + assign io_csr_11_dataOut = _T_305 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@566.6 CSR.scala 44:25:@571.6] + assign io_csr_11_dataWrite = _T_299 & io_bus_write; // @[CSR.scala 41:27:@567.6 CSR.scala 43:27:@570.6] + assign io_csr_14_dataOut = _T_338 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@623.6 CSR.scala 44:25:@628.6] + assign io_csr_14_dataWrite = _T_332 & io_bus_write; // @[CSR.scala 41:27:@624.6 CSR.scala 43:27:@627.6] + assign io_csr_15_dataOut = _T_349 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@642.6 CSR.scala 44:25:@647.6] + assign io_csr_15_dataWrite = _T_343 & io_bus_write; // @[CSR.scala 41:27:@643.6 CSR.scala 43:27:@646.6] + assign io_bus_dataIn = _T_344 ? io_csr_15_dataIn : _GEN_56; // @[CSR.scala 29:17:@344.4] +endmodule +module AddressGeneratorTL_TL_TL( // @[:@650.2] + input clock, // @[:@651.4] + input reset, // @[:@652.4] + input io_ctl_start, // @[:@653.4] + output io_ctl_busy, // @[:@653.4] + input [31:0] io_ctl_startAddress, // @[:@653.4] + input [31:0] io_ctl_lineLength, // @[:@653.4] + input [31:0] io_ctl_lineCount, // @[:@653.4] + input [31:0] io_ctl_lineGap, // @[:@653.4] + input io_xfer_done, // @[:@653.4] + output [31:0] io_xfer_address, // @[:@653.4] + output [31:0] io_xfer_length, // @[:@653.4] + output io_xfer_valid // @[:@653.4] +); + reg [1:0] state; // @[AddressGenerator.scala 29:22:@655.4] + reg [31:0] _RAND_0; + reg [31:0] lineCount; // @[AddressGenerator.scala 31:26:@656.4] + reg [31:0] _RAND_1; + reg [31:0] lineGap; // @[AddressGenerator.scala 32:24:@657.4] + reg [31:0] _RAND_2; + reg [31:0] address_o; // @[AddressGenerator.scala 34:26:@658.4] + reg [31:0] _RAND_3; + reg [31:0] address_i; // @[AddressGenerator.scala 35:26:@659.4] + reg [31:0] _RAND_4; + reg [31:0] length_o; // @[AddressGenerator.scala 36:25:@660.4] reg [31:0] _RAND_5; - reg [31:0] length_i; // @[AddressGenerator.scala 37:25:@591.4] + reg [31:0] length_i; // @[AddressGenerator.scala 37:25:@661.4] reg [31:0] _RAND_6; - reg valid; // @[AddressGenerator.scala 38:22:@592.4] + reg valid; // @[AddressGenerator.scala 38:22:@662.4] reg [31:0] _RAND_7; - reg busy; // @[AddressGenerator.scala 40:21:@594.4] + reg busy; // @[AddressGenerator.scala 40:21:@664.4] reg [31:0] _RAND_8; - wire _T_46; // @[AddressGenerator.scala 48:14:@600.4] - wire _GEN_0; // @[AddressGenerator.scala 48:24:@601.4] - wire _T_49; // @[Conditional.scala 37:30:@607.4] - wire [1:0] _GEN_1; // @[AddressGenerator.scala 56:25:@609.6] - wire [31:0] _GEN_2; // @[AddressGenerator.scala 56:25:@609.6] - wire [31:0] _GEN_3; // @[AddressGenerator.scala 56:25:@609.6] - wire [31:0] _GEN_4; // @[AddressGenerator.scala 56:25:@609.6] - wire [31:0] _GEN_5; // @[AddressGenerator.scala 56:25:@609.6] - wire _T_51; // @[Conditional.scala 37:30:@619.6] - wire [34:0] _T_54; // @[AddressGenerator.scala 71:42:@624.8] - wire [34:0] _GEN_28; // @[AddressGenerator.scala 71:30:@625.8] - wire [35:0] _T_55; // @[AddressGenerator.scala 71:30:@625.8] - wire [34:0] _T_56; // @[AddressGenerator.scala 71:30:@626.8] - wire [34:0] _T_58; // @[AddressGenerator.scala 71:74:@627.8] - wire [35:0] _T_59; // @[AddressGenerator.scala 71:63:@628.8] - wire [34:0] _T_60; // @[AddressGenerator.scala 71:63:@629.8] - wire [32:0] _T_62; // @[AddressGenerator.scala 73:30:@631.8] - wire [32:0] _T_63; // @[AddressGenerator.scala 73:30:@632.8] - wire [31:0] _T_64; // @[AddressGenerator.scala 73:30:@633.8] - wire _T_65; // @[Conditional.scala 37:30:@638.8] - wire _T_69; // @[AddressGenerator.scala 80:24:@643.12] - wire [1:0] _GEN_7; // @[AddressGenerator.scala 80:30:@644.12] - wire [1:0] _GEN_8; // @[AddressGenerator.scala 79:25:@642.10] - wire _GEN_9; // @[Conditional.scala 39:67:@639.8] - wire [1:0] _GEN_11; // @[Conditional.scala 39:67:@639.8] - wire _GEN_12; // @[Conditional.scala 39:67:@620.6] - wire [31:0] _GEN_13; // @[Conditional.scala 39:67:@620.6] - wire [31:0] _GEN_14; // @[Conditional.scala 39:67:@620.6] - wire [34:0] _GEN_15; // @[Conditional.scala 39:67:@620.6] - wire [31:0] _GEN_16; // @[Conditional.scala 39:67:@620.6] - wire [1:0] _GEN_17; // @[Conditional.scala 39:67:@620.6] - wire [1:0] _GEN_19; // @[Conditional.scala 40:58:@608.4] - wire [34:0] _GEN_20; // @[Conditional.scala 40:58:@608.4] - wire [31:0] _GEN_21; // @[Conditional.scala 40:58:@608.4] - wire [31:0] _GEN_22; // @[Conditional.scala 40:58:@608.4] - wire [31:0] _GEN_23; // @[Conditional.scala 40:58:@608.4] - wire _GEN_25; // @[Conditional.scala 40:58:@608.4] - wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@608.4] - wire [31:0] _GEN_27; // @[Conditional.scala 40:58:@608.4] - assign _T_46 = state == 2'h0; // @[AddressGenerator.scala 48:14:@600.4] - assign _GEN_0 = _T_46 ? 1'h0 : 1'h1; // @[AddressGenerator.scala 48:24:@601.4] - assign _T_49 = 2'h0 == state; // @[Conditional.scala 37:30:@607.4] - assign _GEN_1 = io_ctl_start ? 2'h1 : state; // @[AddressGenerator.scala 56:25:@609.6] - assign _GEN_2 = io_ctl_start ? io_ctl_startAddress : address_i; // @[AddressGenerator.scala 56:25:@609.6] - assign _GEN_3 = io_ctl_start ? io_ctl_lineLength : length_i; // @[AddressGenerator.scala 56:25:@609.6] - assign _GEN_4 = io_ctl_start ? io_ctl_lineCount : lineCount; // @[AddressGenerator.scala 56:25:@609.6] - assign _GEN_5 = io_ctl_start ? io_ctl_lineGap : lineGap; // @[AddressGenerator.scala 56:25:@609.6] - assign _T_51 = 2'h1 == state; // @[Conditional.scala 37:30:@619.6] - assign _T_54 = length_i * 32'h4; // @[AddressGenerator.scala 71:42:@624.8] - assign _GEN_28 = {{3'd0}, address_i}; // @[AddressGenerator.scala 71:30:@625.8] - assign _T_55 = _GEN_28 + _T_54; // @[AddressGenerator.scala 71:30:@625.8] - assign _T_56 = _GEN_28 + _T_54; // @[AddressGenerator.scala 71:30:@626.8] - assign _T_58 = lineGap * 32'h4; // @[AddressGenerator.scala 71:74:@627.8] - assign _T_59 = _T_56 + _T_58; // @[AddressGenerator.scala 71:63:@628.8] - assign _T_60 = _T_56 + _T_58; // @[AddressGenerator.scala 71:63:@629.8] - assign _T_62 = lineCount - 32'h1; // @[AddressGenerator.scala 73:30:@631.8] - assign _T_63 = $unsigned(_T_62); // @[AddressGenerator.scala 73:30:@632.8] - assign _T_64 = _T_63[31:0]; // @[AddressGenerator.scala 73:30:@633.8] - assign _T_65 = 2'h2 == state; // @[Conditional.scala 37:30:@638.8] - assign _T_69 = lineCount > 32'h0; // @[AddressGenerator.scala 80:24:@643.12] - assign _GEN_7 = _T_69 ? 2'h1 : 2'h0; // @[AddressGenerator.scala 80:30:@644.12] - assign _GEN_8 = io_xfer_done ? _GEN_7 : state; // @[AddressGenerator.scala 79:25:@642.10] - assign _GEN_9 = _T_65 ? 1'h0 : valid; // @[Conditional.scala 39:67:@639.8] - assign _GEN_11 = _T_65 ? _GEN_8 : state; // @[Conditional.scala 39:67:@639.8] - assign _GEN_12 = _T_51 ? 1'h1 : _GEN_9; // @[Conditional.scala 39:67:@620.6] - assign _GEN_13 = _T_51 ? address_i : address_o; // @[Conditional.scala 39:67:@620.6] - assign _GEN_14 = _T_51 ? length_i : length_o; // @[Conditional.scala 39:67:@620.6] - assign _GEN_15 = _T_51 ? _T_60 : {{3'd0}, address_i}; // @[Conditional.scala 39:67:@620.6] - assign _GEN_16 = _T_51 ? _T_64 : lineCount; // @[Conditional.scala 39:67:@620.6] - assign _GEN_17 = _T_51 ? 2'h2 : _GEN_11; // @[Conditional.scala 39:67:@620.6] - assign _GEN_19 = _T_49 ? _GEN_1 : _GEN_17; // @[Conditional.scala 40:58:@608.4] - assign _GEN_20 = _T_49 ? {{3'd0}, _GEN_2} : _GEN_15; // @[Conditional.scala 40:58:@608.4] - assign _GEN_21 = _T_49 ? _GEN_3 : length_i; // @[Conditional.scala 40:58:@608.4] - assign _GEN_22 = _T_49 ? _GEN_4 : _GEN_16; // @[Conditional.scala 40:58:@608.4] - assign _GEN_23 = _T_49 ? _GEN_5 : lineGap; // @[Conditional.scala 40:58:@608.4] - assign _GEN_25 = _T_49 ? valid : _GEN_12; // @[Conditional.scala 40:58:@608.4] - assign _GEN_26 = _T_49 ? address_o : _GEN_13; // @[Conditional.scala 40:58:@608.4] - assign _GEN_27 = _T_49 ? length_o : _GEN_14; // @[Conditional.scala 40:58:@608.4] - assign io_ctl_busy = busy; // @[AddressGenerator.scala 46:15:@599.4] - assign io_xfer_address = address_o; // @[AddressGenerator.scala 42:19:@595.4] - assign io_xfer_length = length_o; // @[AddressGenerator.scala 43:18:@596.4] - assign io_xfer_valid = valid; // @[AddressGenerator.scala 44:17:@597.4] + wire _T_46; // @[AddressGenerator.scala 48:14:@670.4] + wire _GEN_0; // @[AddressGenerator.scala 48:24:@671.4] + wire _T_49; // @[Conditional.scala 37:30:@677.4] + wire [1:0] _GEN_1; // @[AddressGenerator.scala 56:25:@679.6] + wire [31:0] _GEN_2; // @[AddressGenerator.scala 56:25:@679.6] + wire [31:0] _GEN_3; // @[AddressGenerator.scala 56:25:@679.6] + wire [31:0] _GEN_4; // @[AddressGenerator.scala 56:25:@679.6] + wire [31:0] _GEN_5; // @[AddressGenerator.scala 56:25:@679.6] + wire _T_51; // @[Conditional.scala 37:30:@689.6] + wire [34:0] _T_54; // @[AddressGenerator.scala 71:42:@694.8] + wire [34:0] _GEN_28; // @[AddressGenerator.scala 71:30:@695.8] + wire [35:0] _T_55; // @[AddressGenerator.scala 71:30:@695.8] + wire [34:0] _T_56; // @[AddressGenerator.scala 71:30:@696.8] + wire [34:0] _T_58; // @[AddressGenerator.scala 71:74:@697.8] + wire [35:0] _T_59; // @[AddressGenerator.scala 71:63:@698.8] + wire [34:0] _T_60; // @[AddressGenerator.scala 71:63:@699.8] + wire [32:0] _T_62; // @[AddressGenerator.scala 73:30:@701.8] + wire [32:0] _T_63; // @[AddressGenerator.scala 73:30:@702.8] + wire [31:0] _T_64; // @[AddressGenerator.scala 73:30:@703.8] + wire _T_65; // @[Conditional.scala 37:30:@708.8] + wire _T_69; // @[AddressGenerator.scala 80:24:@713.12] + wire [1:0] _GEN_7; // @[AddressGenerator.scala 80:30:@714.12] + wire [1:0] _GEN_8; // @[AddressGenerator.scala 79:25:@712.10] + wire _GEN_9; // @[Conditional.scala 39:67:@709.8] + wire [1:0] _GEN_11; // @[Conditional.scala 39:67:@709.8] + wire _GEN_12; // @[Conditional.scala 39:67:@690.6] + wire [31:0] _GEN_13; // @[Conditional.scala 39:67:@690.6] + wire [31:0] _GEN_14; // @[Conditional.scala 39:67:@690.6] + wire [34:0] _GEN_15; // @[Conditional.scala 39:67:@690.6] + wire [31:0] _GEN_16; // @[Conditional.scala 39:67:@690.6] + wire [1:0] _GEN_17; // @[Conditional.scala 39:67:@690.6] + wire [1:0] _GEN_19; // @[Conditional.scala 40:58:@678.4] + wire [34:0] _GEN_20; // @[Conditional.scala 40:58:@678.4] + wire [31:0] _GEN_21; // @[Conditional.scala 40:58:@678.4] + wire [31:0] _GEN_22; // @[Conditional.scala 40:58:@678.4] + wire [31:0] _GEN_23; // @[Conditional.scala 40:58:@678.4] + wire _GEN_25; // @[Conditional.scala 40:58:@678.4] + wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@678.4] + wire [31:0] _GEN_27; // @[Conditional.scala 40:58:@678.4] + assign _T_46 = state == 2'h0; // @[AddressGenerator.scala 48:14:@670.4] + assign _GEN_0 = _T_46 ? 1'h0 : 1'h1; // @[AddressGenerator.scala 48:24:@671.4] + assign _T_49 = 2'h0 == state; // @[Conditional.scala 37:30:@677.4] + assign _GEN_1 = io_ctl_start ? 2'h1 : state; // @[AddressGenerator.scala 56:25:@679.6] + assign _GEN_2 = io_ctl_start ? io_ctl_startAddress : address_i; // @[AddressGenerator.scala 56:25:@679.6] + assign _GEN_3 = io_ctl_start ? io_ctl_lineLength : length_i; // @[AddressGenerator.scala 56:25:@679.6] + assign _GEN_4 = io_ctl_start ? io_ctl_lineCount : lineCount; // @[AddressGenerator.scala 56:25:@679.6] + assign _GEN_5 = io_ctl_start ? io_ctl_lineGap : lineGap; // @[AddressGenerator.scala 56:25:@679.6] + assign _T_51 = 2'h1 == state; // @[Conditional.scala 37:30:@689.6] + assign _T_54 = length_i * 32'h4; // @[AddressGenerator.scala 71:42:@694.8] + assign _GEN_28 = {{3'd0}, address_i}; // @[AddressGenerator.scala 71:30:@695.8] + assign _T_55 = _GEN_28 + _T_54; // @[AddressGenerator.scala 71:30:@695.8] + assign _T_56 = _GEN_28 + _T_54; // @[AddressGenerator.scala 71:30:@696.8] + assign _T_58 = lineGap * 32'h4; // @[AddressGenerator.scala 71:74:@697.8] + assign _T_59 = _T_56 + _T_58; // @[AddressGenerator.scala 71:63:@698.8] + assign _T_60 = _T_56 + _T_58; // @[AddressGenerator.scala 71:63:@699.8] + assign _T_62 = lineCount - 32'h1; // @[AddressGenerator.scala 73:30:@701.8] + assign _T_63 = $unsigned(_T_62); // @[AddressGenerator.scala 73:30:@702.8] + assign _T_64 = _T_63[31:0]; // @[AddressGenerator.scala 73:30:@703.8] + assign _T_65 = 2'h2 == state; // @[Conditional.scala 37:30:@708.8] + assign _T_69 = lineCount > 32'h0; // @[AddressGenerator.scala 80:24:@713.12] + assign _GEN_7 = _T_69 ? 2'h1 : 2'h0; // @[AddressGenerator.scala 80:30:@714.12] + assign _GEN_8 = io_xfer_done ? _GEN_7 : state; // @[AddressGenerator.scala 79:25:@712.10] + assign _GEN_9 = _T_65 ? 1'h0 : valid; // @[Conditional.scala 39:67:@709.8] + assign _GEN_11 = _T_65 ? _GEN_8 : state; // @[Conditional.scala 39:67:@709.8] + assign _GEN_12 = _T_51 ? 1'h1 : _GEN_9; // @[Conditional.scala 39:67:@690.6] + assign _GEN_13 = _T_51 ? address_i : address_o; // @[Conditional.scala 39:67:@690.6] + assign _GEN_14 = _T_51 ? length_i : length_o; // @[Conditional.scala 39:67:@690.6] + assign _GEN_15 = _T_51 ? _T_60 : {{3'd0}, address_i}; // @[Conditional.scala 39:67:@690.6] + assign _GEN_16 = _T_51 ? _T_64 : lineCount; // @[Conditional.scala 39:67:@690.6] + assign _GEN_17 = _T_51 ? 2'h2 : _GEN_11; // @[Conditional.scala 39:67:@690.6] + assign _GEN_19 = _T_49 ? _GEN_1 : _GEN_17; // @[Conditional.scala 40:58:@678.4] + assign _GEN_20 = _T_49 ? {{3'd0}, _GEN_2} : _GEN_15; // @[Conditional.scala 40:58:@678.4] + assign _GEN_21 = _T_49 ? _GEN_3 : length_i; // @[Conditional.scala 40:58:@678.4] + assign _GEN_22 = _T_49 ? _GEN_4 : _GEN_16; // @[Conditional.scala 40:58:@678.4] + assign _GEN_23 = _T_49 ? _GEN_5 : lineGap; // @[Conditional.scala 40:58:@678.4] + assign _GEN_25 = _T_49 ? valid : _GEN_12; // @[Conditional.scala 40:58:@678.4] + assign _GEN_26 = _T_49 ? address_o : _GEN_13; // @[Conditional.scala 40:58:@678.4] + assign _GEN_27 = _T_49 ? length_o : _GEN_14; // @[Conditional.scala 40:58:@678.4] + assign io_ctl_busy = busy; // @[AddressGenerator.scala 46:15:@669.4] + assign io_xfer_address = address_o; // @[AddressGenerator.scala 42:19:@665.4] + assign io_xfer_length = length_o; // @[AddressGenerator.scala 43:18:@666.4] + assign io_xfer_valid = valid; // @[AddressGenerator.scala 44:17:@667.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1025,137 +1267,137 @@ end end endmodule -module TransferSplitterTL_TL_TL( // @[:@653.2] - output io_xferIn_done, // @[:@656.4] - input [31:0] io_xferIn_address, // @[:@656.4] - input [31:0] io_xferIn_length, // @[:@656.4] - input io_xferIn_valid, // @[:@656.4] - input io_xferOut_done, // @[:@656.4] - output [31:0] io_xferOut_address, // @[:@656.4] - output [31:0] io_xferOut_length, // @[:@656.4] - output io_xferOut_valid // @[:@656.4] +module TransferSplitterTL_TL_TL( // @[:@723.2] + output io_xferIn_done, // @[:@726.4] + input [31:0] io_xferIn_address, // @[:@726.4] + input [31:0] io_xferIn_length, // @[:@726.4] + input io_xferIn_valid, // @[:@726.4] + input io_xferOut_done, // @[:@726.4] + output [31:0] io_xferOut_address, // @[:@726.4] + output [31:0] io_xferOut_length, // @[:@726.4] + output io_xferOut_valid // @[:@726.4] ); - assign io_xferIn_done = io_xferOut_done; // @[TransferSplitter.scala 124:16:@662.4] - assign io_xferOut_address = io_xferIn_address; // @[TransferSplitter.scala 124:16:@661.4] - assign io_xferOut_length = io_xferIn_length; // @[TransferSplitter.scala 124:16:@660.4] - assign io_xferOut_valid = io_xferIn_valid; // @[TransferSplitter.scala 124:16:@659.4] + assign io_xferIn_done = io_xferOut_done; // @[TransferSplitter.scala 124:16:@732.4] + assign io_xferOut_address = io_xferIn_address; // @[TransferSplitter.scala 124:16:@731.4] + assign io_xferOut_length = io_xferIn_length; // @[TransferSplitter.scala 124:16:@730.4] + assign io_xferOut_valid = io_xferIn_valid; // @[TransferSplitter.scala 124:16:@729.4] endmodule -module TransferSplitterTL_TL_TL_1( // @[:@737.2] - input clock, // @[:@738.4] - input reset, // @[:@739.4] - output io_xferIn_done, // @[:@740.4] - input [31:0] io_xferIn_address, // @[:@740.4] - input [31:0] io_xferIn_length, // @[:@740.4] - input io_xferIn_valid, // @[:@740.4] - input io_xferOut_done, // @[:@740.4] - output [31:0] io_xferOut_address, // @[:@740.4] - output [31:0] io_xferOut_length, // @[:@740.4] - output io_xferOut_valid // @[:@740.4] +module TransferSplitterTL_TL_TL_1( // @[:@807.2] + input clock, // @[:@808.4] + input reset, // @[:@809.4] + output io_xferIn_done, // @[:@810.4] + input [31:0] io_xferIn_address, // @[:@810.4] + input [31:0] io_xferIn_length, // @[:@810.4] + input io_xferIn_valid, // @[:@810.4] + input io_xferOut_done, // @[:@810.4] + output [31:0] io_xferOut_address, // @[:@810.4] + output [31:0] io_xferOut_length, // @[:@810.4] + output io_xferOut_valid // @[:@810.4] ); - reg [31:0] _T_42; // @[TransferSplitter.scala 35:28:@742.4] + reg [31:0] _T_42; // @[TransferSplitter.scala 35:28:@812.4] reg [31:0] _RAND_0; - reg [31:0] _T_45; // @[TransferSplitter.scala 36:27:@743.4] + reg [31:0] _T_45; // @[TransferSplitter.scala 36:27:@813.4] reg [31:0] _RAND_1; - reg [31:0] _T_48; // @[TransferSplitter.scala 38:28:@744.4] + reg [31:0] _T_48; // @[TransferSplitter.scala 38:28:@814.4] reg [31:0] _RAND_2; - reg [31:0] _T_51; // @[TransferSplitter.scala 39:27:@745.4] + reg [31:0] _T_51; // @[TransferSplitter.scala 39:27:@815.4] reg [31:0] _RAND_3; - reg _T_60; // @[TransferSplitter.scala 44:23:@748.4] + reg _T_60; // @[TransferSplitter.scala 44:23:@818.4] reg [31:0] _RAND_4; - reg _T_63; // @[TransferSplitter.scala 45:24:@749.4] + reg _T_63; // @[TransferSplitter.scala 45:24:@819.4] reg [31:0] _RAND_5; - reg [1:0] _T_65; // @[TransferSplitter.scala 47:24:@750.4] + reg [1:0] _T_65; // @[TransferSplitter.scala 47:24:@820.4] reg [31:0] _RAND_6; - wire _T_66; // @[Conditional.scala 37:30:@756.4] - wire [31:0] _GEN_0; // @[TransferSplitter.scala 60:31:@759.6] - wire [31:0] _GEN_1; // @[TransferSplitter.scala 60:31:@759.6] - wire [1:0] _GEN_3; // @[TransferSplitter.scala 60:31:@759.6] - wire _T_68; // @[Conditional.scala 37:30:@767.6] - wire _T_71; // @[TransferSplitter.scala 73:23:@773.8] - wire [32:0] _T_74; // @[TransferSplitter.scala 76:34:@776.10] - wire [32:0] _T_75; // @[TransferSplitter.scala 76:34:@777.10] - wire [31:0] _T_76; // @[TransferSplitter.scala 76:34:@778.10] - wire [11:0] _T_79; // @[TransferSplitter.scala 77:50:@780.10] - wire [31:0] _GEN_33; // @[TransferSplitter.scala 77:36:@781.10] - wire [32:0] _T_80; // @[TransferSplitter.scala 77:36:@781.10] - wire [31:0] _T_81; // @[TransferSplitter.scala 77:36:@782.10] - wire [34:0] _T_84; // @[TransferSplitter.scala 95:47:@788.10] - wire [34:0] _GEN_34; // @[TransferSplitter.scala 95:36:@789.10] - wire [35:0] _T_85; // @[TransferSplitter.scala 95:36:@789.10] - wire [34:0] _T_86; // @[TransferSplitter.scala 95:36:@790.10] - wire [31:0] _GEN_4; // @[TransferSplitter.scala 73:38:@774.8] - wire [31:0] _GEN_5; // @[TransferSplitter.scala 73:38:@774.8] - wire [34:0] _GEN_6; // @[TransferSplitter.scala 73:38:@774.8] - wire _T_87; // @[Conditional.scala 37:30:@795.8] - wire _T_91; // @[TransferSplitter.scala 114:25:@800.12] - wire [1:0] _GEN_7; // @[TransferSplitter.scala 114:32:@801.12] - wire _GEN_8; // @[TransferSplitter.scala 114:32:@801.12] - wire [1:0] _GEN_9; // @[TransferSplitter.scala 113:31:@799.10] - wire _GEN_10; // @[TransferSplitter.scala 113:31:@799.10] - wire _GEN_11; // @[Conditional.scala 39:67:@796.8] - wire [1:0] _GEN_13; // @[Conditional.scala 39:67:@796.8] - wire _GEN_14; // @[Conditional.scala 39:67:@796.8] - wire [31:0] _GEN_15; // @[Conditional.scala 39:67:@768.6] - wire _GEN_17; // @[Conditional.scala 39:67:@768.6] - wire [1:0] _GEN_18; // @[Conditional.scala 39:67:@768.6] - wire [31:0] _GEN_19; // @[Conditional.scala 39:67:@768.6] - wire [31:0] _GEN_20; // @[Conditional.scala 39:67:@768.6] - wire [34:0] _GEN_21; // @[Conditional.scala 39:67:@768.6] - wire _GEN_23; // @[Conditional.scala 39:67:@768.6] - wire _GEN_24; // @[Conditional.scala 40:58:@757.4] - wire [34:0] _GEN_25; // @[Conditional.scala 40:58:@757.4] - wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@757.4] - wire [1:0] _GEN_28; // @[Conditional.scala 40:58:@757.4] - wire [31:0] _GEN_29; // @[Conditional.scala 40:58:@757.4] - wire _GEN_31; // @[Conditional.scala 40:58:@757.4] - wire [31:0] _GEN_32; // @[Conditional.scala 40:58:@757.4] - assign _T_66 = 2'h0 == _T_65; // @[Conditional.scala 37:30:@756.4] - assign _GEN_0 = io_xferIn_valid ? io_xferIn_address : _T_42; // @[TransferSplitter.scala 60:31:@759.6] - assign _GEN_1 = io_xferIn_valid ? io_xferIn_length : _T_45; // @[TransferSplitter.scala 60:31:@759.6] - assign _GEN_3 = io_xferIn_valid ? 2'h1 : _T_65; // @[TransferSplitter.scala 60:31:@759.6] - assign _T_68 = 2'h1 == _T_65; // @[Conditional.scala 37:30:@767.6] - assign _T_71 = _T_45 > 32'h100; // @[TransferSplitter.scala 73:23:@773.8] - assign _T_74 = _T_45 - 32'h100; // @[TransferSplitter.scala 76:34:@776.10] - assign _T_75 = $unsigned(_T_74); // @[TransferSplitter.scala 76:34:@777.10] - assign _T_76 = _T_75[31:0]; // @[TransferSplitter.scala 76:34:@778.10] - assign _T_79 = 9'h100 * 9'h4; // @[TransferSplitter.scala 77:50:@780.10] - assign _GEN_33 = {{20'd0}, _T_79}; // @[TransferSplitter.scala 77:36:@781.10] - assign _T_80 = _T_42 + _GEN_33; // @[TransferSplitter.scala 77:36:@781.10] - assign _T_81 = _T_42 + _GEN_33; // @[TransferSplitter.scala 77:36:@782.10] - assign _T_84 = _T_45 * 32'h4; // @[TransferSplitter.scala 95:47:@788.10] - assign _GEN_34 = {{3'd0}, _T_42}; // @[TransferSplitter.scala 95:36:@789.10] - assign _T_85 = _GEN_34 + _T_84; // @[TransferSplitter.scala 95:36:@789.10] - assign _T_86 = _GEN_34 + _T_84; // @[TransferSplitter.scala 95:36:@790.10] - assign _GEN_4 = _T_71 ? 32'h100 : _T_45; // @[TransferSplitter.scala 73:38:@774.8] - assign _GEN_5 = _T_71 ? _T_76 : 32'h0; // @[TransferSplitter.scala 73:38:@774.8] - assign _GEN_6 = _T_71 ? {{3'd0}, _T_81} : _T_86; // @[TransferSplitter.scala 73:38:@774.8] - assign _T_87 = 2'h2 == _T_65; // @[Conditional.scala 37:30:@795.8] - assign _T_91 = _T_45 > 32'h0; // @[TransferSplitter.scala 114:25:@800.12] - assign _GEN_7 = _T_91 ? 2'h1 : 2'h0; // @[TransferSplitter.scala 114:32:@801.12] - assign _GEN_8 = _T_91 ? _T_60 : 1'h1; // @[TransferSplitter.scala 114:32:@801.12] - assign _GEN_9 = io_xferOut_done ? _GEN_7 : _T_65; // @[TransferSplitter.scala 113:31:@799.10] - assign _GEN_10 = io_xferOut_done ? _GEN_8 : _T_60; // @[TransferSplitter.scala 113:31:@799.10] - assign _GEN_11 = _T_87 ? 1'h0 : _T_63; // @[Conditional.scala 39:67:@796.8] - assign _GEN_13 = _T_87 ? _GEN_9 : _T_65; // @[Conditional.scala 39:67:@796.8] - assign _GEN_14 = _T_87 ? _GEN_10 : _T_60; // @[Conditional.scala 39:67:@796.8] - assign _GEN_15 = _T_68 ? _T_42 : _T_48; // @[Conditional.scala 39:67:@768.6] - assign _GEN_17 = _T_68 ? 1'h1 : _GEN_11; // @[Conditional.scala 39:67:@768.6] - assign _GEN_18 = _T_68 ? 2'h2 : _GEN_13; // @[Conditional.scala 39:67:@768.6] - assign _GEN_19 = _T_68 ? _GEN_4 : _T_51; // @[Conditional.scala 39:67:@768.6] - assign _GEN_20 = _T_68 ? _GEN_5 : _T_45; // @[Conditional.scala 39:67:@768.6] - assign _GEN_21 = _T_68 ? _GEN_6 : {{3'd0}, _T_42}; // @[Conditional.scala 39:67:@768.6] - assign _GEN_23 = _T_68 ? _T_60 : _GEN_14; // @[Conditional.scala 39:67:@768.6] - assign _GEN_24 = _T_66 ? 1'h0 : _GEN_23; // @[Conditional.scala 40:58:@757.4] - assign _GEN_25 = _T_66 ? {{3'd0}, _GEN_0} : _GEN_21; // @[Conditional.scala 40:58:@757.4] - assign _GEN_26 = _T_66 ? _GEN_1 : _GEN_20; // @[Conditional.scala 40:58:@757.4] - assign _GEN_28 = _T_66 ? _GEN_3 : _GEN_18; // @[Conditional.scala 40:58:@757.4] - assign _GEN_29 = _T_66 ? _T_48 : _GEN_15; // @[Conditional.scala 40:58:@757.4] - assign _GEN_31 = _T_66 ? _T_63 : _GEN_17; // @[Conditional.scala 40:58:@757.4] - assign _GEN_32 = _T_66 ? _T_51 : _GEN_19; // @[Conditional.scala 40:58:@757.4] - assign io_xferIn_done = _T_60; // @[TransferSplitter.scala 49:20:@751.4] - assign io_xferOut_address = _T_48; // @[TransferSplitter.scala 53:24:@754.4] - assign io_xferOut_length = _T_51; // @[TransferSplitter.scala 54:23:@755.4] - assign io_xferOut_valid = _T_63; // @[TransferSplitter.scala 50:22:@752.4] + wire _T_66; // @[Conditional.scala 37:30:@826.4] + wire [31:0] _GEN_0; // @[TransferSplitter.scala 60:31:@829.6] + wire [31:0] _GEN_1; // @[TransferSplitter.scala 60:31:@829.6] + wire [1:0] _GEN_3; // @[TransferSplitter.scala 60:31:@829.6] + wire _T_68; // @[Conditional.scala 37:30:@837.6] + wire _T_71; // @[TransferSplitter.scala 73:23:@843.8] + wire [32:0] _T_74; // @[TransferSplitter.scala 76:34:@846.10] + wire [32:0] _T_75; // @[TransferSplitter.scala 76:34:@847.10] + wire [31:0] _T_76; // @[TransferSplitter.scala 76:34:@848.10] + wire [11:0] _T_79; // @[TransferSplitter.scala 77:50:@850.10] + wire [31:0] _GEN_33; // @[TransferSplitter.scala 77:36:@851.10] + wire [32:0] _T_80; // @[TransferSplitter.scala 77:36:@851.10] + wire [31:0] _T_81; // @[TransferSplitter.scala 77:36:@852.10] + wire [34:0] _T_84; // @[TransferSplitter.scala 95:47:@858.10] + wire [34:0] _GEN_34; // @[TransferSplitter.scala 95:36:@859.10] + wire [35:0] _T_85; // @[TransferSplitter.scala 95:36:@859.10] + wire [34:0] _T_86; // @[TransferSplitter.scala 95:36:@860.10] + wire [31:0] _GEN_4; // @[TransferSplitter.scala 73:38:@844.8] + wire [31:0] _GEN_5; // @[TransferSplitter.scala 73:38:@844.8] + wire [34:0] _GEN_6; // @[TransferSplitter.scala 73:38:@844.8] + wire _T_87; // @[Conditional.scala 37:30:@865.8] + wire _T_91; // @[TransferSplitter.scala 114:25:@870.12] + wire [1:0] _GEN_7; // @[TransferSplitter.scala 114:32:@871.12] + wire _GEN_8; // @[TransferSplitter.scala 114:32:@871.12] + wire [1:0] _GEN_9; // @[TransferSplitter.scala 113:31:@869.10] + wire _GEN_10; // @[TransferSplitter.scala 113:31:@869.10] + wire _GEN_11; // @[Conditional.scala 39:67:@866.8] + wire [1:0] _GEN_13; // @[Conditional.scala 39:67:@866.8] + wire _GEN_14; // @[Conditional.scala 39:67:@866.8] + wire [31:0] _GEN_15; // @[Conditional.scala 39:67:@838.6] + wire _GEN_17; // @[Conditional.scala 39:67:@838.6] + wire [1:0] _GEN_18; // @[Conditional.scala 39:67:@838.6] + wire [31:0] _GEN_19; // @[Conditional.scala 39:67:@838.6] + wire [31:0] _GEN_20; // @[Conditional.scala 39:67:@838.6] + wire [34:0] _GEN_21; // @[Conditional.scala 39:67:@838.6] + wire _GEN_23; // @[Conditional.scala 39:67:@838.6] + wire _GEN_24; // @[Conditional.scala 40:58:@827.4] + wire [34:0] _GEN_25; // @[Conditional.scala 40:58:@827.4] + wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@827.4] + wire [1:0] _GEN_28; // @[Conditional.scala 40:58:@827.4] + wire [31:0] _GEN_29; // @[Conditional.scala 40:58:@827.4] + wire _GEN_31; // @[Conditional.scala 40:58:@827.4] + wire [31:0] _GEN_32; // @[Conditional.scala 40:58:@827.4] + assign _T_66 = 2'h0 == _T_65; // @[Conditional.scala 37:30:@826.4] + assign _GEN_0 = io_xferIn_valid ? io_xferIn_address : _T_42; // @[TransferSplitter.scala 60:31:@829.6] + assign _GEN_1 = io_xferIn_valid ? io_xferIn_length : _T_45; // @[TransferSplitter.scala 60:31:@829.6] + assign _GEN_3 = io_xferIn_valid ? 2'h1 : _T_65; // @[TransferSplitter.scala 60:31:@829.6] + assign _T_68 = 2'h1 == _T_65; // @[Conditional.scala 37:30:@837.6] + assign _T_71 = _T_45 > 32'h100; // @[TransferSplitter.scala 73:23:@843.8] + assign _T_74 = _T_45 - 32'h100; // @[TransferSplitter.scala 76:34:@846.10] + assign _T_75 = $unsigned(_T_74); // @[TransferSplitter.scala 76:34:@847.10] + assign _T_76 = _T_75[31:0]; // @[TransferSplitter.scala 76:34:@848.10] + assign _T_79 = 9'h100 * 9'h4; // @[TransferSplitter.scala 77:50:@850.10] + assign _GEN_33 = {{20'd0}, _T_79}; // @[TransferSplitter.scala 77:36:@851.10] + assign _T_80 = _T_42 + _GEN_33; // @[TransferSplitter.scala 77:36:@851.10] + assign _T_81 = _T_42 + _GEN_33; // @[TransferSplitter.scala 77:36:@852.10] + assign _T_84 = _T_45 * 32'h4; // @[TransferSplitter.scala 95:47:@858.10] + assign _GEN_34 = {{3'd0}, _T_42}; // @[TransferSplitter.scala 95:36:@859.10] + assign _T_85 = _GEN_34 + _T_84; // @[TransferSplitter.scala 95:36:@859.10] + assign _T_86 = _GEN_34 + _T_84; // @[TransferSplitter.scala 95:36:@860.10] + assign _GEN_4 = _T_71 ? 32'h100 : _T_45; // @[TransferSplitter.scala 73:38:@844.8] + assign _GEN_5 = _T_71 ? _T_76 : 32'h0; // @[TransferSplitter.scala 73:38:@844.8] + assign _GEN_6 = _T_71 ? {{3'd0}, _T_81} : _T_86; // @[TransferSplitter.scala 73:38:@844.8] + assign _T_87 = 2'h2 == _T_65; // @[Conditional.scala 37:30:@865.8] + assign _T_91 = _T_45 > 32'h0; // @[TransferSplitter.scala 114:25:@870.12] + assign _GEN_7 = _T_91 ? 2'h1 : 2'h0; // @[TransferSplitter.scala 114:32:@871.12] + assign _GEN_8 = _T_91 ? _T_60 : 1'h1; // @[TransferSplitter.scala 114:32:@871.12] + assign _GEN_9 = io_xferOut_done ? _GEN_7 : _T_65; // @[TransferSplitter.scala 113:31:@869.10] + assign _GEN_10 = io_xferOut_done ? _GEN_8 : _T_60; // @[TransferSplitter.scala 113:31:@869.10] + assign _GEN_11 = _T_87 ? 1'h0 : _T_63; // @[Conditional.scala 39:67:@866.8] + assign _GEN_13 = _T_87 ? _GEN_9 : _T_65; // @[Conditional.scala 39:67:@866.8] + assign _GEN_14 = _T_87 ? _GEN_10 : _T_60; // @[Conditional.scala 39:67:@866.8] + assign _GEN_15 = _T_68 ? _T_42 : _T_48; // @[Conditional.scala 39:67:@838.6] + assign _GEN_17 = _T_68 ? 1'h1 : _GEN_11; // @[Conditional.scala 39:67:@838.6] + assign _GEN_18 = _T_68 ? 2'h2 : _GEN_13; // @[Conditional.scala 39:67:@838.6] + assign _GEN_19 = _T_68 ? _GEN_4 : _T_51; // @[Conditional.scala 39:67:@838.6] + assign _GEN_20 = _T_68 ? _GEN_5 : _T_45; // @[Conditional.scala 39:67:@838.6] + assign _GEN_21 = _T_68 ? _GEN_6 : {{3'd0}, _T_42}; // @[Conditional.scala 39:67:@838.6] + assign _GEN_23 = _T_68 ? _T_60 : _GEN_14; // @[Conditional.scala 39:67:@838.6] + assign _GEN_24 = _T_66 ? 1'h0 : _GEN_23; // @[Conditional.scala 40:58:@827.4] + assign _GEN_25 = _T_66 ? {{3'd0}, _GEN_0} : _GEN_21; // @[Conditional.scala 40:58:@827.4] + assign _GEN_26 = _T_66 ? _GEN_1 : _GEN_20; // @[Conditional.scala 40:58:@827.4] + assign _GEN_28 = _T_66 ? _GEN_3 : _GEN_18; // @[Conditional.scala 40:58:@827.4] + assign _GEN_29 = _T_66 ? _T_48 : _GEN_15; // @[Conditional.scala 40:58:@827.4] + assign _GEN_31 = _T_66 ? _T_63 : _GEN_17; // @[Conditional.scala 40:58:@827.4] + assign _GEN_32 = _T_66 ? _T_51 : _GEN_19; // @[Conditional.scala 40:58:@827.4] + assign io_xferIn_done = _T_60; // @[TransferSplitter.scala 49:20:@821.4] + assign io_xferOut_address = _T_48; // @[TransferSplitter.scala 53:24:@824.4] + assign io_xferOut_length = _T_51; // @[TransferSplitter.scala 54:23:@825.4] + assign io_xferOut_valid = _T_63; // @[TransferSplitter.scala 50:22:@822.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1310,25 +1552,25 @@ end end endmodule -module ClearCSRTL_TL_TL( // @[:@811.2] - input clock, // @[:@812.4] - input reset, // @[:@813.4] - input [31:0] io_csr_dataOut, // @[:@814.4] - input io_csr_dataWrite, // @[:@814.4] - output [31:0] io_csr_dataIn, // @[:@814.4] - output [31:0] io_value, // @[:@814.4] - input [31:0] io_clear // @[:@814.4] +module ClearCSRTL_TL_TL( // @[:@881.2] + input clock, // @[:@882.4] + input reset, // @[:@883.4] + input [31:0] io_csr_dataOut, // @[:@884.4] + input io_csr_dataWrite, // @[:@884.4] + output [31:0] io_csr_dataIn, // @[:@884.4] + output [31:0] io_value, // @[:@884.4] + input [31:0] io_clear // @[:@884.4] ); - reg [31:0] reg$; // @[ClearCSR.scala 28:20:@816.4] + reg [31:0] reg$; // @[ClearCSR.scala 28:20:@886.4] reg [31:0] _RAND_0; - wire [31:0] _T_29; // @[ClearCSR.scala 36:19:@823.6] - wire [31:0] _T_30; // @[ClearCSR.scala 36:16:@824.6] - wire [31:0] _GEN_0; // @[ClearCSR.scala 33:25:@819.4] - assign _T_29 = ~ io_clear; // @[ClearCSR.scala 36:19:@823.6] - assign _T_30 = reg$ & _T_29; // @[ClearCSR.scala 36:16:@824.6] - assign _GEN_0 = io_csr_dataWrite ? io_csr_dataOut : _T_30; // @[ClearCSR.scala 33:25:@819.4] - assign io_csr_dataIn = reg$; // @[ClearCSR.scala 30:17:@817.4] - assign io_value = reg$; // @[ClearCSR.scala 31:12:@818.4] + wire [31:0] _T_29; // @[ClearCSR.scala 36:19:@893.6] + wire [31:0] _T_30; // @[ClearCSR.scala 36:16:@894.6] + wire [31:0] _GEN_0; // @[ClearCSR.scala 33:25:@889.4] + assign _T_29 = ~ io_clear; // @[ClearCSR.scala 36:19:@893.6] + assign _T_30 = reg$ & _T_29; // @[ClearCSR.scala 36:16:@894.6] + assign _GEN_0 = io_csr_dataWrite ? io_csr_dataOut : _T_30; // @[ClearCSR.scala 33:25:@889.4] + assign io_csr_dataIn = reg$; // @[ClearCSR.scala 30:17:@887.4] + assign io_value = reg$; // @[ClearCSR.scala 31:12:@888.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1371,14 +1613,14 @@ end end endmodule -module StatusCSRTL_TL_TL( // @[:@828.2] - input clock, // @[:@829.4] - output [31:0] io_csr_dataIn, // @[:@831.4] - input [31:0] io_value // @[:@831.4] +module StatusCSRTL_TL_TL( // @[:@898.2] + input clock, // @[:@899.4] + output [31:0] io_csr_dataIn, // @[:@901.4] + input [31:0] io_value // @[:@901.4] ); - reg [31:0] reg$; // @[StatusCSR.scala 27:20:@833.4] + reg [31:0] reg$; // @[StatusCSR.scala 27:20:@903.4] reg [31:0] _RAND_0; - assign io_csr_dataIn = reg$; // @[StatusCSR.scala 29:17:@835.4] + assign io_csr_dataIn = reg$; // @[StatusCSR.scala 29:17:@905.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1413,20 +1655,20 @@ reg$ <= io_value; end endmodule -module SimpleCSRTL_TL_TL( // @[:@837.2] - input clock, // @[:@838.4] - input reset, // @[:@839.4] - input [31:0] io_csr_dataOut, // @[:@840.4] - input io_csr_dataWrite, // @[:@840.4] - output [31:0] io_csr_dataIn, // @[:@840.4] - output [31:0] io_value // @[:@840.4] +module SimpleCSRTL_TL_TL( // @[:@907.2] + input clock, // @[:@908.4] + input reset, // @[:@909.4] + input [31:0] io_csr_dataOut, // @[:@910.4] + input io_csr_dataWrite, // @[:@910.4] + output [31:0] io_csr_dataIn, // @[:@910.4] + output [31:0] io_value // @[:@910.4] ); - reg [31:0] reg$; // @[SimpleCSR.scala 27:20:@842.4] + reg [31:0] reg$; // @[SimpleCSR.scala 27:20:@912.4] reg [31:0] _RAND_0; - wire [31:0] _GEN_0; // @[SimpleCSR.scala 32:25:@845.4] - assign _GEN_0 = io_csr_dataWrite ? io_csr_dataOut : reg$; // @[SimpleCSR.scala 32:25:@845.4] - assign io_csr_dataIn = reg$; // @[SimpleCSR.scala 29:17:@843.4] - assign io_value = reg$; // @[SimpleCSR.scala 30:12:@844.4] + wire [31:0] _GEN_0; // @[SimpleCSR.scala 32:25:@915.4] + assign _GEN_0 = io_csr_dataWrite ? io_csr_dataOut : reg$; // @[SimpleCSR.scala 32:25:@915.4] + assign io_csr_dataIn = reg$; // @[SimpleCSR.scala 29:17:@913.4] + assign io_value = reg$; // @[SimpleCSR.scala 30:12:@914.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1467,29 +1709,29 @@ end end endmodule -module SetCSRTL_TL_TL( // @[:@849.2] - input clock, // @[:@850.4] - input reset, // @[:@851.4] - input [31:0] io_csr_dataOut, // @[:@852.4] - input io_csr_dataWrite, // @[:@852.4] - output [31:0] io_csr_dataIn, // @[:@852.4] - output [31:0] io_value, // @[:@852.4] - input [31:0] io_set // @[:@852.4] +module SetCSRTL_TL_TL( // @[:@919.2] + input clock, // @[:@920.4] + input reset, // @[:@921.4] + input [31:0] io_csr_dataOut, // @[:@922.4] + input io_csr_dataWrite, // @[:@922.4] + output [31:0] io_csr_dataIn, // @[:@922.4] + output [31:0] io_value, // @[:@922.4] + input [31:0] io_set // @[:@922.4] ); - reg [31:0] reg$; // @[SetCSR.scala 28:20:@854.4] + reg [31:0] reg$; // @[SetCSR.scala 28:20:@924.4] reg [31:0] _RAND_0; - wire [31:0] _T_29; // @[SetCSR.scala 34:20:@858.6] - wire [31:0] _T_30; // @[SetCSR.scala 34:17:@859.6] - wire [31:0] _T_31; // @[SetCSR.scala 34:45:@860.6] - wire [31:0] _T_32; // @[SetCSR.scala 36:16:@864.6] - wire [31:0] _GEN_0; // @[SetCSR.scala 33:25:@857.4] - assign _T_29 = ~ io_csr_dataOut; // @[SetCSR.scala 34:20:@858.6] - assign _T_30 = reg$ & _T_29; // @[SetCSR.scala 34:17:@859.6] - assign _T_31 = _T_30 | io_set; // @[SetCSR.scala 34:45:@860.6] - assign _T_32 = reg$ | io_set; // @[SetCSR.scala 36:16:@864.6] - assign _GEN_0 = io_csr_dataWrite ? _T_31 : _T_32; // @[SetCSR.scala 33:25:@857.4] - assign io_csr_dataIn = reg$; // @[SetCSR.scala 30:17:@855.4] - assign io_value = reg$; // @[SetCSR.scala 31:12:@856.4] + wire [31:0] _T_29; // @[SetCSR.scala 34:20:@928.6] + wire [31:0] _T_30; // @[SetCSR.scala 34:17:@929.6] + wire [31:0] _T_31; // @[SetCSR.scala 34:45:@930.6] + wire [31:0] _T_32; // @[SetCSR.scala 36:16:@934.6] + wire [31:0] _GEN_0; // @[SetCSR.scala 33:25:@927.4] + assign _T_29 = ~ io_csr_dataOut; // @[SetCSR.scala 34:20:@928.6] + assign _T_30 = reg$ & _T_29; // @[SetCSR.scala 34:17:@929.6] + assign _T_31 = _T_30 | io_set; // @[SetCSR.scala 34:45:@930.6] + assign _T_32 = reg$ | io_set; // @[SetCSR.scala 36:16:@934.6] + assign _GEN_0 = io_csr_dataWrite ? _T_31 : _T_32; // @[SetCSR.scala 33:25:@927.4] + assign io_csr_dataIn = reg$; // @[SetCSR.scala 30:17:@925.4] + assign io_value = reg$; // @[SetCSR.scala 31:12:@926.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1532,57 +1774,57 @@ end end endmodule -module InterruptControllerTL_TL_TL( // @[:@868.2] - input clock, // @[:@869.4] - input reset, // @[:@870.4] - output io_irq_readerDone, // @[:@871.4] - output io_irq_writerDone, // @[:@871.4] - input io_readBusy, // @[:@871.4] - input io_writeBusy, // @[:@871.4] - input [31:0] io_imr_dataOut, // @[:@871.4] - input io_imr_dataWrite, // @[:@871.4] - output [31:0] io_imr_dataIn, // @[:@871.4] - input [31:0] io_isr_dataOut, // @[:@871.4] - input io_isr_dataWrite, // @[:@871.4] - output [31:0] io_isr_dataIn // @[:@871.4] +module InterruptControllerTL_TL_TL( // @[:@938.2] + input clock, // @[:@939.4] + input reset, // @[:@940.4] + output io_irq_readerDone, // @[:@941.4] + output io_irq_writerDone, // @[:@941.4] + input io_readBusy, // @[:@941.4] + input io_writeBusy, // @[:@941.4] + input [31:0] io_imr_dataOut, // @[:@941.4] + input io_imr_dataWrite, // @[:@941.4] + output [31:0] io_imr_dataIn, // @[:@941.4] + input [31:0] io_isr_dataOut, // @[:@941.4] + input io_isr_dataWrite, // @[:@941.4] + output [31:0] io_isr_dataIn // @[:@941.4] ); - wire SimpleCSRTL_TL_TL_clock; // @[SimpleCSR.scala 40:21:@873.4] - wire SimpleCSRTL_TL_TL_reset; // @[SimpleCSR.scala 40:21:@873.4] - wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@873.4] - wire SimpleCSRTL_TL_TL_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@873.4] - wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@873.4] - wire [31:0] SimpleCSRTL_TL_TL_io_value; // @[SimpleCSR.scala 40:21:@873.4] - wire SetCSRTL_TL_TL_clock; // @[SetCSR.scala 43:21:@905.4] - wire SetCSRTL_TL_TL_reset; // @[SetCSR.scala 43:21:@905.4] - wire [31:0] SetCSRTL_TL_TL_io_csr_dataOut; // @[SetCSR.scala 43:21:@905.4] - wire SetCSRTL_TL_TL_io_csr_dataWrite; // @[SetCSR.scala 43:21:@905.4] - wire [31:0] SetCSRTL_TL_TL_io_csr_dataIn; // @[SetCSR.scala 43:21:@905.4] - wire [31:0] SetCSRTL_TL_TL_io_value; // @[SetCSR.scala 43:21:@905.4] - wire [31:0] SetCSRTL_TL_TL_io_set; // @[SetCSR.scala 43:21:@905.4] - reg readBusy; // @[InterruptController.scala 33:25:@882.4] + wire SimpleCSRTL_TL_TL_clock; // @[SimpleCSR.scala 40:21:@943.4] + wire SimpleCSRTL_TL_TL_reset; // @[SimpleCSR.scala 40:21:@943.4] + wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@943.4] + wire SimpleCSRTL_TL_TL_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@943.4] + wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@943.4] + wire [31:0] SimpleCSRTL_TL_TL_io_value; // @[SimpleCSR.scala 40:21:@943.4] + wire SetCSRTL_TL_TL_clock; // @[SetCSR.scala 43:21:@975.4] + wire SetCSRTL_TL_TL_reset; // @[SetCSR.scala 43:21:@975.4] + wire [31:0] SetCSRTL_TL_TL_io_csr_dataOut; // @[SetCSR.scala 43:21:@975.4] + wire SetCSRTL_TL_TL_io_csr_dataWrite; // @[SetCSR.scala 43:21:@975.4] + wire [31:0] SetCSRTL_TL_TL_io_csr_dataIn; // @[SetCSR.scala 43:21:@975.4] + wire [31:0] SetCSRTL_TL_TL_io_value; // @[SetCSR.scala 43:21:@975.4] + wire [31:0] SetCSRTL_TL_TL_io_set; // @[SetCSR.scala 43:21:@975.4] + reg readBusy; // @[InterruptController.scala 33:25:@952.4] reg [31:0] _RAND_0; - reg readBusyOld; // @[InterruptController.scala 34:28:@884.4] + reg readBusyOld; // @[InterruptController.scala 34:28:@954.4] reg [31:0] _RAND_1; - reg writeBusy; // @[InterruptController.scala 36:26:@886.4] + reg writeBusy; // @[InterruptController.scala 36:26:@956.4] reg [31:0] _RAND_2; - reg writeBusyOld; // @[InterruptController.scala 37:29:@888.4] + reg writeBusyOld; // @[InterruptController.scala 37:29:@958.4] reg [31:0] _RAND_3; - reg writeBusyIrq; // @[InterruptController.scala 39:29:@890.4] + reg writeBusyIrq; // @[InterruptController.scala 39:29:@960.4] reg [31:0] _RAND_4; - reg readBusyIrq; // @[InterruptController.scala 40:28:@891.4] + reg readBusyIrq; // @[InterruptController.scala 40:28:@961.4] reg [31:0] _RAND_5; - wire _T_59; // @[InterruptController.scala 42:35:@892.4] - wire _T_60; // @[InterruptController.scala 42:32:@893.4] - wire [31:0] mask; // @[:@880.4 :@881.4] - wire _T_61; // @[InterruptController.scala 42:53:@894.4] - wire _T_62; // @[InterruptController.scala 42:46:@895.4] - wire _T_64; // @[InterruptController.scala 43:33:@897.4] - wire _T_65; // @[InterruptController.scala 43:30:@898.4] - wire _T_66; // @[InterruptController.scala 43:50:@899.4] - wire _T_67; // @[InterruptController.scala 43:43:@900.4] - wire [1:0] irq; // @[Cat.scala 30:58:@902.4] - wire [31:0] isr; // @[:@913.4 :@914.4] - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL ( // @[SimpleCSR.scala 40:21:@873.4] + wire _T_59; // @[InterruptController.scala 42:35:@962.4] + wire _T_60; // @[InterruptController.scala 42:32:@963.4] + wire [31:0] mask; // @[:@950.4 :@951.4] + wire _T_61; // @[InterruptController.scala 42:53:@964.4] + wire _T_62; // @[InterruptController.scala 42:46:@965.4] + wire _T_64; // @[InterruptController.scala 43:33:@967.4] + wire _T_65; // @[InterruptController.scala 43:30:@968.4] + wire _T_66; // @[InterruptController.scala 43:50:@969.4] + wire _T_67; // @[InterruptController.scala 43:43:@970.4] + wire [1:0] irq; // @[Cat.scala 30:58:@972.4] + wire [31:0] isr; // @[:@983.4 :@984.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL ( // @[SimpleCSR.scala 40:21:@943.4] .clock(SimpleCSRTL_TL_TL_clock), .reset(SimpleCSRTL_TL_TL_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_io_csr_dataOut), @@ -1590,7 +1832,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_io_value) ); - SetCSRTL_TL_TL SetCSRTL_TL_TL ( // @[SetCSR.scala 43:21:@905.4] + SetCSRTL_TL_TL SetCSRTL_TL_TL ( // @[SetCSR.scala 43:21:@975.4] .clock(SetCSRTL_TL_TL_clock), .reset(SetCSRTL_TL_TL_reset), .io_csr_dataOut(SetCSRTL_TL_TL_io_csr_dataOut), @@ -1599,30 +1841,30 @@ .io_value(SetCSRTL_TL_TL_io_value), .io_set(SetCSRTL_TL_TL_io_set) ); - assign _T_59 = writeBusy == 1'h0; // @[InterruptController.scala 42:35:@892.4] - assign _T_60 = writeBusyOld & _T_59; // @[InterruptController.scala 42:32:@893.4] - assign mask = SimpleCSRTL_TL_TL_io_value; // @[:@880.4 :@881.4] - assign _T_61 = mask[0]; // @[InterruptController.scala 42:53:@894.4] - assign _T_62 = _T_60 & _T_61; // @[InterruptController.scala 42:46:@895.4] - assign _T_64 = readBusy == 1'h0; // @[InterruptController.scala 43:33:@897.4] - assign _T_65 = readBusyOld & _T_64; // @[InterruptController.scala 43:30:@898.4] - assign _T_66 = mask[1]; // @[InterruptController.scala 43:50:@899.4] - assign _T_67 = _T_65 & _T_66; // @[InterruptController.scala 43:43:@900.4] - assign irq = {readBusyIrq,writeBusyIrq}; // @[Cat.scala 30:58:@902.4] - assign isr = SetCSRTL_TL_TL_io_value; // @[:@913.4 :@914.4] - assign io_irq_readerDone = isr[1]; // @[InterruptController.scala 50:21:@918.4] - assign io_irq_writerDone = isr[0]; // @[InterruptController.scala 49:21:@916.4] - assign io_imr_dataIn = SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@876.4] - assign io_isr_dataIn = SetCSRTL_TL_TL_io_csr_dataIn; // @[SetCSR.scala 47:16:@909.4] - assign SimpleCSRTL_TL_TL_clock = clock; // @[:@874.4] - assign SimpleCSRTL_TL_TL_reset = reset; // @[:@875.4] - assign SimpleCSRTL_TL_TL_io_csr_dataOut = io_imr_dataOut; // @[SimpleCSR.scala 42:16:@878.4] - assign SimpleCSRTL_TL_TL_io_csr_dataWrite = io_imr_dataWrite; // @[SimpleCSR.scala 42:16:@877.4] - assign SetCSRTL_TL_TL_clock = clock; // @[:@906.4] - assign SetCSRTL_TL_TL_reset = reset; // @[:@907.4] - assign SetCSRTL_TL_TL_io_csr_dataOut = io_isr_dataOut; // @[SetCSR.scala 47:16:@911.4] - assign SetCSRTL_TL_TL_io_csr_dataWrite = io_isr_dataWrite; // @[SetCSR.scala 47:16:@910.4] - assign SetCSRTL_TL_TL_io_set = {{30'd0}, irq}; // @[SetCSR.scala 45:16:@908.4] + assign _T_59 = writeBusy == 1'h0; // @[InterruptController.scala 42:35:@962.4] + assign _T_60 = writeBusyOld & _T_59; // @[InterruptController.scala 42:32:@963.4] + assign mask = SimpleCSRTL_TL_TL_io_value; // @[:@950.4 :@951.4] + assign _T_61 = mask[0]; // @[InterruptController.scala 42:53:@964.4] + assign _T_62 = _T_60 & _T_61; // @[InterruptController.scala 42:46:@965.4] + assign _T_64 = readBusy == 1'h0; // @[InterruptController.scala 43:33:@967.4] + assign _T_65 = readBusyOld & _T_64; // @[InterruptController.scala 43:30:@968.4] + assign _T_66 = mask[1]; // @[InterruptController.scala 43:50:@969.4] + assign _T_67 = _T_65 & _T_66; // @[InterruptController.scala 43:43:@970.4] + assign irq = {readBusyIrq,writeBusyIrq}; // @[Cat.scala 30:58:@972.4] + assign isr = SetCSRTL_TL_TL_io_value; // @[:@983.4 :@984.4] + assign io_irq_readerDone = isr[1]; // @[InterruptController.scala 50:21:@988.4] + assign io_irq_writerDone = isr[0]; // @[InterruptController.scala 49:21:@986.4] + assign io_imr_dataIn = SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@946.4] + assign io_isr_dataIn = SetCSRTL_TL_TL_io_csr_dataIn; // @[SetCSR.scala 47:16:@979.4] + assign SimpleCSRTL_TL_TL_clock = clock; // @[:@944.4] + assign SimpleCSRTL_TL_TL_reset = reset; // @[:@945.4] + assign SimpleCSRTL_TL_TL_io_csr_dataOut = io_imr_dataOut; // @[SimpleCSR.scala 42:16:@948.4] + assign SimpleCSRTL_TL_TL_io_csr_dataWrite = io_imr_dataWrite; // @[SimpleCSR.scala 42:16:@947.4] + assign SetCSRTL_TL_TL_clock = clock; // @[:@976.4] + assign SetCSRTL_TL_TL_reset = reset; // @[:@977.4] + assign SetCSRTL_TL_TL_io_csr_dataOut = io_isr_dataOut; // @[SetCSR.scala 47:16:@981.4] + assign SetCSRTL_TL_TL_io_csr_dataWrite = io_isr_dataWrite; // @[SetCSR.scala 47:16:@980.4] + assign SetCSRTL_TL_TL_io_set = {{30'd0}, irq}; // @[SetCSR.scala 45:16:@978.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1690,228 +1932,228 @@ end end endmodule -module WorkerCSRWrapperTL_TL_TL( // @[:@1058.2] - input clock, // @[:@1059.4] - input reset, // @[:@1060.4] - input [31:0] io_csr_0_dataOut, // @[:@1061.4] - input io_csr_0_dataWrite, // @[:@1061.4] - output [31:0] io_csr_0_dataIn, // @[:@1061.4] - output [31:0] io_csr_1_dataIn, // @[:@1061.4] - input [31:0] io_csr_2_dataOut, // @[:@1061.4] - input io_csr_2_dataWrite, // @[:@1061.4] - output [31:0] io_csr_2_dataIn, // @[:@1061.4] - input [31:0] io_csr_3_dataOut, // @[:@1061.4] - input io_csr_3_dataWrite, // @[:@1061.4] - output [31:0] io_csr_3_dataIn, // @[:@1061.4] - input [31:0] io_csr_4_dataOut, // @[:@1061.4] - input io_csr_4_dataWrite, // @[:@1061.4] - output [31:0] io_csr_4_dataIn, // @[:@1061.4] - input [31:0] io_csr_5_dataOut, // @[:@1061.4] - input io_csr_5_dataWrite, // @[:@1061.4] - output [31:0] io_csr_5_dataIn, // @[:@1061.4] - input [31:0] io_csr_6_dataOut, // @[:@1061.4] - input io_csr_6_dataWrite, // @[:@1061.4] - output [31:0] io_csr_6_dataIn, // @[:@1061.4] - input [31:0] io_csr_7_dataOut, // @[:@1061.4] - input io_csr_7_dataWrite, // @[:@1061.4] - output [31:0] io_csr_7_dataIn, // @[:@1061.4] - input [31:0] io_csr_8_dataOut, // @[:@1061.4] - input io_csr_8_dataWrite, // @[:@1061.4] - output [31:0] io_csr_8_dataIn, // @[:@1061.4] - input [31:0] io_csr_9_dataOut, // @[:@1061.4] - input io_csr_9_dataWrite, // @[:@1061.4] - output [31:0] io_csr_9_dataIn, // @[:@1061.4] - input [31:0] io_csr_10_dataOut, // @[:@1061.4] - input io_csr_10_dataWrite, // @[:@1061.4] - output [31:0] io_csr_10_dataIn, // @[:@1061.4] - input [31:0] io_csr_11_dataOut, // @[:@1061.4] - input io_csr_11_dataWrite, // @[:@1061.4] - output [31:0] io_csr_11_dataIn, // @[:@1061.4] - output [31:0] io_csr_12_dataIn, // @[:@1061.4] - output [31:0] io_csr_13_dataIn, // @[:@1061.4] - input [31:0] io_csr_14_dataOut, // @[:@1061.4] - input io_csr_14_dataWrite, // @[:@1061.4] - output [31:0] io_csr_14_dataIn, // @[:@1061.4] - input [31:0] io_csr_15_dataOut, // @[:@1061.4] - input io_csr_15_dataWrite, // @[:@1061.4] - output [31:0] io_csr_15_dataIn, // @[:@1061.4] - output io_irq_readerDone, // @[:@1061.4] - output io_irq_writerDone, // @[:@1061.4] - input io_sync_readerSync, // @[:@1061.4] - input io_sync_writerSync, // @[:@1061.4] - input io_xferRead_done, // @[:@1061.4] - output [31:0] io_xferRead_address, // @[:@1061.4] - output [31:0] io_xferRead_length, // @[:@1061.4] - output io_xferRead_valid, // @[:@1061.4] - input io_xferWrite_done, // @[:@1061.4] - output [31:0] io_xferWrite_address, // @[:@1061.4] - output [31:0] io_xferWrite_length, // @[:@1061.4] - output io_xferWrite_valid // @[:@1061.4] +module WorkerCSRWrapperTL_TL_TL( // @[:@1128.2] + input clock, // @[:@1129.4] + input reset, // @[:@1130.4] + input [31:0] io_csr_0_dataOut, // @[:@1131.4] + input io_csr_0_dataWrite, // @[:@1131.4] + output [31:0] io_csr_0_dataIn, // @[:@1131.4] + output [31:0] io_csr_1_dataIn, // @[:@1131.4] + input [31:0] io_csr_2_dataOut, // @[:@1131.4] + input io_csr_2_dataWrite, // @[:@1131.4] + output [31:0] io_csr_2_dataIn, // @[:@1131.4] + input [31:0] io_csr_3_dataOut, // @[:@1131.4] + input io_csr_3_dataWrite, // @[:@1131.4] + output [31:0] io_csr_3_dataIn, // @[:@1131.4] + input [31:0] io_csr_4_dataOut, // @[:@1131.4] + input io_csr_4_dataWrite, // @[:@1131.4] + output [31:0] io_csr_4_dataIn, // @[:@1131.4] + input [31:0] io_csr_5_dataOut, // @[:@1131.4] + input io_csr_5_dataWrite, // @[:@1131.4] + output [31:0] io_csr_5_dataIn, // @[:@1131.4] + input [31:0] io_csr_6_dataOut, // @[:@1131.4] + input io_csr_6_dataWrite, // @[:@1131.4] + output [31:0] io_csr_6_dataIn, // @[:@1131.4] + input [31:0] io_csr_7_dataOut, // @[:@1131.4] + input io_csr_7_dataWrite, // @[:@1131.4] + output [31:0] io_csr_7_dataIn, // @[:@1131.4] + input [31:0] io_csr_8_dataOut, // @[:@1131.4] + input io_csr_8_dataWrite, // @[:@1131.4] + output [31:0] io_csr_8_dataIn, // @[:@1131.4] + input [31:0] io_csr_9_dataOut, // @[:@1131.4] + input io_csr_9_dataWrite, // @[:@1131.4] + output [31:0] io_csr_9_dataIn, // @[:@1131.4] + input [31:0] io_csr_10_dataOut, // @[:@1131.4] + input io_csr_10_dataWrite, // @[:@1131.4] + output [31:0] io_csr_10_dataIn, // @[:@1131.4] + input [31:0] io_csr_11_dataOut, // @[:@1131.4] + input io_csr_11_dataWrite, // @[:@1131.4] + output [31:0] io_csr_11_dataIn, // @[:@1131.4] + output [31:0] io_csr_12_dataIn, // @[:@1131.4] + output [31:0] io_csr_13_dataIn, // @[:@1131.4] + input [31:0] io_csr_14_dataOut, // @[:@1131.4] + input io_csr_14_dataWrite, // @[:@1131.4] + output [31:0] io_csr_14_dataIn, // @[:@1131.4] + input [31:0] io_csr_15_dataOut, // @[:@1131.4] + input io_csr_15_dataWrite, // @[:@1131.4] + output [31:0] io_csr_15_dataIn, // @[:@1131.4] + output io_irq_readerDone, // @[:@1131.4] + output io_irq_writerDone, // @[:@1131.4] + input io_sync_readerSync, // @[:@1131.4] + input io_sync_writerSync, // @[:@1131.4] + input io_xferRead_done, // @[:@1131.4] + output [31:0] io_xferRead_address, // @[:@1131.4] + output [31:0] io_xferRead_length, // @[:@1131.4] + output io_xferRead_valid, // @[:@1131.4] + input io_xferWrite_done, // @[:@1131.4] + output [31:0] io_xferWrite_address, // @[:@1131.4] + output [31:0] io_xferWrite_length, // @[:@1131.4] + output io_xferWrite_valid // @[:@1131.4] ); - wire addressGeneratorRead_clock; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire addressGeneratorRead_reset; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire addressGeneratorRead_io_ctl_start; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire addressGeneratorRead_io_ctl_busy; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire [31:0] addressGeneratorRead_io_ctl_startAddress; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire [31:0] addressGeneratorRead_io_ctl_lineLength; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire [31:0] addressGeneratorRead_io_ctl_lineCount; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire [31:0] addressGeneratorRead_io_ctl_lineGap; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire addressGeneratorRead_io_xfer_done; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire [31:0] addressGeneratorRead_io_xfer_address; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire [31:0] addressGeneratorRead_io_xfer_length; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire addressGeneratorRead_io_xfer_valid; // @[WorkerCSRWrapper.scala 33:36:@1063.4] - wire transferSplitterRead_io_xferIn_done; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire [31:0] transferSplitterRead_io_xferIn_address; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire [31:0] transferSplitterRead_io_xferIn_length; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire transferSplitterRead_io_xferIn_valid; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire transferSplitterRead_io_xferOut_done; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire [31:0] transferSplitterRead_io_xferOut_address; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire [31:0] transferSplitterRead_io_xferOut_length; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire transferSplitterRead_io_xferOut_valid; // @[WorkerCSRWrapper.scala 34:36:@1066.4] - wire addressGeneratorWrite_clock; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire addressGeneratorWrite_reset; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire addressGeneratorWrite_io_ctl_start; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire addressGeneratorWrite_io_ctl_busy; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire [31:0] addressGeneratorWrite_io_ctl_startAddress; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire [31:0] addressGeneratorWrite_io_ctl_lineLength; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire [31:0] addressGeneratorWrite_io_ctl_lineCount; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire [31:0] addressGeneratorWrite_io_ctl_lineGap; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire addressGeneratorWrite_io_xfer_done; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire [31:0] addressGeneratorWrite_io_xfer_address; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire [31:0] addressGeneratorWrite_io_xfer_length; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire addressGeneratorWrite_io_xfer_valid; // @[WorkerCSRWrapper.scala 36:37:@1069.4] - wire transferSplitterWrite_clock; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire transferSplitterWrite_reset; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire transferSplitterWrite_io_xferIn_done; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire [31:0] transferSplitterWrite_io_xferIn_address; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire [31:0] transferSplitterWrite_io_xferIn_length; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire transferSplitterWrite_io_xferIn_valid; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire transferSplitterWrite_io_xferOut_done; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire [31:0] transferSplitterWrite_io_xferOut_address; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire [31:0] transferSplitterWrite_io_xferOut_length; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire transferSplitterWrite_io_xferOut_valid; // @[WorkerCSRWrapper.scala 37:37:@1072.4] - wire ClearCSRTL_TL_TL_clock; // @[ClearCSR.scala 42:21:@1092.4] - wire ClearCSRTL_TL_TL_reset; // @[ClearCSR.scala 42:21:@1092.4] - wire [31:0] ClearCSRTL_TL_TL_io_csr_dataOut; // @[ClearCSR.scala 42:21:@1092.4] - wire ClearCSRTL_TL_TL_io_csr_dataWrite; // @[ClearCSR.scala 42:21:@1092.4] - wire [31:0] ClearCSRTL_TL_TL_io_csr_dataIn; // @[ClearCSR.scala 42:21:@1092.4] - wire [31:0] ClearCSRTL_TL_TL_io_value; // @[ClearCSR.scala 42:21:@1092.4] - wire [31:0] ClearCSRTL_TL_TL_io_clear; // @[ClearCSR.scala 42:21:@1092.4] - wire StatusCSRTL_TL_TL_clock; // @[StatusCSR.scala 34:21:@1101.4] - wire [31:0] StatusCSRTL_TL_TL_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1101.4] - wire [31:0] StatusCSRTL_TL_TL_io_value; // @[StatusCSR.scala 34:21:@1101.4] - wire InterruptControllerTL_TL_TL_clock; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_reset; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_io_irq_readerDone; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_io_irq_writerDone; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_io_readBusy; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_io_writeBusy; // @[InterruptController.scala 55:22:@1109.4] - wire [31:0] InterruptControllerTL_TL_TL_io_imr_dataOut; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_io_imr_dataWrite; // @[InterruptController.scala 55:22:@1109.4] - wire [31:0] InterruptControllerTL_TL_TL_io_imr_dataIn; // @[InterruptController.scala 55:22:@1109.4] - wire [31:0] InterruptControllerTL_TL_TL_io_isr_dataOut; // @[InterruptController.scala 55:22:@1109.4] - wire InterruptControllerTL_TL_TL_io_isr_dataWrite; // @[InterruptController.scala 55:22:@1109.4] - wire [31:0] InterruptControllerTL_TL_TL_io_isr_dataIn; // @[InterruptController.scala 55:22:@1109.4] - wire SimpleCSRTL_TL_TL_clock; // @[SimpleCSR.scala 40:21:@1146.4] - wire SimpleCSRTL_TL_TL_reset; // @[SimpleCSR.scala 40:21:@1146.4] - wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1146.4] - wire SimpleCSRTL_TL_TL_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1146.4] - wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1146.4] - wire [31:0] SimpleCSRTL_TL_TL_io_value; // @[SimpleCSR.scala 40:21:@1146.4] - wire SimpleCSRTL_TL_TL_1_clock; // @[SimpleCSR.scala 40:21:@1154.4] - wire SimpleCSRTL_TL_TL_1_reset; // @[SimpleCSR.scala 40:21:@1154.4] - wire [31:0] SimpleCSRTL_TL_TL_1_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1154.4] - wire SimpleCSRTL_TL_TL_1_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1154.4] - wire [31:0] SimpleCSRTL_TL_TL_1_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1154.4] - wire [31:0] SimpleCSRTL_TL_TL_1_io_value; // @[SimpleCSR.scala 40:21:@1154.4] - wire SimpleCSRTL_TL_TL_2_clock; // @[SimpleCSR.scala 40:21:@1162.4] - wire SimpleCSRTL_TL_TL_2_reset; // @[SimpleCSR.scala 40:21:@1162.4] - wire [31:0] SimpleCSRTL_TL_TL_2_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1162.4] - wire SimpleCSRTL_TL_TL_2_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1162.4] - wire [31:0] SimpleCSRTL_TL_TL_2_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1162.4] - wire [31:0] SimpleCSRTL_TL_TL_2_io_value; // @[SimpleCSR.scala 40:21:@1162.4] - wire SimpleCSRTL_TL_TL_3_clock; // @[SimpleCSR.scala 40:21:@1170.4] - wire SimpleCSRTL_TL_TL_3_reset; // @[SimpleCSR.scala 40:21:@1170.4] - wire [31:0] SimpleCSRTL_TL_TL_3_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1170.4] - wire SimpleCSRTL_TL_TL_3_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1170.4] - wire [31:0] SimpleCSRTL_TL_TL_3_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1170.4] - wire [31:0] SimpleCSRTL_TL_TL_3_io_value; // @[SimpleCSR.scala 40:21:@1170.4] - wire SimpleCSRTL_TL_TL_4_clock; // @[SimpleCSR.scala 40:21:@1179.4] - wire SimpleCSRTL_TL_TL_4_reset; // @[SimpleCSR.scala 40:21:@1179.4] - wire [31:0] SimpleCSRTL_TL_TL_4_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1179.4] - wire SimpleCSRTL_TL_TL_4_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1179.4] - wire [31:0] SimpleCSRTL_TL_TL_4_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1179.4] - wire [31:0] SimpleCSRTL_TL_TL_4_io_value; // @[SimpleCSR.scala 40:21:@1179.4] - wire SimpleCSRTL_TL_TL_5_clock; // @[SimpleCSR.scala 40:21:@1187.4] - wire SimpleCSRTL_TL_TL_5_reset; // @[SimpleCSR.scala 40:21:@1187.4] - wire [31:0] SimpleCSRTL_TL_TL_5_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1187.4] - wire SimpleCSRTL_TL_TL_5_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1187.4] - wire [31:0] SimpleCSRTL_TL_TL_5_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1187.4] - wire [31:0] SimpleCSRTL_TL_TL_5_io_value; // @[SimpleCSR.scala 40:21:@1187.4] - wire SimpleCSRTL_TL_TL_6_clock; // @[SimpleCSR.scala 40:21:@1195.4] - wire SimpleCSRTL_TL_TL_6_reset; // @[SimpleCSR.scala 40:21:@1195.4] - wire [31:0] SimpleCSRTL_TL_TL_6_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1195.4] - wire SimpleCSRTL_TL_TL_6_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1195.4] - wire [31:0] SimpleCSRTL_TL_TL_6_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1195.4] - wire [31:0] SimpleCSRTL_TL_TL_6_io_value; // @[SimpleCSR.scala 40:21:@1195.4] - wire SimpleCSRTL_TL_TL_7_clock; // @[SimpleCSR.scala 40:21:@1203.4] - wire SimpleCSRTL_TL_TL_7_reset; // @[SimpleCSR.scala 40:21:@1203.4] - wire [31:0] SimpleCSRTL_TL_TL_7_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1203.4] - wire SimpleCSRTL_TL_TL_7_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1203.4] - wire [31:0] SimpleCSRTL_TL_TL_7_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1203.4] - wire [31:0] SimpleCSRTL_TL_TL_7_io_value; // @[SimpleCSR.scala 40:21:@1203.4] - wire StatusCSRTL_TL_TL_1_clock; // @[StatusCSR.scala 34:21:@1211.4] - wire [31:0] StatusCSRTL_TL_TL_1_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1211.4] - wire [31:0] StatusCSRTL_TL_TL_1_io_value; // @[StatusCSR.scala 34:21:@1211.4] - wire StatusCSRTL_TL_TL_2_clock; // @[StatusCSR.scala 34:21:@1219.4] - wire [31:0] StatusCSRTL_TL_TL_2_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1219.4] - wire [31:0] StatusCSRTL_TL_TL_2_io_value; // @[StatusCSR.scala 34:21:@1219.4] - wire SimpleCSRTL_TL_TL_8_clock; // @[SimpleCSR.scala 40:21:@1227.4] - wire SimpleCSRTL_TL_TL_8_reset; // @[SimpleCSR.scala 40:21:@1227.4] - wire [31:0] SimpleCSRTL_TL_TL_8_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1227.4] - wire SimpleCSRTL_TL_TL_8_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1227.4] - wire [31:0] SimpleCSRTL_TL_TL_8_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1227.4] - wire [31:0] SimpleCSRTL_TL_TL_8_io_value; // @[SimpleCSR.scala 40:21:@1227.4] - wire SimpleCSRTL_TL_TL_9_clock; // @[SimpleCSR.scala 40:21:@1234.4] - wire SimpleCSRTL_TL_TL_9_reset; // @[SimpleCSR.scala 40:21:@1234.4] - wire [31:0] SimpleCSRTL_TL_TL_9_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1234.4] - wire SimpleCSRTL_TL_TL_9_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1234.4] - wire [31:0] SimpleCSRTL_TL_TL_9_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1234.4] - wire [31:0] SimpleCSRTL_TL_TL_9_io_value; // @[SimpleCSR.scala 40:21:@1234.4] - reg [1:0] status; // @[WorkerCSRWrapper.scala 39:23:@1076.4] + wire addressGeneratorRead_clock; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire addressGeneratorRead_reset; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire addressGeneratorRead_io_ctl_start; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire addressGeneratorRead_io_ctl_busy; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire [31:0] addressGeneratorRead_io_ctl_startAddress; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire [31:0] addressGeneratorRead_io_ctl_lineLength; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire [31:0] addressGeneratorRead_io_ctl_lineCount; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire [31:0] addressGeneratorRead_io_ctl_lineGap; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire addressGeneratorRead_io_xfer_done; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire [31:0] addressGeneratorRead_io_xfer_address; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire [31:0] addressGeneratorRead_io_xfer_length; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire addressGeneratorRead_io_xfer_valid; // @[WorkerCSRWrapper.scala 33:36:@1133.4] + wire transferSplitterRead_io_xferIn_done; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire [31:0] transferSplitterRead_io_xferIn_address; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire [31:0] transferSplitterRead_io_xferIn_length; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire transferSplitterRead_io_xferIn_valid; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire transferSplitterRead_io_xferOut_done; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire [31:0] transferSplitterRead_io_xferOut_address; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire [31:0] transferSplitterRead_io_xferOut_length; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire transferSplitterRead_io_xferOut_valid; // @[WorkerCSRWrapper.scala 34:36:@1136.4] + wire addressGeneratorWrite_clock; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire addressGeneratorWrite_reset; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire addressGeneratorWrite_io_ctl_start; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire addressGeneratorWrite_io_ctl_busy; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire [31:0] addressGeneratorWrite_io_ctl_startAddress; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire [31:0] addressGeneratorWrite_io_ctl_lineLength; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire [31:0] addressGeneratorWrite_io_ctl_lineCount; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire [31:0] addressGeneratorWrite_io_ctl_lineGap; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire addressGeneratorWrite_io_xfer_done; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire [31:0] addressGeneratorWrite_io_xfer_address; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire [31:0] addressGeneratorWrite_io_xfer_length; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire addressGeneratorWrite_io_xfer_valid; // @[WorkerCSRWrapper.scala 36:37:@1139.4] + wire transferSplitterWrite_clock; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire transferSplitterWrite_reset; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire transferSplitterWrite_io_xferIn_done; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire [31:0] transferSplitterWrite_io_xferIn_address; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire [31:0] transferSplitterWrite_io_xferIn_length; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire transferSplitterWrite_io_xferIn_valid; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire transferSplitterWrite_io_xferOut_done; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire [31:0] transferSplitterWrite_io_xferOut_address; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire [31:0] transferSplitterWrite_io_xferOut_length; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire transferSplitterWrite_io_xferOut_valid; // @[WorkerCSRWrapper.scala 37:37:@1142.4] + wire ClearCSRTL_TL_TL_clock; // @[ClearCSR.scala 42:21:@1162.4] + wire ClearCSRTL_TL_TL_reset; // @[ClearCSR.scala 42:21:@1162.4] + wire [31:0] ClearCSRTL_TL_TL_io_csr_dataOut; // @[ClearCSR.scala 42:21:@1162.4] + wire ClearCSRTL_TL_TL_io_csr_dataWrite; // @[ClearCSR.scala 42:21:@1162.4] + wire [31:0] ClearCSRTL_TL_TL_io_csr_dataIn; // @[ClearCSR.scala 42:21:@1162.4] + wire [31:0] ClearCSRTL_TL_TL_io_value; // @[ClearCSR.scala 42:21:@1162.4] + wire [31:0] ClearCSRTL_TL_TL_io_clear; // @[ClearCSR.scala 42:21:@1162.4] + wire StatusCSRTL_TL_TL_clock; // @[StatusCSR.scala 34:21:@1171.4] + wire [31:0] StatusCSRTL_TL_TL_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1171.4] + wire [31:0] StatusCSRTL_TL_TL_io_value; // @[StatusCSR.scala 34:21:@1171.4] + wire InterruptControllerTL_TL_TL_clock; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_reset; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_io_irq_readerDone; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_io_irq_writerDone; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_io_readBusy; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_io_writeBusy; // @[InterruptController.scala 55:22:@1179.4] + wire [31:0] InterruptControllerTL_TL_TL_io_imr_dataOut; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_io_imr_dataWrite; // @[InterruptController.scala 55:22:@1179.4] + wire [31:0] InterruptControllerTL_TL_TL_io_imr_dataIn; // @[InterruptController.scala 55:22:@1179.4] + wire [31:0] InterruptControllerTL_TL_TL_io_isr_dataOut; // @[InterruptController.scala 55:22:@1179.4] + wire InterruptControllerTL_TL_TL_io_isr_dataWrite; // @[InterruptController.scala 55:22:@1179.4] + wire [31:0] InterruptControllerTL_TL_TL_io_isr_dataIn; // @[InterruptController.scala 55:22:@1179.4] + wire SimpleCSRTL_TL_TL_clock; // @[SimpleCSR.scala 40:21:@1216.4] + wire SimpleCSRTL_TL_TL_reset; // @[SimpleCSR.scala 40:21:@1216.4] + wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1216.4] + wire SimpleCSRTL_TL_TL_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1216.4] + wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1216.4] + wire [31:0] SimpleCSRTL_TL_TL_io_value; // @[SimpleCSR.scala 40:21:@1216.4] + wire SimpleCSRTL_TL_TL_1_clock; // @[SimpleCSR.scala 40:21:@1224.4] + wire SimpleCSRTL_TL_TL_1_reset; // @[SimpleCSR.scala 40:21:@1224.4] + wire [31:0] SimpleCSRTL_TL_TL_1_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1224.4] + wire SimpleCSRTL_TL_TL_1_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1224.4] + wire [31:0] SimpleCSRTL_TL_TL_1_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1224.4] + wire [31:0] SimpleCSRTL_TL_TL_1_io_value; // @[SimpleCSR.scala 40:21:@1224.4] + wire SimpleCSRTL_TL_TL_2_clock; // @[SimpleCSR.scala 40:21:@1232.4] + wire SimpleCSRTL_TL_TL_2_reset; // @[SimpleCSR.scala 40:21:@1232.4] + wire [31:0] SimpleCSRTL_TL_TL_2_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1232.4] + wire SimpleCSRTL_TL_TL_2_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1232.4] + wire [31:0] SimpleCSRTL_TL_TL_2_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1232.4] + wire [31:0] SimpleCSRTL_TL_TL_2_io_value; // @[SimpleCSR.scala 40:21:@1232.4] + wire SimpleCSRTL_TL_TL_3_clock; // @[SimpleCSR.scala 40:21:@1240.4] + wire SimpleCSRTL_TL_TL_3_reset; // @[SimpleCSR.scala 40:21:@1240.4] + wire [31:0] SimpleCSRTL_TL_TL_3_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1240.4] + wire SimpleCSRTL_TL_TL_3_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1240.4] + wire [31:0] SimpleCSRTL_TL_TL_3_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1240.4] + wire [31:0] SimpleCSRTL_TL_TL_3_io_value; // @[SimpleCSR.scala 40:21:@1240.4] + wire SimpleCSRTL_TL_TL_4_clock; // @[SimpleCSR.scala 40:21:@1249.4] + wire SimpleCSRTL_TL_TL_4_reset; // @[SimpleCSR.scala 40:21:@1249.4] + wire [31:0] SimpleCSRTL_TL_TL_4_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1249.4] + wire SimpleCSRTL_TL_TL_4_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1249.4] + wire [31:0] SimpleCSRTL_TL_TL_4_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1249.4] + wire [31:0] SimpleCSRTL_TL_TL_4_io_value; // @[SimpleCSR.scala 40:21:@1249.4] + wire SimpleCSRTL_TL_TL_5_clock; // @[SimpleCSR.scala 40:21:@1257.4] + wire SimpleCSRTL_TL_TL_5_reset; // @[SimpleCSR.scala 40:21:@1257.4] + wire [31:0] SimpleCSRTL_TL_TL_5_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1257.4] + wire SimpleCSRTL_TL_TL_5_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1257.4] + wire [31:0] SimpleCSRTL_TL_TL_5_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1257.4] + wire [31:0] SimpleCSRTL_TL_TL_5_io_value; // @[SimpleCSR.scala 40:21:@1257.4] + wire SimpleCSRTL_TL_TL_6_clock; // @[SimpleCSR.scala 40:21:@1265.4] + wire SimpleCSRTL_TL_TL_6_reset; // @[SimpleCSR.scala 40:21:@1265.4] + wire [31:0] SimpleCSRTL_TL_TL_6_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1265.4] + wire SimpleCSRTL_TL_TL_6_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1265.4] + wire [31:0] SimpleCSRTL_TL_TL_6_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1265.4] + wire [31:0] SimpleCSRTL_TL_TL_6_io_value; // @[SimpleCSR.scala 40:21:@1265.4] + wire SimpleCSRTL_TL_TL_7_clock; // @[SimpleCSR.scala 40:21:@1273.4] + wire SimpleCSRTL_TL_TL_7_reset; // @[SimpleCSR.scala 40:21:@1273.4] + wire [31:0] SimpleCSRTL_TL_TL_7_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1273.4] + wire SimpleCSRTL_TL_TL_7_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1273.4] + wire [31:0] SimpleCSRTL_TL_TL_7_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1273.4] + wire [31:0] SimpleCSRTL_TL_TL_7_io_value; // @[SimpleCSR.scala 40:21:@1273.4] + wire StatusCSRTL_TL_TL_1_clock; // @[StatusCSR.scala 34:21:@1281.4] + wire [31:0] StatusCSRTL_TL_TL_1_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1281.4] + wire [31:0] StatusCSRTL_TL_TL_1_io_value; // @[StatusCSR.scala 34:21:@1281.4] + wire StatusCSRTL_TL_TL_2_clock; // @[StatusCSR.scala 34:21:@1289.4] + wire [31:0] StatusCSRTL_TL_TL_2_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1289.4] + wire [31:0] StatusCSRTL_TL_TL_2_io_value; // @[StatusCSR.scala 34:21:@1289.4] + wire SimpleCSRTL_TL_TL_8_clock; // @[SimpleCSR.scala 40:21:@1297.4] + wire SimpleCSRTL_TL_TL_8_reset; // @[SimpleCSR.scala 40:21:@1297.4] + wire [31:0] SimpleCSRTL_TL_TL_8_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1297.4] + wire SimpleCSRTL_TL_TL_8_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1297.4] + wire [31:0] SimpleCSRTL_TL_TL_8_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1297.4] + wire [31:0] SimpleCSRTL_TL_TL_8_io_value; // @[SimpleCSR.scala 40:21:@1297.4] + wire SimpleCSRTL_TL_TL_9_clock; // @[SimpleCSR.scala 40:21:@1304.4] + wire SimpleCSRTL_TL_TL_9_reset; // @[SimpleCSR.scala 40:21:@1304.4] + wire [31:0] SimpleCSRTL_TL_TL_9_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1304.4] + wire SimpleCSRTL_TL_TL_9_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1304.4] + wire [31:0] SimpleCSRTL_TL_TL_9_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1304.4] + wire [31:0] SimpleCSRTL_TL_TL_9_io_value; // @[SimpleCSR.scala 40:21:@1304.4] + reg [1:0] status; // @[WorkerCSRWrapper.scala 39:23:@1146.4] reg [31:0] _RAND_0; - reg readerSync; // @[WorkerCSRWrapper.scala 41:27:@1078.4] + reg readerSync; // @[WorkerCSRWrapper.scala 41:27:@1148.4] reg [31:0] _RAND_1; - reg readerSyncOld; // @[WorkerCSRWrapper.scala 42:30:@1080.4] + reg readerSyncOld; // @[WorkerCSRWrapper.scala 42:30:@1150.4] reg [31:0] _RAND_2; - reg writerSync; // @[WorkerCSRWrapper.scala 44:27:@1082.4] + reg writerSync; // @[WorkerCSRWrapper.scala 44:27:@1152.4] reg [31:0] _RAND_3; - reg writerSyncOld; // @[WorkerCSRWrapper.scala 45:30:@1084.4] + reg writerSyncOld; // @[WorkerCSRWrapper.scala 45:30:@1154.4] reg [31:0] _RAND_4; - reg readerStart; // @[WorkerCSRWrapper.scala 47:28:@1086.4] + reg readerStart; // @[WorkerCSRWrapper.scala 47:28:@1156.4] reg [31:0] _RAND_5; - reg writerStart; // @[WorkerCSRWrapper.scala 48:28:@1087.4] + reg writerStart; // @[WorkerCSRWrapper.scala 48:28:@1157.4] reg [31:0] _RAND_6; - wire [1:0] _T_207; // @[Cat.scala 30:58:@1124.4] - wire [31:0] control; // @[WorkerCSRWrapper.scala 50:21:@1088.4 WorkerCSRWrapper.scala 59:11:@1100.4] - wire _T_208; // @[WorkerCSRWrapper.scala 66:56:@1125.4] - wire _T_209; // @[WorkerCSRWrapper.scala 66:68:@1126.4] - wire [1:0] _T_210; // @[Cat.scala 30:58:@1127.4] - wire [1:0] _T_211; // @[WorkerCSRWrapper.scala 66:44:@1128.4] - wire [1:0] clear; // @[WorkerCSRWrapper.scala 66:42:@1129.4] - wire _T_214; // @[WorkerCSRWrapper.scala 68:20:@1131.4] - wire _T_215; // @[WorkerCSRWrapper.scala 68:35:@1132.4] - wire _T_216; // @[WorkerCSRWrapper.scala 68:60:@1133.4] - wire _T_217; // @[WorkerCSRWrapper.scala 68:50:@1134.4] - wire _T_218; // @[WorkerCSRWrapper.scala 68:75:@1135.4] - wire _T_219; // @[WorkerCSRWrapper.scala 68:65:@1136.4] - wire _T_221; // @[WorkerCSRWrapper.scala 69:20:@1138.4] - wire _T_222; // @[WorkerCSRWrapper.scala 69:35:@1139.4] - wire _T_223; // @[WorkerCSRWrapper.scala 69:60:@1140.4] - wire _T_224; // @[WorkerCSRWrapper.scala 69:50:@1141.4] - wire _T_225; // @[WorkerCSRWrapper.scala 69:75:@1142.4] - wire _T_226; // @[WorkerCSRWrapper.scala 69:65:@1143.4] - AddressGeneratorTL_TL_TL addressGeneratorRead ( // @[WorkerCSRWrapper.scala 33:36:@1063.4] + wire [1:0] _T_207; // @[Cat.scala 30:58:@1194.4] + wire [31:0] control; // @[WorkerCSRWrapper.scala 50:21:@1158.4 WorkerCSRWrapper.scala 59:11:@1170.4] + wire _T_208; // @[WorkerCSRWrapper.scala 66:56:@1195.4] + wire _T_209; // @[WorkerCSRWrapper.scala 66:68:@1196.4] + wire [1:0] _T_210; // @[Cat.scala 30:58:@1197.4] + wire [1:0] _T_211; // @[WorkerCSRWrapper.scala 66:44:@1198.4] + wire [1:0] clear; // @[WorkerCSRWrapper.scala 66:42:@1199.4] + wire _T_214; // @[WorkerCSRWrapper.scala 68:20:@1201.4] + wire _T_215; // @[WorkerCSRWrapper.scala 68:35:@1202.4] + wire _T_216; // @[WorkerCSRWrapper.scala 68:60:@1203.4] + wire _T_217; // @[WorkerCSRWrapper.scala 68:50:@1204.4] + wire _T_218; // @[WorkerCSRWrapper.scala 68:75:@1205.4] + wire _T_219; // @[WorkerCSRWrapper.scala 68:65:@1206.4] + wire _T_221; // @[WorkerCSRWrapper.scala 69:20:@1208.4] + wire _T_222; // @[WorkerCSRWrapper.scala 69:35:@1209.4] + wire _T_223; // @[WorkerCSRWrapper.scala 69:60:@1210.4] + wire _T_224; // @[WorkerCSRWrapper.scala 69:50:@1211.4] + wire _T_225; // @[WorkerCSRWrapper.scala 69:75:@1212.4] + wire _T_226; // @[WorkerCSRWrapper.scala 69:65:@1213.4] + AddressGeneratorTL_TL_TL addressGeneratorRead ( // @[WorkerCSRWrapper.scala 33:36:@1133.4] .clock(addressGeneratorRead_clock), .reset(addressGeneratorRead_reset), .io_ctl_start(addressGeneratorRead_io_ctl_start), @@ -1925,7 +2167,7 @@ .io_xfer_length(addressGeneratorRead_io_xfer_length), .io_xfer_valid(addressGeneratorRead_io_xfer_valid) ); - TransferSplitterTL_TL_TL transferSplitterRead ( // @[WorkerCSRWrapper.scala 34:36:@1066.4] + TransferSplitterTL_TL_TL transferSplitterRead ( // @[WorkerCSRWrapper.scala 34:36:@1136.4] .io_xferIn_done(transferSplitterRead_io_xferIn_done), .io_xferIn_address(transferSplitterRead_io_xferIn_address), .io_xferIn_length(transferSplitterRead_io_xferIn_length), @@ -1935,7 +2177,7 @@ .io_xferOut_length(transferSplitterRead_io_xferOut_length), .io_xferOut_valid(transferSplitterRead_io_xferOut_valid) ); - AddressGeneratorTL_TL_TL addressGeneratorWrite ( // @[WorkerCSRWrapper.scala 36:37:@1069.4] + AddressGeneratorTL_TL_TL addressGeneratorWrite ( // @[WorkerCSRWrapper.scala 36:37:@1139.4] .clock(addressGeneratorWrite_clock), .reset(addressGeneratorWrite_reset), .io_ctl_start(addressGeneratorWrite_io_ctl_start), @@ -1949,7 +2191,7 @@ .io_xfer_length(addressGeneratorWrite_io_xfer_length), .io_xfer_valid(addressGeneratorWrite_io_xfer_valid) ); - TransferSplitterTL_TL_TL_1 transferSplitterWrite ( // @[WorkerCSRWrapper.scala 37:37:@1072.4] + TransferSplitterTL_TL_TL_1 transferSplitterWrite ( // @[WorkerCSRWrapper.scala 37:37:@1142.4] .clock(transferSplitterWrite_clock), .reset(transferSplitterWrite_reset), .io_xferIn_done(transferSplitterWrite_io_xferIn_done), @@ -1961,7 +2203,7 @@ .io_xferOut_length(transferSplitterWrite_io_xferOut_length), .io_xferOut_valid(transferSplitterWrite_io_xferOut_valid) ); - ClearCSRTL_TL_TL ClearCSRTL_TL_TL ( // @[ClearCSR.scala 42:21:@1092.4] + ClearCSRTL_TL_TL ClearCSRTL_TL_TL ( // @[ClearCSR.scala 42:21:@1162.4] .clock(ClearCSRTL_TL_TL_clock), .reset(ClearCSRTL_TL_TL_reset), .io_csr_dataOut(ClearCSRTL_TL_TL_io_csr_dataOut), @@ -1970,12 +2212,12 @@ .io_value(ClearCSRTL_TL_TL_io_value), .io_clear(ClearCSRTL_TL_TL_io_clear) ); - StatusCSRTL_TL_TL StatusCSRTL_TL_TL ( // @[StatusCSR.scala 34:21:@1101.4] + StatusCSRTL_TL_TL StatusCSRTL_TL_TL ( // @[StatusCSR.scala 34:21:@1171.4] .clock(StatusCSRTL_TL_TL_clock), .io_csr_dataIn(StatusCSRTL_TL_TL_io_csr_dataIn), .io_value(StatusCSRTL_TL_TL_io_value) ); - InterruptControllerTL_TL_TL InterruptControllerTL_TL_TL ( // @[InterruptController.scala 55:22:@1109.4] + InterruptControllerTL_TL_TL InterruptControllerTL_TL_TL ( // @[InterruptController.scala 55:22:@1179.4] .clock(InterruptControllerTL_TL_TL_clock), .reset(InterruptControllerTL_TL_TL_reset), .io_irq_readerDone(InterruptControllerTL_TL_TL_io_irq_readerDone), @@ -1989,7 +2231,7 @@ .io_isr_dataWrite(InterruptControllerTL_TL_TL_io_isr_dataWrite), .io_isr_dataIn(InterruptControllerTL_TL_TL_io_isr_dataIn) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL ( // @[SimpleCSR.scala 40:21:@1146.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL ( // @[SimpleCSR.scala 40:21:@1216.4] .clock(SimpleCSRTL_TL_TL_clock), .reset(SimpleCSRTL_TL_TL_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_io_csr_dataOut), @@ -1997,7 +2239,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_1 ( // @[SimpleCSR.scala 40:21:@1154.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_1 ( // @[SimpleCSR.scala 40:21:@1224.4] .clock(SimpleCSRTL_TL_TL_1_clock), .reset(SimpleCSRTL_TL_TL_1_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_1_io_csr_dataOut), @@ -2005,7 +2247,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_1_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_1_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_2 ( // @[SimpleCSR.scala 40:21:@1162.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_2 ( // @[SimpleCSR.scala 40:21:@1232.4] .clock(SimpleCSRTL_TL_TL_2_clock), .reset(SimpleCSRTL_TL_TL_2_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_2_io_csr_dataOut), @@ -2013,7 +2255,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_2_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_2_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_3 ( // @[SimpleCSR.scala 40:21:@1170.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_3 ( // @[SimpleCSR.scala 40:21:@1240.4] .clock(SimpleCSRTL_TL_TL_3_clock), .reset(SimpleCSRTL_TL_TL_3_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_3_io_csr_dataOut), @@ -2021,7 +2263,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_3_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_3_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_4 ( // @[SimpleCSR.scala 40:21:@1179.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_4 ( // @[SimpleCSR.scala 40:21:@1249.4] .clock(SimpleCSRTL_TL_TL_4_clock), .reset(SimpleCSRTL_TL_TL_4_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_4_io_csr_dataOut), @@ -2029,7 +2271,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_4_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_4_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_5 ( // @[SimpleCSR.scala 40:21:@1187.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_5 ( // @[SimpleCSR.scala 40:21:@1257.4] .clock(SimpleCSRTL_TL_TL_5_clock), .reset(SimpleCSRTL_TL_TL_5_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_5_io_csr_dataOut), @@ -2037,7 +2279,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_5_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_5_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_6 ( // @[SimpleCSR.scala 40:21:@1195.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_6 ( // @[SimpleCSR.scala 40:21:@1265.4] .clock(SimpleCSRTL_TL_TL_6_clock), .reset(SimpleCSRTL_TL_TL_6_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_6_io_csr_dataOut), @@ -2045,7 +2287,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_6_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_6_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_7 ( // @[SimpleCSR.scala 40:21:@1203.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_7 ( // @[SimpleCSR.scala 40:21:@1273.4] .clock(SimpleCSRTL_TL_TL_7_clock), .reset(SimpleCSRTL_TL_TL_7_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_7_io_csr_dataOut), @@ -2053,17 +2295,17 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_7_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_7_io_value) ); - StatusCSRTL_TL_TL StatusCSRTL_TL_TL_1 ( // @[StatusCSR.scala 34:21:@1211.4] + StatusCSRTL_TL_TL StatusCSRTL_TL_TL_1 ( // @[StatusCSR.scala 34:21:@1281.4] .clock(StatusCSRTL_TL_TL_1_clock), .io_csr_dataIn(StatusCSRTL_TL_TL_1_io_csr_dataIn), .io_value(StatusCSRTL_TL_TL_1_io_value) ); - StatusCSRTL_TL_TL StatusCSRTL_TL_TL_2 ( // @[StatusCSR.scala 34:21:@1219.4] + StatusCSRTL_TL_TL StatusCSRTL_TL_TL_2 ( // @[StatusCSR.scala 34:21:@1289.4] .clock(StatusCSRTL_TL_TL_2_clock), .io_csr_dataIn(StatusCSRTL_TL_TL_2_io_csr_dataIn), .io_value(StatusCSRTL_TL_TL_2_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_8 ( // @[SimpleCSR.scala 40:21:@1227.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_8 ( // @[SimpleCSR.scala 40:21:@1297.4] .clock(SimpleCSRTL_TL_TL_8_clock), .reset(SimpleCSRTL_TL_TL_8_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_8_io_csr_dataOut), @@ -2071,7 +2313,7 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_8_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_8_io_value) ); - SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_9 ( // @[SimpleCSR.scala 40:21:@1234.4] + SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_9 ( // @[SimpleCSR.scala 40:21:@1304.4] .clock(SimpleCSRTL_TL_TL_9_clock), .reset(SimpleCSRTL_TL_TL_9_reset), .io_csr_dataOut(SimpleCSRTL_TL_TL_9_io_csr_dataOut), @@ -2079,134 +2321,134 @@ .io_csr_dataIn(SimpleCSRTL_TL_TL_9_io_csr_dataIn), .io_value(SimpleCSRTL_TL_TL_9_io_value) ); - assign _T_207 = {readerStart,writerStart}; // @[Cat.scala 30:58:@1124.4] - assign control = ClearCSRTL_TL_TL_io_value; // @[WorkerCSRWrapper.scala 50:21:@1088.4 WorkerCSRWrapper.scala 59:11:@1100.4] - assign _T_208 = control[5]; // @[WorkerCSRWrapper.scala 66:56:@1125.4] - assign _T_209 = control[4]; // @[WorkerCSRWrapper.scala 66:68:@1126.4] - assign _T_210 = {_T_208,_T_209}; // @[Cat.scala 30:58:@1127.4] - assign _T_211 = ~ _T_210; // @[WorkerCSRWrapper.scala 66:44:@1128.4] - assign clear = _T_207 & _T_211; // @[WorkerCSRWrapper.scala 66:42:@1129.4] - assign _T_214 = readerSyncOld == 1'h0; // @[WorkerCSRWrapper.scala 68:20:@1131.4] - assign _T_215 = _T_214 & readerSync; // @[WorkerCSRWrapper.scala 68:35:@1132.4] - assign _T_216 = control[3]; // @[WorkerCSRWrapper.scala 68:60:@1133.4] - assign _T_217 = _T_215 | _T_216; // @[WorkerCSRWrapper.scala 68:50:@1134.4] - assign _T_218 = control[1]; // @[WorkerCSRWrapper.scala 68:75:@1135.4] - assign _T_219 = _T_217 & _T_218; // @[WorkerCSRWrapper.scala 68:65:@1136.4] - assign _T_221 = writerSyncOld == 1'h0; // @[WorkerCSRWrapper.scala 69:20:@1138.4] - assign _T_222 = _T_221 & writerSync; // @[WorkerCSRWrapper.scala 69:35:@1139.4] - assign _T_223 = control[2]; // @[WorkerCSRWrapper.scala 69:60:@1140.4] - assign _T_224 = _T_222 | _T_223; // @[WorkerCSRWrapper.scala 69:50:@1141.4] - assign _T_225 = control[0]; // @[WorkerCSRWrapper.scala 69:75:@1142.4] - assign _T_226 = _T_224 & _T_225; // @[WorkerCSRWrapper.scala 69:65:@1143.4] - assign io_csr_0_dataIn = ClearCSRTL_TL_TL_io_csr_dataIn; // @[ClearCSR.scala 46:16:@1096.4] - assign io_csr_1_dataIn = StatusCSRTL_TL_TL_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1104.4] - assign io_csr_2_dataIn = InterruptControllerTL_TL_TL_io_imr_dataIn; // @[InterruptController.scala 60:17:@1114.4] - assign io_csr_3_dataIn = InterruptControllerTL_TL_TL_io_isr_dataIn; // @[InterruptController.scala 61:17:@1118.4] - assign io_csr_4_dataIn = SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1149.4] - assign io_csr_5_dataIn = SimpleCSRTL_TL_TL_1_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1157.4] - assign io_csr_6_dataIn = SimpleCSRTL_TL_TL_2_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1165.4] - assign io_csr_7_dataIn = SimpleCSRTL_TL_TL_3_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1173.4] - assign io_csr_8_dataIn = SimpleCSRTL_TL_TL_4_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1182.4] - assign io_csr_9_dataIn = SimpleCSRTL_TL_TL_5_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1190.4] - assign io_csr_10_dataIn = SimpleCSRTL_TL_TL_6_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1198.4] - assign io_csr_11_dataIn = SimpleCSRTL_TL_TL_7_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1206.4] - assign io_csr_12_dataIn = StatusCSRTL_TL_TL_1_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1214.4] - assign io_csr_13_dataIn = StatusCSRTL_TL_TL_2_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1222.4] - assign io_csr_14_dataIn = SimpleCSRTL_TL_TL_8_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1230.4] - assign io_csr_15_dataIn = SimpleCSRTL_TL_TL_9_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1237.4] - assign io_irq_readerDone = InterruptControllerTL_TL_TL_io_irq_readerDone; // @[WorkerCSRWrapper.scala 63:10:@1123.4] - assign io_irq_writerDone = InterruptControllerTL_TL_TL_io_irq_writerDone; // @[WorkerCSRWrapper.scala 63:10:@1122.4] - assign io_xferRead_address = transferSplitterRead_io_xferOut_address; // @[WorkerCSRWrapper.scala 91:15:@1249.4] - assign io_xferRead_length = transferSplitterRead_io_xferOut_length; // @[WorkerCSRWrapper.scala 91:15:@1248.4] - assign io_xferRead_valid = transferSplitterRead_io_xferOut_valid; // @[WorkerCSRWrapper.scala 91:15:@1247.4] - assign io_xferWrite_address = transferSplitterWrite_io_xferOut_address; // @[WorkerCSRWrapper.scala 94:16:@1259.4] - assign io_xferWrite_length = transferSplitterWrite_io_xferOut_length; // @[WorkerCSRWrapper.scala 94:16:@1258.4] - assign io_xferWrite_valid = transferSplitterWrite_io_xferOut_valid; // @[WorkerCSRWrapper.scala 94:16:@1257.4] - assign addressGeneratorRead_clock = clock; // @[:@1064.4] - assign addressGeneratorRead_reset = reset; // @[:@1065.4] - assign addressGeneratorRead_io_ctl_start = readerStart; // @[WorkerCSRWrapper.scala 71:37:@1145.4] - assign addressGeneratorRead_io_ctl_startAddress = SimpleCSRTL_TL_TL_io_value; // @[WorkerCSRWrapper.scala 72:44:@1153.4] - assign addressGeneratorRead_io_ctl_lineLength = SimpleCSRTL_TL_TL_1_io_value; // @[WorkerCSRWrapper.scala 73:42:@1161.4] - assign addressGeneratorRead_io_ctl_lineCount = SimpleCSRTL_TL_TL_2_io_value; // @[WorkerCSRWrapper.scala 74:41:@1169.4] - assign addressGeneratorRead_io_ctl_lineGap = SimpleCSRTL_TL_TL_3_io_value; // @[WorkerCSRWrapper.scala 75:39:@1177.4] - assign addressGeneratorRead_io_xfer_done = transferSplitterRead_io_xferIn_done; // @[WorkerCSRWrapper.scala 90:34:@1245.4] - assign transferSplitterRead_io_xferIn_address = addressGeneratorRead_io_xfer_address; // @[WorkerCSRWrapper.scala 90:34:@1244.4] - assign transferSplitterRead_io_xferIn_length = addressGeneratorRead_io_xfer_length; // @[WorkerCSRWrapper.scala 90:34:@1243.4] - assign transferSplitterRead_io_xferIn_valid = addressGeneratorRead_io_xfer_valid; // @[WorkerCSRWrapper.scala 90:34:@1242.4] - assign transferSplitterRead_io_xferOut_done = io_xferRead_done; // @[WorkerCSRWrapper.scala 91:15:@1250.4] - assign addressGeneratorWrite_clock = clock; // @[:@1070.4] - assign addressGeneratorWrite_reset = reset; // @[:@1071.4] - assign addressGeneratorWrite_io_ctl_start = writerStart; // @[WorkerCSRWrapper.scala 77:38:@1178.4] - assign addressGeneratorWrite_io_ctl_startAddress = SimpleCSRTL_TL_TL_4_io_value; // @[WorkerCSRWrapper.scala 78:45:@1186.4] - assign addressGeneratorWrite_io_ctl_lineLength = SimpleCSRTL_TL_TL_5_io_value; // @[WorkerCSRWrapper.scala 79:43:@1194.4] - assign addressGeneratorWrite_io_ctl_lineCount = SimpleCSRTL_TL_TL_6_io_value; // @[WorkerCSRWrapper.scala 80:42:@1202.4] - assign addressGeneratorWrite_io_ctl_lineGap = SimpleCSRTL_TL_TL_7_io_value; // @[WorkerCSRWrapper.scala 81:40:@1210.4] - assign addressGeneratorWrite_io_xfer_done = transferSplitterWrite_io_xferIn_done; // @[WorkerCSRWrapper.scala 93:35:@1255.4] - assign transferSplitterWrite_clock = clock; // @[:@1073.4] - assign transferSplitterWrite_reset = reset; // @[:@1074.4] - assign transferSplitterWrite_io_xferIn_address = addressGeneratorWrite_io_xfer_address; // @[WorkerCSRWrapper.scala 93:35:@1254.4] - assign transferSplitterWrite_io_xferIn_length = addressGeneratorWrite_io_xfer_length; // @[WorkerCSRWrapper.scala 93:35:@1253.4] - assign transferSplitterWrite_io_xferIn_valid = addressGeneratorWrite_io_xfer_valid; // @[WorkerCSRWrapper.scala 93:35:@1252.4] - assign transferSplitterWrite_io_xferOut_done = io_xferWrite_done; // @[WorkerCSRWrapper.scala 94:16:@1260.4] - assign ClearCSRTL_TL_TL_clock = clock; // @[:@1093.4] - assign ClearCSRTL_TL_TL_reset = reset; // @[:@1094.4] - assign ClearCSRTL_TL_TL_io_csr_dataOut = io_csr_0_dataOut; // @[ClearCSR.scala 46:16:@1098.4] - assign ClearCSRTL_TL_TL_io_csr_dataWrite = io_csr_0_dataWrite; // @[ClearCSR.scala 46:16:@1097.4] - assign ClearCSRTL_TL_TL_io_clear = {{30'd0}, clear}; // @[ClearCSR.scala 44:18:@1095.4] - assign StatusCSRTL_TL_TL_clock = clock; // @[:@1102.4] - assign StatusCSRTL_TL_TL_io_value = {{30'd0}, status}; // @[StatusCSR.scala 38:18:@1108.4] - assign InterruptControllerTL_TL_TL_clock = clock; // @[:@1110.4] - assign InterruptControllerTL_TL_TL_reset = reset; // @[:@1111.4] - assign InterruptControllerTL_TL_TL_io_readBusy = addressGeneratorRead_io_ctl_busy; // @[InterruptController.scala 57:22:@1112.4] - assign InterruptControllerTL_TL_TL_io_writeBusy = addressGeneratorWrite_io_ctl_busy; // @[InterruptController.scala 58:23:@1113.4] - assign InterruptControllerTL_TL_TL_io_imr_dataOut = io_csr_2_dataOut; // @[InterruptController.scala 60:17:@1116.4] - assign InterruptControllerTL_TL_TL_io_imr_dataWrite = io_csr_2_dataWrite; // @[InterruptController.scala 60:17:@1115.4] - assign InterruptControllerTL_TL_TL_io_isr_dataOut = io_csr_3_dataOut; // @[InterruptController.scala 61:17:@1120.4] - assign InterruptControllerTL_TL_TL_io_isr_dataWrite = io_csr_3_dataWrite; // @[InterruptController.scala 61:17:@1119.4] - assign SimpleCSRTL_TL_TL_clock = clock; // @[:@1147.4] - assign SimpleCSRTL_TL_TL_reset = reset; // @[:@1148.4] - assign SimpleCSRTL_TL_TL_io_csr_dataOut = io_csr_4_dataOut; // @[SimpleCSR.scala 42:16:@1151.4] - assign SimpleCSRTL_TL_TL_io_csr_dataWrite = io_csr_4_dataWrite; // @[SimpleCSR.scala 42:16:@1150.4] - assign SimpleCSRTL_TL_TL_1_clock = clock; // @[:@1155.4] - assign SimpleCSRTL_TL_TL_1_reset = reset; // @[:@1156.4] - assign SimpleCSRTL_TL_TL_1_io_csr_dataOut = io_csr_5_dataOut; // @[SimpleCSR.scala 42:16:@1159.4] - assign SimpleCSRTL_TL_TL_1_io_csr_dataWrite = io_csr_5_dataWrite; // @[SimpleCSR.scala 42:16:@1158.4] - assign SimpleCSRTL_TL_TL_2_clock = clock; // @[:@1163.4] - assign SimpleCSRTL_TL_TL_2_reset = reset; // @[:@1164.4] - assign SimpleCSRTL_TL_TL_2_io_csr_dataOut = io_csr_6_dataOut; // @[SimpleCSR.scala 42:16:@1167.4] - assign SimpleCSRTL_TL_TL_2_io_csr_dataWrite = io_csr_6_dataWrite; // @[SimpleCSR.scala 42:16:@1166.4] - assign SimpleCSRTL_TL_TL_3_clock = clock; // @[:@1171.4] - assign SimpleCSRTL_TL_TL_3_reset = reset; // @[:@1172.4] - assign SimpleCSRTL_TL_TL_3_io_csr_dataOut = io_csr_7_dataOut; // @[SimpleCSR.scala 42:16:@1175.4] - assign SimpleCSRTL_TL_TL_3_io_csr_dataWrite = io_csr_7_dataWrite; // @[SimpleCSR.scala 42:16:@1174.4] - assign SimpleCSRTL_TL_TL_4_clock = clock; // @[:@1180.4] - assign SimpleCSRTL_TL_TL_4_reset = reset; // @[:@1181.4] - assign SimpleCSRTL_TL_TL_4_io_csr_dataOut = io_csr_8_dataOut; // @[SimpleCSR.scala 42:16:@1184.4] - assign SimpleCSRTL_TL_TL_4_io_csr_dataWrite = io_csr_8_dataWrite; // @[SimpleCSR.scala 42:16:@1183.4] - assign SimpleCSRTL_TL_TL_5_clock = clock; // @[:@1188.4] - assign SimpleCSRTL_TL_TL_5_reset = reset; // @[:@1189.4] - assign SimpleCSRTL_TL_TL_5_io_csr_dataOut = io_csr_9_dataOut; // @[SimpleCSR.scala 42:16:@1192.4] - assign SimpleCSRTL_TL_TL_5_io_csr_dataWrite = io_csr_9_dataWrite; // @[SimpleCSR.scala 42:16:@1191.4] - assign SimpleCSRTL_TL_TL_6_clock = clock; // @[:@1196.4] - assign SimpleCSRTL_TL_TL_6_reset = reset; // @[:@1197.4] - assign SimpleCSRTL_TL_TL_6_io_csr_dataOut = io_csr_10_dataOut; // @[SimpleCSR.scala 42:16:@1200.4] - assign SimpleCSRTL_TL_TL_6_io_csr_dataWrite = io_csr_10_dataWrite; // @[SimpleCSR.scala 42:16:@1199.4] - assign SimpleCSRTL_TL_TL_7_clock = clock; // @[:@1204.4] - assign SimpleCSRTL_TL_TL_7_reset = reset; // @[:@1205.4] - assign SimpleCSRTL_TL_TL_7_io_csr_dataOut = io_csr_11_dataOut; // @[SimpleCSR.scala 42:16:@1208.4] - assign SimpleCSRTL_TL_TL_7_io_csr_dataWrite = io_csr_11_dataWrite; // @[SimpleCSR.scala 42:16:@1207.4] - assign StatusCSRTL_TL_TL_1_clock = clock; // @[:@1212.4] - assign StatusCSRTL_TL_TL_1_io_value = 32'h0; // @[StatusCSR.scala 38:18:@1218.4] - assign StatusCSRTL_TL_TL_2_clock = clock; // @[:@1220.4] - assign StatusCSRTL_TL_TL_2_io_value = 32'h555; // @[StatusCSR.scala 38:18:@1226.4] - assign SimpleCSRTL_TL_TL_8_clock = clock; // @[:@1228.4] - assign SimpleCSRTL_TL_TL_8_reset = reset; // @[:@1229.4] - assign SimpleCSRTL_TL_TL_8_io_csr_dataOut = io_csr_14_dataOut; // @[SimpleCSR.scala 42:16:@1232.4] - assign SimpleCSRTL_TL_TL_8_io_csr_dataWrite = io_csr_14_dataWrite; // @[SimpleCSR.scala 42:16:@1231.4] - assign SimpleCSRTL_TL_TL_9_clock = clock; // @[:@1235.4] - assign SimpleCSRTL_TL_TL_9_reset = reset; // @[:@1236.4] - assign SimpleCSRTL_TL_TL_9_io_csr_dataOut = io_csr_15_dataOut; // @[SimpleCSR.scala 42:16:@1239.4] - assign SimpleCSRTL_TL_TL_9_io_csr_dataWrite = io_csr_15_dataWrite; // @[SimpleCSR.scala 42:16:@1238.4] + assign _T_207 = {readerStart,writerStart}; // @[Cat.scala 30:58:@1194.4] + assign control = ClearCSRTL_TL_TL_io_value; // @[WorkerCSRWrapper.scala 50:21:@1158.4 WorkerCSRWrapper.scala 59:11:@1170.4] + assign _T_208 = control[5]; // @[WorkerCSRWrapper.scala 66:56:@1195.4] + assign _T_209 = control[4]; // @[WorkerCSRWrapper.scala 66:68:@1196.4] + assign _T_210 = {_T_208,_T_209}; // @[Cat.scala 30:58:@1197.4] + assign _T_211 = ~ _T_210; // @[WorkerCSRWrapper.scala 66:44:@1198.4] + assign clear = _T_207 & _T_211; // @[WorkerCSRWrapper.scala 66:42:@1199.4] + assign _T_214 = readerSyncOld == 1'h0; // @[WorkerCSRWrapper.scala 68:20:@1201.4] + assign _T_215 = _T_214 & readerSync; // @[WorkerCSRWrapper.scala 68:35:@1202.4] + assign _T_216 = control[3]; // @[WorkerCSRWrapper.scala 68:60:@1203.4] + assign _T_217 = _T_215 | _T_216; // @[WorkerCSRWrapper.scala 68:50:@1204.4] + assign _T_218 = control[1]; // @[WorkerCSRWrapper.scala 68:75:@1205.4] + assign _T_219 = _T_217 & _T_218; // @[WorkerCSRWrapper.scala 68:65:@1206.4] + assign _T_221 = writerSyncOld == 1'h0; // @[WorkerCSRWrapper.scala 69:20:@1208.4] + assign _T_222 = _T_221 & writerSync; // @[WorkerCSRWrapper.scala 69:35:@1209.4] + assign _T_223 = control[2]; // @[WorkerCSRWrapper.scala 69:60:@1210.4] + assign _T_224 = _T_222 | _T_223; // @[WorkerCSRWrapper.scala 69:50:@1211.4] + assign _T_225 = control[0]; // @[WorkerCSRWrapper.scala 69:75:@1212.4] + assign _T_226 = _T_224 & _T_225; // @[WorkerCSRWrapper.scala 69:65:@1213.4] + assign io_csr_0_dataIn = ClearCSRTL_TL_TL_io_csr_dataIn; // @[ClearCSR.scala 46:16:@1166.4] + assign io_csr_1_dataIn = StatusCSRTL_TL_TL_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1174.4] + assign io_csr_2_dataIn = InterruptControllerTL_TL_TL_io_imr_dataIn; // @[InterruptController.scala 60:17:@1184.4] + assign io_csr_3_dataIn = InterruptControllerTL_TL_TL_io_isr_dataIn; // @[InterruptController.scala 61:17:@1188.4] + assign io_csr_4_dataIn = SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1219.4] + assign io_csr_5_dataIn = SimpleCSRTL_TL_TL_1_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1227.4] + assign io_csr_6_dataIn = SimpleCSRTL_TL_TL_2_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1235.4] + assign io_csr_7_dataIn = SimpleCSRTL_TL_TL_3_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1243.4] + assign io_csr_8_dataIn = SimpleCSRTL_TL_TL_4_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1252.4] + assign io_csr_9_dataIn = SimpleCSRTL_TL_TL_5_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1260.4] + assign io_csr_10_dataIn = SimpleCSRTL_TL_TL_6_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1268.4] + assign io_csr_11_dataIn = SimpleCSRTL_TL_TL_7_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1276.4] + assign io_csr_12_dataIn = StatusCSRTL_TL_TL_1_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1284.4] + assign io_csr_13_dataIn = StatusCSRTL_TL_TL_2_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1292.4] + assign io_csr_14_dataIn = SimpleCSRTL_TL_TL_8_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1300.4] + assign io_csr_15_dataIn = SimpleCSRTL_TL_TL_9_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1307.4] + assign io_irq_readerDone = InterruptControllerTL_TL_TL_io_irq_readerDone; // @[WorkerCSRWrapper.scala 63:10:@1193.4] + assign io_irq_writerDone = InterruptControllerTL_TL_TL_io_irq_writerDone; // @[WorkerCSRWrapper.scala 63:10:@1192.4] + assign io_xferRead_address = transferSplitterRead_io_xferOut_address; // @[WorkerCSRWrapper.scala 91:15:@1319.4] + assign io_xferRead_length = transferSplitterRead_io_xferOut_length; // @[WorkerCSRWrapper.scala 91:15:@1318.4] + assign io_xferRead_valid = transferSplitterRead_io_xferOut_valid; // @[WorkerCSRWrapper.scala 91:15:@1317.4] + assign io_xferWrite_address = transferSplitterWrite_io_xferOut_address; // @[WorkerCSRWrapper.scala 94:16:@1329.4] + assign io_xferWrite_length = transferSplitterWrite_io_xferOut_length; // @[WorkerCSRWrapper.scala 94:16:@1328.4] + assign io_xferWrite_valid = transferSplitterWrite_io_xferOut_valid; // @[WorkerCSRWrapper.scala 94:16:@1327.4] + assign addressGeneratorRead_clock = clock; // @[:@1134.4] + assign addressGeneratorRead_reset = reset; // @[:@1135.4] + assign addressGeneratorRead_io_ctl_start = readerStart; // @[WorkerCSRWrapper.scala 71:37:@1215.4] + assign addressGeneratorRead_io_ctl_startAddress = SimpleCSRTL_TL_TL_io_value; // @[WorkerCSRWrapper.scala 72:44:@1223.4] + assign addressGeneratorRead_io_ctl_lineLength = SimpleCSRTL_TL_TL_1_io_value; // @[WorkerCSRWrapper.scala 73:42:@1231.4] + assign addressGeneratorRead_io_ctl_lineCount = SimpleCSRTL_TL_TL_2_io_value; // @[WorkerCSRWrapper.scala 74:41:@1239.4] + assign addressGeneratorRead_io_ctl_lineGap = SimpleCSRTL_TL_TL_3_io_value; // @[WorkerCSRWrapper.scala 75:39:@1247.4] + assign addressGeneratorRead_io_xfer_done = transferSplitterRead_io_xferIn_done; // @[WorkerCSRWrapper.scala 90:34:@1315.4] + assign transferSplitterRead_io_xferIn_address = addressGeneratorRead_io_xfer_address; // @[WorkerCSRWrapper.scala 90:34:@1314.4] + assign transferSplitterRead_io_xferIn_length = addressGeneratorRead_io_xfer_length; // @[WorkerCSRWrapper.scala 90:34:@1313.4] + assign transferSplitterRead_io_xferIn_valid = addressGeneratorRead_io_xfer_valid; // @[WorkerCSRWrapper.scala 90:34:@1312.4] + assign transferSplitterRead_io_xferOut_done = io_xferRead_done; // @[WorkerCSRWrapper.scala 91:15:@1320.4] + assign addressGeneratorWrite_clock = clock; // @[:@1140.4] + assign addressGeneratorWrite_reset = reset; // @[:@1141.4] + assign addressGeneratorWrite_io_ctl_start = writerStart; // @[WorkerCSRWrapper.scala 77:38:@1248.4] + assign addressGeneratorWrite_io_ctl_startAddress = SimpleCSRTL_TL_TL_4_io_value; // @[WorkerCSRWrapper.scala 78:45:@1256.4] + assign addressGeneratorWrite_io_ctl_lineLength = SimpleCSRTL_TL_TL_5_io_value; // @[WorkerCSRWrapper.scala 79:43:@1264.4] + assign addressGeneratorWrite_io_ctl_lineCount = SimpleCSRTL_TL_TL_6_io_value; // @[WorkerCSRWrapper.scala 80:42:@1272.4] + assign addressGeneratorWrite_io_ctl_lineGap = SimpleCSRTL_TL_TL_7_io_value; // @[WorkerCSRWrapper.scala 81:40:@1280.4] + assign addressGeneratorWrite_io_xfer_done = transferSplitterWrite_io_xferIn_done; // @[WorkerCSRWrapper.scala 93:35:@1325.4] + assign transferSplitterWrite_clock = clock; // @[:@1143.4] + assign transferSplitterWrite_reset = reset; // @[:@1144.4] + assign transferSplitterWrite_io_xferIn_address = addressGeneratorWrite_io_xfer_address; // @[WorkerCSRWrapper.scala 93:35:@1324.4] + assign transferSplitterWrite_io_xferIn_length = addressGeneratorWrite_io_xfer_length; // @[WorkerCSRWrapper.scala 93:35:@1323.4] + assign transferSplitterWrite_io_xferIn_valid = addressGeneratorWrite_io_xfer_valid; // @[WorkerCSRWrapper.scala 93:35:@1322.4] + assign transferSplitterWrite_io_xferOut_done = io_xferWrite_done; // @[WorkerCSRWrapper.scala 94:16:@1330.4] + assign ClearCSRTL_TL_TL_clock = clock; // @[:@1163.4] + assign ClearCSRTL_TL_TL_reset = reset; // @[:@1164.4] + assign ClearCSRTL_TL_TL_io_csr_dataOut = io_csr_0_dataOut; // @[ClearCSR.scala 46:16:@1168.4] + assign ClearCSRTL_TL_TL_io_csr_dataWrite = io_csr_0_dataWrite; // @[ClearCSR.scala 46:16:@1167.4] + assign ClearCSRTL_TL_TL_io_clear = {{30'd0}, clear}; // @[ClearCSR.scala 44:18:@1165.4] + assign StatusCSRTL_TL_TL_clock = clock; // @[:@1172.4] + assign StatusCSRTL_TL_TL_io_value = {{30'd0}, status}; // @[StatusCSR.scala 38:18:@1178.4] + assign InterruptControllerTL_TL_TL_clock = clock; // @[:@1180.4] + assign InterruptControllerTL_TL_TL_reset = reset; // @[:@1181.4] + assign InterruptControllerTL_TL_TL_io_readBusy = addressGeneratorRead_io_ctl_busy; // @[InterruptController.scala 57:22:@1182.4] + assign InterruptControllerTL_TL_TL_io_writeBusy = addressGeneratorWrite_io_ctl_busy; // @[InterruptController.scala 58:23:@1183.4] + assign InterruptControllerTL_TL_TL_io_imr_dataOut = io_csr_2_dataOut; // @[InterruptController.scala 60:17:@1186.4] + assign InterruptControllerTL_TL_TL_io_imr_dataWrite = io_csr_2_dataWrite; // @[InterruptController.scala 60:17:@1185.4] + assign InterruptControllerTL_TL_TL_io_isr_dataOut = io_csr_3_dataOut; // @[InterruptController.scala 61:17:@1190.4] + assign InterruptControllerTL_TL_TL_io_isr_dataWrite = io_csr_3_dataWrite; // @[InterruptController.scala 61:17:@1189.4] + assign SimpleCSRTL_TL_TL_clock = clock; // @[:@1217.4] + assign SimpleCSRTL_TL_TL_reset = reset; // @[:@1218.4] + assign SimpleCSRTL_TL_TL_io_csr_dataOut = io_csr_4_dataOut; // @[SimpleCSR.scala 42:16:@1221.4] + assign SimpleCSRTL_TL_TL_io_csr_dataWrite = io_csr_4_dataWrite; // @[SimpleCSR.scala 42:16:@1220.4] + assign SimpleCSRTL_TL_TL_1_clock = clock; // @[:@1225.4] + assign SimpleCSRTL_TL_TL_1_reset = reset; // @[:@1226.4] + assign SimpleCSRTL_TL_TL_1_io_csr_dataOut = io_csr_5_dataOut; // @[SimpleCSR.scala 42:16:@1229.4] + assign SimpleCSRTL_TL_TL_1_io_csr_dataWrite = io_csr_5_dataWrite; // @[SimpleCSR.scala 42:16:@1228.4] + assign SimpleCSRTL_TL_TL_2_clock = clock; // @[:@1233.4] + assign SimpleCSRTL_TL_TL_2_reset = reset; // @[:@1234.4] + assign SimpleCSRTL_TL_TL_2_io_csr_dataOut = io_csr_6_dataOut; // @[SimpleCSR.scala 42:16:@1237.4] + assign SimpleCSRTL_TL_TL_2_io_csr_dataWrite = io_csr_6_dataWrite; // @[SimpleCSR.scala 42:16:@1236.4] + assign SimpleCSRTL_TL_TL_3_clock = clock; // @[:@1241.4] + assign SimpleCSRTL_TL_TL_3_reset = reset; // @[:@1242.4] + assign SimpleCSRTL_TL_TL_3_io_csr_dataOut = io_csr_7_dataOut; // @[SimpleCSR.scala 42:16:@1245.4] + assign SimpleCSRTL_TL_TL_3_io_csr_dataWrite = io_csr_7_dataWrite; // @[SimpleCSR.scala 42:16:@1244.4] + assign SimpleCSRTL_TL_TL_4_clock = clock; // @[:@1250.4] + assign SimpleCSRTL_TL_TL_4_reset = reset; // @[:@1251.4] + assign SimpleCSRTL_TL_TL_4_io_csr_dataOut = io_csr_8_dataOut; // @[SimpleCSR.scala 42:16:@1254.4] + assign SimpleCSRTL_TL_TL_4_io_csr_dataWrite = io_csr_8_dataWrite; // @[SimpleCSR.scala 42:16:@1253.4] + assign SimpleCSRTL_TL_TL_5_clock = clock; // @[:@1258.4] + assign SimpleCSRTL_TL_TL_5_reset = reset; // @[:@1259.4] + assign SimpleCSRTL_TL_TL_5_io_csr_dataOut = io_csr_9_dataOut; // @[SimpleCSR.scala 42:16:@1262.4] + assign SimpleCSRTL_TL_TL_5_io_csr_dataWrite = io_csr_9_dataWrite; // @[SimpleCSR.scala 42:16:@1261.4] + assign SimpleCSRTL_TL_TL_6_clock = clock; // @[:@1266.4] + assign SimpleCSRTL_TL_TL_6_reset = reset; // @[:@1267.4] + assign SimpleCSRTL_TL_TL_6_io_csr_dataOut = io_csr_10_dataOut; // @[SimpleCSR.scala 42:16:@1270.4] + assign SimpleCSRTL_TL_TL_6_io_csr_dataWrite = io_csr_10_dataWrite; // @[SimpleCSR.scala 42:16:@1269.4] + assign SimpleCSRTL_TL_TL_7_clock = clock; // @[:@1274.4] + assign SimpleCSRTL_TL_TL_7_reset = reset; // @[:@1275.4] + assign SimpleCSRTL_TL_TL_7_io_csr_dataOut = io_csr_11_dataOut; // @[SimpleCSR.scala 42:16:@1278.4] + assign SimpleCSRTL_TL_TL_7_io_csr_dataWrite = io_csr_11_dataWrite; // @[SimpleCSR.scala 42:16:@1277.4] + assign StatusCSRTL_TL_TL_1_clock = clock; // @[:@1282.4] + assign StatusCSRTL_TL_TL_1_io_value = 32'h0; // @[StatusCSR.scala 38:18:@1288.4] + assign StatusCSRTL_TL_TL_2_clock = clock; // @[:@1290.4] + assign StatusCSRTL_TL_TL_2_io_value = 32'h555; // @[StatusCSR.scala 38:18:@1296.4] + assign SimpleCSRTL_TL_TL_8_clock = clock; // @[:@1298.4] + assign SimpleCSRTL_TL_TL_8_reset = reset; // @[:@1299.4] + assign SimpleCSRTL_TL_TL_8_io_csr_dataOut = io_csr_14_dataOut; // @[SimpleCSR.scala 42:16:@1302.4] + assign SimpleCSRTL_TL_TL_8_io_csr_dataWrite = io_csr_14_dataWrite; // @[SimpleCSR.scala 42:16:@1301.4] + assign SimpleCSRTL_TL_TL_9_clock = clock; // @[:@1305.4] + assign SimpleCSRTL_TL_TL_9_reset = reset; // @[:@1306.4] + assign SimpleCSRTL_TL_TL_9_io_csr_dataOut = io_csr_15_dataOut; // @[SimpleCSR.scala 42:16:@1309.4] + assign SimpleCSRTL_TL_TL_9_io_csr_dataWrite = io_csr_15_dataWrite; // @[SimpleCSR.scala 42:16:@1308.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2279,67 +2521,67 @@ end end endmodule -module Queue( // @[:@1262.2] - input clock, // @[:@1263.4] - input reset, // @[:@1264.4] - output io_enq_ready, // @[:@1265.4] - input io_enq_valid, // @[:@1265.4] - input [31:0] io_enq_bits, // @[:@1265.4] - input io_deq_ready, // @[:@1265.4] - output io_deq_valid, // @[:@1265.4] - output [31:0] io_deq_bits // @[:@1265.4] +module Queue( // @[:@1332.2] + input clock, // @[:@1333.4] + input reset, // @[:@1334.4] + output io_enq_ready, // @[:@1335.4] + input io_enq_valid, // @[:@1335.4] + input [31:0] io_enq_bits, // @[:@1335.4] + input io_deq_ready, // @[:@1335.4] + output io_deq_valid, // @[:@1335.4] + output [31:0] io_deq_bits // @[:@1335.4] ); - reg [31:0] ram [0:511]; // @[Decoupled.scala 215:24:@1267.4] + reg [31:0] ram [0:511]; // @[Decoupled.scala 215:24:@1337.4] reg [31:0] _RAND_0; - wire [31:0] ram__T_63_data; // @[Decoupled.scala 215:24:@1267.4] - wire [8:0] ram__T_63_addr; // @[Decoupled.scala 215:24:@1267.4] - wire [31:0] ram__T_49_data; // @[Decoupled.scala 215:24:@1267.4] - wire [8:0] ram__T_49_addr; // @[Decoupled.scala 215:24:@1267.4] - wire ram__T_49_mask; // @[Decoupled.scala 215:24:@1267.4] - wire ram__T_49_en; // @[Decoupled.scala 215:24:@1267.4] - reg [8:0] value; // @[Counter.scala 26:33:@1268.4] + wire [31:0] ram__T_63_data; // @[Decoupled.scala 215:24:@1337.4] + wire [8:0] ram__T_63_addr; // @[Decoupled.scala 215:24:@1337.4] + wire [31:0] ram__T_49_data; // @[Decoupled.scala 215:24:@1337.4] + wire [8:0] ram__T_49_addr; // @[Decoupled.scala 215:24:@1337.4] + wire ram__T_49_mask; // @[Decoupled.scala 215:24:@1337.4] + wire ram__T_49_en; // @[Decoupled.scala 215:24:@1337.4] + reg [8:0] value; // @[Counter.scala 26:33:@1338.4] reg [31:0] _RAND_1; - reg [8:0] value_1; // @[Counter.scala 26:33:@1269.4] + reg [8:0] value_1; // @[Counter.scala 26:33:@1339.4] reg [31:0] _RAND_2; - reg maybe_full; // @[Decoupled.scala 218:35:@1270.4] + reg maybe_full; // @[Decoupled.scala 218:35:@1340.4] reg [31:0] _RAND_3; - wire _T_41; // @[Decoupled.scala 220:41:@1271.4] - wire _T_43; // @[Decoupled.scala 221:36:@1272.4] - wire empty; // @[Decoupled.scala 221:33:@1273.4] - wire _T_44; // @[Decoupled.scala 222:32:@1274.4] - wire do_enq; // @[Decoupled.scala 37:37:@1275.4] - wire do_deq; // @[Decoupled.scala 37:37:@1278.4] - wire [9:0] _T_52; // @[Counter.scala 35:22:@1285.6] - wire [8:0] _T_53; // @[Counter.scala 35:22:@1286.6] - wire [8:0] _GEN_5; // @[Decoupled.scala 226:17:@1281.4] - wire [9:0] _T_56; // @[Counter.scala 35:22:@1291.6] - wire [8:0] _T_57; // @[Counter.scala 35:22:@1292.6] - wire [8:0] _GEN_6; // @[Decoupled.scala 230:17:@1289.4] - wire _T_58; // @[Decoupled.scala 233:16:@1295.4] - wire _GEN_7; // @[Decoupled.scala 233:28:@1296.4] + wire _T_41; // @[Decoupled.scala 220:41:@1341.4] + wire _T_43; // @[Decoupled.scala 221:36:@1342.4] + wire empty; // @[Decoupled.scala 221:33:@1343.4] + wire _T_44; // @[Decoupled.scala 222:32:@1344.4] + wire do_enq; // @[Decoupled.scala 37:37:@1345.4] + wire do_deq; // @[Decoupled.scala 37:37:@1348.4] + wire [9:0] _T_52; // @[Counter.scala 35:22:@1355.6] + wire [8:0] _T_53; // @[Counter.scala 35:22:@1356.6] + wire [8:0] _GEN_5; // @[Decoupled.scala 226:17:@1351.4] + wire [9:0] _T_56; // @[Counter.scala 35:22:@1361.6] + wire [8:0] _T_57; // @[Counter.scala 35:22:@1362.6] + wire [8:0] _GEN_6; // @[Decoupled.scala 230:17:@1359.4] + wire _T_58; // @[Decoupled.scala 233:16:@1365.4] + wire _GEN_7; // @[Decoupled.scala 233:28:@1366.4] assign ram__T_63_addr = value_1; - assign ram__T_63_data = ram[ram__T_63_addr]; // @[Decoupled.scala 215:24:@1267.4] + assign ram__T_63_data = ram[ram__T_63_addr]; // @[Decoupled.scala 215:24:@1337.4] assign ram__T_49_data = io_enq_bits; assign ram__T_49_addr = value; assign ram__T_49_mask = 1'h1; assign ram__T_49_en = io_enq_ready & io_enq_valid; - assign _T_41 = value == value_1; // @[Decoupled.scala 220:41:@1271.4] - assign _T_43 = maybe_full == 1'h0; // @[Decoupled.scala 221:36:@1272.4] - assign empty = _T_41 & _T_43; // @[Decoupled.scala 221:33:@1273.4] - assign _T_44 = _T_41 & maybe_full; // @[Decoupled.scala 222:32:@1274.4] - assign do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:@1275.4] - assign do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:@1278.4] - assign _T_52 = value + 9'h1; // @[Counter.scala 35:22:@1285.6] - assign _T_53 = value + 9'h1; // @[Counter.scala 35:22:@1286.6] - assign _GEN_5 = do_enq ? _T_53 : value; // @[Decoupled.scala 226:17:@1281.4] - assign _T_56 = value_1 + 9'h1; // @[Counter.scala 35:22:@1291.6] - assign _T_57 = value_1 + 9'h1; // @[Counter.scala 35:22:@1292.6] - assign _GEN_6 = do_deq ? _T_57 : value_1; // @[Decoupled.scala 230:17:@1289.4] - assign _T_58 = do_enq != do_deq; // @[Decoupled.scala 233:16:@1295.4] - assign _GEN_7 = _T_58 ? do_enq : maybe_full; // @[Decoupled.scala 233:28:@1296.4] - assign io_enq_ready = _T_44 == 1'h0; // @[Decoupled.scala 238:16:@1302.4] - assign io_deq_valid = empty == 1'h0; // @[Decoupled.scala 237:16:@1300.4] - assign io_deq_bits = ram__T_63_data; // @[Decoupled.scala 239:15:@1304.4] + assign _T_41 = value == value_1; // @[Decoupled.scala 220:41:@1341.4] + assign _T_43 = maybe_full == 1'h0; // @[Decoupled.scala 221:36:@1342.4] + assign empty = _T_41 & _T_43; // @[Decoupled.scala 221:33:@1343.4] + assign _T_44 = _T_41 & maybe_full; // @[Decoupled.scala 222:32:@1344.4] + assign do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:@1345.4] + assign do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:@1348.4] + assign _T_52 = value + 9'h1; // @[Counter.scala 35:22:@1355.6] + assign _T_53 = value + 9'h1; // @[Counter.scala 35:22:@1356.6] + assign _GEN_5 = do_enq ? _T_53 : value; // @[Decoupled.scala 226:17:@1351.4] + assign _T_56 = value_1 + 9'h1; // @[Counter.scala 35:22:@1361.6] + assign _T_57 = value_1 + 9'h1; // @[Counter.scala 35:22:@1362.6] + assign _GEN_6 = do_deq ? _T_57 : value_1; // @[Decoupled.scala 230:17:@1359.4] + assign _T_58 = do_enq != do_deq; // @[Decoupled.scala 233:16:@1365.4] + assign _GEN_7 = _T_58 ? do_enq : maybe_full; // @[Decoupled.scala 233:28:@1366.4] + assign io_enq_ready = _T_44 == 1'h0; // @[Decoupled.scala 238:16:@1372.4] + assign io_deq_valid = empty == 1'h0; // @[Decoupled.scala 237:16:@1370.4] + assign io_deq_bits = ram__T_63_data; // @[Decoupled.scala 239:15:@1374.4] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2385,7 +2627,7 @@ `endif // RANDOMIZE always @(posedge clock) begin if(ram__T_49_en & ram__T_49_mask) begin - ram[ram__T_49_addr] <= ram__T_49_data; // @[Decoupled.scala 215:24:@1267.4] + ram[ram__T_49_addr] <= ram__T_49_data; // @[Decoupled.scala 215:24:@1337.4] end if (reset) begin value <= 9'h0; @@ -2410,233 +2652,236 @@ end end endmodule -module DMATopTL_TL_TL( // @[:@1313.2] - input clock, // @[:@1314.4] - input reset, // @[:@1315.4] - input [2:0] io_control_a_opcode, // @[:@1316.4] - input [2:0] io_control_a_param, // @[:@1316.4] - input [1:0] io_control_a_size, // @[:@1316.4] - input [9:0] io_control_a_source, // @[:@1316.4] - input [31:0] io_control_a_address, // @[:@1316.4] - input [3:0] io_control_a_mask, // @[:@1316.4] - input [31:0] io_control_a_data, // @[:@1316.4] - input io_control_a_corrupt, // @[:@1316.4] - input io_control_a_valid, // @[:@1316.4] - output io_control_a_ready, // @[:@1316.4] - output [2:0] io_control_d_opcode, // @[:@1316.4] - output [2:0] io_control_d_param, // @[:@1316.4] - output [1:0] io_control_d_size, // @[:@1316.4] - output [9:0] io_control_d_source, // @[:@1316.4] - output io_control_d_sink, // @[:@1316.4] - output io_control_d_denied, // @[:@1316.4] - output [31:0] io_control_d_data, // @[:@1316.4] - output io_control_d_corrupt, // @[:@1316.4] - output io_control_d_valid, // @[:@1316.4] - input io_control_d_ready, // @[:@1316.4] - output [2:0] io_read_a_opcode, // @[:@1316.4] - output [2:0] io_read_a_param, // @[:@1316.4] - output [1:0] io_read_a_size, // @[:@1316.4] - output [9:0] io_read_a_source, // @[:@1316.4] - output [31:0] io_read_a_address, // @[:@1316.4] - output [3:0] io_read_a_mask, // @[:@1316.4] - output [31:0] io_read_a_data, // @[:@1316.4] - output io_read_a_corrupt, // @[:@1316.4] - output io_read_a_valid, // @[:@1316.4] - input io_read_a_ready, // @[:@1316.4] - input [2:0] io_read_d_opcode, // @[:@1316.4] - input [2:0] io_read_d_param, // @[:@1316.4] - input [1:0] io_read_d_size, // @[:@1316.4] - input [9:0] io_read_d_source, // @[:@1316.4] - input io_read_d_sink, // @[:@1316.4] - input io_read_d_denied, // @[:@1316.4] - input [31:0] io_read_d_data, // @[:@1316.4] - input io_read_d_corrupt, // @[:@1316.4] - input io_read_d_valid, // @[:@1316.4] - output io_read_d_ready, // @[:@1316.4] - output [2:0] io_write_a_opcode, // @[:@1316.4] - output [2:0] io_write_a_param, // @[:@1316.4] - output [1:0] io_write_a_size, // @[:@1316.4] - output [9:0] io_write_a_source, // @[:@1316.4] - output [31:0] io_write_a_address, // @[:@1316.4] - output [3:0] io_write_a_mask, // @[:@1316.4] - output [31:0] io_write_a_data, // @[:@1316.4] - output io_write_a_corrupt, // @[:@1316.4] - output io_write_a_valid, // @[:@1316.4] - input io_write_a_ready, // @[:@1316.4] - input [2:0] io_write_d_opcode, // @[:@1316.4] - input [2:0] io_write_d_param, // @[:@1316.4] - input [1:0] io_write_d_size, // @[:@1316.4] - input [9:0] io_write_d_source, // @[:@1316.4] - input io_write_d_sink, // @[:@1316.4] - input io_write_d_denied, // @[:@1316.4] - input [31:0] io_write_d_data, // @[:@1316.4] - input io_write_d_corrupt, // @[:@1316.4] - input io_write_d_valid, // @[:@1316.4] - output io_write_d_ready, // @[:@1316.4] - output io_irq_readerDone, // @[:@1316.4] - output io_irq_writerDone, // @[:@1316.4] - input io_sync_readerSync, // @[:@1316.4] - input io_sync_writerSync // @[:@1316.4] +module DMATopTL_TL_TL( // @[:@1383.2] + input clock, // @[:@1384.4] + input reset, // @[:@1385.4] + input [2:0] io_control_a_opcode, // @[:@1386.4] + input [2:0] io_control_a_param, // @[:@1386.4] + input [1:0] io_control_a_size, // @[:@1386.4] + input [9:0] io_control_a_source, // @[:@1386.4] + input [31:0] io_control_a_address, // @[:@1386.4] + input [3:0] io_control_a_mask, // @[:@1386.4] + input [31:0] io_control_a_data, // @[:@1386.4] + input io_control_a_corrupt, // @[:@1386.4] + input io_control_a_valid, // @[:@1386.4] + output io_control_a_ready, // @[:@1386.4] + output [2:0] io_control_d_opcode, // @[:@1386.4] + output [2:0] io_control_d_param, // @[:@1386.4] + output [1:0] io_control_d_size, // @[:@1386.4] + output [9:0] io_control_d_source, // @[:@1386.4] + output io_control_d_sink, // @[:@1386.4] + output io_control_d_denied, // @[:@1386.4] + output [31:0] io_control_d_data, // @[:@1386.4] + output io_control_d_corrupt, // @[:@1386.4] + output io_control_d_valid, // @[:@1386.4] + input io_control_d_ready, // @[:@1386.4] + output [2:0] io_read_a_opcode, // @[:@1386.4] + output [2:0] io_read_a_param, // @[:@1386.4] + output [1:0] io_read_a_size, // @[:@1386.4] + output [9:0] io_read_a_source, // @[:@1386.4] + output [31:0] io_read_a_address, // @[:@1386.4] + output [3:0] io_read_a_mask, // @[:@1386.4] + output [31:0] io_read_a_data, // @[:@1386.4] + output io_read_a_corrupt, // @[:@1386.4] + output io_read_a_valid, // @[:@1386.4] + input io_read_a_ready, // @[:@1386.4] + input [2:0] io_read_d_opcode, // @[:@1386.4] + input [2:0] io_read_d_param, // @[:@1386.4] + input [1:0] io_read_d_size, // @[:@1386.4] + input [9:0] io_read_d_source, // @[:@1386.4] + input io_read_d_sink, // @[:@1386.4] + input io_read_d_denied, // @[:@1386.4] + input [31:0] io_read_d_data, // @[:@1386.4] + input io_read_d_corrupt, // @[:@1386.4] + input io_read_d_valid, // @[:@1386.4] + output io_read_d_ready, // @[:@1386.4] + output [2:0] io_write_a_opcode, // @[:@1386.4] + output [2:0] io_write_a_param, // @[:@1386.4] + output [1:0] io_write_a_size, // @[:@1386.4] + output [9:0] io_write_a_source, // @[:@1386.4] + output [31:0] io_write_a_address, // @[:@1386.4] + output [3:0] io_write_a_mask, // @[:@1386.4] + output [31:0] io_write_a_data, // @[:@1386.4] + output io_write_a_corrupt, // @[:@1386.4] + output io_write_a_valid, // @[:@1386.4] + input io_write_a_ready, // @[:@1386.4] + input [2:0] io_write_d_opcode, // @[:@1386.4] + input [2:0] io_write_d_param, // @[:@1386.4] + input [1:0] io_write_d_size, // @[:@1386.4] + input [9:0] io_write_d_source, // @[:@1386.4] + input io_write_d_sink, // @[:@1386.4] + input io_write_d_denied, // @[:@1386.4] + input [31:0] io_write_d_data, // @[:@1386.4] + input io_write_d_corrupt, // @[:@1386.4] + input io_write_d_valid, // @[:@1386.4] + output io_write_d_ready, // @[:@1386.4] + output io_irq_readerDone, // @[:@1386.4] + output io_irq_writerDone, // @[:@1386.4] + input io_sync_readerSync, // @[:@1386.4] + input io_sync_writerSync // @[:@1386.4] ); - wire csrFrontend_clock; // @[DMATop.scala 38:27:@1318.4] - wire csrFrontend_reset; // @[DMATop.scala 38:27:@1318.4] - wire [2:0] csrFrontend_io_ctl_a_opcode; // @[DMATop.scala 38:27:@1318.4] - wire [1:0] csrFrontend_io_ctl_a_size; // @[DMATop.scala 38:27:@1318.4] - wire [9:0] csrFrontend_io_ctl_a_source; // @[DMATop.scala 38:27:@1318.4] - wire [31:0] csrFrontend_io_ctl_a_address; // @[DMATop.scala 38:27:@1318.4] - wire [31:0] csrFrontend_io_ctl_a_data; // @[DMATop.scala 38:27:@1318.4] - wire csrFrontend_io_ctl_a_valid; // @[DMATop.scala 38:27:@1318.4] - wire csrFrontend_io_ctl_a_ready; // @[DMATop.scala 38:27:@1318.4] - wire [2:0] csrFrontend_io_ctl_d_opcode; // @[DMATop.scala 38:27:@1318.4] - wire [1:0] csrFrontend_io_ctl_d_size; // @[DMATop.scala 38:27:@1318.4] - wire [9:0] csrFrontend_io_ctl_d_source; // @[DMATop.scala 38:27:@1318.4] - wire [31:0] csrFrontend_io_ctl_d_data; // @[DMATop.scala 38:27:@1318.4] - wire csrFrontend_io_ctl_d_valid; // @[DMATop.scala 38:27:@1318.4] - wire [3:0] csrFrontend_io_bus_addr; // @[DMATop.scala 38:27:@1318.4] - wire [31:0] csrFrontend_io_bus_dataOut; // @[DMATop.scala 38:27:@1318.4] - wire [31:0] csrFrontend_io_bus_dataIn; // @[DMATop.scala 38:27:@1318.4] - wire csrFrontend_io_bus_write; // @[DMATop.scala 38:27:@1318.4] - wire csrFrontend_io_bus_read; // @[DMATop.scala 38:27:@1318.4] - wire readerFrontend_clock; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_reset; // @[DMATop.scala 40:30:@1321.4] - wire [31:0] readerFrontend_io_bus_a_address; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_bus_a_valid; // @[DMATop.scala 40:30:@1321.4] - wire [31:0] readerFrontend_io_bus_d_data; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_bus_d_valid; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_bus_d_ready; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_dataIO_ready; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_dataIO_valid; // @[DMATop.scala 40:30:@1321.4] - wire [31:0] readerFrontend_io_dataIO_bits; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_xfer_done; // @[DMATop.scala 40:30:@1321.4] - wire [31:0] readerFrontend_io_xfer_address; // @[DMATop.scala 40:30:@1321.4] - wire [31:0] readerFrontend_io_xfer_length; // @[DMATop.scala 40:30:@1321.4] - wire readerFrontend_io_xfer_valid; // @[DMATop.scala 40:30:@1321.4] - wire writerFrontend_clock; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_reset; // @[DMATop.scala 42:30:@1324.4] - wire [31:0] writerFrontend_io_bus_a_address; // @[DMATop.scala 42:30:@1324.4] - wire [31:0] writerFrontend_io_bus_a_data; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_bus_a_valid; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_bus_d_valid; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_bus_d_ready; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_dataIO_ready; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_dataIO_valid; // @[DMATop.scala 42:30:@1324.4] - wire [31:0] writerFrontend_io_dataIO_bits; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_xfer_done; // @[DMATop.scala 42:30:@1324.4] - wire [31:0] writerFrontend_io_xfer_address; // @[DMATop.scala 42:30:@1324.4] - wire [31:0] writerFrontend_io_xfer_length; // @[DMATop.scala 42:30:@1324.4] - wire writerFrontend_io_xfer_valid; // @[DMATop.scala 42:30:@1324.4] - wire [31:0] csr_io_csr_0_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_0_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_0_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_1_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_2_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_2_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_2_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_3_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_3_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_3_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_4_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_4_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_4_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_5_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_5_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_5_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_6_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_6_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_6_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_7_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_7_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_7_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_8_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_8_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_8_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_9_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_9_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_9_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_10_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_10_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_10_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_11_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_11_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_11_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_12_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_13_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_14_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_14_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_14_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_15_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_csr_15_dataWrite; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_csr_15_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire [3:0] csr_io_bus_addr; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_bus_dataOut; // @[DMATop.scala 44:19:@1327.4] - wire [31:0] csr_io_bus_dataIn; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_bus_write; // @[DMATop.scala 44:19:@1327.4] - wire csr_io_bus_read; // @[DMATop.scala 44:19:@1327.4] - wire ctl_clock; // @[DMATop.scala 46:19:@1330.4] - wire ctl_reset; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_0_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_0_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_0_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_1_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_2_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_2_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_2_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_3_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_3_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_3_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_4_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_4_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_4_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_5_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_5_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_5_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_6_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_6_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_6_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_7_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_7_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_7_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_8_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_8_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_8_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_9_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_9_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_9_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_10_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_10_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_10_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_11_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_11_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_11_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_12_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_13_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_14_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_14_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_14_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_15_dataOut; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_csr_15_dataWrite; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_csr_15_dataIn; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_irq_readerDone; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_irq_writerDone; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_sync_readerSync; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_sync_writerSync; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_xferRead_done; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_xferRead_address; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_xferRead_length; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_xferRead_valid; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_xferWrite_done; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_xferWrite_address; // @[DMATop.scala 46:19:@1330.4] - wire [31:0] ctl_io_xferWrite_length; // @[DMATop.scala 46:19:@1330.4] - wire ctl_io_xferWrite_valid; // @[DMATop.scala 46:19:@1330.4] - wire queue_clock; // @[Decoupled.scala 294:21:@1333.4] - wire queue_reset; // @[Decoupled.scala 294:21:@1333.4] - wire queue_io_enq_ready; // @[Decoupled.scala 294:21:@1333.4] - wire queue_io_enq_valid; // @[Decoupled.scala 294:21:@1333.4] - wire [31:0] queue_io_enq_bits; // @[Decoupled.scala 294:21:@1333.4] - wire queue_io_deq_ready; // @[Decoupled.scala 294:21:@1333.4] - wire queue_io_deq_valid; // @[Decoupled.scala 294:21:@1333.4] - wire [31:0] queue_io_deq_bits; // @[Decoupled.scala 294:21:@1333.4] - TLULCSRTL_TL_TL csrFrontend ( // @[DMATop.scala 38:27:@1318.4] + wire csrFrontend_clock; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_reset; // @[DMATop.scala 38:27:@1388.4] + wire [2:0] csrFrontend_io_ctl_a_opcode; // @[DMATop.scala 38:27:@1388.4] + wire [1:0] csrFrontend_io_ctl_a_size; // @[DMATop.scala 38:27:@1388.4] + wire [9:0] csrFrontend_io_ctl_a_source; // @[DMATop.scala 38:27:@1388.4] + wire [31:0] csrFrontend_io_ctl_a_address; // @[DMATop.scala 38:27:@1388.4] + wire [31:0] csrFrontend_io_ctl_a_data; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_io_ctl_a_valid; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_io_ctl_a_ready; // @[DMATop.scala 38:27:@1388.4] + wire [2:0] csrFrontend_io_ctl_d_opcode; // @[DMATop.scala 38:27:@1388.4] + wire [1:0] csrFrontend_io_ctl_d_size; // @[DMATop.scala 38:27:@1388.4] + wire [9:0] csrFrontend_io_ctl_d_source; // @[DMATop.scala 38:27:@1388.4] + wire [31:0] csrFrontend_io_ctl_d_data; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_io_ctl_d_valid; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_io_ctl_d_ready; // @[DMATop.scala 38:27:@1388.4] + wire [3:0] csrFrontend_io_bus_addr; // @[DMATop.scala 38:27:@1388.4] + wire [31:0] csrFrontend_io_bus_dataOut; // @[DMATop.scala 38:27:@1388.4] + wire [31:0] csrFrontend_io_bus_dataIn; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_io_bus_write; // @[DMATop.scala 38:27:@1388.4] + wire csrFrontend_io_bus_read; // @[DMATop.scala 38:27:@1388.4] + wire readerFrontend_clock; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_reset; // @[DMATop.scala 40:30:@1391.4] + wire [31:0] readerFrontend_io_bus_a_address; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_bus_a_valid; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_bus_a_ready; // @[DMATop.scala 40:30:@1391.4] + wire [31:0] readerFrontend_io_bus_d_data; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_bus_d_valid; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_bus_d_ready; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_dataIO_ready; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_dataIO_valid; // @[DMATop.scala 40:30:@1391.4] + wire [31:0] readerFrontend_io_dataIO_bits; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_xfer_done; // @[DMATop.scala 40:30:@1391.4] + wire [31:0] readerFrontend_io_xfer_address; // @[DMATop.scala 40:30:@1391.4] + wire [31:0] readerFrontend_io_xfer_length; // @[DMATop.scala 40:30:@1391.4] + wire readerFrontend_io_xfer_valid; // @[DMATop.scala 40:30:@1391.4] + wire writerFrontend_clock; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_reset; // @[DMATop.scala 42:30:@1394.4] + wire [31:0] writerFrontend_io_bus_a_address; // @[DMATop.scala 42:30:@1394.4] + wire [31:0] writerFrontend_io_bus_a_data; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_bus_a_valid; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_bus_a_ready; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_bus_d_valid; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_bus_d_ready; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_dataIO_ready; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_dataIO_valid; // @[DMATop.scala 42:30:@1394.4] + wire [31:0] writerFrontend_io_dataIO_bits; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_xfer_done; // @[DMATop.scala 42:30:@1394.4] + wire [31:0] writerFrontend_io_xfer_address; // @[DMATop.scala 42:30:@1394.4] + wire [31:0] writerFrontend_io_xfer_length; // @[DMATop.scala 42:30:@1394.4] + wire writerFrontend_io_xfer_valid; // @[DMATop.scala 42:30:@1394.4] + wire [31:0] csr_io_csr_0_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_0_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_0_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_1_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_2_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_2_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_2_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_3_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_3_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_3_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_4_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_4_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_4_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_5_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_5_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_5_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_6_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_6_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_6_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_7_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_7_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_7_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_8_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_8_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_8_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_9_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_9_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_9_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_10_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_10_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_10_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_11_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_11_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_11_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_12_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_13_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_14_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_14_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_14_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_15_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_csr_15_dataWrite; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_csr_15_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire [3:0] csr_io_bus_addr; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_bus_dataOut; // @[DMATop.scala 44:19:@1397.4] + wire [31:0] csr_io_bus_dataIn; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_bus_write; // @[DMATop.scala 44:19:@1397.4] + wire csr_io_bus_read; // @[DMATop.scala 44:19:@1397.4] + wire ctl_clock; // @[DMATop.scala 46:19:@1400.4] + wire ctl_reset; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_0_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_0_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_0_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_1_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_2_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_2_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_2_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_3_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_3_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_3_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_4_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_4_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_4_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_5_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_5_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_5_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_6_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_6_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_6_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_7_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_7_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_7_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_8_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_8_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_8_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_9_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_9_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_9_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_10_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_10_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_10_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_11_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_11_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_11_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_12_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_13_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_14_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_14_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_14_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_15_dataOut; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_csr_15_dataWrite; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_csr_15_dataIn; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_irq_readerDone; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_irq_writerDone; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_sync_readerSync; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_sync_writerSync; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_xferRead_done; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_xferRead_address; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_xferRead_length; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_xferRead_valid; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_xferWrite_done; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_xferWrite_address; // @[DMATop.scala 46:19:@1400.4] + wire [31:0] ctl_io_xferWrite_length; // @[DMATop.scala 46:19:@1400.4] + wire ctl_io_xferWrite_valid; // @[DMATop.scala 46:19:@1400.4] + wire queue_clock; // @[Decoupled.scala 294:21:@1403.4] + wire queue_reset; // @[Decoupled.scala 294:21:@1403.4] + wire queue_io_enq_ready; // @[Decoupled.scala 294:21:@1403.4] + wire queue_io_enq_valid; // @[Decoupled.scala 294:21:@1403.4] + wire [31:0] queue_io_enq_bits; // @[Decoupled.scala 294:21:@1403.4] + wire queue_io_deq_ready; // @[Decoupled.scala 294:21:@1403.4] + wire queue_io_deq_valid; // @[Decoupled.scala 294:21:@1403.4] + wire [31:0] queue_io_deq_bits; // @[Decoupled.scala 294:21:@1403.4] + TLULCSRTL_TL_TL csrFrontend ( // @[DMATop.scala 38:27:@1388.4] .clock(csrFrontend_clock), .reset(csrFrontend_reset), .io_ctl_a_opcode(csrFrontend_io_ctl_a_opcode), @@ -2651,17 +2896,19 @@ .io_ctl_d_source(csrFrontend_io_ctl_d_source), .io_ctl_d_data(csrFrontend_io_ctl_d_data), .io_ctl_d_valid(csrFrontend_io_ctl_d_valid), + .io_ctl_d_ready(csrFrontend_io_ctl_d_ready), .io_bus_addr(csrFrontend_io_bus_addr), .io_bus_dataOut(csrFrontend_io_bus_dataOut), .io_bus_dataIn(csrFrontend_io_bus_dataIn), .io_bus_write(csrFrontend_io_bus_write), .io_bus_read(csrFrontend_io_bus_read) ); - TLULReaderTL_TL_TL readerFrontend ( // @[DMATop.scala 40:30:@1321.4] + TLULReaderTL_TL_TL readerFrontend ( // @[DMATop.scala 40:30:@1391.4] .clock(readerFrontend_clock), .reset(readerFrontend_reset), .io_bus_a_address(readerFrontend_io_bus_a_address), .io_bus_a_valid(readerFrontend_io_bus_a_valid), + .io_bus_a_ready(readerFrontend_io_bus_a_ready), .io_bus_d_data(readerFrontend_io_bus_d_data), .io_bus_d_valid(readerFrontend_io_bus_d_valid), .io_bus_d_ready(readerFrontend_io_bus_d_ready), @@ -2673,12 +2920,13 @@ .io_xfer_length(readerFrontend_io_xfer_length), .io_xfer_valid(readerFrontend_io_xfer_valid) ); - TLULWriterTL_TL_TL writerFrontend ( // @[DMATop.scala 42:30:@1324.4] + TLULWriterTL_TL_TL writerFrontend ( // @[DMATop.scala 42:30:@1394.4] .clock(writerFrontend_clock), .reset(writerFrontend_reset), .io_bus_a_address(writerFrontend_io_bus_a_address), .io_bus_a_data(writerFrontend_io_bus_a_data), .io_bus_a_valid(writerFrontend_io_bus_a_valid), + .io_bus_a_ready(writerFrontend_io_bus_a_ready), .io_bus_d_valid(writerFrontend_io_bus_d_valid), .io_bus_d_ready(writerFrontend_io_bus_d_ready), .io_dataIO_ready(writerFrontend_io_dataIO_ready), @@ -2689,7 +2937,7 @@ .io_xfer_length(writerFrontend_io_xfer_length), .io_xfer_valid(writerFrontend_io_xfer_valid) ); - CSRTL_TL_TL csr ( // @[DMATop.scala 44:19:@1327.4] + CSRTL_TL_TL csr ( // @[DMATop.scala 44:19:@1397.4] .io_csr_0_dataOut(csr_io_csr_0_dataOut), .io_csr_0_dataWrite(csr_io_csr_0_dataWrite), .io_csr_0_dataIn(csr_io_csr_0_dataIn), @@ -2738,7 +2986,7 @@ .io_bus_write(csr_io_bus_write), .io_bus_read(csr_io_bus_read) ); - WorkerCSRWrapperTL_TL_TL ctl ( // @[DMATop.scala 46:19:@1330.4] + WorkerCSRWrapperTL_TL_TL ctl ( // @[DMATop.scala 46:19:@1400.4] .clock(ctl_clock), .reset(ctl_reset), .io_csr_0_dataOut(ctl_io_csr_0_dataOut), @@ -2796,7 +3044,7 @@ .io_xferWrite_length(ctl_io_xferWrite_length), .io_xferWrite_valid(ctl_io_xferWrite_valid) ); - Queue queue ( // @[Decoupled.scala 294:21:@1333.4] + Queue queue ( // @[Decoupled.scala 294:21:@1403.4] .clock(queue_clock), .reset(queue_reset), .io_enq_ready(queue_io_enq_ready), @@ -2806,118 +3054,121 @@ .io_deq_valid(queue_io_deq_valid), .io_deq_bits(queue_io_deq_bits) ); - assign io_control_a_ready = csrFrontend_io_ctl_a_ready; // @[DMATop.scala 52:22:@1352.4] - assign io_control_d_opcode = csrFrontend_io_ctl_d_opcode; // @[DMATop.scala 52:22:@1351.4] - assign io_control_d_param = 3'h0; // @[DMATop.scala 52:22:@1350.4] - assign io_control_d_size = csrFrontend_io_ctl_d_size; // @[DMATop.scala 52:22:@1349.4] - assign io_control_d_source = csrFrontend_io_ctl_d_source; // @[DMATop.scala 52:22:@1348.4] - assign io_control_d_sink = 1'h0; // @[DMATop.scala 52:22:@1347.4] - assign io_control_d_denied = 1'h0; // @[DMATop.scala 52:22:@1346.4] - assign io_control_d_data = csrFrontend_io_ctl_d_data; // @[DMATop.scala 52:22:@1345.4] - assign io_control_d_corrupt = 1'h0; // @[DMATop.scala 52:22:@1344.4] - assign io_control_d_valid = csrFrontend_io_ctl_d_valid; // @[DMATop.scala 52:22:@1343.4] - assign io_read_a_opcode = 3'h4; // @[DMATop.scala 58:11:@1460.4] - assign io_read_a_param = 3'h0; // @[DMATop.scala 58:11:@1459.4] - assign io_read_a_size = 2'h2; // @[DMATop.scala 58:11:@1458.4] - assign io_read_a_source = 10'h0; // @[DMATop.scala 58:11:@1457.4] - assign io_read_a_address = readerFrontend_io_bus_a_address; // @[DMATop.scala 58:11:@1456.4] - assign io_read_a_mask = 4'hf; // @[DMATop.scala 58:11:@1455.4] - assign io_read_a_data = 32'h0; // @[DMATop.scala 58:11:@1454.4] - assign io_read_a_corrupt = 1'h0; // @[DMATop.scala 58:11:@1453.4] - assign io_read_a_valid = readerFrontend_io_bus_a_valid; // @[DMATop.scala 58:11:@1452.4] - assign io_read_d_ready = readerFrontend_io_bus_d_ready; // @[DMATop.scala 58:11:@1441.4] - assign io_write_a_opcode = 3'h0; // @[DMATop.scala 59:12:@1480.4] - assign io_write_a_param = 3'h0; // @[DMATop.scala 59:12:@1479.4] - assign io_write_a_size = 2'h2; // @[DMATop.scala 59:12:@1478.4] - assign io_write_a_source = 10'h0; // @[DMATop.scala 59:12:@1477.4] - assign io_write_a_address = writerFrontend_io_bus_a_address; // @[DMATop.scala 59:12:@1476.4] - assign io_write_a_mask = 4'hf; // @[DMATop.scala 59:12:@1475.4] - assign io_write_a_data = writerFrontend_io_bus_a_data; // @[DMATop.scala 59:12:@1474.4] - assign io_write_a_corrupt = 1'h0; // @[DMATop.scala 59:12:@1473.4] - assign io_write_a_valid = writerFrontend_io_bus_a_valid; // @[DMATop.scala 59:12:@1472.4] - assign io_write_d_ready = writerFrontend_io_bus_d_ready; // @[DMATop.scala 59:12:@1461.4] - assign io_irq_readerDone = ctl_io_irq_readerDone; // @[DMATop.scala 61:10:@1482.4] - assign io_irq_writerDone = ctl_io_irq_writerDone; // @[DMATop.scala 61:10:@1481.4] - assign csrFrontend_clock = clock; // @[:@1319.4] - assign csrFrontend_reset = reset; // @[:@1320.4] - assign csrFrontend_io_ctl_a_opcode = io_control_a_opcode; // @[DMATop.scala 52:22:@1361.4] - assign csrFrontend_io_ctl_a_size = io_control_a_size; // @[DMATop.scala 52:22:@1359.4] - assign csrFrontend_io_ctl_a_source = io_control_a_source; // @[DMATop.scala 52:22:@1358.4] - assign csrFrontend_io_ctl_a_address = io_control_a_address; // @[DMATop.scala 52:22:@1357.4] - assign csrFrontend_io_ctl_a_data = io_control_a_data; // @[DMATop.scala 52:22:@1355.4] - assign csrFrontend_io_ctl_a_valid = io_control_a_valid; // @[DMATop.scala 52:22:@1353.4] - assign csrFrontend_io_bus_dataIn = csr_io_bus_dataIn; // @[DMATop.scala 53:14:@1364.4] - assign readerFrontend_clock = clock; // @[:@1322.4] - assign readerFrontend_reset = reset; // @[:@1323.4] - assign readerFrontend_io_bus_d_data = io_read_d_data; // @[DMATop.scala 58:11:@1444.4] - assign readerFrontend_io_bus_d_valid = io_read_d_valid; // @[DMATop.scala 58:11:@1442.4] - assign readerFrontend_io_dataIO_ready = queue_io_enq_ready; // @[Decoupled.scala 297:17:@1338.4] - assign readerFrontend_io_xfer_address = ctl_io_xferRead_address; // @[DMATop.scala 55:26:@1434.4] - assign readerFrontend_io_xfer_length = ctl_io_xferRead_length; // @[DMATop.scala 55:26:@1433.4] - assign readerFrontend_io_xfer_valid = ctl_io_xferRead_valid; // @[DMATop.scala 55:26:@1432.4] - assign writerFrontend_clock = clock; // @[:@1325.4] - assign writerFrontend_reset = reset; // @[:@1326.4] - assign writerFrontend_io_bus_d_valid = io_write_d_valid; // @[DMATop.scala 59:12:@1462.4] - assign writerFrontend_io_dataIO_valid = queue_io_deq_valid; // @[DMATop.scala 50:9:@1340.4] - assign writerFrontend_io_dataIO_bits = queue_io_deq_bits; // @[DMATop.scala 50:9:@1339.4] - assign writerFrontend_io_xfer_address = ctl_io_xferWrite_address; // @[DMATop.scala 56:26:@1439.4] - assign writerFrontend_io_xfer_length = ctl_io_xferWrite_length; // @[DMATop.scala 56:26:@1438.4] - assign writerFrontend_io_xfer_valid = ctl_io_xferWrite_valid; // @[DMATop.scala 56:26:@1437.4] - assign csr_io_csr_0_dataIn = ctl_io_csr_0_dataIn; // @[DMATop.scala 54:14:@1367.4] - assign csr_io_csr_1_dataIn = ctl_io_csr_1_dataIn; // @[DMATop.scala 54:14:@1371.4] - assign csr_io_csr_2_dataIn = ctl_io_csr_2_dataIn; // @[DMATop.scala 54:14:@1375.4] - assign csr_io_csr_3_dataIn = ctl_io_csr_3_dataIn; // @[DMATop.scala 54:14:@1379.4] - assign csr_io_csr_4_dataIn = ctl_io_csr_4_dataIn; // @[DMATop.scala 54:14:@1383.4] - assign csr_io_csr_5_dataIn = ctl_io_csr_5_dataIn; // @[DMATop.scala 54:14:@1387.4] - assign csr_io_csr_6_dataIn = ctl_io_csr_6_dataIn; // @[DMATop.scala 54:14:@1391.4] - assign csr_io_csr_7_dataIn = ctl_io_csr_7_dataIn; // @[DMATop.scala 54:14:@1395.4] - assign csr_io_csr_8_dataIn = ctl_io_csr_8_dataIn; // @[DMATop.scala 54:14:@1399.4] - assign csr_io_csr_9_dataIn = ctl_io_csr_9_dataIn; // @[DMATop.scala 54:14:@1403.4] - assign csr_io_csr_10_dataIn = ctl_io_csr_10_dataIn; // @[DMATop.scala 54:14:@1407.4] - assign csr_io_csr_11_dataIn = ctl_io_csr_11_dataIn; // @[DMATop.scala 54:14:@1411.4] - assign csr_io_csr_12_dataIn = ctl_io_csr_12_dataIn; // @[DMATop.scala 54:14:@1415.4] - assign csr_io_csr_13_dataIn = ctl_io_csr_13_dataIn; // @[DMATop.scala 54:14:@1419.4] - assign csr_io_csr_14_dataIn = ctl_io_csr_14_dataIn; // @[DMATop.scala 54:14:@1423.4] - assign csr_io_csr_15_dataIn = ctl_io_csr_15_dataIn; // @[DMATop.scala 54:14:@1427.4] - assign csr_io_bus_addr = csrFrontend_io_bus_addr; // @[DMATop.scala 53:14:@1366.4] - assign csr_io_bus_dataOut = csrFrontend_io_bus_dataOut; // @[DMATop.scala 53:14:@1365.4] - assign csr_io_bus_write = csrFrontend_io_bus_write; // @[DMATop.scala 53:14:@1363.4] - assign csr_io_bus_read = csrFrontend_io_bus_read; // @[DMATop.scala 53:14:@1362.4] - assign ctl_clock = clock; // @[:@1331.4] - assign ctl_reset = reset; // @[:@1332.4] - assign ctl_io_csr_0_dataOut = csr_io_csr_0_dataOut; // @[DMATop.scala 54:14:@1369.4] - assign ctl_io_csr_0_dataWrite = csr_io_csr_0_dataWrite; // @[DMATop.scala 54:14:@1368.4] - assign ctl_io_csr_2_dataOut = csr_io_csr_2_dataOut; // @[DMATop.scala 54:14:@1377.4] - assign ctl_io_csr_2_dataWrite = csr_io_csr_2_dataWrite; // @[DMATop.scala 54:14:@1376.4] - assign ctl_io_csr_3_dataOut = csr_io_csr_3_dataOut; // @[DMATop.scala 54:14:@1381.4] - assign ctl_io_csr_3_dataWrite = csr_io_csr_3_dataWrite; // @[DMATop.scala 54:14:@1380.4] - assign ctl_io_csr_4_dataOut = csr_io_csr_4_dataOut; // @[DMATop.scala 54:14:@1385.4] - assign ctl_io_csr_4_dataWrite = csr_io_csr_4_dataWrite; // @[DMATop.scala 54:14:@1384.4] - assign ctl_io_csr_5_dataOut = csr_io_csr_5_dataOut; // @[DMATop.scala 54:14:@1389.4] - assign ctl_io_csr_5_dataWrite = csr_io_csr_5_dataWrite; // @[DMATop.scala 54:14:@1388.4] - assign ctl_io_csr_6_dataOut = csr_io_csr_6_dataOut; // @[DMATop.scala 54:14:@1393.4] - assign ctl_io_csr_6_dataWrite = csr_io_csr_6_dataWrite; // @[DMATop.scala 54:14:@1392.4] - assign ctl_io_csr_7_dataOut = csr_io_csr_7_dataOut; // @[DMATop.scala 54:14:@1397.4] - assign ctl_io_csr_7_dataWrite = csr_io_csr_7_dataWrite; // @[DMATop.scala 54:14:@1396.4] - assign ctl_io_csr_8_dataOut = csr_io_csr_8_dataOut; // @[DMATop.scala 54:14:@1401.4] - assign ctl_io_csr_8_dataWrite = csr_io_csr_8_dataWrite; // @[DMATop.scala 54:14:@1400.4] - assign ctl_io_csr_9_dataOut = csr_io_csr_9_dataOut; // @[DMATop.scala 54:14:@1405.4] - assign ctl_io_csr_9_dataWrite = csr_io_csr_9_dataWrite; // @[DMATop.scala 54:14:@1404.4] - assign ctl_io_csr_10_dataOut = csr_io_csr_10_dataOut; // @[DMATop.scala 54:14:@1409.4] - assign ctl_io_csr_10_dataWrite = csr_io_csr_10_dataWrite; // @[DMATop.scala 54:14:@1408.4] - assign ctl_io_csr_11_dataOut = csr_io_csr_11_dataOut; // @[DMATop.scala 54:14:@1413.4] - assign ctl_io_csr_11_dataWrite = csr_io_csr_11_dataWrite; // @[DMATop.scala 54:14:@1412.4] - assign ctl_io_csr_14_dataOut = csr_io_csr_14_dataOut; // @[DMATop.scala 54:14:@1425.4] - assign ctl_io_csr_14_dataWrite = csr_io_csr_14_dataWrite; // @[DMATop.scala 54:14:@1424.4] - assign ctl_io_csr_15_dataOut = csr_io_csr_15_dataOut; // @[DMATop.scala 54:14:@1429.4] - assign ctl_io_csr_15_dataWrite = csr_io_csr_15_dataWrite; // @[DMATop.scala 54:14:@1428.4] - assign ctl_io_sync_readerSync = io_sync_readerSync; // @[DMATop.scala 62:11:@1484.4] - assign ctl_io_sync_writerSync = io_sync_writerSync; // @[DMATop.scala 62:11:@1483.4] - assign ctl_io_xferRead_done = readerFrontend_io_xfer_done; // @[DMATop.scala 55:26:@1435.4] - assign ctl_io_xferWrite_done = writerFrontend_io_xfer_done; // @[DMATop.scala 56:26:@1440.4] - assign queue_clock = clock; // @[:@1334.4] - assign queue_reset = reset; // @[:@1335.4] - assign queue_io_enq_valid = readerFrontend_io_dataIO_valid; // @[Decoupled.scala 295:22:@1336.4] - assign queue_io_enq_bits = readerFrontend_io_dataIO_bits; // @[Decoupled.scala 296:21:@1337.4] - assign queue_io_deq_ready = writerFrontend_io_dataIO_ready; // @[DMATop.scala 50:9:@1341.4] + assign io_control_a_ready = csrFrontend_io_ctl_a_ready; // @[DMATop.scala 52:22:@1422.4] + assign io_control_d_opcode = csrFrontend_io_ctl_d_opcode; // @[DMATop.scala 52:22:@1421.4] + assign io_control_d_param = 3'h0; // @[DMATop.scala 52:22:@1420.4] + assign io_control_d_size = csrFrontend_io_ctl_d_size; // @[DMATop.scala 52:22:@1419.4] + assign io_control_d_source = csrFrontend_io_ctl_d_source; // @[DMATop.scala 52:22:@1418.4] + assign io_control_d_sink = 1'h0; // @[DMATop.scala 52:22:@1417.4] + assign io_control_d_denied = 1'h0; // @[DMATop.scala 52:22:@1416.4] + assign io_control_d_data = csrFrontend_io_ctl_d_data; // @[DMATop.scala 52:22:@1415.4] + assign io_control_d_corrupt = 1'h0; // @[DMATop.scala 52:22:@1414.4] + assign io_control_d_valid = csrFrontend_io_ctl_d_valid; // @[DMATop.scala 52:22:@1413.4] + assign io_read_a_opcode = 3'h4; // @[DMATop.scala 58:11:@1530.4] + assign io_read_a_param = 3'h0; // @[DMATop.scala 58:11:@1529.4] + assign io_read_a_size = 2'h2; // @[DMATop.scala 58:11:@1528.4] + assign io_read_a_source = 10'h0; // @[DMATop.scala 58:11:@1527.4] + assign io_read_a_address = readerFrontend_io_bus_a_address; // @[DMATop.scala 58:11:@1526.4] + assign io_read_a_mask = 4'hf; // @[DMATop.scala 58:11:@1525.4] + assign io_read_a_data = 32'h0; // @[DMATop.scala 58:11:@1524.4] + assign io_read_a_corrupt = 1'h0; // @[DMATop.scala 58:11:@1523.4] + assign io_read_a_valid = readerFrontend_io_bus_a_valid; // @[DMATop.scala 58:11:@1522.4] + assign io_read_d_ready = readerFrontend_io_bus_d_ready; // @[DMATop.scala 58:11:@1511.4] + assign io_write_a_opcode = 3'h0; // @[DMATop.scala 59:12:@1550.4] + assign io_write_a_param = 3'h0; // @[DMATop.scala 59:12:@1549.4] + assign io_write_a_size = 2'h2; // @[DMATop.scala 59:12:@1548.4] + assign io_write_a_source = 10'h0; // @[DMATop.scala 59:12:@1547.4] + assign io_write_a_address = writerFrontend_io_bus_a_address; // @[DMATop.scala 59:12:@1546.4] + assign io_write_a_mask = 4'hf; // @[DMATop.scala 59:12:@1545.4] + assign io_write_a_data = writerFrontend_io_bus_a_data; // @[DMATop.scala 59:12:@1544.4] + assign io_write_a_corrupt = 1'h0; // @[DMATop.scala 59:12:@1543.4] + assign io_write_a_valid = writerFrontend_io_bus_a_valid; // @[DMATop.scala 59:12:@1542.4] + assign io_write_d_ready = writerFrontend_io_bus_d_ready; // @[DMATop.scala 59:12:@1531.4] + assign io_irq_readerDone = ctl_io_irq_readerDone; // @[DMATop.scala 61:10:@1552.4] + assign io_irq_writerDone = ctl_io_irq_writerDone; // @[DMATop.scala 61:10:@1551.4] + assign csrFrontend_clock = clock; // @[:@1389.4] + assign csrFrontend_reset = reset; // @[:@1390.4] + assign csrFrontend_io_ctl_a_opcode = io_control_a_opcode; // @[DMATop.scala 52:22:@1431.4] + assign csrFrontend_io_ctl_a_size = io_control_a_size; // @[DMATop.scala 52:22:@1429.4] + assign csrFrontend_io_ctl_a_source = io_control_a_source; // @[DMATop.scala 52:22:@1428.4] + assign csrFrontend_io_ctl_a_address = io_control_a_address; // @[DMATop.scala 52:22:@1427.4] + assign csrFrontend_io_ctl_a_data = io_control_a_data; // @[DMATop.scala 52:22:@1425.4] + assign csrFrontend_io_ctl_a_valid = io_control_a_valid; // @[DMATop.scala 52:22:@1423.4] + assign csrFrontend_io_ctl_d_ready = io_control_d_ready; // @[DMATop.scala 52:22:@1412.4] + assign csrFrontend_io_bus_dataIn = csr_io_bus_dataIn; // @[DMATop.scala 53:14:@1434.4] + assign readerFrontend_clock = clock; // @[:@1392.4] + assign readerFrontend_reset = reset; // @[:@1393.4] + assign readerFrontend_io_bus_a_ready = io_read_a_ready; // @[DMATop.scala 58:11:@1521.4] + assign readerFrontend_io_bus_d_data = io_read_d_data; // @[DMATop.scala 58:11:@1514.4] + assign readerFrontend_io_bus_d_valid = io_read_d_valid; // @[DMATop.scala 58:11:@1512.4] + assign readerFrontend_io_dataIO_ready = queue_io_enq_ready; // @[Decoupled.scala 297:17:@1408.4] + assign readerFrontend_io_xfer_address = ctl_io_xferRead_address; // @[DMATop.scala 55:26:@1504.4] + assign readerFrontend_io_xfer_length = ctl_io_xferRead_length; // @[DMATop.scala 55:26:@1503.4] + assign readerFrontend_io_xfer_valid = ctl_io_xferRead_valid; // @[DMATop.scala 55:26:@1502.4] + assign writerFrontend_clock = clock; // @[:@1395.4] + assign writerFrontend_reset = reset; // @[:@1396.4] + assign writerFrontend_io_bus_a_ready = io_write_a_ready; // @[DMATop.scala 59:12:@1541.4] + assign writerFrontend_io_bus_d_valid = io_write_d_valid; // @[DMATop.scala 59:12:@1532.4] + assign writerFrontend_io_dataIO_valid = queue_io_deq_valid; // @[DMATop.scala 50:9:@1410.4] + assign writerFrontend_io_dataIO_bits = queue_io_deq_bits; // @[DMATop.scala 50:9:@1409.4] + assign writerFrontend_io_xfer_address = ctl_io_xferWrite_address; // @[DMATop.scala 56:26:@1509.4] + assign writerFrontend_io_xfer_length = ctl_io_xferWrite_length; // @[DMATop.scala 56:26:@1508.4] + assign writerFrontend_io_xfer_valid = ctl_io_xferWrite_valid; // @[DMATop.scala 56:26:@1507.4] + assign csr_io_csr_0_dataIn = ctl_io_csr_0_dataIn; // @[DMATop.scala 54:14:@1437.4] + assign csr_io_csr_1_dataIn = ctl_io_csr_1_dataIn; // @[DMATop.scala 54:14:@1441.4] + assign csr_io_csr_2_dataIn = ctl_io_csr_2_dataIn; // @[DMATop.scala 54:14:@1445.4] + assign csr_io_csr_3_dataIn = ctl_io_csr_3_dataIn; // @[DMATop.scala 54:14:@1449.4] + assign csr_io_csr_4_dataIn = ctl_io_csr_4_dataIn; // @[DMATop.scala 54:14:@1453.4] + assign csr_io_csr_5_dataIn = ctl_io_csr_5_dataIn; // @[DMATop.scala 54:14:@1457.4] + assign csr_io_csr_6_dataIn = ctl_io_csr_6_dataIn; // @[DMATop.scala 54:14:@1461.4] + assign csr_io_csr_7_dataIn = ctl_io_csr_7_dataIn; // @[DMATop.scala 54:14:@1465.4] + assign csr_io_csr_8_dataIn = ctl_io_csr_8_dataIn; // @[DMATop.scala 54:14:@1469.4] + assign csr_io_csr_9_dataIn = ctl_io_csr_9_dataIn; // @[DMATop.scala 54:14:@1473.4] + assign csr_io_csr_10_dataIn = ctl_io_csr_10_dataIn; // @[DMATop.scala 54:14:@1477.4] + assign csr_io_csr_11_dataIn = ctl_io_csr_11_dataIn; // @[DMATop.scala 54:14:@1481.4] + assign csr_io_csr_12_dataIn = ctl_io_csr_12_dataIn; // @[DMATop.scala 54:14:@1485.4] + assign csr_io_csr_13_dataIn = ctl_io_csr_13_dataIn; // @[DMATop.scala 54:14:@1489.4] + assign csr_io_csr_14_dataIn = ctl_io_csr_14_dataIn; // @[DMATop.scala 54:14:@1493.4] + assign csr_io_csr_15_dataIn = ctl_io_csr_15_dataIn; // @[DMATop.scala 54:14:@1497.4] + assign csr_io_bus_addr = csrFrontend_io_bus_addr; // @[DMATop.scala 53:14:@1436.4] + assign csr_io_bus_dataOut = csrFrontend_io_bus_dataOut; // @[DMATop.scala 53:14:@1435.4] + assign csr_io_bus_write = csrFrontend_io_bus_write; // @[DMATop.scala 53:14:@1433.4] + assign csr_io_bus_read = csrFrontend_io_bus_read; // @[DMATop.scala 53:14:@1432.4] + assign ctl_clock = clock; // @[:@1401.4] + assign ctl_reset = reset; // @[:@1402.4] + assign ctl_io_csr_0_dataOut = csr_io_csr_0_dataOut; // @[DMATop.scala 54:14:@1439.4] + assign ctl_io_csr_0_dataWrite = csr_io_csr_0_dataWrite; // @[DMATop.scala 54:14:@1438.4] + assign ctl_io_csr_2_dataOut = csr_io_csr_2_dataOut; // @[DMATop.scala 54:14:@1447.4] + assign ctl_io_csr_2_dataWrite = csr_io_csr_2_dataWrite; // @[DMATop.scala 54:14:@1446.4] + assign ctl_io_csr_3_dataOut = csr_io_csr_3_dataOut; // @[DMATop.scala 54:14:@1451.4] + assign ctl_io_csr_3_dataWrite = csr_io_csr_3_dataWrite; // @[DMATop.scala 54:14:@1450.4] + assign ctl_io_csr_4_dataOut = csr_io_csr_4_dataOut; // @[DMATop.scala 54:14:@1455.4] + assign ctl_io_csr_4_dataWrite = csr_io_csr_4_dataWrite; // @[DMATop.scala 54:14:@1454.4] + assign ctl_io_csr_5_dataOut = csr_io_csr_5_dataOut; // @[DMATop.scala 54:14:@1459.4] + assign ctl_io_csr_5_dataWrite = csr_io_csr_5_dataWrite; // @[DMATop.scala 54:14:@1458.4] + assign ctl_io_csr_6_dataOut = csr_io_csr_6_dataOut; // @[DMATop.scala 54:14:@1463.4] + assign ctl_io_csr_6_dataWrite = csr_io_csr_6_dataWrite; // @[DMATop.scala 54:14:@1462.4] + assign ctl_io_csr_7_dataOut = csr_io_csr_7_dataOut; // @[DMATop.scala 54:14:@1467.4] + assign ctl_io_csr_7_dataWrite = csr_io_csr_7_dataWrite; // @[DMATop.scala 54:14:@1466.4] + assign ctl_io_csr_8_dataOut = csr_io_csr_8_dataOut; // @[DMATop.scala 54:14:@1471.4] + assign ctl_io_csr_8_dataWrite = csr_io_csr_8_dataWrite; // @[DMATop.scala 54:14:@1470.4] + assign ctl_io_csr_9_dataOut = csr_io_csr_9_dataOut; // @[DMATop.scala 54:14:@1475.4] + assign ctl_io_csr_9_dataWrite = csr_io_csr_9_dataWrite; // @[DMATop.scala 54:14:@1474.4] + assign ctl_io_csr_10_dataOut = csr_io_csr_10_dataOut; // @[DMATop.scala 54:14:@1479.4] + assign ctl_io_csr_10_dataWrite = csr_io_csr_10_dataWrite; // @[DMATop.scala 54:14:@1478.4] + assign ctl_io_csr_11_dataOut = csr_io_csr_11_dataOut; // @[DMATop.scala 54:14:@1483.4] + assign ctl_io_csr_11_dataWrite = csr_io_csr_11_dataWrite; // @[DMATop.scala 54:14:@1482.4] + assign ctl_io_csr_14_dataOut = csr_io_csr_14_dataOut; // @[DMATop.scala 54:14:@1495.4] + assign ctl_io_csr_14_dataWrite = csr_io_csr_14_dataWrite; // @[DMATop.scala 54:14:@1494.4] + assign ctl_io_csr_15_dataOut = csr_io_csr_15_dataOut; // @[DMATop.scala 54:14:@1499.4] + assign ctl_io_csr_15_dataWrite = csr_io_csr_15_dataWrite; // @[DMATop.scala 54:14:@1498.4] + assign ctl_io_sync_readerSync = io_sync_readerSync; // @[DMATop.scala 62:11:@1554.4] + assign ctl_io_sync_writerSync = io_sync_writerSync; // @[DMATop.scala 62:11:@1553.4] + assign ctl_io_xferRead_done = readerFrontend_io_xfer_done; // @[DMATop.scala 55:26:@1505.4] + assign ctl_io_xferWrite_done = writerFrontend_io_xfer_done; // @[DMATop.scala 56:26:@1510.4] + assign queue_clock = clock; // @[:@1404.4] + assign queue_reset = reset; // @[:@1405.4] + assign queue_io_enq_valid = readerFrontend_io_dataIO_valid; // @[Decoupled.scala 295:22:@1406.4] + assign queue_io_enq_bits = readerFrontend_io_dataIO_bits; // @[Decoupled.scala 296:21:@1407.4] + assign queue_io_deq_ready = writerFrontend_io_dataIO_ready; // @[DMATop.scala 50:9:@1411.4] endmodule