Merge "Fix problem with chip_sw_pwrmgr_random_sleep_all_reset_reqs"
diff --git a/hw/top_matcha/data/clocks_nexus.xdc b/hw/top_matcha/data/clocks_nexus.xdc
index 74cbd85..8763a73 100644
--- a/hw/top_matcha/data/clocks_nexus.xdc
+++ b/hw/top_matcha/data/clocks_nexus.xdc
@@ -2,7 +2,7 @@
## Licensed under the Apache License, Version 2.0, see LICENSE for details.
## SPDX-License-Identifier: Apache-2.0
-## Clock Signal
+## Clock Signal - 100M >> 1/100e6 = 1e-8s = 10ns
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports IO_CLK]
## Rename MMCM outputs for less bug-prone parsing.
@@ -11,6 +11,11 @@
create_generated_clock -name clk_usb_48 [get_pin clkgen/pll/CLKOUT1]
create_generated_clock -name clk_aon [get_pin clkgen/pll/CLKOUT4]
+# Store clock periods in variables
+set clk_main_period [get_property PERIOD [get_clocks clk_main]]
+set clk_usb_48_period [get_property PERIOD [get_clocks clk_usb_48]]
+set clk_aon_period [get_property PERIOD [get_clocks clk_aon]]
+
## Clock Domain Crossings
set clks_10_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]]
set clks_48_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT1]]
@@ -42,15 +47,15 @@
] \
]
-## JTAG clocks
+## JTAG clocks TODO - clock frequency
create_clock -add -name lc_jtag_tck -period 200.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
create_clock -add -name rv_jtag_tck -period 200.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
## SPI clocks
set spi_dev_data [get_ports {SPI_DEV_D0 SPI_DEV_D1 SPI_DEV_D2 SPI_DEV_D3}]
-create_clock -add -name clk_spi -period 100.00 -waveform {0 50} [get_ports SPI_DEV_CLK]
-create_clock -add -name clk_cs -period 1000.00 -waveform {0 50} [get_ports SPI_DEV_CS_L]
-set_input_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
+create_clock -add -name clk_spi -period $clk_main_period -waveform {0 50} [get_ports SPI_DEV_CLK]
+create_clock -add -name clk_cs -period [expr $clk_main_period * 10] -waveform {0 50} [get_ports SPI_DEV_CS_L]
+set_input_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
set_output_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
# set_input_delay -clock clk_spi -clock_fall -min ${spi_dev_in_delay_min} ${spi_dev_data} -add_delay
# set_input_delay -clock clk_spi -clock_fall -max ${spi_dev_in_delay_max} ${spi_dev_data} -add_delay
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 55305c3..adc626e 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -1721,6 +1721,20 @@
run_opts: ["+clk_idx=5"]
}
{
+ name: chip_sw_clkmgr_off_video_trans
+ uvm_test_seq: chip_sw_clkmgr_off_gateable_clk_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_video_clk_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+clk_idx=4"]
+ }
+ {
+ name: chip_sw_clkmgr_off_audio_trans
+ uvm_test_seq: chip_sw_clkmgr_off_gateable_clk_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_audio_clk_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+clk_idx=6"]
+ }
+ {
name: chip_sw_clkmgr_external_clk_src_for_lc
uvm_test_seq: chip_sw_lc_ctrl_transition_vseq
sw_images: ["//sw/device/tests/sim_dv:clkmgr_external_clk_src_for_lc_test:1"]
@@ -2077,6 +2091,7 @@
"chip_sw_sysrst_ctrl_inputs",
"chip_sw_uart_smoketest",
"chip_sw_uart_tx_rx",
+ "chip_tap_straps_rma",
]
}
{
@@ -2085,6 +2100,7 @@
tests: [
"chip_padctrl_attributes",
"chip_plic_all_irqs",
+ "chip_rv_dm_lc_disabled",
"chip_rv_dm_ndm_reset_req",
"chip_sw_aes_smoketest",
"chip_sw_alert_handler_escalation",
@@ -2099,9 +2115,11 @@
"chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_external_clk_src_for_sw_fast",
"chip_sw_clkmgr_external_clk_src_for_sw_slow",
+ "chip_sw_clkmgr_off_audio_trans",
"chip_sw_clkmgr_off_ml_trans",
"chip_sw_clkmgr_off_peri",
"chip_sw_clkmgr_off_smc_trans",
+ "chip_sw_clkmgr_off_video_trans",
"chip_sw_clkmgr_reset_frequency",
"chip_sw_clkmgr_sleep_frequency",
"chip_sw_clkmgr_smoketest",
@@ -2188,6 +2206,7 @@
tests: [
"chip_padctrl_attributes",
"chip_plic_all_irqs",
+ "chip_rv_dm_lc_disabled",
"chip_rv_dm_ndm_reset_req",
"chip_sw_aes_smoketest",
"chip_sw_alert_handler_escalation",
@@ -2202,9 +2221,11 @@
"chip_sw_cam_ctrl_test",
"chip_sw_clkmgr_external_clk_src_for_sw_fast",
"chip_sw_clkmgr_external_clk_src_for_sw_slow",
+ "chip_sw_clkmgr_off_audio_trans",
"chip_sw_clkmgr_off_ml_trans",
"chip_sw_clkmgr_off_peri",
"chip_sw_clkmgr_off_smc_trans",
+ "chip_sw_clkmgr_off_video_trans",
"chip_sw_clkmgr_reset_frequency",
"chip_sw_clkmgr_sleep_frequency",
"chip_sw_clkmgr_smoketest",
diff --git a/hw/top_matcha/dv/env/seq_lib/chip_rv_dm_lc_disabled_vseq.sv b/hw/top_matcha/dv/env/seq_lib/chip_rv_dm_lc_disabled_vseq.sv
index 7e62783..de2ff16 100644
--- a/hw/top_matcha/dv/env/seq_lib/chip_rv_dm_lc_disabled_vseq.sv
+++ b/hw/top_matcha/dv/env/seq_lib/chip_rv_dm_lc_disabled_vseq.sv
@@ -1,3 +1,4 @@
+// Copyright 2023 Google LLC.
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
@@ -38,7 +39,7 @@
virtual task pre_start();
// Select RV_DM TAP via the TAP straps.
- cfg.chip_vif.tap_straps_if.drive(JtagTapRvDm);
+ cfg.select_jtag = JtagTapRvDm;
super.pre_start();
max_outstanding_accesses = 1;
endtask
diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD
index bce31d3..c5fa7d0 100644
--- a/sw/device/lib/testing/test_rom/BUILD
+++ b/sw/device/lib/testing/test_rom/BUILD
@@ -26,14 +26,9 @@
opentitan_rom_binary(
name = "test_rom",
- srcs = [
- "test_rom.c",
- "test_rom_start.S",
- ],
deps = [
":linker_script",
- ":test_rom_lib",
- "//sw/device/silicon_creator/rom:bootstrap",
+ ":test_rom_otp_lib",
],
)
@@ -48,7 +43,19 @@
":linker_script",
":test_rom_lib",
"//sw/device/silicon_creator/rom:bootstrap_no_otp",
- ]
+ ],
+)
+
+cc_library(
+ name = "test_rom_otp_lib",
+ srcs = [
+ "test_rom.c",
+ "test_rom_start.S",
+ ],
+ deps = [
+ ":test_rom_lib",
+ "//sw/device/silicon_creator/rom:bootstrap",
+ ],
)
cc_library(
@@ -63,8 +70,8 @@
"//hw/top_matcha/ip/flash_ctrl/data/autogen:flash_ctrl_regs",
"//hw/top_matcha/ip/sensor_ctrl/data:sensor_ctrl_regs",
"//hw/top_matcha/sw/autogen:top_matcha",
- "//sw/device/lib/testing:pinmux_testutils",
"//sw/device/lib/dif:pinmux",
+ "//sw/device/lib/testing:pinmux_testutils",
"@lowrisc_opentitan//hw/ip/csrng/data:csrng_regs",
"@lowrisc_opentitan//hw/ip/edn/data:edn_regs",
"@lowrisc_opentitan//hw/ip/entropy_src/data:entropy_src_regs",
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index 9e9f935..21913dc 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -670,7 +670,7 @@
deps = [
":test_lib_base",
"//sw/device/lib/testing/test_rom:linker_script",
- "//sw/device/lib/testing/test_rom:test_rom_lib",
+ "//sw/device/lib/testing/test_rom:test_rom_otp_lib",
],
)
@@ -946,6 +946,22 @@
],
)
+matcha_dv_test(
+ name = "clkmgr_off_video_clk_test",
+ srcs = ["clkmgr_off_video_clk_test.c"],
+ deps = [
+ ":clkmgr_off_clk_impl",
+ ],
+)
+
+matcha_dv_test(
+ name = "clkmgr_off_audio_clk_test",
+ srcs = ["clkmgr_off_audio_clk_test.c"],
+ deps = [
+ ":clkmgr_off_clk_impl",
+ ],
+)
+
cc_library(
name = "clkmgr_external_clk_src_for_sw_impl",
srcs = ["@lowrisc_opentitan//sw/device/tests:clkmgr_external_clk_src_for_sw_impl.c"],
diff --git a/sw/device/tests/clkmgr_off_audio_clk_test.c b/sw/device/tests/clkmgr_off_audio_clk_test.c
new file mode 100644
index 0000000..04dee74
--- /dev/null
+++ b/sw/device/tests/clkmgr_off_audio_clk_test.c
@@ -0,0 +1,60 @@
+// Copyright 2023 Google LLC.
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This test checks that when audio_clk is disabled, the corresponding output
+// signal from clkmgr will be constant 0
+//
+
+#include "hw/top_matcha/sw/autogen/top_matcha.h"
+#include "sw/device/lib/base/abs_mmio.h"
+#include "sw/device/lib/base/memory.h"
+#include "sw/device/lib/dif/dif_aon_timer.h"
+#include "sw/device/lib/dif/dif_base.h"
+#include "sw/device/lib/dif/dif_clkmgr.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/testing/aon_timer_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+
+OTTF_DEFINE_TEST_CONFIG();
+
+static dif_aon_timer_t aon_timer;
+
+/**
+ * Turn off the clock for 400us, then turn on
+ * Check the result in chip_sw_clkmgr_off_peri_vseq
+ */
+static void test_gateable_clocks_off_without_reset(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_gateable_clock_t clock) {
+ // Make sure the clock for the unit is on.
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_set_enabled(clkmgr, clock, kDifToggleEnabled));
+
+ LOG_INFO("Testing gateable clock ...");
+
+ // Disable the peripheral's clock.
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_set_enabled(clkmgr, clock, kDifToggleDisabled));
+ // Wait for the clock to really turn off.
+ busy_spin_micros(400);
+ // Enalbe the clock
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_set_enabled(clkmgr, clock, kDifToggleEnabled));
+}
+
+bool test_main(void) {
+ dif_clkmgr_t clkmgr;
+
+ CHECK_DIF_OK(dif_clkmgr_init(
+ mmio_region_from_addr(TOP_MATCHA_CLKMGR_AON_BASE_ADDR), &clkmgr));
+
+ // Initialize aon timer.
+ CHECK_DIF_OK(dif_aon_timer_init(
+ mmio_region_from_addr(TOP_MATCHA_AON_TIMER_AON_BASE_ADDR), &aon_timer));
+
+ test_gateable_clocks_off_without_reset(&clkmgr,
+ kTopMatchaGateableClocksAudioPeri);
+ return true;
+}
diff --git a/sw/device/tests/clkmgr_off_video_clk_test.c b/sw/device/tests/clkmgr_off_video_clk_test.c
new file mode 100644
index 0000000..679fb58
--- /dev/null
+++ b/sw/device/tests/clkmgr_off_video_clk_test.c
@@ -0,0 +1,60 @@
+// Copyright 2023 Google LLC.
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This test checks that when video_clk is disabled, the corresponding output
+// signal from clkmgr will be constant 0
+//
+
+#include "hw/top_matcha/sw/autogen/top_matcha.h"
+#include "sw/device/lib/base/abs_mmio.h"
+#include "sw/device/lib/base/memory.h"
+#include "sw/device/lib/dif/dif_aon_timer.h"
+#include "sw/device/lib/dif/dif_base.h"
+#include "sw/device/lib/dif/dif_clkmgr.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/testing/aon_timer_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+
+OTTF_DEFINE_TEST_CONFIG();
+
+static dif_aon_timer_t aon_timer;
+
+/**
+ * Turn off the clock for 400us, then turn on
+ * Check the result in chip_sw_clkmgr_off_peri_vseq
+ */
+static void test_gateable_clocks_off_without_reset(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_gateable_clock_t clock) {
+ // Make sure the clock for the unit is on.
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_set_enabled(clkmgr, clock, kDifToggleEnabled));
+
+ LOG_INFO("Testing gateable clock ...");
+
+ // Disable the peripheral's clock.
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_set_enabled(clkmgr, clock, kDifToggleDisabled));
+ // Wait for the clock to really turn off.
+ busy_spin_micros(400);
+ // Enalbe the clock
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_set_enabled(clkmgr, clock, kDifToggleEnabled));
+}
+
+bool test_main(void) {
+ dif_clkmgr_t clkmgr;
+
+ CHECK_DIF_OK(dif_clkmgr_init(
+ mmio_region_from_addr(TOP_MATCHA_CLKMGR_AON_BASE_ADDR), &clkmgr));
+
+ // Initialize aon timer.
+ CHECK_DIF_OK(dif_aon_timer_init(
+ mmio_region_from_addr(TOP_MATCHA_AON_TIMER_AON_BASE_ADDR), &aon_timer));
+
+ test_gateable_clocks_off_without_reset(&clkmgr,
+ kTopMatchaGateableClocksVideoPeri);
+ return true;
+}
