Add chip_sw_rv_dm_ndm_reset_req_when_cpu_halted in edacloud regression
suites

Change-Id: Ie8c6d51266b379fabe6fa27cf3ca2926a89e49c8

hw/top_matcha/dv/chip_sim_cfg.hjson

diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index cde514d..be7b57b 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -1716,7 +1716,7 @@
     {
       name: chip_sw_rv_dm_ndm_reset_req_when_cpu_halted
       uvm_test_seq: "chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq"
-      sw_images: ["//sw/device/tests/sim_dv:rv_dm_ndm_reset_req_when_cpu_halted:1"]
+      sw_images: ["//sw/device/tests/sim_dv:rv_dm_ndm_reset_req_when_cpu_halted:1:matcha"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+use_jtag_dmi=1"]
     }
@@ -1993,6 +1993,7 @@
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
         "chip_sw_rstmgr_sw_rst",
+        "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
         "chip_sw_rv_plic_smoketest",
         "chip_sw_rv_timer_irq",
         "chip_sw_smc_cam_irq_test",
@@ -2045,6 +2046,7 @@
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
         "chip_sw_rstmgr_sw_rst",
+        "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
         "chip_sw_rv_plic_smoketest",
         "chip_sw_rv_timer_irq",
         "chip_sw_smc_cam_irq_test",

sw/device/tests/sim_dv/BUILD

diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index fe999fc..0425930 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -110,3 +110,13 @@
         "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
     ],
 )
+
+matcha_dv_test(
+    name = "rv_dm_ndm_reset_req_when_cpu_halted",
+    srcs = ["@lowrisc_opentitan//sw/device/tests/sim_dv:rv_dm_ndm_reset_req_when_cpu_halted.c"],
+    deps = [
+        "//sw/device/lib/dif:rstmgr",
+        "//sw/device/tests:test_dv_lib_opentitan",
+        "@lowrisc_opentitan//sw/device/lib/testing:rstmgr_testutils",
+    ],
+)