Add all remaining tests in sw test suites into dv regression Bug: 287644985 Change-Id: I6aa4190f1c523b82e62c01a3354ae757e8001215
diff --git a/hw/top_matcha/data/chip_testplan.hjson b/hw/top_matcha/data/chip_testplan.hjson index 725de65..7db13e0 100644 --- a/hw/top_matcha/data/chip_testplan.hjson +++ b/hw/top_matcha/data/chip_testplan.hjson
@@ -110,6 +110,16 @@ stage: V1 tests: ["chip_sw_gpio"] } + { + name: chip_sw_crt_test + desc: '''Verify C runtime functionality. + + - The SW test setup data in .bss and .data region. + - The SW test verify both CRT clear and copy functions. + ''' + stage: V1 + tests: ["chip_sw_crt_test"] + } // SPI_DEVICE (pre-verified IP) integration tests: { @@ -284,6 +294,22 @@ // TBD if it can be combined with chip_sw_i2c_host_tx_rx tests: [] } + + // I2S integration tests: + { + name: chip_sw_i2s_tx_rx + desc: '''Verify the transmission of data over the chip's I2S interface. + + - Setup I2S tx rx IRQs in plic. + - Create a workload and send it over I2S. + - Check the interrupt is received. + - Check the transaction is finished and the fifo is empty. + ''' + stage: V2 + tests: ["chip_sw_smc_i2s_rx_test", + "chip_sw_smc_i2s_tx_test"] + } + // USB (pre-verified IP) integration tests: { name: chip_sw_usb_fs_tx_rx @@ -945,6 +971,17 @@ stage: V2 tests: ["chip_sw_smc_plic_vsi_irq"] } + { + name: chip_sw_atomics_test + desc: '''Verify atomic instruction on SMC core. + + - SW bringup SMC core + - SW config valid and invalid address. + - SW runs atomic instructions and verify the functionality + ''' + stage: V2 + tests: ["chip_sw_atomics_test"] + } // CLKMGR tests: { name: chip_sw_clkmgr_idle_trans @@ -2077,7 +2114,7 @@ - Program the smc_ctrl register to enable SMC core to boot. ''' stage: V2 - tests: [] + tests: ["chip_sw_smc_ctrl_test"] } // CAM_CTRL (pre-verified IP) integration tests: @@ -2085,13 +2122,14 @@ name: chip_sw_cam_ctrl desc: '''Verify that the cam_ctrl can control himax cam sensor. + - Program the cam_ctrl to toggle internal registers and verify the result - Program the cam_ctrl to driver the trigger output to sensor. - Program testbench to generate interrupt from cam_sensor, to verify if cam_ctrl generate interrupt to host's PLIC (SMC core). - TO-DO: test to be added. ''' stage: V2 - tests: [] + tests: ["chip_sw_cam_ctrl_test"] } // Mailbox (pre-verified IP) integration tests: { @@ -2147,7 +2185,7 @@ it was cleared. ''' stage: V2 - tests: [] + tests: ["chip_sw_dma_main_test"] } /////////////////////////////////////////////////////// // Security Peripherals // @@ -3798,6 +3836,24 @@ tests: ["chip_sw_i2c_boot"] } { + // TODO(b/287644985): revise mem_test.c into smc_sram_smoke test. + name: chip_sw_mem_test + desc: '''Verify the access to all of the memory instances + + - SW bring up secure core + - SW read/write random data in SMC ram memory region + - SW read/write random data in ML data memory region + - SW vefiry the written data matches the read data + ''' + stage: V2 + tests: ["chip_sw_mem_test"] + } + + ////////////////// + // CPU // + // RV_CORE_SMC // + ////////////////// + { name: chip_sw_boot_smc desc: '''Verify the full SMC core image download with bootstrap signal set. @@ -3822,6 +3878,18 @@ tests: ["chip_sw_smc_kelvin_hello_test"] } { + name: chip_sw_smc_isp_wrapper_test + desc: '''Verify ISP is enabled and generate data + + - SW enable ISP to a simple mode. + - SW verify ISP status registers are updated. + - SW randomly read/write the memory region which is accessible by ISP. + - SW validate the writtne data matches the read data. + ''' + stage: V2 + tests: ["chip_sw_smc_isp_wrapper_test"] + } + { name: chip_sw_smc_isp_simple_test_data desc: '''Verify ISP control path and data path @@ -3927,6 +3995,20 @@ "chip_sw_smc_page_boundary_test", "chip_sw_smc_supervisor_mode_test", "chip_sw_smc_virtual_memory_test"] + + } + // SMC RV_TIMER integration tests: + { + name: chip_sw_smc_rv_timer_test + desc: '''Verify the timeout interrupt assertion. + + - Configure the SMC RV_TIMER to generate interrupt after a set timeout. + - Issue a WFI to wait for the interrupt to trigger. + - Service the interrupt when it triggers; verify that it came from rv_timer. + - Verify that the interrupt triggered only after the timeout elapsed. + ''' + stage: V2 + tests: ["chip_sw_smc_rv_timer_test"] } { name: chip_sw_video_pipe_smoketest @@ -3943,17 +4025,16 @@ tests: ["chip_sw_video_pipe_smoketest"] } { - name: chip_sw_run_ml_workload - desc: '''Verify the launch ML workload at ml core at either Kelvin or Malamute. + name: chip_sw_smc_kelvin_run_checksum_test + desc: '''Verify checksum test on Kelvin core. - - SW download ML exe binary from external QSPI Flash to ML memory. - - SW download ML model from external QSPI Flash to ML memory. - - SW enable both camera and ISP to grab one frame of image. - - SW enable the ML core to run one inference and verify the result. - workload. + - SW bring up both SMC and ML cores. + - SW write a test image onto ML DMEM. + - SW start Kelvin core to read image data and compute checksum. + - SW validate the compuated checksum matches the golden checksum. ''' stage: V2 - tests: [] + tests: ["chip_sw_smc_kelvin_checksum_test"] } ]
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson index cde514d..0bb3864 100644 --- a/hw/top_matcha/dv/chip_sim_cfg.hjson +++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -506,6 +506,83 @@ run_opts:["+sw_test_timeout_ns=40_000_000"] } { + name: chip_sw_atomics_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests:atomics_test:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_cam_ctrl_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests:cam_ctrl_test:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_crt_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests:crt_test:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_dma_main_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests:dma_main_test:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_mem_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests:mem_test:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_ctrl_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests:smc_ctrl_test:1:ot_flash_binary:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_i2s_rx_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_i2s_rx_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_simple_sec"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_i2s_tx_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_i2s_tx_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_rom"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_rv_timer_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_rv_timer_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_simple_sec"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_kelvin_checksum_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_kelvin_checksum_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_simple_sec"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { + name: chip_sw_smc_isp_wrapper_test + uvm_test_seq: chip_sw_base_vseq + sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_test:6:matcha"] + en_run_modes: ["sw_test_mode_test_simple_sec"] + run_opts:["+sw_test_timeout_ns=40_000_000"] + } + { // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson. name: "chip_csr_bit_bash" // Don't test over 200 randomly picked CSRs at a time. @@ -1934,11 +2011,14 @@ tests: [ "chip_sw_alert_test", "chip_sw_aon_timer_smoketest", + "chip_sw_cam_ctrl_test", "chip_sw_clkmgr_smoketest", + "chip_sw_crt_test", "chip_sw_csrng_smoketest", + "chip_sw_dma_main_test", "chip_sw_example_flash", - "chip_sw_flash_ctrl_access", "chip_sw_i2c_host_tx_rx", + "chip_sw_mem_test", "chip_sw_rom_ctrl_integrity_check", "chip_sw_rstmgr_smoketest", "chip_sw_rstmgr_sw_req", @@ -1946,15 +2026,19 @@ "chip_sw_rv_plic_smoketest", "chip_sw_rv_timer_irq", "chip_sw_smc_cam_irq_test", + "chip_sw_smc_ctrl_test", "chip_sw_smc_env_test", + "chip_sw_smc_i2s_rx_test", "chip_sw_smc_interrupt_boundary_test", "chip_sw_smc_isp_wrapper_irq_test", + "chip_sw_smc_isp_wrapper_test", "chip_sw_smc_isp_wrapper_tpg_64_64_test", "chip_sw_smc_lsu_interrupt_boundary_test", "chip_sw_smc_lsu_page_boundary_test", "chip_sw_smc_ml_sram_smoketest", "chip_sw_smc_ml_top_irq_test", "chip_sw_smc_page_boundary_test", + "chip_sw_smc_rv_timer_test", "chip_sw_smc_supervisor_mode_test", "chip_sw_smc_virtual_memory_test", "chip_sw_spi_device_tx_rx", @@ -1973,8 +2057,12 @@ "chip_sw_alert_handler_ping_timeout", "chip_sw_alert_test", "chip_sw_aon_timer_smoketest", + "chip_sw_atomics_test", + "chip_sw_cam_ctrl_test", "chip_sw_clkmgr_smoketest", + "chip_sw_crt_test", "chip_sw_csrng_smoketest", + "chip_sw_dma_main_test", "chip_sw_entropy_src_smoketest", "chip_sw_example_flash", "chip_sw_flash_ctrl_access", @@ -1983,6 +2071,7 @@ "chip_sw_hmac_enc", "chip_sw_hmac_smoketest", "chip_sw_i2c_host_tx_rx", + "chip_sw_mem_test", "chip_sw_keymgr_key_derivation", "chip_sw_kmac_idle", "chip_sw_kmac_smoketest", @@ -1996,16 +2085,22 @@ "chip_sw_rv_plic_smoketest", "chip_sw_rv_timer_irq", "chip_sw_smc_cam_irq_test", + "chip_sw_smc_ctrl_test", "chip_sw_smc_env_test", + "chip_sw_smc_i2s_rx_test", + "chip_sw_smc_i2s_tx_test", "chip_sw_smc_interrupt_boundary_test", "chip_sw_smc_isp_wrapper_irq_test", + "chip_sw_smc_isp_wrapper_test", "chip_sw_smc_isp_wrapper_tpg_64_64_test", + "chip_sw_smc_kelvin_checksum_test", "chip_sw_smc_kelvin_hello_test", "chip_sw_smc_lsu_interrupt_boundary_test", "chip_sw_smc_lsu_page_boundary_test", "chip_sw_smc_ml_sram_smoketest", "chip_sw_smc_ml_top_irq_test", "chip_sw_smc_page_boundary_test", + "chip_sw_smc_rv_timer_test", "chip_sw_smc_supervisor_mode_test", "chip_sw_smc_tlul_mailbox_test", "chip_sw_smc_virtual_memory_test", @@ -2025,8 +2120,12 @@ "chip_sw_alert_handler_ping_timeout", "chip_sw_alert_test", "chip_sw_aon_timer_smoketest", + "chip_sw_atomics_test", + "chip_sw_cam_ctrl_test", "chip_sw_clkmgr_smoketest", + "chip_sw_crt_test", "chip_sw_csrng_smoketest", + "chip_sw_dma_main_test", "chip_sw_entropy_src_smoketest", "chip_sw_example_flash", "chip_sw_flash_ctrl_access", @@ -2035,6 +2134,7 @@ "chip_sw_hmac_enc", "chip_sw_hmac_smoketest", "chip_sw_i2c_host_tx_rx", + "chip_sw_mem_test", "chip_sw_keymgr_key_derivation", "chip_sw_kmac_idle", "chip_sw_kmac_smoketest", @@ -2048,16 +2148,22 @@ "chip_sw_rv_plic_smoketest", "chip_sw_rv_timer_irq", "chip_sw_smc_cam_irq_test", + "chip_sw_smc_ctrl_test", "chip_sw_smc_env_test", + "chip_sw_smc_i2s_rx_test", + "chip_sw_smc_i2s_tx_test", "chip_sw_smc_interrupt_boundary_test", "chip_sw_smc_isp_wrapper_irq_test", + "chip_sw_smc_isp_wrapper_test", "chip_sw_smc_isp_wrapper_tpg_64_64_test", + "chip_sw_smc_kelvin_checksum_test", "chip_sw_smc_kelvin_hello_test", "chip_sw_smc_lsu_interrupt_boundary_test", "chip_sw_smc_lsu_page_boundary_test", "chip_sw_smc_ml_sram_smoketest", "chip_sw_smc_ml_top_irq_test", "chip_sw_smc_page_boundary_test", + "chip_sw_smc_rv_timer_test", "chip_sw_smc_supervisor_mode_test", "chip_sw_smc_tlul_mailbox_test", "chip_sw_smc_virtual_memory_test",
diff --git a/sw/device/tests/mem_test.c b/sw/device/tests/mem_test.c index 43073fc..59a8f3c 100644 --- a/sw/device/tests/mem_test.c +++ b/sw/device/tests/mem_test.c
@@ -31,8 +31,6 @@ mmio_region_t base_addr = mmio_region_from_addr(TOP_MATCHA_RAM_SMC_BASE_ADDR); - mem_val = mmio_region_read32(base_addr, 0x0); - mmio_region_write32(base_addr, 0x0, 0x55aa55aa); mem_val = mmio_region_read32(base_addr, 0x0); CHECK(mem_val == 0x55aa55aa, @@ -53,8 +51,6 @@ mmio_region_t ml_dmem_base_addr = mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR); - mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0); - mmio_region_write32(ml_dmem_base_addr, 0x0, 0x55aa55aa); mmio_region_write32(ml_dmem_base_addr, 0x4, 0x12345678); mmio_region_write32(ml_dmem_base_addr, 0x8, 0x55aa55aa);