| /* |
| * Copyright 2023 Google LLC |
| * Copyright lowRISC contributors |
| * |
| * Licensed under the Apache License, Version 2.0 (the "License"); |
| * you may not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * http://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, |
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| */ |
| |
| |
| #include "sw/device/lib/dif/dif_isp_wrapper.h" |
| |
| #include <stddef.h> |
| |
| #include "sw/device/lib/base/bitfield.h" |
| #include "sw/device/lib/base/macros.h" |
| #include "sw/device/lib/dif/dif_base.h" |
| |
| #include "external/isp_yocto/include/yocto_isp_register_address.h" |
| #include "isp_wrapper_regs.h" // Generated. |
| |
| // ISP configuration: |
| // TPG 128 * 64, raw, bypass modes |
| dif_result_t dif_isp_wrapper_set_en(const dif_isp_wrapper_t *isp_wrapper) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| mmio_region_write32(isp_wrapper->base_addr, ISP_IMSC, 0xffffffff); |
| mmio_region_write32(isp_wrapper->base_addr, MI_IMSC, 0xffffffff); |
| mmio_region_write32(isp_wrapper->base_addr, VI_CCL, 0x00000002); |
| mmio_region_write32(isp_wrapper->base_addr, VI_ICCL, 0x00000059); |
| mmio_region_write32(isp_wrapper->base_addr, VI_IRCL, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_H_OFFS, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_V_OFFS, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_H_SIZE, 0x00000080); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_V_SIZE, 0x00000040); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_TOTAL_IN, 0x00bfc25f); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_ACT_IN, 0x00200040); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_FP_IN, 0x002bc11b); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_BP_IN, 0x0039c0a7); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_W_IN, 0x003a405d); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_GAP_IN, 0x000a8015); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_GAP_STD_IN, 0x00000010); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_RANDOM_SEED, 0xb6ccff1c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_FRAME_NUM, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_H_OFFS, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_V_OFFS, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_H_SIZE, 0x00000080); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_V_SIZE, 0x00000040); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_CTRL, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_A_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_B_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_C_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_D_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_CONF, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_H_OFFSET, 0x00000012); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_V_OFFSET, 0x0000001f); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_H_SIZE, 0x00000012); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_V_SIZE, 0x00000004); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_DGAIN_RB, 0x006600ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_DGAIN_G, 0x00dd00e3); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_DEMOSAIC, 0x00000462); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_MODE, 0x00000a12); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_BL0, 0x0000036d); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_BL1, 0x0000028e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_SH0, 0x000003c8); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_SH1, 0x000003e2); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_LUM_WEIGHT, 0x000259b5); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_SH1, 0x0000003e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_SH0, 0x0000003d); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_MID, 0x0000002c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_BL0, 0x00000021); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_BL1, 0x0000000c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_CTRL, 0x0000000a); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_COUNT_START, 0x00200040); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_A, 0x01f4018c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_B, 0x012e01ca); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_C, 0x003401a4); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_X_NORM, 0x00030008); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_Y_NORM, 0x00020015); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_MODE, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_0, 0x000001ae); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_1, 0x000002b0); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_2, 0x000002db); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_3, 0x000002f9); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_4, 0x000002fd); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_5, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_6, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_7, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_8, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_9, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_10, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_11, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_12, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_13, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_14, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_15, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_16, 0x000002fe); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_PROP, 0x80000007); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_H_OFFS, 0x0000005b); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_V_OFFS, 0x00000022); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_H_SIZE, 0x00000005); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_V_SIZE, 0x00000009); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_FRAMES, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_REF, 0x00006b55); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_THRESH, 0xeaef51fa); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_0, 0x00000004); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_1, 0x0000011b); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_2, 0x000001af); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_3, 0x000001e0); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_4, 0x00000020); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_5, 0x00000140); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_6, 0x00000053); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_7, 0x0000002e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_8, 0x000001b7); |
| mmio_region_write32(isp_wrapper->base_addr, FORMAT_CONV_CTRL, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_0, 0x00000588); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_1, 0x000005d9); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_2, 0x000004ea); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_3, 0x000004f9); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_4, 0x0000031e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_5, 0x000006db); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_6, 0x000004f6); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_7, 0x00000307); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_8, 0x00000085); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_OFFSET_R, 0x00000310); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_OFFSET_G, 0x00000592); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_OFFSET_B, 0x00000d58); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_IMSC, 0x000400fc); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ERR_CLR, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_BASE_AD_INIT, 0x5a000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_SIZE_INIT, 0x0000a800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_IRQ_OFFS_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_BASE_AD_INIT, 0x5a00a800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_SIZE_INIT, 0x00005400); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_BASE_AD_INIT, 0x5a00a800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_SIZE_INIT, 0x00005400); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_IMSC, 0x000003ff); |
| mmio_region_write32(isp_wrapper->base_addr, MI_STATUS_CLR, 0x00000053); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_BASE_AD_INIT2, 0x5a01f800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_BASE_AD_INIT2, 0x5a02a000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_BASE_AD_INIT2, 0x5a02f800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_LLENGTH, 0x00000080); |
| mmio_region_write32(isp_wrapper->base_addr, MI_OUTPUT_ALIGN_FORMAT, 0x00000401); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_OUTPUT_FIFO_SIZE, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_PIC_WIDTH, 0x00000080); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_PIC_HEIGHT, 0x00000040); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_PIC_SIZE, 0x00002000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_CTRL, 0x0000011c); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_HY, 0x0000c177); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_HCB, 0x0000ec82); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_HCR, 0x00000057); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_VY, 0x000075d8); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_VC, 0x000075d8); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_HY, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_HC, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_VY, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_VC, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_FORMAT_CONV_CTRL, 0x000000fa); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_BASE_AD_INIT, 0x2354d5f8); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_SIZE_INIT, 0x00008000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_LLENGTH, 0x00000080); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_BASE_AD_INIT, 0x9fff2d98); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_SIZE_INIT, 0x01673858); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_BASE_AD_INIT, 0xd3bbca68); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_SIZE_INIT, 0x0f8bf230); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_PIC_WIDTH, 0x00000080); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_PIC_HEIGHT, 0x00000040); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_PIC_SIZE, 0x00002000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_BASE_AD_INIT2, 0x1939f6d8); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_BASE_AD_INIT2, 0xf9f91948); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_BASE_AD_INIT2, 0x8335a0b0); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_PROP, 0x00000089); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_CTRL, 0x0000011c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CTRL, 0x80007250); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_CTRL, 0x00000d95); |
| mmio_region_write32(isp_wrapper->base_addr, MI_CTRL, 0x68360808); |
| mmio_region_write32(isp_wrapper->base_addr, MI_INIT, 0x000000b0); |
| |
| return kDifOk; |
| } |
| |
| // ISP confituration: live, raw and bypass modes |
| // Input arguments are frame weight, frame height and Y,Cb,Cr written addresses. |
| dif_result_t _dif_isp_wrapper_set_raw_byp_en( |
| const dif_isp_wrapper_t *isp_wrapper, const uint32_t frame_h_size, |
| const uint32_t frame_v_size, const uint32_t frame_h_offs, |
| const uint32_t frame_v_offs, |
| // TODO(ykwang): put these variables into a config variable. |
| const uint32_t y_base_ad_init_addr, const uint32_t cb_base_ad_init_addr, |
| const uint32_t cr_base_ad_init_addr, const uint32_t y_base_ad_init2_addr, |
| const uint32_t cb_base_ad_init2_addr, |
| const uint32_t cr_base_ad_init2_addr) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| mmio_region_write32(isp_wrapper->base_addr, ISP_IMSC, 0xffffffff); |
| mmio_region_write32(isp_wrapper->base_addr, MI_IMSC, 0xffffffff); |
| mmio_region_write32(isp_wrapper->base_addr, VI_CCL, 0x00000002); |
| mmio_region_write32(isp_wrapper->base_addr, VI_ICCL, 0x00000059); |
| mmio_region_write32(isp_wrapper->base_addr, VI_IRCL, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_H_OFFS, frame_h_offs); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_V_OFFS, frame_v_offs); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_H_SIZE, frame_h_size); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_V_SIZE, frame_v_size); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_TOTAL_IN, 0x011d8518); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_ACT_IN, 0x00a001e0); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_FP_IN, 0x001c8126); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_BP_IN, 0x00454129); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_W_IN, 0x001bc0e9); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_GAP_IN, 0x003540a0); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_GAP_STD_IN, 0x00000050); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_RANDOM_SEED, 0xe30ce95f); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_FRAME_NUM, 0x00000003); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_H_OFFS, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_V_OFFS, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_H_SIZE, frame_h_size); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_OUT_V_SIZE, frame_v_size); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_CTRL, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_A_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_B_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_C_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_BLS_D_FIXED, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_CONF, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_H_OFFSET, 0x000000d3); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_V_OFFSET, 0x00000017); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_H_SIZE, 0x00000043); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_EXP_V_SIZE, 0x00000048); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_DGAIN_RB, 0x01a200d7); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_DGAIN_G, 0x00f9011e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_DEMOSAIC, 0x000004f6); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_MODE, 0x00000810); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_BL0, 0x00000230); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_BL1, 0x00000018); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_SH0, 0x00000287); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_THRES_SH1, 0x000003f2); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_LUM_WEIGHT, 0x00061fdc); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_SH1, 0x00000031); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_SH0, 0x00000031); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_MID, 0x0000002c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_BL0, 0x0000001a); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_FILT_FAC_BL1, 0x00000016); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_CTRL, 0x00000004); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_COUNT_START, 0x00f00140); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_A, 0x01160187); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_B, 0x005f004c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_C, 0x0138017a); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_X_NORM, 0x00020001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CAC_Y_NORM, 0x00060015); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_MODE, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_0, 0x00000170); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_1, 0x00000178); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_2, 0x00000181); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_3, 0x0000018e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_4, 0x00000194); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_5, 0x000001b4); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_6, 0x000001b7); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_7, 0x000001b9); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_8, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_9, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_10, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_11, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_12, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_13, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_14, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_15, 0x000001ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_GAMMA_OUT_Y_16, 0x00000303); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_PROP, 0x00000002); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_H_OFFS, 0x00000052); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_V_OFFS, 0x0000016f); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_H_SIZE, 0x000001be); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_V_SIZE, 0x00000061); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_FRAMES, 0x00000001); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_REF, 0x0000b0c6); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_AWB_THRESH, 0x0b145491); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_0, 0x0000008d); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_1, 0x000000b1); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_2, 0x000000a2); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_3, 0x00000078); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_4, 0x00000169); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_5, 0x000000ba); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_6, 0x0000015c); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_7, 0x000000f8); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CC_COEFF_8, 0x0000017c); |
| mmio_region_write32(isp_wrapper->base_addr, FORMAT_CONV_CTRL, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_0, 0x000005ff); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_1, 0x00000707); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_2, 0x00000464); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_3, 0x00000008); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_4, 0x00000058); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_5, 0x000007de); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_6, 0x00000241); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_7, 0x000006ff); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_COEFF_8, 0x0000007d); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_OFFSET_R, 0x000005ec); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_OFFSET_G, 0x00000d7e); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CT_OFFSET_B, 0x00000dd7); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_IMSC, 0x000400fc); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ERR_CLR, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_BASE_AD_INIT, |
| y_base_ad_init_addr); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_SIZE_INIT, |
| frame_h_size * frame_v_size); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_IRQ_OFFS_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_BASE_AD_INIT, |
| cb_base_ad_init_addr); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_SIZE_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_BASE_AD_INIT, |
| cr_base_ad_init_addr); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_SIZE_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_OFFS_CNT_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_IMSC, 0x000003ff); |
| mmio_region_write32(isp_wrapper->base_addr, MI_STATUS_CLR, 0x00000077); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_BASE_AD_INIT2, |
| y_base_ad_init2_addr); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CB_BASE_AD_INIT2, |
| cb_base_ad_init2_addr); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_CR_BASE_AD_INIT2, |
| cr_base_ad_init2_addr); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_LLENGTH, frame_h_size); |
| mmio_region_write32(isp_wrapper->base_addr, MI_OUTPUT_ALIGN_FORMAT, |
| 0x00000401); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_OUTPUT_FIFO_SIZE, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_PIC_WIDTH, frame_h_size); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_PIC_HEIGHT, frame_v_size); |
| mmio_region_write32(isp_wrapper->base_addr, MI_MP_Y_PIC_SIZE, |
| frame_h_size * frame_v_size); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_CTRL, 0x000001c0); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_HY, 0x0000546d); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_HCB, 0x0000db23); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_HCR, 0x000071b7); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_VY, 0x00007803); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_SCALE_VC, 0x00005628); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_HY, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_HC, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_VY, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_PHASE_VC, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_FORMAT_CONV_CTRL, |
| 0x000000fa); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_BASE_AD_INIT, 0x50000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_SIZE_INIT, 0x0006c1c0); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_OFFS_CNT_INIT, |
| 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_LLENGTH, 0x00000128); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_BASE_AD_INIT, |
| 0x5006c800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_SIZE_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_OFFS_CNT_INIT, |
| 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_BASE_AD_INIT, |
| 0x5006c800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_SIZE_INIT, 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_OFFS_CNT_INIT, |
| 0x00000000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_PIC_WIDTH, 0x00000124); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_PIC_HEIGHT, 0x00000176); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_PIC_SIZE, 0x0001b070); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_Y_BASE_AD_INIT2, |
| 0x500d9000); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CB_BASE_AD_INIT2, |
| 0x50145800); |
| mmio_region_write32(isp_wrapper->base_addr, MI_SP_CR_BASE_AD_INIT2, |
| 0x50145800); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ACQ_PROP, 0x40011); |
| mmio_region_write32(isp_wrapper->base_addr, SRSZ_CTRL, 0x000001c0); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_CTRL, 0x00207211); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_TPG_CTRL, 0x00000d76); |
| mmio_region_write32(isp_wrapper->base_addr, MI_CTRL, 0x68352808); |
| mmio_region_write32(isp_wrapper->base_addr, MI_INIT, 0x000000b0); |
| return kDifOk; |
| } |
| |
| // ISP configuration: |
| // raw:320x240, byp:320x240 |
| dif_result_t dif_isp_wrapper_set_raw_320x240_byp_320x240_en( |
| const dif_isp_wrapper_t *isp_wrapper) { |
| return _dif_isp_wrapper_set_raw_byp_en(isp_wrapper, 0x140, 0xf0, 0x2, 0x2, |
| 0x5a000000, 0x5a01a000, 0x5a01a000, |
| 0x5a020000, 0x5a03a000, 0x5a03a000); |
| } |
| |
| // ISP configuration: |
| // raw:320x240, byp:320x240, hps image address: 0x00300000 |
| dif_result_t dif_isp_wrapper_set_ml_mem_byp_320x240_en( |
| const dif_isp_wrapper_t *isp_wrapper) { |
| return _dif_isp_wrapper_set_raw_byp_en(isp_wrapper, 0x140, 0xf0, 0x2, 0x2, |
| 0x5a300000, 0x5a320000, 0x5a320000, |
| 0x5a340000, 0x5a360000, 0x5a360000); |
| } |
| |
| // ISP configuration: |
| // raw:324x324, byp:324x324 |
| dif_result_t dif_isp_wrapper_set_raw_324x324_byp_324x324_en( |
| const dif_isp_wrapper_t *isp_wrapper) { |
| return _dif_isp_wrapper_set_raw_byp_en(isp_wrapper, 0x144, 0x144, 0x0, 0x0, |
| 0x5a000000, 0x5a01a000, 0x5a01a000, |
| 0x5a034000, 0x5a04e000, 0x5a04e000); |
| } |
| |
| dif_result_t dif_isp_wrapper_clear_en(const dif_isp_wrapper_t *isp_wrapper) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| //TODO(Ray): not used currently, will update to real interrupt clear registers |
| mmio_region_write32(isp_wrapper->base_addr, 0xb00, 0x00040000); |
| return kDifOk; |
| } |
| |
| // TODO(ykwang): replace mask function with done which clears status registers. |
| dif_result_t dif_isp_wrapper_isp_irq_mask(const dif_isp_wrapper_t *isp_wrapper) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| //ISP_IMSC Interrupt mask, 0 active |
| mmio_region_write32(isp_wrapper->base_addr, 0xb00, 0x00000000); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_mi_irq_mask(const dif_isp_wrapper_t *isp_wrapper) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| //MI_IMSC Interrupt mask, 0 active |
| mmio_region_write32(isp_wrapper->base_addr, 0xef8, 0x00000000); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_isp_irq_done( |
| const dif_isp_wrapper_t *isp_wrapper) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| uint32_t irq_status = mmio_region_read32(isp_wrapper->base_addr, ISP_MIS); |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ICR, irq_status); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_mi_irq_done(const dif_isp_wrapper_t *isp_wrapper) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| uint32_t irq_status = |
| mmio_region_read32(isp_wrapper->base_addr, MI_MIS); |
| mmio_region_write32(isp_wrapper->base_addr, MI_ICR, irq_status); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_read_en(const dif_isp_wrapper_t *isp_wrapper, |
| uint32_t *result) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| //MI_MIS Masked Interrupt Status |
| *result = mmio_region_read32(isp_wrapper->base_addr, 0xf00); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_read_mi_mis(const dif_isp_wrapper_t *isp_wrapper, uint32_t *result) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| *result = mmio_region_read32(isp_wrapper->base_addr, MI_MIS); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_read_isp_mis(const dif_isp_wrapper_t *isp_wrapper, uint32_t *result) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| *result = mmio_region_read32(isp_wrapper->base_addr, ISP_MIS); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_write_isp_icr(const dif_isp_wrapper_t *isp_wrapper, uint32_t val) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| mmio_region_write32(isp_wrapper->base_addr, ISP_ICR, val); |
| return kDifOk; |
| } |
| |
| dif_result_t dif_isp_wrapper_write_mi_icr(const dif_isp_wrapper_t *isp_wrapper, uint32_t val) { |
| if (isp_wrapper == NULL) { |
| return kDifBadArg; |
| } |
| mmio_region_write32(isp_wrapper->base_addr, MI_ICR, val); |
| return kDifOk; |
| } |
