Fixes for HPS on ASIC - ifdef in a few fixes for the HPS demo on ASIC: different pinmuxing, primarily. - for the ASIC, un-rotate the camera to match the physical layout. - register settings for the pico ISP in ASIC Change-Id: Ie5c7f77e56d8807b224a8de3fe61c387be2a6c8c
diff --git a/sw/device/examples/demo_hps_live/BUILD b/sw/device/examples/demo_hps_live/BUILD index 4c0b3dc..e8b2bdf 100644 --- a/sw/device/examples/demo_hps_live/BUILD +++ b/sw/device/examples/demo_hps_live/BUILD
@@ -5,6 +5,7 @@ load( "//rules:matcha.bzl", + "ASIC_CORE_TARGETS", "NEXUS_CORE_TARGETS", "sec_flash_binary", "smc_flash_binary", @@ -15,7 +16,6 @@ name = "hps_demo", srcs = [ "hps_demo_sc.c", - "hps_demo_smc_fpga_nexus_bin_c.h", ], copts = [ "-nostdlib", @@ -23,8 +23,10 @@ ], per_device_deps = { "fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")], + "asic": [ASIC_CORE_TARGETS.get("secure_core")], }, deps = [ + ":hps_demo_smc_h", "//hw/top_matcha/ip/ml_top/data:ml_top_regs", "//sw/device/lib/dif:rv_plic_sec", "//sw/device/lib/dif:smc_ctrl", @@ -46,6 +48,7 @@ ], per_device_deps = { "fpga_nexus": [NEXUS_CORE_TARGETS.get("smc")], + "asic": [ASIC_CORE_TARGETS.get("smc")], }, deps = [ "//hw/top_matcha/ip/ml_top/data:ml_top_regs", @@ -58,3 +61,15 @@ "@lowrisc_opentitan//sw/device/lib/dif:rv_timer", ], ) + +cc_library( + name = "hps_demo_smc_h", + hdrs = select({ + "//rules:sparrow_platform": [ + "hps_demo_smc_asic_bin_c.h", + ], + "//conditions:default": [ + "hps_demo_smc_fpga_nexus_bin_c.h", + ], + }), +)
diff --git a/sw/device/examples/demo_hps_live/hps_demo_sc.c b/sw/device/examples/demo_hps_live/hps_demo_sc.c index 0300213..e5a77f4 100644 --- a/sw/device/examples/demo_hps_live/hps_demo_sc.c +++ b/sw/device/examples/demo_hps_live/hps_demo_sc.c
@@ -15,7 +15,6 @@ */ #include "hw/top_matcha/sw/autogen/top_matcha.h" -#include "sw/device/examples/demo_hps_live/hps_demo_smc_fpga_nexus_bin_c.h" // Generated. #include "sw/device/lib/arch/device.h" #include "sw/device/lib/dif/dif_gpio.h" #include "sw/device/lib/dif/dif_pinmux.h" @@ -30,6 +29,12 @@ #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_test_config.h" +#if defined(MATCHA_SPARROW) +#include "sw/device/examples/demo_hps_live/hps_demo_smc_asic_bin_c.h" // Generated. +#else +#include "sw/device/examples/demo_hps_live/hps_demo_smc_fpga_nexus_bin_c.h" // Generated. +#endif + /* * Sample program to run some code on all cores in the system. * SC - Orchestrate the other cores, print status to UART. @@ -103,10 +108,17 @@ CHECK_DIF_OK(dif_pinmux_init( mmio_region_from_addr(TOP_MATCHA_PINMUX_AON_BASE_ADDR), &pinmux)); +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIob11, + kTopMatchaPinmuxOutselGpioGpio16)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIob12, + kTopMatchaPinmuxOutselGpioGpio17)); +#else CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod0, kTopMatchaPinmuxOutselGpioGpio16)); CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod1, kTopMatchaPinmuxOutselGpioGpio17)); +#endif CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIoc0, kTopMatchaPinmuxOutselGpioGpio22)); CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, @@ -123,6 +135,19 @@ CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInCamI2cScl, kTopMatchaPinmuxInselIoa4)); // Mux ISP wrapper +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData0, kTopMatchaPinmuxInselIob0)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData1, kTopMatchaPinmuxInselIob1)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData2, kTopMatchaPinmuxInselIob2)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData3, kTopMatchaPinmuxInselIob3)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData4, kTopMatchaPinmuxInselIob4)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData5, kTopMatchaPinmuxInselIob5)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData6, kTopMatchaPinmuxInselIob6)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData7, kTopMatchaPinmuxInselIob7)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSVsync, kTopMatchaPinmuxInselIob9)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSHsync, kTopMatchaPinmuxInselIob8)); + CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInVsiCtlWrapperIspSclk, kTopMatchaPinmuxInselIob10)); +#else CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSData0, kTopMatchaPinmuxInselIob0)); CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSData1, kTopMatchaPinmuxInselIob1)); CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSData2, kTopMatchaPinmuxInselIob2)); @@ -134,6 +159,7 @@ CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSVsync, kTopMatchaPinmuxInselIoa2)); CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSHsync, kTopMatchaPinmuxInselIoa3)); CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSPclk, kTopMatchaPinmuxInselIob8)); +#endif CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIoa2, kTopMatchaPinmuxOutselConstantHighZ)); CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIoa3, kTopMatchaPinmuxOutselConstantHighZ)); @@ -152,9 +178,15 @@ CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIoa7, kTopMatchaPinmuxOutselCamCtrlCamTrig)); // Mux SPI_HOST2 (clk, mosi, cs) +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIor12, kTopMatchaPinmuxOutselSpiHost2Sck)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIor10, kTopMatchaPinmuxOutselSpiHost2Sd0)); + CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIor13, kTopMatchaPinmuxOutselSpiHost2Csb)); +#else CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIor12, kTopMatchaPinmuxOutselSpiHost2Sck)); CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIob10, kTopMatchaPinmuxOutselSpiHost2Sd0)); CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIor13, kTopMatchaPinmuxOutselSpiHost2Csb)); +#endif CHECK_DIF_OK( dif_gpio_init(mmio_region_from_addr(TOP_MATCHA_GPIO_BASE_ADDR), &gpio));
diff --git a/sw/device/examples/demo_hps_live/hps_demo_smc.c b/sw/device/examples/demo_hps_live/hps_demo_smc.c index 5cd11cf..7741835 100644 --- a/sw/device/examples/demo_hps_live/hps_demo_smc.c +++ b/sw/device/examples/demo_hps_live/hps_demo_smc.c
@@ -20,6 +20,7 @@ #include "hw/top_matcha/sw/autogen/top_matcha.h" #include "sw/device/examples/testdata/kelvin_model_ml_bin.h" // Generated. #include "sw/device/lib/arch/device.h" +#include "sw/device/lib/base/math.h" #include "sw/device/lib/camera_hm01b0.h" #include "sw/device/lib/dif/dif_isp_wrapper.h" #include "sw/device/lib/dif/dif_ml_top.h" @@ -42,6 +43,14 @@ #define TOP_MATCHA_RAM_ML_DMEM_CMD_OFFSET_ADDR 0x003FF000 #define IMAGE_FRAME_SIZE 320 * 240 +#if defined(MATCHA_SPARROW) +#define COUNTER_FREQ 1000000 +#else +#define COUNTER_FREQ 1000 +#endif + +#define COUNTER_SCALE (COUNTER_FREQ / 1000) + OTTF_DEFINE_TEST_CONFIG(); static dif_isp_wrapper_t isp_wrapper; @@ -127,11 +136,19 @@ // NOTE: This initialization is superfluous, since the `default` case below // is effectively noreturn, but the compiler is unable to prove this. switch (interrupt_id) { +#if defined(MATCHA_SPARROW) + case kTopMatchaPlicIrqIdVideoAudioWrapperIsp: +#else case kTopMatchaPlicIrqIdIspWrapperIsp: +#endif isp_frame_done = true; CHECK_DIF_OK(dif_isp_wrapper_isp_irq_done(&isp_wrapper)); break; +#if defined(MATCHA_SPARROW) + case kTopMatchaPlicIrqIdVideoAudioWrapperMi: +#else case kTopMatchaPlicIrqIdIspWrapperMi: +#endif CHECK_DIF_OK(dif_isp_wrapper_mi_irq_done(&isp_wrapper)); break; default: @@ -165,18 +182,31 @@ // Check if the interrupted peripheral is ISP WRAPPER. top_matcha_plic_peripheral_smc_t peripheral_id = top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id]; +#if defined(MATCHA_SPARROW) + CHECK(peripheral_id == kTopMatchaPlicPeripheralVideoAudioWrapper || + peripheral_id == kTopMatchaPlicPeripheralCamI2c || + peripheral_id == kTopMatchaPlicPeripheralSpiHost2 || + peripheral_id == kTopMatchaPlicPeripheralTlulMailboxSmc || + peripheral_id == kTopMatchaPlicPeripheralMlTop, + "Unexpected peripheral in ISR: %d", peripheral_id); +#else CHECK(peripheral_id == kTopMatchaPlicPeripheralIspWrapper || peripheral_id == kTopMatchaPlicPeripheralCamI2c || peripheral_id == kTopMatchaPlicPeripheralSpiHost2 || peripheral_id == kTopMatchaPlicPeripheralTlulMailboxSmc || peripheral_id == kTopMatchaPlicPeripheralMlTop, "Unexpected peripheral in ISR: %d", peripheral_id); +#endif switch (peripheral_id) { case kTopMatchaPlicPeripheralCamI2c: { CHECK_DIF_OK(camera_hm01b0_irq_handler(interrupt_id)); break; } +#if defined(MATCHA_SPARROW) + case kTopMatchaPlicPeripheralVideoAudioWrapper: +#else case kTopMatchaPlicPeripheralIspWrapper: +#endif handle_isp_wrapper_isrs(interrupt_id); break; case kTopMatchaPlicPeripheralTlulMailboxSmc: { @@ -207,10 +237,17 @@ static void plic_smc_configure_irqs(dif_rv_plic_t *plic) { CHECK_DIF_OK(camera_hm01b0_irq_init(plic, kTopMatchaPlicTargetIbex0Smc)); // Set IRQ priorities to MAX +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(dif_rv_plic_irq_set_priority( + plic, kTopMatchaPlicIrqIdVideoAudioWrapperIsp, kDifRvPlicMaxPriority)); + CHECK_DIF_OK(dif_rv_plic_irq_set_priority( + plic, kTopMatchaPlicIrqIdVideoAudioWrapperMi, kDifRvPlicMaxPriority)); +#else CHECK_DIF_OK(dif_rv_plic_irq_set_priority( plic, kTopMatchaPlicIrqIdIspWrapperIsp, kDifRvPlicMaxPriority)); CHECK_DIF_OK(dif_rv_plic_irq_set_priority( plic, kTopMatchaPlicIrqIdIspWrapperMi, kDifRvPlicMaxPriority)); +#endif CHECK_DIF_OK(dif_rv_plic_irq_set_priority( plic, kTopMatchaPlicIrqIdMlTopFinish, kDifRvPlicMaxPriority)); CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, kTopMatchaPlicIrqIdMlTopFault, @@ -222,12 +259,21 @@ // Enable IRQs in PLIC // Enable ISP IRQs +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(dif_rv_plic_irq_set_enabled( + plic, kTopMatchaPlicIrqIdVideoAudioWrapperIsp, kTopMatchaPlicTargetIbex0Smc, + kDifToggleEnabled)); + CHECK_DIF_OK(dif_rv_plic_irq_set_enabled( + plic, kTopMatchaPlicIrqIdVideoAudioWrapperMi, kTopMatchaPlicTargetIbex0Smc, + kDifToggleEnabled)); +#else CHECK_DIF_OK(dif_rv_plic_irq_set_enabled( plic, kTopMatchaPlicIrqIdIspWrapperIsp, kTopMatchaPlicTargetIbex0Smc, kDifToggleEnabled)); CHECK_DIF_OK(dif_rv_plic_irq_set_enabled( plic, kTopMatchaPlicIrqIdIspWrapperMi, kTopMatchaPlicTargetIbex0Smc, kDifToggleEnabled)); +#endif // Enable Mailbox IRQs CHECK_DIF_OK(dif_rv_plic_irq_set_enabled( plic, kTopMatchaPlicIrqIdTlulMailboxSmcRtirq, @@ -246,8 +292,13 @@ void _ottf_main(void) { test_status_set(kTestStatusInTest); +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(dif_isp_wrapper_init( + mmio_region_from_addr(TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR), &isp_wrapper)); +#else CHECK_DIF_OK(dif_isp_wrapper_init( mmio_region_from_addr(TOP_MATCHA_ISP_WRAPPER_BASE_ADDR), &isp_wrapper)); +#endif CHECK_DIF_OK(dif_rv_plic_init( mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc)); LOG_INFO("Configure isp into CAM live mode."); @@ -350,7 +401,7 @@ CHECK_DIF_OK(dif_rv_timer_init( mmio_region_from_addr(TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR), &rv_timer)); CHECK_DIF_OK(dif_rv_timer_approximate_tick_params(kClockFreqPeripheralHz, - 1000, &tick_params)); + COUNTER_FREQ, &tick_params)); CHECK_DIF_OK(dif_rv_timer_set_tick_params(&rv_timer, 0, tick_params)); CHECK_DIF_OK( dif_rv_timer_counter_set_enabled(&rv_timer, 0, kDifToggleEnabled)); @@ -367,6 +418,6 @@ handle_isp_wrapper_isp_irq(); CHECK_DIF_OK(dif_rv_timer_counter_read(&rv_timer, 0, &counter_end)); LOG_INFO("Capture + eval + render took %d ms", - (uint32_t)(counter_end - counter_start)); + (uint32_t)udiv64_slow(counter_end - counter_start, COUNTER_SCALE, NULL)); } }
diff --git a/sw/device/lib/arch/device_sc_asic.c b/sw/device/lib/arch/device_sc_asic.c index 27d3dc6..00fe315 100644 --- a/sw/device/lib/arch/device_sc_asic.c +++ b/sw/device/lib/arch/device_sc_asic.c
@@ -41,8 +41,8 @@ const uint64_t kClockFreqAonHz = 200 * 1000; // 200kHz const uint64_t kClockFreqSpiFlashHz = 24 * 1000 * 1000; // 24MHz -const uint64_t kClockFreqSpiDisplayHz = 5 * 1000 * 1000; // 5MHz -const uint64_t kClockFreqSpiPassthroughHz = 5 * 1000 * 1000; // 5MHz +const uint64_t kClockFreqSpiDisplayHz = 24 * 1000 * 1000; // 5MHz +const uint64_t kClockFreqSpiPassthroughHz = 24 * 1000 * 1000; // 5MHz const uint64_t kUartBaudrate = 115200;
diff --git a/sw/device/lib/arch/device_smc_asic.c b/sw/device/lib/arch/device_smc_asic.c index 5133734..26ccf05 100644 --- a/sw/device/lib/arch/device_smc_asic.c +++ b/sw/device/lib/arch/device_smc_asic.c
@@ -41,8 +41,8 @@ const uint64_t kClockFreqAonHz = 200 * 1000; // 200kHz const uint64_t kClockFreqSpiFlashHz = 24 * 1000 * 1000; // 24MHz -const uint64_t kClockFreqSpiDisplayHz = 5 * 1000 * 1000; // 5MHz -const uint64_t kClockFreqSpiPassthroughHz = 5 * 1000 * 1000; // 5MHz +const uint64_t kClockFreqSpiDisplayHz = 24 * 1000 * 1000; // 5MHz +const uint64_t kClockFreqSpiPassthroughHz = 24 * 1000 * 1000; // 5MHz const uint64_t kUartBaudrate = 115200;
diff --git a/sw/device/lib/camera_hm01b0.c b/sw/device/lib/camera_hm01b0.c index 337a59a..56e8b18 100644 --- a/sw/device/lib/camera_hm01b0.c +++ b/sw/device/lib/camera_hm01b0.c
@@ -17,6 +17,7 @@ #include "sw/device/lib/camera_hm01b0.h" #include "hw/top_matcha/sw/autogen/top_matcha.h" +#include "sw/device/lib/base/math.h" #include "sw/device/lib/camera_hm01b0_regs.h" #include "sw/device/lib/dif/dif_base.h" #include "sw/device/lib/dif/dif_i2c.h" @@ -100,12 +101,13 @@ } dif_result_t camera_hm01b0_init(void) { + uint64_t i2cclk = udiv64_slow(1000000000U, 24000000, NULL); CHECK_DIF_OK(dif_i2c_init(mmio_region_from_addr(TOP_MATCHA_CAM_I2C_BASE_ADDR), &cam_i2c)); dif_i2c_config_t cam_i2c_config; dif_i2c_timing_config_t cam_i2c_timing_config = { .lowest_target_device_speed = kDifI2cSpeedStandard, - .clock_period_nanos = 400, + .clock_period_nanos = i2cclk, .sda_rise_nanos = 800, .sda_fall_nanos = 600, .scl_period_nanos = 1000000 / 100000, @@ -173,7 +175,11 @@ CHECK_DIF_OK(camera_hm01b0_write_reg(HM01B0_SW_RESET, 0x00)); CHECK_DIF_OK(camera_hm01b0_write_reg(HM01B0_MODE_SELECT, 0x00)); +#if defined(MATCHA_SPARROW) + CHECK_DIF_OK(camera_hm01b0_write_reg(HM01B0_IMAGE_ORIENTATION, 0x00)); +#else CHECK_DIF_OK(camera_hm01b0_write_reg(HM01B0_IMAGE_ORIENTATION, 0x03)); +#endif CHECK_DIF_OK(camera_hm01b0_write_reg(HM01B0_BLC_TGT, 0x08)); CHECK_DIF_OK(camera_hm01b0_write_reg(HM01B0_BLC2_TGT, 0x08)); CHECK_DIF_OK(camera_hm01b0_write_reg(0x3044, 0x0A));
diff --git a/sw/device/lib/dif/BUILD b/sw/device/lib/dif/BUILD index 19a0f06..8008deb 100644 --- a/sw/device/lib/dif/BUILD +++ b/sw/device/lib/dif/BUILD
@@ -50,8 +50,14 @@ srcs = [ "autogen/dif_isp_wrapper_autogen.c", "autogen/dif_isp_wrapper_autogen.h", - "dif_isp_wrapper.c", - ], + ] + select({ + "//rules:sparrow_platform": [ + "dif_isp_wrapper_pico.c", + ], + "//conditions:default": [ + "dif_isp_wrapper.c", + ], + }), hdrs = [ "dif_isp_wrapper.h", "@isp_yocto//include:yocto_isp_register_address.h",
diff --git a/sw/device/lib/dif/dif_isp_wrapper_pico.c b/sw/device/lib/dif/dif_isp_wrapper_pico.c new file mode 100644 index 0000000..ab04034 --- /dev/null +++ b/sw/device/lib/dif/dif_isp_wrapper_pico.c
@@ -0,0 +1,1400 @@ +// Copyright 2022 Google LLC. +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/dif/dif_isp_wrapper.h" + +#include <stddef.h> + +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "isp_wrapper_regs.h" // Generated. + +// ISP configuration: +// size: 120 * 64, colar bar, force triggering interrupts(isp_irq and mi_irq) +dif_result_t dif_isp_wrapper_set_en(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + + mmio_region_write32(isp_wrapper->base_addr, 0x0000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0010, 0x00000049); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0014, 0x00000000); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0400, 0x00206016); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0004, 0x00000011); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x000C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0010, 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0014, 0x00000040); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x04, + 0x00d9c054); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x08, + 0x001e0040); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x0C, 0x002e400f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x10, 0x00484004); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x14, 0x00454001); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x18, + 0x000a0015); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x1C, + 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x20, + 0x4d777439); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x24, + 0x00000003); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x004, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x00C, 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x010, 0x00000040); + + + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x0, 0x00010001); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x4, 0x01580393); + + + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x0, 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x4, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x8, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0xC, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x10, 0x00000000); + + + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x000, 0x80000001); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x004, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x008, 0x00000008); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x00C, 0x00000015); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x010, 0x00000008); + + + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x0, + 0x011a0109); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x4, 0x01260109); + + + mmio_region_write32(isp_wrapper->base_addr, 0x810, 0x00000004); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x000, 0x000003f3); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x004, + 0x0000001a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x008, + 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x00C, 0x00000029); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x010, 0x00000043); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x014, + 0x00032040); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x018, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x01C, 0x0000000a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x020, 0x00000008); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x024, 0x00000004); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x028, + 0x00000000); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x000, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x004, + 0x0020003c); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x008, 0x002b01e5); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x00C, 0x01f10014); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x010, 0x01fa0000); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x014, 0x00050010); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x018, 0x00050010); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x04, 0x000000f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x08, 0x00000252); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x0C, 0x000000c9); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x10, 0x000000db); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x14, 0x00000036); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x18, 0x00000269); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x1C, 0x0000008a); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x20, 0x00000299); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x24, 0x00000217); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x28, 0x00000118); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x2C, 0x000001d1); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x30, 0x000003ed); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x34, 0x000001c1); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x38, 0x000000f8); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x3C, 0x0000026a); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x40, 0x000002f4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x44, 0x0000024e); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0550, 0x80000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0554, 0x00000060); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0558, 0x0000002f); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x055c, 0x00000009); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0560, 0x0000000d); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0564, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0568, 0x0000a504); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x056C, 0x11b98318); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x0, 0x00000026); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x4, 0x0000004b); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x8, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0xC, 0x000001ea); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x10, 0x000001d6); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x14, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x18, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x1C, 0x000001ca); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x20, 0x000001f6); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0xA24, + 0x00000000); + + + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A30, 0x000000dd); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A34, 0x000007c6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A38, 0x000007df); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A3C, 0x000007bf); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A40, 0x000000ec); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A44, 0x000007de); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A48, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A4C, 0x000007ae); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A50, 0x000000e0); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A54, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A58, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A5C, 0x00000000); + + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B00, 0x0004007c); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B18, 0x00000001); + + + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0C00, + 0x00008c10); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0C00, + 0x000041f5); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0C00, + 0x0000604f); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0C00, + 0x0000bad1); + mmio_region_write32(isp_wrapper->base_addr, 0x14 + 0x0C00, + 0x0000d46c); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x6C + 0x0C00, + 0x0000006a); + + + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0E00, + 0x5a000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0E00, + 0x00001e00); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0E00, + 0x5a002000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0E00, + 0x00001e00); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x2C + 0x0E00, + 0x5a004000); + mmio_region_write32(isp_wrapper->base_addr, 0x30 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x34 + 0x0E00, + 0x00000000); + + mmio_region_write32(isp_wrapper->base_addr, 0xF8 + 0x0E00, 0x0000007d); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x108 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x110 + 0x0E00, + 0x00000000); + + mmio_region_write32(isp_wrapper->base_addr, 0x130 + 0x0E00, + 0x00008000); + mmio_region_write32(isp_wrapper->base_addr, 0x134 + 0x0E00, + 0x0000a000); + mmio_region_write32(isp_wrapper->base_addr, 0x138 + 0x0E00, + 0x0000c000); + + mmio_region_write32(isp_wrapper->base_addr, 0x150 + 0x0E00, + 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x15C + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x160 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x164 + 0x0E00, + 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x168 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x16C + 0x0E00, + 0x00001e00); + + + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0E00, 0x007a2801); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x00, 0x00000c63); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00207257); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0C00, 0x00000120); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0E00, 0x00000050); + return kDifOk; +} + +// ISP configuration: +// size: 64 * 64, TPG(test pattern generation mode) +dif_result_t +dif_isp_wrapper_set_tpg_64_64_en(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0010, 0x00000049); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0014, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00206016); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0004, 0x00000011); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x000C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0010, 0x00000080); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0014, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x04, + 0x00d1c054); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x08, + 0x00200040); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x0C, 0x003e400f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x10, 0x002e4004); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x14, 0x00454001); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x18, + 0x000a8015); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x1C, + 0x00000010); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x20, + 0x4d777439); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x24, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x004, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x00C, 0x00000080); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x010, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x0, 0x00010001); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x4, 0x01580393); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x0, 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x4, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x8, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0xC, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x000, 0x80000001); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x004, 0x00000017); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x008, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x00C, 0x00000013); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x010, 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x0, + 0x011a0109); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x4, 0x01260109); + mmio_region_write32(isp_wrapper->base_addr, 0x810, 0x00000004); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x000, 0x000003f3); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x004, + 0x0000001a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x008, + 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x00C, 0x00000029); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x010, 0x00000043); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x014, + 0x00032040); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x018, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x01C, 0x0000000a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x020, 0x00000008); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x024, 0x00000004); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x028, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x000, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x004, + 0x00200040); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x008, 0x002b01e5); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x00C, 0x01f10014); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x010, 0x01fa0000); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x014, 0x00050010); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x018, 0x00050010); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x04, 0x000000f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x08, 0x00000252); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x0C, 0x000000c9); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x10, 0x000000db); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x14, 0x00000036); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x18, 0x00000269); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x1C, 0x0000008a); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x20, 0x00000299); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x24, 0x00000217); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x28, 0x00000118); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x2C, 0x000001d1); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x30, 0x000003ed); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x34, 0x000001c1); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x38, 0x000000f8); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x3C, 0x0000026a); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x40, 0x000002f4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x44, 0x0000024e); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0550, 0x80000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0554, 0x00000074); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0558, 0x00000021); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x055c, 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0560, 0x00000010); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0564, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0568, 0x0000a504); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x056C, 0x11b98318); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x0, 0x00000026); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x4, 0x0000004b); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x8, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0xC, 0x000001ea); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x10, 0x000001d6); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x14, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x18, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x1C, 0x000001ca); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x20, 0x000001f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0xA24, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A30, 0x000000dd); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A34, 0x000007c6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A38, 0x000007df); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A3C, 0x000007bf); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A40, 0x000000ec); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A44, 0x000007de); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A48, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A4C, 0x000007ae); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A50, 0x000000e0); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A54, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A58, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A5C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B00, 0x0004007c); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B18, 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0C00, + 0x00007efe); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0C00, + 0x00007df8); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0C00, + 0x00007df8); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0C00, + 0x00008c10); + mmio_region_write32(isp_wrapper->base_addr, 0x14 + 0x0C00, + 0x0000bad1); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x6C + 0x0C00, + 0x0000006a); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0E00, + 0x5a000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0E00, + 0x00001000); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0E00, + 0x5a001000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0E00, + 0x00001000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x2C + 0x0E00, + 0x5a002000); + mmio_region_write32(isp_wrapper->base_addr, 0x30 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x34 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0xF8 + 0x0E00, 0x0000007d); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x108 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x110 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x130 + 0x0E00, + 0x00004000); + mmio_region_write32(isp_wrapper->base_addr, 0x134 + 0x0E00, + 0x00005000); + mmio_region_write32(isp_wrapper->base_addr, 0x138 + 0x0E00, + 0x00006000); + mmio_region_write32(isp_wrapper->base_addr, 0x150 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x15C + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x160 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x164 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x168 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x16C + 0x0E00, + 0x00001000); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0E00, 0x007a2801); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x00, 0x00000c63); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00207257); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0C00, 0x00000103); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0E00, 0x00000050); + return kDifOk; +} + +dif_result_t +dif_isp_wrapper_set_tpg_64_64_en_for_enc(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0010, 0x00000049); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0014, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00206016); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0004, 0x00000011); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x000C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0010, 0x00000080); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0014, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x04, + 0x00d1c054); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x08, + 0x00200040); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x0C, 0x003e400f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x10, 0x002e4004); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x14, 0x00454001); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x18, + 0x000a8015); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x1C, + 0x00000010); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x20, + 0x4d777439); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x24, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x004, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x00C, 0x00000080); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x010, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x0, 0x00010001); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x4, 0x01580393); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x0, 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x4, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x8, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0xC, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x000, 0x80000001); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x004, 0x00000017); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x008, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x00C, 0x00000013); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x010, 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x0, + 0x011a0109); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x4, 0x01260109); + mmio_region_write32(isp_wrapper->base_addr, 0x810, 0x00000004); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x000, 0x000003f3); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x004, + 0x0000001a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x008, + 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x00C, 0x00000029); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x010, 0x00000043); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x014, + 0x00032040); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x018, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x01C, 0x0000000a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x020, 0x00000008); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x024, 0x00000004); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x028, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x000, 0x0000000c); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x004, + 0x00200040); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x008, 0x002b01e5); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x00C, 0x01f10014); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x010, 0x01fa0000); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x014, 0x00050010); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x018, 0x00050010); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x04, 0x000000f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x08, 0x00000252); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x0C, 0x000000c9); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x10, 0x000000db); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x14, 0x00000036); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x18, 0x00000269); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x1C, 0x0000008a); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x20, 0x00000299); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x24, 0x00000217); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x28, 0x00000118); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x2C, 0x000001d1); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x30, 0x000003ed); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x34, 0x000001c1); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x38, 0x000000f8); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x3C, 0x0000026a); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x40, 0x000002f4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x44, 0x0000024e); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0550, 0x80000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0554, 0x00000074); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0558, 0x00000021); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x055c, 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0560, 0x00000010); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0564, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0568, 0x0000a504); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x056C, 0x11b98318); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x0, 0x00000026); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x4, 0x0000004b); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x8, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0xC, 0x000001ea); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x10, 0x000001d6); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x14, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x18, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x1C, 0x000001ca); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x20, 0x000001f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0xA24, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A30, 0x000000dd); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A34, 0x000007c6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A38, 0x000007df); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A3C, 0x000007bf); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A40, 0x000000ec); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A44, 0x000007de); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A48, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A4C, 0x000007ae); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A50, 0x000000e0); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A54, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A58, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A5C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B00, 0x0004007c); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B18, 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0C00, + 0x00007efe); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0C00, + 0x00007df8); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0C00, + 0x00007df8); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0C00, + 0x00008c10); + mmio_region_write32(isp_wrapper->base_addr, 0x14 + 0x0C00, + 0x0000bad1); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x6C + 0x0C00, + 0x0000006a); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0E00, + 0x55000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0E00, + 0x00001000); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0E00, + 0x55001000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0E00, + 0x00001000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x2C + 0x0E00, + 0x55002000); + mmio_region_write32(isp_wrapper->base_addr, 0x30 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x34 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0xF8 + 0x0E00, 0x0000007d); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x108 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x110 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x130 + 0x0E00, + 0x00004000); + mmio_region_write32(isp_wrapper->base_addr, 0x134 + 0x0E00, + 0x00005000); + mmio_region_write32(isp_wrapper->base_addr, 0x138 + 0x0E00, + 0x00006000); + mmio_region_write32(isp_wrapper->base_addr, 0x150 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x15C + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x160 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x164 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x168 + 0x0E00, + 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x16C + 0x0E00, + 0x00001000); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0E00, 0x007a2801); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x00, 0x00000c63); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00207257); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0C00, 0x00000103); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0E00, 0x00000050); + return kDifOk; +} + +dif_result_t +dif_isp_wrapper_set_ml_mem_byp_324x324_en(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0010, 0x00000049); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0014, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00206018); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0004, 0x00000199); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x000C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0010, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0014, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x04, + 0x00ad3f05); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x08, + 0x00510144); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x0C, 0x0d6e000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x10, 0x028b8004); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x14, 0x0bad0001); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x18, + 0x04a1415b); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x1C, + 0x00002a97); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x20, + 0x4d777439); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x24, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x004, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x00C, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x010, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x0, 0x00010001); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x4, 0x01580393); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x0, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x4, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x8, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0xC, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x000, 0x80000001); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x004, 0x00000020); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x008, 0x00000028); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x00C, 0x00000030); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x010, 0x00000036); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x0, + 0x011a00d1); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x4, 0x01260109); + mmio_region_write32(isp_wrapper->base_addr, 0x810, 0x00000414); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x000, 0x00000692); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x004, + 0x00000167); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x008, + 0x00000142); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x00C, 0x00000177); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x010, 0x000001c7); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x014, + 0x0006698a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x018, 0x00000032); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x01C, 0x00000023); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x020, 0x00000019); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x024, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x028, + 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x000, 0x0000000a); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x004, + 0x00a200a2); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x008, 0x00170118); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x00C, 0x01d101ed); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x010, 0x01c100f8); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x014, 0x00020005); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x018, 0x00050019); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x04, 0x000002f4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x08, 0x0000024e); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x0C, 0x00000083); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x10, 0x000001af); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x14, 0x00000346); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x18, 0x000000a5); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x1C, 0x00000304); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x20, 0x00000111); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x24, 0x000003b9); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x28, 0x00000383); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x2C, 0x00000018); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x30, 0x0000028c); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x34, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x38, 0x00000087); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x3C, 0x00000047); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x40, 0x000001a4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x44, 0x000002bc); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0550, 0x80000007); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0554, 0x0000011c); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0558, 0x000000c1); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x055c, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0560, 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0564, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0568, 0x0000c2e6); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x056C, 0x8ef9ad1e); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x0, 0x00000026); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x4, 0x0000004b); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x8, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0xC, 0x000001ea); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x10, 0x000001d6); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x14, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x18, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x1C, 0x000001ca); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x20, 0x000001f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0xA24, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A30, 0x000000dd); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A34, 0x000007c6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A38, 0x000007df); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A3C, 0x000007bf); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A40, 0x000000ec); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A44, 0x000007de); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A48, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A4C, 0x000007ae); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A50, 0x000000e0); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A54, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A58, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A5C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B00, 0x00000020); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B18, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0C00, + 0x00008469); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0C00, + 0x0000a674); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0C00, + 0x0000fa3d); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0C00, + 0x0000ef61); + mmio_region_write32(isp_wrapper->base_addr, 0x14 + 0x0C00, + 0x0000f9b7); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x6C + 0x0C00, + 0x000000fa); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0E00, + 0x5a300000); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0E00, + 0x00019f20); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0E00, + 0x5a320000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x2C + 0x0E00, + 0x5a320000); + mmio_region_write32(isp_wrapper->base_addr, 0x30 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x34 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0xF8 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x108 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x110 + 0x0E00, + 0x00000003); + mmio_region_write32(isp_wrapper->base_addr, 0x130 + 0x0E00, + 0x5a340000); + mmio_region_write32(isp_wrapper->base_addr, 0x134 + 0x0E00, + 0x5a360000); + mmio_region_write32(isp_wrapper->base_addr, 0x138 + 0x0E00, + 0x5a360000); + mmio_region_write32(isp_wrapper->base_addr, 0x150 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x15C + 0x0E00, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x160 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x164 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x168 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x16C + 0x0E00, + 0x00019a10); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0E00, 0x003a2808); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x00, 0x00000868); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00207259); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0C00, 0x00000190); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0E00, 0x000000b0); + return kDifOk; +} + +dif_result_t _dif_isp_wrapper_set_raw_320x240_byp_320x240_en( + const dif_isp_wrapper_t *isp_wrapper, + const uint32_t y_base_ad_init_addr, const uint32_t cb_base_ad_init_addr, + const uint32_t cr_base_ad_init_addr, const uint32_t y_base_ad_init2_addr, + const uint32_t cb_base_ad_init2_addr, const uint32_t cr_base_ad_init2_addr) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0010, 0x00000049); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0014, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00206018); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0004, 0x000199); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0008, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x000C, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0010, 0x00000140); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0014, 0x000000f0); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x04, + 0x00ad3f05); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x08, + 0x00510144); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x0C, 0x0d6e000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x10, 0x028b8004); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x14, 0x0bad0001); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x18, + 0x04a1415b); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x1C, + 0x00002a97); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x20, + 0x4d777439); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x24, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x004, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x00C, 0x00000140); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x010, 0x000000f0); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x0, 0x00010001); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x4, 0x01580393); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x0, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x4, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x8, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0xC, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x000, 0x80000001); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x004, 0x00000020); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x008, 0x00000028); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x00C, 0x00000030); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x010, 0x00000036); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x0, + 0x011a00d1); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x4, 0x01260109); + mmio_region_write32(isp_wrapper->base_addr, 0x810, 0x00000414); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x000, 0x00000692); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x004, + 0x00000167); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x008, + 0x00000142); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x00C, 0x00000177); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x010, 0x000001c7); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x014, + 0x0006698a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x018, 0x00000032); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x01C, 0x00000023); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x020, 0x00000019); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x024, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x028, + 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x000, 0x0000000a); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x004, + 0x00a200a2); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x008, 0x00170118); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x00C, 0x01d101ed); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x010, 0x01c100f8); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x014, 0x00020005); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x018, 0x00050019); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x04, 0x000002f4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x08, 0x0000024e); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x0C, 0x00000083); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x10, 0x000001af); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x14, 0x00000346); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x18, 0x000000a5); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x1C, 0x00000304); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x20, 0x00000111); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x24, 0x000003b9); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x28, 0x00000383); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x2C, 0x00000018); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x30, 0x0000028c); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x34, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x38, 0x00000087); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x3C, 0x00000047); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x40, 0x000001a4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x44, 0x000002bc); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0550, 0x80000007); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0554, 0x0000011c); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0558, 0x000000c1); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x055c, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0560, 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0564, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0568, 0x0000c2e6); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x056C, 0x8ef9ad1e); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x0, 0x00000026); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x4, 0x0000004b); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x8, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0xC, 0x000001ea); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x10, 0x000001d6); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x14, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x18, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x1C, 0x000001ca); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x20, 0x000001f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0xA24, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A30, 0x000000dd); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A34, 0x000007c6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A38, 0x000007df); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A3C, 0x000007bf); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A40, 0x000000ec); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A44, 0x000007de); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A48, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A4C, 0x000007ae); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A50, 0x000000e0); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A54, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A58, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A5C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B00, 0x00000020); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B18, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0C00, + 0x00008469); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0C00, + 0x0000a674); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0C00, + 0x0000fa3d); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0C00, + 0x0000ef61); + mmio_region_write32(isp_wrapper->base_addr, 0x14 + 0x0C00, + 0x0000f9b7); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x6C + 0x0C00, + 0x000000fa); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0E00, + y_base_ad_init_addr); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0E00, + 0x00012c00); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0E00, + cb_base_ad_init_addr); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x2C + 0x0E00, + cr_base_ad_init_addr); + mmio_region_write32(isp_wrapper->base_addr, 0x30 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x34 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0xF8 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x108 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x110 + 0x0E00, + 0x00000003); + mmio_region_write32(isp_wrapper->base_addr, 0x130 + 0x0E00, + y_base_ad_init2_addr); + mmio_region_write32(isp_wrapper->base_addr, 0x134 + 0x0E00, + cb_base_ad_init2_addr); + mmio_region_write32(isp_wrapper->base_addr, 0x138 + 0x0E00, + cr_base_ad_init2_addr); + mmio_region_write32(isp_wrapper->base_addr, 0x150 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x15C + 0x0E00, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x160 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x164 + 0x0E00, + 0x00000140); + mmio_region_write32(isp_wrapper->base_addr, 0x168 + 0x0E00, + 0x000000f0); + mmio_region_write32(isp_wrapper->base_addr, 0x16C + 0x0E00, + 0x00012c00); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0E00, 0x003a2808); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x00, 0x00000868); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00207251); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0C00, 0x00000190); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0E00, 0x000000b0); + return kDifOk; +} +// ISP configuration: +// raw:320x240, byp:320x240 +dif_result_t dif_isp_wrapper_set_raw_320x240_byp_320x240_en( + const dif_isp_wrapper_t *isp_wrapper) +{ + return _dif_isp_wrapper_set_raw_320x240_byp_320x240_en(isp_wrapper, + 0x5a000000, + 0x5a01a000, + 0x5a01a000, + 0x5a020000, + 0x5a03a000, + 0x5a03a000); +} + +// ISP configuration: +// raw:320x240, byp:320x240, hps image address: 0x00300000 +dif_result_t +dif_isp_wrapper_set_ml_mem_byp_320x240_en(const dif_isp_wrapper_t *isp_wrapper) +{ + return _dif_isp_wrapper_set_raw_320x240_byp_320x240_en(isp_wrapper, + 0x5a300000, + 0x5a320000, + 0x5a320000, + 0x5a340000, + 0x5a360000, + 0x5a360000); +} + + +// ISP configuration: +// raw:324x324, byp:324x324 +dif_result_t dif_isp_wrapper_set_raw_324x324_byp_324x324_en( + const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0010, 0x00000049); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0014, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00206018); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0004, 0x00000199); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x000C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0010, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0014, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x04, + 0x00ad3f05); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x08, + 0x00510144); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x0C, 0x0d6e000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x10, 0x028b8004); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x14, 0x0bad0001); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x18, + 0x04a1415b); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x1C, + 0x00002a97); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x20, + 0x4d777439); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x24, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x000, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x004, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x008, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x00C, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x0600 + 0x010, 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x0, 0x00010001); + mmio_region_write32(isp_wrapper->base_addr, 0x624 + 0x4, 0x01580393); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x0, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x4, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x8, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0xC, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x700 + 0x10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x000, 0x80000001); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x004, 0x00000020); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x008, 0x00000028); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x00C, 0x00000030); + mmio_region_write32(isp_wrapper->base_addr, 0x720 + 0x010, 0x00000036); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x0, + 0x011a00d1); + mmio_region_write32(isp_wrapper->base_addr, 0x800 + 0x4, 0x01260109); + mmio_region_write32(isp_wrapper->base_addr, 0x810, 0x00000414); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x000, 0x00000692); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x004, + 0x00000167); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x008, + 0x00000142); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x00C, 0x00000177); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x010, 0x000001c7); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x014, + 0x0006698a); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x018, 0x00000032); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x01C, 0x00000023); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x020, 0x00000019); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x024, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0814 + 0x028, + 0x00000006); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x000, 0x0000000a); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x004, + 0x00a200a2); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x008, 0x00170118); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x00C, 0x01d101ed); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x010, 0x01c100f8); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x014, 0x00020005); + mmio_region_write32(isp_wrapper->base_addr, 0x0870 + 0x018, 0x00050019); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x04, 0x000002f4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x08, 0x0000024e); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x0C, 0x00000083); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x10, 0x000001af); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x14, 0x00000346); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x18, 0x000000a5); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x1C, 0x00000304); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x20, 0x00000111); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x24, 0x000003b9); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x28, 0x00000383); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x2C, 0x00000018); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x30, 0x0000028c); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x34, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x38, 0x00000087); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x3C, 0x00000047); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x40, 0x000001a4); + mmio_region_write32(isp_wrapper->base_addr, 0x0900 + 0x44, 0x000002bc); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0550, 0x80000007); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0554, 0x0000011c); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0558, 0x000000c1); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x055c, 0x0000001e); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0560, 0x00000078); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0564, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0568, 0x0000c2e6); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x056C, 0x8ef9ad1e); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x0, 0x00000026); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x4, 0x0000004b); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x8, 0x0000000f); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0xC, 0x000001ea); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x10, 0x000001d6); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x14, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x18, 0x00000040); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x1C, 0x000001ca); + mmio_region_write32(isp_wrapper->base_addr, 0x0A00 + 0x20, 0x000001f6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0xA24, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A30, 0x000000dd); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A34, 0x000007c6); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A38, 0x000007df); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A3C, 0x000007bf); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A40, 0x000000ec); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A44, 0x000007de); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A48, 0x00000002); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A4C, 0x000007ae); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A50, 0x000000e0); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A54, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A58, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0A5C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B00, 0x00000020); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B10, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B18, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0C00, + 0x00008469); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0C00, + 0x0000a674); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0C00, + 0x0000fa3d); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0C00, + 0x0000ef61); + mmio_region_write32(isp_wrapper->base_addr, 0x14 + 0x0C00, + 0x0000f9b7); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0C00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x6C + 0x0C00, + 0x000000fa); + mmio_region_write32(isp_wrapper->base_addr, 0x08 + 0x0E00, + 0x5a000000); + mmio_region_write32(isp_wrapper->base_addr, 0x0C + 0x0E00, + 0x00019f20); + mmio_region_write32(isp_wrapper->base_addr, 0x10 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x18 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x1C + 0x0E00, + 0x5a01a000); + mmio_region_write32(isp_wrapper->base_addr, 0x20 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x24 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x2C + 0x0E00, + 0x5a01a000); + mmio_region_write32(isp_wrapper->base_addr, 0x30 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x34 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0xF8 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x108 + 0x0E00, 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x110 + 0x0E00, + 0x00000003); + mmio_region_write32(isp_wrapper->base_addr, 0x130 + 0x0E00, + 0x00034000); + mmio_region_write32(isp_wrapper->base_addr, 0x134 + 0x0E00, + 0x0004e000); + mmio_region_write32(isp_wrapper->base_addr, 0x138 + 0x0E00, + 0x0004e000); + mmio_region_write32(isp_wrapper->base_addr, 0x150 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x15C + 0x0E00, + 0x00000001); + mmio_region_write32(isp_wrapper->base_addr, 0x160 + 0x0E00, + 0x00000000); + mmio_region_write32(isp_wrapper->base_addr, 0x164 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x168 + 0x0E00, + 0x00000144); + mmio_region_write32(isp_wrapper->base_addr, 0x16C + 0x0E00, + 0x00019a10); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0E00, 0x003a2808); + mmio_region_write32(isp_wrapper->base_addr, 0x0500 + 0x00, 0x00000868); + mmio_region_write32(isp_wrapper->base_addr, 0x0400 + 0x0000, 0x00207259); + mmio_region_write32(isp_wrapper->base_addr, 0x00 + 0x0C00, 0x00000190); + mmio_region_write32(isp_wrapper->base_addr, 0x04 + 0x0E00, 0x000000b0); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_clear_en(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0xb00, 0x00040000); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_isp_irq_mask(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + // ISP_IMSC Interrupt mask, 0 active + mmio_region_write32(isp_wrapper->base_addr, 0xb00, 0x00000000); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_mi_irq_mask(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + // MI_IMSC Interrupt mask, 0 active + mmio_region_write32(isp_wrapper->base_addr, 0xef8, 0x00000000); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_isp_irq_done(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + uint32_t irq_status = mmio_region_read32(isp_wrapper->base_addr, 0x0000 + 0x0B08); + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, irq_status); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_mi_irq_done(const dif_isp_wrapper_t *isp_wrapper) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + uint32_t irq_status = + mmio_region_read32(isp_wrapper->base_addr, 0x100 + 0x0E00); + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, irq_status); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_read_en(const dif_isp_wrapper_t *isp_wrapper, + uint32_t *result) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + // MI_MIS Masked Interrupt Status + *result = mmio_region_read32(isp_wrapper->base_addr, 0xf00); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_read_mi_mis(const dif_isp_wrapper_t *isp_wrapper, + uint32_t *result) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + *result = mmio_region_read32(isp_wrapper->base_addr, 0x100 + 0x0E00); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_read_isp_mis(const dif_isp_wrapper_t *isp_wrapper, + uint32_t *result) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + *result = mmio_region_read32(isp_wrapper->base_addr, 0x0000 + 0x0B08); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_read_isp_ris(const dif_isp_wrapper_t *isp_wrapper, + uint32_t *val) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + *val = mmio_region_read32(isp_wrapper->base_addr, 0x0000 + 0x0B04); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_read_mi_ris(const dif_isp_wrapper_t *isp_wrapper, + uint32_t *val) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + *val = mmio_region_read32(isp_wrapper->base_addr, 0xFC + 0x0E00); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_write_isp_icr(const dif_isp_wrapper_t *isp_wrapper, + uint32_t val) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x0000 + 0x0B0C, val); + return kDifOk; +} + +dif_result_t dif_isp_wrapper_write_mi_icr(const dif_isp_wrapper_t *isp_wrapper, + uint32_t val) +{ + if (isp_wrapper == NULL) { + return kDifBadArg; + } + mmio_region_write32(isp_wrapper->base_addr, 0x104 + 0x0E00, val); + return kDifOk; +}