Revert "I2S Add to Pinmux" This reverts commit 1402ddc83acc05e861f2347834d6525630adff53. Reason for revert: Causes DV breakage as direct I2S pins are removed that are referenced in DV test. Change-Id: I0d68ad412747476edf573ff17dac9c162164553a
diff --git a/hw/top_matcha/data/clocks_nexus.xdc b/hw/top_matcha/data/clocks_nexus.xdc index 8a4396e..75c267e 100644 --- a/hw/top_matcha/data/clocks_nexus.xdc +++ b/hw/top_matcha/data/clocks_nexus.xdc
@@ -113,19 +113,19 @@ create_generated_clock -name clk_i2s_rx -divide_by 22 -source [get_pin ${u_pll}/CLKOUT1] [get_pins top_matcha/u_i2s0/i2s_core/bufg_rx_audio_clk/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] create_generated_clock -name clk_i2s_tx -divide_by 22 -source [get_pin ${u_pll}/CLKOUT1] [get_pins top_matcha/u_i2s0/i2s_core/bufg_tx_audio_clk/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O] -# ## I2S IO Delay -# set_input_delay -clock clk_i2s_rx 0 [get_ports I2S0_RX_SCLK] -# set_input_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_SD] -# set_input_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_WS] -# set_input_delay -clock clk_i2s_tx 0 [get_ports I2S0_TX_SCLK] -# set_input_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_SD] -# set_input_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_WS] -# set_output_delay -clock clk_i2s_rx 0 [get_ports I2S0_RX_SCLK] -# set_output_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_SD] -# set_output_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_WS] -# set_output_delay -clock clk_i2s_tx 0 [get_ports I2S0_TX_SCLK] -# set_output_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_SD] -# set_output_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_WS] +## I2S IO Delay +set_input_delay -clock clk_i2s_rx 0 [get_ports I2S0_RX_SCLK] +set_input_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_SD] +set_input_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_WS] +set_input_delay -clock clk_i2s_tx 0 [get_ports I2S0_TX_SCLK] +set_input_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_SD] +set_input_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_WS] +set_output_delay -clock clk_i2s_rx 0 [get_ports I2S0_RX_SCLK] +set_output_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_SD] +set_output_delay -clock clk_i2s_rx 5 [get_ports I2S0_RX_WS] +set_output_delay -clock clk_i2s_tx 0 [get_ports I2S0_TX_SCLK] +set_output_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_SD] +set_output_delay -clock clk_i2s_tx 5 [get_ports I2S0_TX_WS] # set clock sense on the input to spi buffers to help the tool understand the clocks are shifted versions of each other # This can also be accomplished through create_genearted_clocks.
diff --git a/hw/top_matcha/data/pins_nexus.xdc b/hw/top_matcha/data/pins_nexus.xdc index b5942d4..f7d5293 100644 --- a/hw/top_matcha/data/pins_nexus.xdc +++ b/hw/top_matcha/data/pins_nexus.xdc
@@ -153,13 +153,13 @@ set_property -dict { PACKAGE_PIN BC40 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD4_10_FPGA ##OLD## J271 pins for prototyping. Bank 63 -set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports { IOD0 }]; #EXP1x10_J271_P1 (default cio_rx_sclk_o) -set_property -dict { PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports { IOD1 }]; #EXP1x10_J271_P3 (default cio_rx_sd_i) -set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS18 } [get_ports { IOD2 }]; #EXP1x10_J271_P5 (default cio_rx_ws_o) -set_property -dict { PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports { IOD3 }]; #EXP1x10_J271_P7 (default cio_tx_sd_o) -set_property -dict { PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports { IOD4 }]; #EXP1x10_J271_P9 (default cio_tx_ws_o) -set_property -dict { PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports { IOD5 }]; #EXP1x10_J271_P11 (default cio_tx_sclk_o) -# set_property -dict { PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P13 +set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports { I2S0_RX_SCLK }]; #EXP1x10_J271_P1 +set_property -dict { PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports { I2S0_RX_WS }]; #EXP1x10_J271_P3 +set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS18 } [get_ports { I2S0_RX_SD }]; #EXP1x10_J271_P5 +set_property -dict { PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports { I2S0_TX_SCLK }]; #EXP1x10_J271_P7 +set_property -dict { PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports { I2S0_TX_WS }]; #EXP1x10_J271_P9 +set_property -dict { PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports { I2S0_TX_SD }]; #EXP1x10_J271_P11 +# set_property -dict { PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P13 #EXP1x10_J271_P19 held by IO_UPHY_DPPULLUP #EXP1x10_J271_P17 unused # set_property -dict { PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P19
diff --git a/hw/top_matcha/data/top_matcha.hjson b/hw/top_matcha/data/top_matcha.hjson index d1c3e0e..a4952c6 100644 --- a/hw/top_matcha/data/top_matcha.hjson +++ b/hw/top_matcha/data/top_matcha.hjson
@@ -1527,12 +1527,12 @@ { name: 'ISP_DVP_VSYNC' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR VSYNC'}, { name: 'CAM_TRIG' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'CAM trigger'}, { name: 'CAM_INT' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'CAM Interrupt'}, - // { name: 'I2S0_RX_SCLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx host clock'}, - // { name: 'I2S0_RX_WS' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx host word select'}, - // { name: 'I2S0_RX_SD' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx serial data'}, - // { name: 'I2S0_TX_SCLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx host clock'}, - // { name: 'I2S0_TX_WS' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx host word select'}, - // { name: 'I2S0_TX_SD' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx serial data'}, + { name: 'I2S0_RX_SCLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx host clock'}, + { name: 'I2S0_RX_WS' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx host word select'}, + { name: 'I2S0_RX_SD' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx serial data'}, + { name: 'I2S0_TX_SCLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx host clock'}, + { name: 'I2S0_TX_WS' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx host word select'}, + { name: 'I2S0_TX_SD' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx serial data'}, // IOA { name: 'IOA0' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'}, @@ -1587,13 +1587,6 @@ { name: 'IOR11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, { name: 'IOR12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, { name: 'IOR13' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, - // IOD - { name: 'IOD0' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, - { name: 'IOD1' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, - { name: 'IOD2' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, - { name: 'IOD3' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, - { name: 'IOD4' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, - { name: 'IOD5' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'}, ] } @@ -1677,6 +1670,13 @@ // Camera I2C -- TO-DO(pbf): May swithc to use MIO/Muxed late for cam_i2c as same as other i2c bus. // Currently use DIO/Manual for cam_i2c instead of MIO in order to shift the UART0 pin assignment from original opentitan. { instance: "cam_i2c", port: '', connection: 'manual' , pad: '' , desc: ''}, + // I2S Host1 + { instance: 'i2s0', port: 'rx_sclk', connection: 'direct', pad: 'I2S0_RX_SCLK' , desc: ''}, + { instance: 'i2s0', port: 'rx_ws', connection: 'direct', pad: 'I2S0_RX_WS' , desc: ''}, + { instance: 'i2s0', port: 'rx_sd', connection: 'direct', pad: 'I2S0_RX_SD' , desc: ''}, + { instance: 'i2s0', port: 'tx_sclk', connection: 'direct', pad: 'I2S0_TX_SCLK' , desc: ''}, + { instance: 'i2s0', port: 'tx_ws', connection: 'direct', pad: 'I2S0_TX_WS' , desc: ''}, + { instance: 'i2s0', port: 'tx_sd', connection: 'direct', pad: 'I2S0_TX_SD' , desc: ''}, // MIOs { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''}, @@ -1694,7 +1694,6 @@ { instance: "sensor_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "pwm_aon", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "otp_ctrl", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''}, - { instance: 'i2s0', port: '', connection: 'muxed' , pad: '' , desc: ''}, // Sysrst ctrl has both muxed and dedicated IOs { instance: "sysrst_ctrl_aon", port: 'ac_present', connection: 'muxed' , pad: '' , desc: ''}, { instance: "sysrst_ctrl_aon", port: 'key0_in', connection: 'muxed' , pad: '' , desc: ''},
diff --git a/hw/top_matcha/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_matcha/ip/pinmux/data/autogen/pinmux.hjson index 55b4b3e..4f9eab9 100644 --- a/hw/top_matcha/ip/pinmux/data/autogen/pinmux.hjson +++ b/hw/top_matcha/ip/pinmux/data/autogen/pinmux.hjson
@@ -313,25 +313,25 @@ { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", - default: "58", + default: "57", local: "true" }, { name: "NMioPeriphOut", desc: "Number of muxed peripheral outputs", type: "int", - default: "80", + default: "75", local: "true" }, { name: "NMioPads", desc: "Number of muxed IO pads", type: "int", - default: "53", + default: "47", local: "true" }, { name: "NDioPads", desc: "Number of dedicated IO pads", type: "int", - default: "37", + default: "43", local: "true" }, { name: "NWkupDetect",
diff --git a/hw/top_matcha/ip/pinmux/doc/autogen/pinout_asic.md b/hw/top_matcha/ip/pinmux/doc/autogen/pinout_asic.md index c7129d2..7ae70bb 100644 --- a/hw/top_matcha/ip/pinmux/doc/autogen/pinout_asic.md +++ b/hw/top_matcha/ip/pinmux/doc/autogen/pinout_asic.md
@@ -54,6 +54,12 @@ | <p style="font-size:smaller">ISP_DVP_VSYNC</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SENSOR VSYNC</p> | | <p style="font-size:smaller">CAM_TRIG</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">CAM trigger</p> | | <p style="font-size:smaller">CAM_INT</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">CAM Interrupt</p> | +| <p style="font-size:smaller">I2S0_RX_SCLK</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S rx host clock</p> | +| <p style="font-size:smaller">I2S0_RX_WS</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S rx host word select</p> | +| <p style="font-size:smaller">I2S0_RX_SD</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S rx serial data</p> | +| <p style="font-size:smaller">I2S0_TX_SCLK</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S tx host clock</p> | +| <p style="font-size:smaller">I2S0_TX_WS</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S tx host word select</p> | +| <p style="font-size:smaller">I2S0_TX_SD</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S tx serial data</p> | | <p style="font-size:smaller">IOA0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIoa0 / kTopMatchaPinmuxMioOutIoa0</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOA1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIoa1 / kTopMatchaPinmuxMioOutIoa1</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOA2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIoa2 / kTopMatchaPinmuxMioOutIoa2</p> | <p style="font-size:smaller">Muxed IO pad</p> | @@ -103,12 +109,6 @@ | <p style="font-size:smaller">IOR11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIor11 / kTopMatchaPinmuxMioOutIor11</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOR12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIor12 / kTopMatchaPinmuxMioOutIor12</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOR13</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIor13 / kTopMatchaPinmuxMioOutIor13</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod0 / kTopMatchaPinmuxMioOutIod0</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod1 / kTopMatchaPinmuxMioOutIod1</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod2 / kTopMatchaPinmuxMioOutIod2</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod3 / kTopMatchaPinmuxMioOutIod3</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod4 / kTopMatchaPinmuxMioOutIod4</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod5 / kTopMatchaPinmuxMioOutIod5</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">AST_MISC</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra infrastructure pad for AST</p> | ## Pinmux Connectivity @@ -188,6 +188,7 @@ | <p style="font-size:smaller">isp_wrapper_s_hsync</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">ISP_DVP_HSYNC</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">isp_wrapper_s_vsync</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">ISP_DVP_VSYNC</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">cam_ctrl_cam_int</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">CAM_INT</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_rx_sd</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_RX_SD</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart0_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInUart0Rx</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart1_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInUart1Rx</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart2_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInUart2Rx</p> | <p style="font-size:smaller"></p> | @@ -196,7 +197,6 @@ | <p style="font-size:smaller">flash_ctrl_tck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInFlashCtrlTck</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">flash_ctrl_tms</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInFlashCtrlTms</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">flash_ctrl_tdi</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInFlashCtrlTdi</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_rx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInI2s0RxSd</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_ac_present</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key0_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key1_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In</p> | <p style="font-size:smaller"></p> | @@ -209,6 +209,11 @@ | <p style="font-size:smaller">spi_host2_sck</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST2_CLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">spi_host2_csb</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST2_CS_L</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">cam_ctrl_cam_trig</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">CAM_TRIG</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_rx_sclk</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_RX_SCLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_rx_ws</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_RX_WS</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_tx_sclk</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_TX_SCLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_tx_ws</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_TX_WS</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_tx_sd</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_TX_SD</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselUart0Tx / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselUart1Tx / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart2_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselUart2Tx / -</p> | <p style="font-size:smaller"></p> | @@ -236,11 +241,6 @@ | <p style="font-size:smaller">pwm_aon_pwm[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselPwmAonPwm4 / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">pwm_aon_pwm[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselPwmAonPwm5 / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">otp_ctrl_test[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselOtpCtrlTest0 / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_rx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0RxSclk / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_rx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0RxWs / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_tx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0TxSclk / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_tx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0TxWs / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_tx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0TxSd / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_bat_disable</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key0_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key1_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out / -</p> | <p style="font-size:smaller"></p> |
diff --git a/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md b/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md index b7a389d..2ddda15 100644 --- a/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md +++ b/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md
@@ -48,6 +48,12 @@ | <p style="font-size:smaller">ISP_DVP_VSYNC</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SENSOR VSYNC</p> | | <p style="font-size:smaller">CAM_TRIG</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">CAM trigger</p> | | <p style="font-size:smaller">CAM_INT</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">CAM Interrupt</p> | +| <p style="font-size:smaller">I2S0_RX_SCLK</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S rx host clock</p> | +| <p style="font-size:smaller">I2S0_RX_WS</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S rx host word select</p> | +| <p style="font-size:smaller">I2S0_RX_SD</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S rx serial data</p> | +| <p style="font-size:smaller">I2S0_TX_SCLK</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S tx host clock</p> | +| <p style="font-size:smaller">I2S0_TX_WS</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S tx host word select</p> | +| <p style="font-size:smaller">I2S0_TX_SD</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">I2S tx serial data</p> | | <p style="font-size:smaller">IOA0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIoa0 / kTopMatchaPinmuxMioOutIoa0</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOA1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIoa1 / kTopMatchaPinmuxMioOutIoa1</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOA2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIoa2 / kTopMatchaPinmuxMioOutIoa2</p> | <p style="font-size:smaller">Muxed IO pad</p> | @@ -97,12 +103,6 @@ | <p style="font-size:smaller">IOR11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIor11 / kTopMatchaPinmuxMioOutIor11</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOR12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIor12 / kTopMatchaPinmuxMioOutIor12</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IOR13</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIor13 / kTopMatchaPinmuxMioOutIor13</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod0 / kTopMatchaPinmuxMioOutIod0</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod1 / kTopMatchaPinmuxMioOutIod1</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod2 / kTopMatchaPinmuxMioOutIod2</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod3 / kTopMatchaPinmuxMioOutIod3</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod4 / kTopMatchaPinmuxMioOutIod4</p> | <p style="font-size:smaller">Muxed IO pad</p> | -| <p style="font-size:smaller">IOD5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxInselIod5 / kTopMatchaPinmuxMioOutIod5</p> | <p style="font-size:smaller">Muxed IO pad</p> | | <p style="font-size:smaller">IO_CLK</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra clock input for FPGA target</p> | | <p style="font-size:smaller">IO_CLK_N</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra clock input for FPGA target</p> | | <p style="font-size:smaller">POR_BUTTON_N</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Power-on reset button input</p> | @@ -187,6 +187,7 @@ | <p style="font-size:smaller">isp_wrapper_s_hsync</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">ISP_DVP_HSYNC</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">isp_wrapper_s_vsync</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">ISP_DVP_VSYNC</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">cam_ctrl_cam_int</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">CAM_INT</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_rx_sd</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_RX_SD</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart0_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInUart0Rx</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart1_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInUart1Rx</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart2_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInUart2Rx</p> | <p style="font-size:smaller"></p> | @@ -195,7 +196,6 @@ | <p style="font-size:smaller">flash_ctrl_tck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInFlashCtrlTck</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">flash_ctrl_tms</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInFlashCtrlTms</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">flash_ctrl_tdi</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInFlashCtrlTdi</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_rx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInI2s0RxSd</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_ac_present</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key0_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key1_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In</p> | <p style="font-size:smaller"></p> | @@ -208,6 +208,11 @@ | <p style="font-size:smaller">spi_host2_sck</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST2_CLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">spi_host2_csb</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST2_CS_L</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">cam_ctrl_cam_trig</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">CAM_TRIG</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_rx_sclk</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_RX_SCLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_rx_ws</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_RX_WS</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_tx_sclk</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_TX_SCLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_tx_ws</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_TX_WS</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | +| <p style="font-size:smaller">i2s0_tx_sd</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">I2S0_TX_SD</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselUart0Tx / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselUart1Tx / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">uart2_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselUart2Tx / -</p> | <p style="font-size:smaller"></p> | @@ -235,11 +240,6 @@ | <p style="font-size:smaller">pwm_aon_pwm[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselPwmAonPwm4 / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">pwm_aon_pwm[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselPwmAonPwm5 / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">otp_ctrl_test[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselOtpCtrlTest0 / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_rx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0RxSclk / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_rx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0RxWs / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_tx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0TxSclk / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_tx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0TxWs / -</p> | <p style="font-size:smaller"></p> | -| <p style="font-size:smaller">i2s0_tx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselI2s0TxSd / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_bat_disable</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key0_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out / -</p> | <p style="font-size:smaller"></p> | | <p style="font-size:smaller">sysrst_ctrl_aon_key1_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out / -</p> | <p style="font-size:smaller"></p> |
diff --git a/hw/top_matcha/ip/pinmux/doc/autogen/targets.md b/hw/top_matcha/ip/pinmux/doc/autogen/targets.md index eb767df..080539b 100644 --- a/hw/top_matcha/ip/pinmux/doc/autogen/targets.md +++ b/hw/top_matcha/ip/pinmux/doc/autogen/targets.md
@@ -7,5 +7,5 @@ | Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables | |:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:---------------------------------------------------------------------------------:| -| ASIC | 4 | 53 | 33 | 12 | 98 | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_asic/index.html) | -| NEXUS | 4 | 53 | 33 | 11 | 97 | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_nexus/index.html) | +| ASIC | 4 | 47 | 39 | 12 | 98 | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_asic/index.html) | +| NEXUS | 4 | 47 | 39 | 11 | 97 | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_nexus/index.html) |
diff --git a/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv index 1644d53..91eb622 100644 --- a/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv +++ b/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -8,10 +8,10 @@ // Param list parameter int AttrDw = 13; - parameter int NMioPeriphIn = 58; - parameter int NMioPeriphOut = 80; - parameter int NMioPads = 53; - parameter int NDioPads = 37; + parameter int NMioPeriphIn = 57; + parameter int NMioPeriphOut = 75; + parameter int NMioPads = 47; + parameter int NDioPads = 43; parameter int NWkupDetect = 8; parameter int WkupCntWidth = 8; parameter int NumAlerts = 1; @@ -243,17 +243,17 @@ // Register -> HW type typedef struct packed { - pinmux_reg2hw_alert_test_reg_t alert_test; // [3228:3227] - pinmux_reg2hw_mio_periph_insel_mreg_t [57:0] mio_periph_insel; // [3226:2879] - pinmux_reg2hw_mio_outsel_mreg_t [52:0] mio_outsel; // [2878:2508] - pinmux_reg2hw_mio_pad_attr_mreg_t [52:0] mio_pad_attr; // [2507:1342] - pinmux_reg2hw_dio_pad_attr_mreg_t [36:0] dio_pad_attr; // [1341:528] - pinmux_reg2hw_mio_pad_sleep_status_mreg_t [52:0] mio_pad_sleep_status; // [527:475] - pinmux_reg2hw_mio_pad_sleep_en_mreg_t [52:0] mio_pad_sleep_en; // [474:422] - pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [52:0] mio_pad_sleep_mode; // [421:316] - pinmux_reg2hw_dio_pad_sleep_status_mreg_t [36:0] dio_pad_sleep_status; // [315:279] - pinmux_reg2hw_dio_pad_sleep_en_mreg_t [36:0] dio_pad_sleep_en; // [278:242] - pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [36:0] dio_pad_sleep_mode; // [241:168] + pinmux_reg2hw_alert_test_reg_t alert_test; // [3180:3179] + pinmux_reg2hw_mio_periph_insel_mreg_t [56:0] mio_periph_insel; // [3178:2837] + pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [2836:2508] + pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [2507:1474] + pinmux_reg2hw_dio_pad_attr_mreg_t [42:0] dio_pad_attr; // [1473:528] + pinmux_reg2hw_mio_pad_sleep_status_mreg_t [46:0] mio_pad_sleep_status; // [527:481] + pinmux_reg2hw_mio_pad_sleep_en_mreg_t [46:0] mio_pad_sleep_en; // [480:434] + pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [46:0] mio_pad_sleep_mode; // [433:340] + pinmux_reg2hw_dio_pad_sleep_status_mreg_t [42:0] dio_pad_sleep_status; // [339:297] + pinmux_reg2hw_dio_pad_sleep_en_mreg_t [42:0] dio_pad_sleep_en; // [296:254] + pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [42:0] dio_pad_sleep_mode; // [253:168] pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [167:160] pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [159:120] pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [119:56] @@ -263,10 +263,10 @@ // HW -> register type typedef struct packed { - pinmux_hw2reg_mio_pad_attr_mreg_t [52:0] mio_pad_attr; // [1365:677] - pinmux_hw2reg_dio_pad_attr_mreg_t [36:0] dio_pad_attr; // [676:196] - pinmux_hw2reg_mio_pad_sleep_status_mreg_t [52:0] mio_pad_sleep_status; // [195:90] - pinmux_hw2reg_dio_pad_sleep_status_mreg_t [36:0] dio_pad_sleep_status; // [89:16] + pinmux_hw2reg_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1365:755] + pinmux_hw2reg_dio_pad_attr_mreg_t [42:0] dio_pad_attr; // [754:196] + pinmux_hw2reg_mio_pad_sleep_status_mreg_t [46:0] mio_pad_sleep_status; // [195:102] + pinmux_hw2reg_dio_pad_sleep_status_mreg_t [42:0] dio_pad_sleep_status; // [101:16] pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [15:0] } pinmux_hw2reg_t; @@ -329,666 +329,652 @@ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h dc; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET = 12'h e0; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET = 12'h e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET = 12'h e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h 100; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 104; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 108; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 10c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 110; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 114; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 118; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 11c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 120; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 124; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 128; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 12c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 130; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 134; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 138; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 13c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 140; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 144; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 148; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 14c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 150; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 154; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 158; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 15c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 160; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 164; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 168; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 16c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 170; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 174; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 178; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 17c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 180; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 184; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 188; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 18c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 190; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 194; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 198; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 19c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 1a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_57_OFFSET = 12'h 1d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 200; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 204; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 208; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 20c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 210; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 214; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 218; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 21c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 220; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 224; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 228; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 22c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 230; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 234; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 238; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 23c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 240; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_47_OFFSET = 12'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_48_OFFSET = 12'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_49_OFFSET = 12'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_50_OFFSET = 12'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_51_OFFSET = 12'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_52_OFFSET = 12'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 304; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 308; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 30c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 310; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 314; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 318; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 31c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 320; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 324; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 328; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 32c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 330; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 334; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 338; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 33c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 340; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 344; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 348; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 34c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 350; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 354; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 358; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 35c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 360; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_47_OFFSET = 12'h 364; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_48_OFFSET = 12'h 368; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_49_OFFSET = 12'h 36c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_50_OFFSET = 12'h 370; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_51_OFFSET = 12'h 374; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_52_OFFSET = 12'h 378; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 37c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 380; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 384; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 388; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 38c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 390; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 394; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 398; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 39c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 400; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 404; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 408; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 40c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 410; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 414; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 418; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 41c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 420; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 424; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 428; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 42c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 430; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 434; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_47_OFFSET = 12'h 438; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_48_OFFSET = 12'h 43c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_49_OFFSET = 12'h 440; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_50_OFFSET = 12'h 444; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_51_OFFSET = 12'h 448; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_52_OFFSET = 12'h 44c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 450; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 454; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 458; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 45c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 460; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 464; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 468; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 46c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 470; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 474; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 478; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 47c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 480; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 484; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 488; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 48c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 490; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 494; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 498; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 49c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 4a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 4a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 4a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 4ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 4b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 4b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 4b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 4bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 4c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 4c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 4c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 4cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 4d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 4d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 4d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 4dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 4e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 4e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 4e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 4ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 500; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 504; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 508; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_47_OFFSET = 12'h 50c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_48_OFFSET = 12'h 510; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_49_OFFSET = 12'h 514; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_50_OFFSET = 12'h 518; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_51_OFFSET = 12'h 51c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_52_OFFSET = 12'h 520; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 524; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 528; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 52c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 530; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 534; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 538; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 53c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 540; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 544; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 548; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 54c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 550; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 554; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 558; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 55c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 560; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 564; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 568; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 56c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 570; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 574; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 578; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 57c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 580; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 584; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 588; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 58c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 590; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 594; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 598; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 59c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 5a0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 5a4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 5a8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 5ac; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 5b0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 5b4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 5b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 5bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 5c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 5c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 5c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 5cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 5d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 5d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 5d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 5dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 5e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 5e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 5e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 5ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 5f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 5f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 12'h 5f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 12'h 5fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 12'h 600; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 12'h 604; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 12'h 608; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 12'h 60c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 12'h 610; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_23_OFFSET = 12'h 614; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_24_OFFSET = 12'h 618; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_25_OFFSET = 12'h 61c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_26_OFFSET = 12'h 620; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_27_OFFSET = 12'h 624; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_28_OFFSET = 12'h 628; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_29_OFFSET = 12'h 62c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_30_OFFSET = 12'h 630; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_31_OFFSET = 12'h 634; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_32_OFFSET = 12'h 638; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_33_OFFSET = 12'h 63c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_34_OFFSET = 12'h 640; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_35_OFFSET = 12'h 644; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_36_OFFSET = 12'h 648; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 64c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 650; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 654; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 658; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 65c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 660; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 664; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 668; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 66c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 670; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 674; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 678; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 67c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 680; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 684; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 688; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 68c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 690; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 694; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 698; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 69c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 6a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 6a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 6a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 6ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 6b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 6b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 6b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 6bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 6c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 6c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 6c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 6cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 6d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 6d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 6d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 6dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 6e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 6e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 6e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 6ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 6f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 6f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 6f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 6fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 700; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 704; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 708; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 70c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_47_OFFSET = 12'h 710; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_48_OFFSET = 12'h 714; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_49_OFFSET = 12'h 718; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_50_OFFSET = 12'h 71c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_51_OFFSET = 12'h 720; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_52_OFFSET = 12'h 724; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 728; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 72c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 730; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 734; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 738; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 73c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 740; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 744; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 748; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 74c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 750; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 754; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 758; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 75c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 760; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 764; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 768; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 76c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 770; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 774; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 778; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 77c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 780; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 784; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 788; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 78c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 790; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 794; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 798; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 79c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 7a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 7a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 7a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 7ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 7b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 7b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 7b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 7bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 7c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 7c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 7c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 7cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 7d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 7d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 7d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 7dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 7e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_47_OFFSET = 12'h 7e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_48_OFFSET = 12'h 7e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_49_OFFSET = 12'h 7ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_50_OFFSET = 12'h 7f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_51_OFFSET = 12'h 7f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_52_OFFSET = 12'h 7f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 7fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 800; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 804; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 808; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 80c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 810; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 814; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 818; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 81c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 820; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 824; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 828; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 82c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 830; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 834; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 838; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 83c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 840; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 844; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 848; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 84c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 850; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 854; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 858; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 85c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 860; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 864; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 868; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 86c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 870; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 874; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 878; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 87c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 880; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 884; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 888; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 88c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 890; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 894; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 898; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 89c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 8a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 8a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 8a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 8ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 8b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 8b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_47_OFFSET = 12'h 8b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_48_OFFSET = 12'h 8bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_49_OFFSET = 12'h 8c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_50_OFFSET = 12'h 8c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_51_OFFSET = 12'h 8c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_52_OFFSET = 12'h 8cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 8d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 8d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 8d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 8dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 8e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 8e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 8e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 8ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 8f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 8f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 8f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 8fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 900; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 904; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 908; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 90c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 910; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 914; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 918; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 91c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 920; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 924; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 928; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 92c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 930; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 934; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 938; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 93c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 940; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 944; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 948; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 94c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 950; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 954; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 958; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 95c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 960; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 964; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 968; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 96c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 970; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 974; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 978; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 97c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 980; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 984; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 988; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 98c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 990; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 994; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 998; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 99c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 9a0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 9a4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 9a8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 12'h 9ac; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 12'h 9b0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 12'h 9b4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 12'h 9b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 12'h 9bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 12'h 9c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 12'h 9c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET = 12'h 9c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET = 12'h 9cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET = 12'h 9d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET = 12'h 9d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET = 12'h 9d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET = 12'h 9dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET = 12'h 9e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET = 12'h 9e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET = 12'h 9e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET = 12'h 9ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET = 12'h 9f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET = 12'h 9f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET = 12'h 9f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET = 12'h 9fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h a00; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h a04; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h a08; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h a0c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h a10; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h a14; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h a18; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h a1c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h a20; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h a24; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h a28; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h a2c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h a30; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h a34; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h a38; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h a3c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 12'h a40; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 12'h a44; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 12'h a48; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 12'h a4c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 12'h a50; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 12'h a54; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 12'h a58; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET = 12'h a5c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET = 12'h a60; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET = 12'h a64; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET = 12'h a68; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET = 12'h a6c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET = 12'h a70; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET = 12'h a74; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET = 12'h a78; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET = 12'h a7c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET = 12'h a80; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET = 12'h a84; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET = 12'h a88; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET = 12'h a8c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET = 12'h a90; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h a94; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h a98; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h a9c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h aa0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h aa4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h aa8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h aac; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h ab0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h ab4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h ab8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h abc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h ac0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h ac4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h ac8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h acc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h ad0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h ad4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h ad8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h adc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h ae0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h ae4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h ae8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h aec; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h af0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h af4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h af8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h afc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h b00; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h b04; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h b08; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h b0c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h b10; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h b14; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h b18; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h b1c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h b20; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h b24; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h b28; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h b2c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h b30; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h b34; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 100; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 104; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 108; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 10c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 110; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 114; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 118; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 11c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 120; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 124; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 128; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 12c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 130; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 134; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 138; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 13c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 140; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 144; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 148; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 14c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 150; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 154; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 158; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 15c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 160; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 164; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 168; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 16c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 170; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 174; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 178; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 17c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 180; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 184; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 188; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 18c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 190; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 194; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 198; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 19c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 200; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 204; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 208; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 20c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 210; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 214; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 218; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 21c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 220; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 224; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 228; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 22c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 230; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 234; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 238; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 23c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 240; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 244; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 304; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 308; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 30c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 310; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 314; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 318; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 31c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 320; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 324; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 408; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 40c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 410; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 414; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 418; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 41c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 420; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 424; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 42c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 430; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 434; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 438; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 43c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 440; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 444; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 448; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 44c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 450; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 454; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 458; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 45c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 464; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 468; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 46c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 470; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 474; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 500; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 504; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 538; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 53c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 548; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 54c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 550; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 554; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 558; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 55c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 560; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 564; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 568; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 56c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 570; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 574; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 578; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 57c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 580; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 584; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 588; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 58c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 590; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 594; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 598; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 59c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 12'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 12'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 12'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 12'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 12'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 12'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 12'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_23_OFFSET = 12'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_24_OFFSET = 12'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_25_OFFSET = 12'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_26_OFFSET = 12'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_27_OFFSET = 12'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_28_OFFSET = 12'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_29_OFFSET = 12'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_30_OFFSET = 12'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_31_OFFSET = 12'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_32_OFFSET = 12'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_33_OFFSET = 12'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_34_OFFSET = 12'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_35_OFFSET = 12'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_36_OFFSET = 12'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_37_OFFSET = 12'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_38_OFFSET = 12'h 600; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_39_OFFSET = 12'h 604; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_40_OFFSET = 12'h 608; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_41_OFFSET = 12'h 60c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_42_OFFSET = 12'h 610; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 614; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 618; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 61c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 620; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 624; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 628; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 62c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 630; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 634; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 638; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 63c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 640; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 644; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 648; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 64c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 650; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 654; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 658; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 65c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 660; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 664; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 668; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 66c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 670; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 674; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 678; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 67c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 680; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 684; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 688; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 68c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 690; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 694; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 698; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 69c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 700; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 704; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 708; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 70c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 710; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 714; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 718; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 71c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 720; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 724; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 728; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 72c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 730; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 734; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 738; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 73c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 740; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 744; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 748; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 74c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 750; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 754; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 758; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 75c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 760; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 764; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 768; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 76c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 770; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 774; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 778; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 77c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 780; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 784; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 788; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 78c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 790; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 794; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 798; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 79c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 7d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 7dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 7e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 7e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 7e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 7ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 7f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 7f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 7f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 7fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 800; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 804; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 808; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 80c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 810; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 814; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 818; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 81c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 820; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 824; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 828; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 82c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 830; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 834; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 838; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 83c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 840; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 844; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 848; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 84c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 850; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 854; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 858; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 85c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 860; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 864; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 868; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 86c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 870; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 874; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 878; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 87c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 880; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 884; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 888; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 88c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 890; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 894; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 898; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 89c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 8a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 8a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 8a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 8ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 8b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 8b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 8b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 8bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 8c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 8c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 8c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 8cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 8d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 8d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 8d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 8dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 8e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 8e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 8e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 8ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 8f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 8f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 8f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 8fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 900; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 904; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 908; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 90c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 910; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 914; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 918; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 91c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 920; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 924; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 928; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 92c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 930; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 934; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 938; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 93c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 940; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 12'h 944; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 12'h 948; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 12'h 94c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 12'h 950; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 12'h 954; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 12'h 958; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 12'h 95c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET = 12'h 960; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET = 12'h 964; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET = 12'h 968; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET = 12'h 96c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET = 12'h 970; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET = 12'h 974; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET = 12'h 978; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET = 12'h 97c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET = 12'h 980; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET = 12'h 984; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET = 12'h 988; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET = 12'h 98c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET = 12'h 990; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET = 12'h 994; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_37_OFFSET = 12'h 998; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_38_OFFSET = 12'h 99c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_39_OFFSET = 12'h 9a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_40_OFFSET = 12'h 9a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_41_OFFSET = 12'h 9a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_42_OFFSET = 12'h 9ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 9b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 9b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 9b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 9bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 9c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 9c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 9c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 9cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 9d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 9d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 9d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 9dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 9e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 9e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 9e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 9ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 9f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 9f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 9f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 9fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 12'h a00; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 12'h a04; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 12'h a08; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET = 12'h a0c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET = 12'h a10; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET = 12'h a14; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET = 12'h a18; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET = 12'h a1c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET = 12'h a20; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET = 12'h a24; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET = 12'h a28; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET = 12'h a2c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET = 12'h a30; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET = 12'h a34; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET = 12'h a38; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET = 12'h a3c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET = 12'h a40; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_37_OFFSET = 12'h a44; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_38_OFFSET = 12'h a48; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_39_OFFSET = 12'h a4c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_40_OFFSET = 12'h a50; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_41_OFFSET = 12'h a54; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_42_OFFSET = 12'h a58; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h a5c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h a60; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h a64; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h a68; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h a6c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h a70; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h a74; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h a78; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h a7c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h a80; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h a84; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h a88; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h a8c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h a90; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h a94; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h a98; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h a9c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h aa0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h aa4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h aa8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h aac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h ab0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h ab4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h ab8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h abc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h ac0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h ac4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h ac8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h acc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h ad0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h ad4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h ad8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h adc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h ae0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h ae4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h ae8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h aec; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h af0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h af4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h af8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h afc; // Reset values for hwext registers and their fields parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; @@ -1463,66 +1449,6 @@ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_OD_EN_46_RESVAL = 1'h 0; parameter logic [1:0] PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_RESVAL = 2'h 0; parameter logic [3:0] PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_RESVAL = 4'h 0; - parameter logic [23:0] PINMUX_MIO_PAD_ATTR_47_RESVAL = 24'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_INVERT_47_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_PULL_EN_47_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_PULL_SELECT_47_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_KEEPER_EN_47_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_SCHMITT_EN_47_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_OD_EN_47_RESVAL = 1'h 0; - parameter logic [1:0] PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_RESVAL = 2'h 0; - parameter logic [3:0] PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_RESVAL = 4'h 0; - parameter logic [23:0] PINMUX_MIO_PAD_ATTR_48_RESVAL = 24'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_INVERT_48_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_PULL_EN_48_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_PULL_SELECT_48_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_KEEPER_EN_48_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_SCHMITT_EN_48_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_OD_EN_48_RESVAL = 1'h 0; - parameter logic [1:0] PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_RESVAL = 2'h 0; - parameter logic [3:0] PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_RESVAL = 4'h 0; - parameter logic [23:0] PINMUX_MIO_PAD_ATTR_49_RESVAL = 24'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_INVERT_49_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_PULL_EN_49_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_PULL_SELECT_49_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_KEEPER_EN_49_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_SCHMITT_EN_49_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_OD_EN_49_RESVAL = 1'h 0; - parameter logic [1:0] PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_RESVAL = 2'h 0; - parameter logic [3:0] PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_RESVAL = 4'h 0; - parameter logic [23:0] PINMUX_MIO_PAD_ATTR_50_RESVAL = 24'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_INVERT_50_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_PULL_EN_50_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_PULL_SELECT_50_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_KEEPER_EN_50_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_SCHMITT_EN_50_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_OD_EN_50_RESVAL = 1'h 0; - parameter logic [1:0] PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_RESVAL = 2'h 0; - parameter logic [3:0] PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_RESVAL = 4'h 0; - parameter logic [23:0] PINMUX_MIO_PAD_ATTR_51_RESVAL = 24'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_INVERT_51_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_PULL_EN_51_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_PULL_SELECT_51_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_KEEPER_EN_51_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_SCHMITT_EN_51_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_OD_EN_51_RESVAL = 1'h 0; - parameter logic [1:0] PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_RESVAL = 2'h 0; - parameter logic [3:0] PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_RESVAL = 4'h 0; - parameter logic [23:0] PINMUX_MIO_PAD_ATTR_52_RESVAL = 24'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_INVERT_52_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_PULL_EN_52_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_PULL_SELECT_52_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_KEEPER_EN_52_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_SCHMITT_EN_52_RESVAL = 1'h 0; - parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_OD_EN_52_RESVAL = 1'h 0; - parameter logic [1:0] PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_RESVAL = 2'h 0; - parameter logic [3:0] PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_RESVAL = 4'h 0; parameter logic [23:0] PINMUX_DIO_PAD_ATTR_0_RESVAL = 24'h 0; parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0; parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0; @@ -1893,6 +1819,66 @@ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_OD_EN_36_RESVAL = 1'h 0; parameter logic [1:0] PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_RESVAL = 2'h 0; parameter logic [3:0] PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_37_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_INVERT_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_PULL_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_PULL_SELECT_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_KEEPER_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_SCHMITT_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_OD_EN_37_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_38_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_INVERT_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_PULL_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_PULL_SELECT_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_KEEPER_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_SCHMITT_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_OD_EN_38_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_39_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_INVERT_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_PULL_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_PULL_SELECT_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_KEEPER_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_SCHMITT_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_OD_EN_39_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_40_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_INVERT_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_PULL_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_PULL_SELECT_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_KEEPER_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_SCHMITT_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_OD_EN_40_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_41_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_INVERT_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_PULL_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_PULL_SELECT_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_KEEPER_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_SCHMITT_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_OD_EN_41_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_42_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_INVERT_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_PULL_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_PULL_SELECT_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_KEEPER_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_SCHMITT_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_OD_EN_42_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_RESVAL = 4'h 0; // Register index typedef enum int { @@ -1954,7 +1940,6 @@ PINMUX_MIO_PERIPH_INSEL_REGWEN_54, PINMUX_MIO_PERIPH_INSEL_REGWEN_55, PINMUX_MIO_PERIPH_INSEL_REGWEN_56, - PINMUX_MIO_PERIPH_INSEL_REGWEN_57, PINMUX_MIO_PERIPH_INSEL_0, PINMUX_MIO_PERIPH_INSEL_1, PINMUX_MIO_PERIPH_INSEL_2, @@ -2012,7 +1997,6 @@ PINMUX_MIO_PERIPH_INSEL_54, PINMUX_MIO_PERIPH_INSEL_55, PINMUX_MIO_PERIPH_INSEL_56, - PINMUX_MIO_PERIPH_INSEL_57, PINMUX_MIO_OUTSEL_REGWEN_0, PINMUX_MIO_OUTSEL_REGWEN_1, PINMUX_MIO_OUTSEL_REGWEN_2, @@ -2060,12 +2044,6 @@ PINMUX_MIO_OUTSEL_REGWEN_44, PINMUX_MIO_OUTSEL_REGWEN_45, PINMUX_MIO_OUTSEL_REGWEN_46, - PINMUX_MIO_OUTSEL_REGWEN_47, - PINMUX_MIO_OUTSEL_REGWEN_48, - PINMUX_MIO_OUTSEL_REGWEN_49, - PINMUX_MIO_OUTSEL_REGWEN_50, - PINMUX_MIO_OUTSEL_REGWEN_51, - PINMUX_MIO_OUTSEL_REGWEN_52, PINMUX_MIO_OUTSEL_0, PINMUX_MIO_OUTSEL_1, PINMUX_MIO_OUTSEL_2, @@ -2113,12 +2091,6 @@ PINMUX_MIO_OUTSEL_44, PINMUX_MIO_OUTSEL_45, PINMUX_MIO_OUTSEL_46, - PINMUX_MIO_OUTSEL_47, - PINMUX_MIO_OUTSEL_48, - PINMUX_MIO_OUTSEL_49, - PINMUX_MIO_OUTSEL_50, - PINMUX_MIO_OUTSEL_51, - PINMUX_MIO_OUTSEL_52, PINMUX_MIO_PAD_ATTR_REGWEN_0, PINMUX_MIO_PAD_ATTR_REGWEN_1, PINMUX_MIO_PAD_ATTR_REGWEN_2, @@ -2166,12 +2138,6 @@ PINMUX_MIO_PAD_ATTR_REGWEN_44, PINMUX_MIO_PAD_ATTR_REGWEN_45, PINMUX_MIO_PAD_ATTR_REGWEN_46, - PINMUX_MIO_PAD_ATTR_REGWEN_47, - PINMUX_MIO_PAD_ATTR_REGWEN_48, - PINMUX_MIO_PAD_ATTR_REGWEN_49, - PINMUX_MIO_PAD_ATTR_REGWEN_50, - PINMUX_MIO_PAD_ATTR_REGWEN_51, - PINMUX_MIO_PAD_ATTR_REGWEN_52, PINMUX_MIO_PAD_ATTR_0, PINMUX_MIO_PAD_ATTR_1, PINMUX_MIO_PAD_ATTR_2, @@ -2219,12 +2185,6 @@ PINMUX_MIO_PAD_ATTR_44, PINMUX_MIO_PAD_ATTR_45, PINMUX_MIO_PAD_ATTR_46, - PINMUX_MIO_PAD_ATTR_47, - PINMUX_MIO_PAD_ATTR_48, - PINMUX_MIO_PAD_ATTR_49, - PINMUX_MIO_PAD_ATTR_50, - PINMUX_MIO_PAD_ATTR_51, - PINMUX_MIO_PAD_ATTR_52, PINMUX_DIO_PAD_ATTR_REGWEN_0, PINMUX_DIO_PAD_ATTR_REGWEN_1, PINMUX_DIO_PAD_ATTR_REGWEN_2, @@ -2262,6 +2222,12 @@ PINMUX_DIO_PAD_ATTR_REGWEN_34, PINMUX_DIO_PAD_ATTR_REGWEN_35, PINMUX_DIO_PAD_ATTR_REGWEN_36, + PINMUX_DIO_PAD_ATTR_REGWEN_37, + PINMUX_DIO_PAD_ATTR_REGWEN_38, + PINMUX_DIO_PAD_ATTR_REGWEN_39, + PINMUX_DIO_PAD_ATTR_REGWEN_40, + PINMUX_DIO_PAD_ATTR_REGWEN_41, + PINMUX_DIO_PAD_ATTR_REGWEN_42, PINMUX_DIO_PAD_ATTR_0, PINMUX_DIO_PAD_ATTR_1, PINMUX_DIO_PAD_ATTR_2, @@ -2299,6 +2265,12 @@ PINMUX_DIO_PAD_ATTR_34, PINMUX_DIO_PAD_ATTR_35, PINMUX_DIO_PAD_ATTR_36, + PINMUX_DIO_PAD_ATTR_37, + PINMUX_DIO_PAD_ATTR_38, + PINMUX_DIO_PAD_ATTR_39, + PINMUX_DIO_PAD_ATTR_40, + PINMUX_DIO_PAD_ATTR_41, + PINMUX_DIO_PAD_ATTR_42, PINMUX_MIO_PAD_SLEEP_STATUS_0, PINMUX_MIO_PAD_SLEEP_STATUS_1, PINMUX_MIO_PAD_SLEEP_REGWEN_0, @@ -2348,12 +2320,6 @@ PINMUX_MIO_PAD_SLEEP_REGWEN_44, PINMUX_MIO_PAD_SLEEP_REGWEN_45, PINMUX_MIO_PAD_SLEEP_REGWEN_46, - PINMUX_MIO_PAD_SLEEP_REGWEN_47, - PINMUX_MIO_PAD_SLEEP_REGWEN_48, - PINMUX_MIO_PAD_SLEEP_REGWEN_49, - PINMUX_MIO_PAD_SLEEP_REGWEN_50, - PINMUX_MIO_PAD_SLEEP_REGWEN_51, - PINMUX_MIO_PAD_SLEEP_REGWEN_52, PINMUX_MIO_PAD_SLEEP_EN_0, PINMUX_MIO_PAD_SLEEP_EN_1, PINMUX_MIO_PAD_SLEEP_EN_2, @@ -2401,12 +2367,6 @@ PINMUX_MIO_PAD_SLEEP_EN_44, PINMUX_MIO_PAD_SLEEP_EN_45, PINMUX_MIO_PAD_SLEEP_EN_46, - PINMUX_MIO_PAD_SLEEP_EN_47, - PINMUX_MIO_PAD_SLEEP_EN_48, - PINMUX_MIO_PAD_SLEEP_EN_49, - PINMUX_MIO_PAD_SLEEP_EN_50, - PINMUX_MIO_PAD_SLEEP_EN_51, - PINMUX_MIO_PAD_SLEEP_EN_52, PINMUX_MIO_PAD_SLEEP_MODE_0, PINMUX_MIO_PAD_SLEEP_MODE_1, PINMUX_MIO_PAD_SLEEP_MODE_2, @@ -2454,12 +2414,6 @@ PINMUX_MIO_PAD_SLEEP_MODE_44, PINMUX_MIO_PAD_SLEEP_MODE_45, PINMUX_MIO_PAD_SLEEP_MODE_46, - PINMUX_MIO_PAD_SLEEP_MODE_47, - PINMUX_MIO_PAD_SLEEP_MODE_48, - PINMUX_MIO_PAD_SLEEP_MODE_49, - PINMUX_MIO_PAD_SLEEP_MODE_50, - PINMUX_MIO_PAD_SLEEP_MODE_51, - PINMUX_MIO_PAD_SLEEP_MODE_52, PINMUX_DIO_PAD_SLEEP_STATUS_0, PINMUX_DIO_PAD_SLEEP_STATUS_1, PINMUX_DIO_PAD_SLEEP_REGWEN_0, @@ -2499,6 +2453,12 @@ PINMUX_DIO_PAD_SLEEP_REGWEN_34, PINMUX_DIO_PAD_SLEEP_REGWEN_35, PINMUX_DIO_PAD_SLEEP_REGWEN_36, + PINMUX_DIO_PAD_SLEEP_REGWEN_37, + PINMUX_DIO_PAD_SLEEP_REGWEN_38, + PINMUX_DIO_PAD_SLEEP_REGWEN_39, + PINMUX_DIO_PAD_SLEEP_REGWEN_40, + PINMUX_DIO_PAD_SLEEP_REGWEN_41, + PINMUX_DIO_PAD_SLEEP_REGWEN_42, PINMUX_DIO_PAD_SLEEP_EN_0, PINMUX_DIO_PAD_SLEEP_EN_1, PINMUX_DIO_PAD_SLEEP_EN_2, @@ -2536,6 +2496,12 @@ PINMUX_DIO_PAD_SLEEP_EN_34, PINMUX_DIO_PAD_SLEEP_EN_35, PINMUX_DIO_PAD_SLEEP_EN_36, + PINMUX_DIO_PAD_SLEEP_EN_37, + PINMUX_DIO_PAD_SLEEP_EN_38, + PINMUX_DIO_PAD_SLEEP_EN_39, + PINMUX_DIO_PAD_SLEEP_EN_40, + PINMUX_DIO_PAD_SLEEP_EN_41, + PINMUX_DIO_PAD_SLEEP_EN_42, PINMUX_DIO_PAD_SLEEP_MODE_0, PINMUX_DIO_PAD_SLEEP_MODE_1, PINMUX_DIO_PAD_SLEEP_MODE_2, @@ -2573,6 +2539,12 @@ PINMUX_DIO_PAD_SLEEP_MODE_34, PINMUX_DIO_PAD_SLEEP_MODE_35, PINMUX_DIO_PAD_SLEEP_MODE_36, + PINMUX_DIO_PAD_SLEEP_MODE_37, + PINMUX_DIO_PAD_SLEEP_MODE_38, + PINMUX_DIO_PAD_SLEEP_MODE_39, + PINMUX_DIO_PAD_SLEEP_MODE_40, + PINMUX_DIO_PAD_SLEEP_MODE_41, + PINMUX_DIO_PAD_SLEEP_MODE_42, PINMUX_WKUP_DETECTOR_REGWEN_0, PINMUX_WKUP_DETECTOR_REGWEN_1, PINMUX_WKUP_DETECTOR_REGWEN_2, @@ -2617,7 +2589,7 @@ } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [718] = '{ + parameter logic [3:0] PINMUX_PERMIT [704] = '{ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 @@ -2676,666 +2648,652 @@ 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_REGWEN_54 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_REGWEN_55 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_REGWEN_56 - 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_REGWEN_57 - 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_0 - 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_1 - 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_2 - 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_3 - 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_4 - 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_5 - 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_6 - 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_7 - 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_8 - 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_9 - 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_10 - 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_11 - 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_12 - 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_13 - 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_14 - 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_15 - 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_16 - 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_17 - 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_18 - 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_19 - 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_20 - 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_21 - 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_22 - 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_23 - 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_24 - 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_25 - 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_26 - 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_27 - 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_28 - 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_29 - 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_30 - 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_31 - 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_32 - 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_33 - 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_34 - 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_35 - 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_36 - 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_37 - 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_38 - 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_39 - 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_40 - 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_41 - 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_42 - 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_43 - 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_44 - 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_45 - 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_46 - 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_47 - 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_48 - 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_49 - 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_50 - 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_51 - 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_52 - 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_53 - 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_54 - 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_55 - 4'b 0001, // index[115] PINMUX_MIO_PERIPH_INSEL_56 - 4'b 0001, // index[116] PINMUX_MIO_PERIPH_INSEL_57 - 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_0 - 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_1 - 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_2 - 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_3 - 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_4 - 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_5 - 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_6 - 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_7 - 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_8 - 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_9 - 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_10 - 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_11 - 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_12 - 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_13 - 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_14 - 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_15 - 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_16 - 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_17 - 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_18 - 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_19 - 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_20 - 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_21 - 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_22 - 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_23 - 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_24 - 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_25 - 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_26 - 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_27 - 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_28 - 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_29 - 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_30 - 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_31 - 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_32 - 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_33 - 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_34 - 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_35 - 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_36 - 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_37 - 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_38 - 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_39 - 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_40 - 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_41 - 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_42 - 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_43 - 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_44 - 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_REGWEN_45 - 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_REGWEN_46 - 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_REGWEN_47 - 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_REGWEN_48 - 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_REGWEN_49 - 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_REGWEN_50 - 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_REGWEN_51 - 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_REGWEN_52 - 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_0 - 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_1 - 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_2 - 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_3 - 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_4 - 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_5 - 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_6 - 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_7 - 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_8 - 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_9 - 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_10 - 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_11 - 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_12 - 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_13 - 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_14 - 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_15 - 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_16 - 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_17 - 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_18 - 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_19 - 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_20 - 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_21 - 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_22 - 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_23 - 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_24 - 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_25 - 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_26 - 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_27 - 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_28 - 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_29 - 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_30 - 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_32 - 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_33 - 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_34 - 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_35 - 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_36 - 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_37 - 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_38 - 4'b 0001, // index[209] PINMUX_MIO_OUTSEL_39 - 4'b 0001, // index[210] PINMUX_MIO_OUTSEL_40 - 4'b 0001, // index[211] PINMUX_MIO_OUTSEL_41 - 4'b 0001, // index[212] PINMUX_MIO_OUTSEL_42 - 4'b 0001, // index[213] PINMUX_MIO_OUTSEL_43 - 4'b 0001, // index[214] PINMUX_MIO_OUTSEL_44 - 4'b 0001, // index[215] PINMUX_MIO_OUTSEL_45 - 4'b 0001, // index[216] PINMUX_MIO_OUTSEL_46 - 4'b 0001, // index[217] PINMUX_MIO_OUTSEL_47 - 4'b 0001, // index[218] PINMUX_MIO_OUTSEL_48 - 4'b 0001, // index[219] PINMUX_MIO_OUTSEL_49 - 4'b 0001, // index[220] PINMUX_MIO_OUTSEL_50 - 4'b 0001, // index[221] PINMUX_MIO_OUTSEL_51 - 4'b 0001, // index[222] PINMUX_MIO_OUTSEL_52 - 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_15 - 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_16 - 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_17 - 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_18 - 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_19 - 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_20 - 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_21 - 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_22 - 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_23 - 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_24 - 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_25 - 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_26 - 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_27 - 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_28 - 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_29 - 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_30 - 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_31 - 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_32 - 4'b 0001, // index[256] PINMUX_MIO_PAD_ATTR_REGWEN_33 - 4'b 0001, // index[257] PINMUX_MIO_PAD_ATTR_REGWEN_34 - 4'b 0001, // index[258] PINMUX_MIO_PAD_ATTR_REGWEN_35 - 4'b 0001, // index[259] PINMUX_MIO_PAD_ATTR_REGWEN_36 - 4'b 0001, // index[260] PINMUX_MIO_PAD_ATTR_REGWEN_37 - 4'b 0001, // index[261] PINMUX_MIO_PAD_ATTR_REGWEN_38 - 4'b 0001, // index[262] PINMUX_MIO_PAD_ATTR_REGWEN_39 - 4'b 0001, // index[263] PINMUX_MIO_PAD_ATTR_REGWEN_40 - 4'b 0001, // index[264] PINMUX_MIO_PAD_ATTR_REGWEN_41 - 4'b 0001, // index[265] PINMUX_MIO_PAD_ATTR_REGWEN_42 - 4'b 0001, // index[266] PINMUX_MIO_PAD_ATTR_REGWEN_43 - 4'b 0001, // index[267] PINMUX_MIO_PAD_ATTR_REGWEN_44 - 4'b 0001, // index[268] PINMUX_MIO_PAD_ATTR_REGWEN_45 - 4'b 0001, // index[269] PINMUX_MIO_PAD_ATTR_REGWEN_46 - 4'b 0001, // index[270] PINMUX_MIO_PAD_ATTR_REGWEN_47 - 4'b 0001, // index[271] PINMUX_MIO_PAD_ATTR_REGWEN_48 - 4'b 0001, // index[272] PINMUX_MIO_PAD_ATTR_REGWEN_49 - 4'b 0001, // index[273] PINMUX_MIO_PAD_ATTR_REGWEN_50 - 4'b 0001, // index[274] PINMUX_MIO_PAD_ATTR_REGWEN_51 - 4'b 0001, // index[275] PINMUX_MIO_PAD_ATTR_REGWEN_52 - 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_0 - 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_1 - 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_2 - 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_3 - 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_4 - 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_5 - 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_6 - 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_7 - 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_8 - 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_9 - 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_10 - 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_11 - 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_12 - 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_13 - 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_14 - 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_15 - 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_16 - 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_17 - 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_18 - 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_19 - 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_20 - 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_21 - 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_22 - 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_23 - 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_24 - 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_25 - 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_26 - 4'b 0111, // index[303] PINMUX_MIO_PAD_ATTR_27 - 4'b 0111, // index[304] PINMUX_MIO_PAD_ATTR_28 - 4'b 0111, // index[305] PINMUX_MIO_PAD_ATTR_29 - 4'b 0111, // index[306] PINMUX_MIO_PAD_ATTR_30 - 4'b 0111, // index[307] PINMUX_MIO_PAD_ATTR_31 - 4'b 0111, // index[308] PINMUX_MIO_PAD_ATTR_32 - 4'b 0111, // index[309] PINMUX_MIO_PAD_ATTR_33 - 4'b 0111, // index[310] PINMUX_MIO_PAD_ATTR_34 - 4'b 0111, // index[311] PINMUX_MIO_PAD_ATTR_35 - 4'b 0111, // index[312] PINMUX_MIO_PAD_ATTR_36 - 4'b 0111, // index[313] PINMUX_MIO_PAD_ATTR_37 - 4'b 0111, // index[314] PINMUX_MIO_PAD_ATTR_38 - 4'b 0111, // index[315] PINMUX_MIO_PAD_ATTR_39 - 4'b 0111, // index[316] PINMUX_MIO_PAD_ATTR_40 - 4'b 0111, // index[317] PINMUX_MIO_PAD_ATTR_41 - 4'b 0111, // index[318] PINMUX_MIO_PAD_ATTR_42 - 4'b 0111, // index[319] PINMUX_MIO_PAD_ATTR_43 - 4'b 0111, // index[320] PINMUX_MIO_PAD_ATTR_44 - 4'b 0111, // index[321] PINMUX_MIO_PAD_ATTR_45 - 4'b 0111, // index[322] PINMUX_MIO_PAD_ATTR_46 - 4'b 0111, // index[323] PINMUX_MIO_PAD_ATTR_47 - 4'b 0111, // index[324] PINMUX_MIO_PAD_ATTR_48 - 4'b 0111, // index[325] PINMUX_MIO_PAD_ATTR_49 - 4'b 0111, // index[326] PINMUX_MIO_PAD_ATTR_50 - 4'b 0111, // index[327] PINMUX_MIO_PAD_ATTR_51 - 4'b 0111, // index[328] PINMUX_MIO_PAD_ATTR_52 - 4'b 0001, // index[329] PINMUX_DIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[330] PINMUX_DIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[331] PINMUX_DIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[332] PINMUX_DIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[333] PINMUX_DIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[334] PINMUX_DIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[335] PINMUX_DIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[336] PINMUX_DIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[337] PINMUX_DIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[338] PINMUX_DIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[339] PINMUX_DIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[340] PINMUX_DIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[341] PINMUX_DIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[342] PINMUX_DIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[343] PINMUX_DIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[344] PINMUX_DIO_PAD_ATTR_REGWEN_15 - 4'b 0001, // index[345] PINMUX_DIO_PAD_ATTR_REGWEN_16 - 4'b 0001, // index[346] PINMUX_DIO_PAD_ATTR_REGWEN_17 - 4'b 0001, // index[347] PINMUX_DIO_PAD_ATTR_REGWEN_18 - 4'b 0001, // index[348] PINMUX_DIO_PAD_ATTR_REGWEN_19 - 4'b 0001, // index[349] PINMUX_DIO_PAD_ATTR_REGWEN_20 - 4'b 0001, // index[350] PINMUX_DIO_PAD_ATTR_REGWEN_21 - 4'b 0001, // index[351] PINMUX_DIO_PAD_ATTR_REGWEN_22 - 4'b 0001, // index[352] PINMUX_DIO_PAD_ATTR_REGWEN_23 - 4'b 0001, // index[353] PINMUX_DIO_PAD_ATTR_REGWEN_24 - 4'b 0001, // index[354] PINMUX_DIO_PAD_ATTR_REGWEN_25 - 4'b 0001, // index[355] PINMUX_DIO_PAD_ATTR_REGWEN_26 - 4'b 0001, // index[356] PINMUX_DIO_PAD_ATTR_REGWEN_27 - 4'b 0001, // index[357] PINMUX_DIO_PAD_ATTR_REGWEN_28 - 4'b 0001, // index[358] PINMUX_DIO_PAD_ATTR_REGWEN_29 - 4'b 0001, // index[359] PINMUX_DIO_PAD_ATTR_REGWEN_30 - 4'b 0001, // index[360] PINMUX_DIO_PAD_ATTR_REGWEN_31 - 4'b 0001, // index[361] PINMUX_DIO_PAD_ATTR_REGWEN_32 - 4'b 0001, // index[362] PINMUX_DIO_PAD_ATTR_REGWEN_33 - 4'b 0001, // index[363] PINMUX_DIO_PAD_ATTR_REGWEN_34 - 4'b 0001, // index[364] PINMUX_DIO_PAD_ATTR_REGWEN_35 - 4'b 0001, // index[365] PINMUX_DIO_PAD_ATTR_REGWEN_36 - 4'b 0111, // index[366] PINMUX_DIO_PAD_ATTR_0 - 4'b 0111, // index[367] PINMUX_DIO_PAD_ATTR_1 - 4'b 0111, // index[368] PINMUX_DIO_PAD_ATTR_2 - 4'b 0111, // index[369] PINMUX_DIO_PAD_ATTR_3 - 4'b 0111, // index[370] PINMUX_DIO_PAD_ATTR_4 - 4'b 0111, // index[371] PINMUX_DIO_PAD_ATTR_5 - 4'b 0111, // index[372] PINMUX_DIO_PAD_ATTR_6 - 4'b 0111, // index[373] PINMUX_DIO_PAD_ATTR_7 - 4'b 0111, // index[374] PINMUX_DIO_PAD_ATTR_8 - 4'b 0111, // index[375] PINMUX_DIO_PAD_ATTR_9 - 4'b 0111, // index[376] PINMUX_DIO_PAD_ATTR_10 - 4'b 0111, // index[377] PINMUX_DIO_PAD_ATTR_11 - 4'b 0111, // index[378] PINMUX_DIO_PAD_ATTR_12 - 4'b 0111, // index[379] PINMUX_DIO_PAD_ATTR_13 - 4'b 0111, // index[380] PINMUX_DIO_PAD_ATTR_14 - 4'b 0111, // index[381] PINMUX_DIO_PAD_ATTR_15 - 4'b 0111, // index[382] PINMUX_DIO_PAD_ATTR_16 - 4'b 0111, // index[383] PINMUX_DIO_PAD_ATTR_17 - 4'b 0111, // index[384] PINMUX_DIO_PAD_ATTR_18 - 4'b 0111, // index[385] PINMUX_DIO_PAD_ATTR_19 - 4'b 0111, // index[386] PINMUX_DIO_PAD_ATTR_20 - 4'b 0111, // index[387] PINMUX_DIO_PAD_ATTR_21 - 4'b 0111, // index[388] PINMUX_DIO_PAD_ATTR_22 - 4'b 0111, // index[389] PINMUX_DIO_PAD_ATTR_23 - 4'b 0111, // index[390] PINMUX_DIO_PAD_ATTR_24 - 4'b 0111, // index[391] PINMUX_DIO_PAD_ATTR_25 - 4'b 0111, // index[392] PINMUX_DIO_PAD_ATTR_26 - 4'b 0111, // index[393] PINMUX_DIO_PAD_ATTR_27 - 4'b 0111, // index[394] PINMUX_DIO_PAD_ATTR_28 - 4'b 0111, // index[395] PINMUX_DIO_PAD_ATTR_29 - 4'b 0111, // index[396] PINMUX_DIO_PAD_ATTR_30 - 4'b 0111, // index[397] PINMUX_DIO_PAD_ATTR_31 - 4'b 0111, // index[398] PINMUX_DIO_PAD_ATTR_32 - 4'b 0111, // index[399] PINMUX_DIO_PAD_ATTR_33 - 4'b 0111, // index[400] PINMUX_DIO_PAD_ATTR_34 - 4'b 0111, // index[401] PINMUX_DIO_PAD_ATTR_35 - 4'b 0111, // index[402] PINMUX_DIO_PAD_ATTR_36 - 4'b 1111, // index[403] PINMUX_MIO_PAD_SLEEP_STATUS_0 - 4'b 0111, // index[404] PINMUX_MIO_PAD_SLEEP_STATUS_1 - 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_REGWEN_16 - 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_REGWEN_17 - 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_REGWEN_18 - 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_REGWEN_19 - 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_REGWEN_20 - 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_REGWEN_21 - 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_REGWEN_22 - 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_REGWEN_23 - 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_REGWEN_24 - 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_REGWEN_25 - 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_REGWEN_26 - 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_REGWEN_27 - 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_REGWEN_28 - 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_REGWEN_29 - 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_REGWEN_30 - 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_REGWEN_31 - 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_REGWEN_32 - 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_REGWEN_33 - 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_REGWEN_34 - 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_REGWEN_35 - 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_REGWEN_36 - 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_REGWEN_37 - 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_REGWEN_38 - 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_REGWEN_39 - 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_REGWEN_40 - 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_REGWEN_41 - 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_REGWEN_42 - 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_REGWEN_43 - 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_REGWEN_44 - 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_REGWEN_45 - 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_REGWEN_46 - 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_REGWEN_47 - 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_REGWEN_48 - 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_REGWEN_49 - 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_REGWEN_50 - 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_REGWEN_51 - 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_REGWEN_52 - 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_EN_16 - 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_EN_17 - 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_EN_18 - 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_EN_19 - 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_EN_20 - 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_EN_21 - 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_EN_22 - 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_EN_23 - 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_EN_24 - 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_EN_25 - 4'b 0001, // index[484] PINMUX_MIO_PAD_SLEEP_EN_26 - 4'b 0001, // index[485] PINMUX_MIO_PAD_SLEEP_EN_27 - 4'b 0001, // index[486] PINMUX_MIO_PAD_SLEEP_EN_28 - 4'b 0001, // index[487] PINMUX_MIO_PAD_SLEEP_EN_29 - 4'b 0001, // index[488] PINMUX_MIO_PAD_SLEEP_EN_30 - 4'b 0001, // index[489] PINMUX_MIO_PAD_SLEEP_EN_31 - 4'b 0001, // index[490] PINMUX_MIO_PAD_SLEEP_EN_32 - 4'b 0001, // index[491] PINMUX_MIO_PAD_SLEEP_EN_33 - 4'b 0001, // index[492] PINMUX_MIO_PAD_SLEEP_EN_34 - 4'b 0001, // index[493] PINMUX_MIO_PAD_SLEEP_EN_35 - 4'b 0001, // index[494] PINMUX_MIO_PAD_SLEEP_EN_36 - 4'b 0001, // index[495] PINMUX_MIO_PAD_SLEEP_EN_37 - 4'b 0001, // index[496] PINMUX_MIO_PAD_SLEEP_EN_38 - 4'b 0001, // index[497] PINMUX_MIO_PAD_SLEEP_EN_39 - 4'b 0001, // index[498] PINMUX_MIO_PAD_SLEEP_EN_40 - 4'b 0001, // index[499] PINMUX_MIO_PAD_SLEEP_EN_41 - 4'b 0001, // index[500] PINMUX_MIO_PAD_SLEEP_EN_42 - 4'b 0001, // index[501] PINMUX_MIO_PAD_SLEEP_EN_43 - 4'b 0001, // index[502] PINMUX_MIO_PAD_SLEEP_EN_44 - 4'b 0001, // index[503] PINMUX_MIO_PAD_SLEEP_EN_45 - 4'b 0001, // index[504] PINMUX_MIO_PAD_SLEEP_EN_46 - 4'b 0001, // index[505] PINMUX_MIO_PAD_SLEEP_EN_47 - 4'b 0001, // index[506] PINMUX_MIO_PAD_SLEEP_EN_48 - 4'b 0001, // index[507] PINMUX_MIO_PAD_SLEEP_EN_49 - 4'b 0001, // index[508] PINMUX_MIO_PAD_SLEEP_EN_50 - 4'b 0001, // index[509] PINMUX_MIO_PAD_SLEEP_EN_51 - 4'b 0001, // index[510] PINMUX_MIO_PAD_SLEEP_EN_52 - 4'b 0001, // index[511] PINMUX_MIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[512] PINMUX_MIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[513] PINMUX_MIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[514] PINMUX_MIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[515] PINMUX_MIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[516] PINMUX_MIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[517] PINMUX_MIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[518] PINMUX_MIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[519] PINMUX_MIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[520] PINMUX_MIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[521] PINMUX_MIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[522] PINMUX_MIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[523] PINMUX_MIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[524] PINMUX_MIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[525] PINMUX_MIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[526] PINMUX_MIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[527] PINMUX_MIO_PAD_SLEEP_MODE_16 - 4'b 0001, // index[528] PINMUX_MIO_PAD_SLEEP_MODE_17 - 4'b 0001, // index[529] PINMUX_MIO_PAD_SLEEP_MODE_18 - 4'b 0001, // index[530] PINMUX_MIO_PAD_SLEEP_MODE_19 - 4'b 0001, // index[531] PINMUX_MIO_PAD_SLEEP_MODE_20 - 4'b 0001, // index[532] PINMUX_MIO_PAD_SLEEP_MODE_21 - 4'b 0001, // index[533] PINMUX_MIO_PAD_SLEEP_MODE_22 - 4'b 0001, // index[534] PINMUX_MIO_PAD_SLEEP_MODE_23 - 4'b 0001, // index[535] PINMUX_MIO_PAD_SLEEP_MODE_24 - 4'b 0001, // index[536] PINMUX_MIO_PAD_SLEEP_MODE_25 - 4'b 0001, // index[537] PINMUX_MIO_PAD_SLEEP_MODE_26 - 4'b 0001, // index[538] PINMUX_MIO_PAD_SLEEP_MODE_27 - 4'b 0001, // index[539] PINMUX_MIO_PAD_SLEEP_MODE_28 - 4'b 0001, // index[540] PINMUX_MIO_PAD_SLEEP_MODE_29 - 4'b 0001, // index[541] PINMUX_MIO_PAD_SLEEP_MODE_30 - 4'b 0001, // index[542] PINMUX_MIO_PAD_SLEEP_MODE_31 - 4'b 0001, // index[543] PINMUX_MIO_PAD_SLEEP_MODE_32 - 4'b 0001, // index[544] PINMUX_MIO_PAD_SLEEP_MODE_33 - 4'b 0001, // index[545] PINMUX_MIO_PAD_SLEEP_MODE_34 - 4'b 0001, // index[546] PINMUX_MIO_PAD_SLEEP_MODE_35 - 4'b 0001, // index[547] PINMUX_MIO_PAD_SLEEP_MODE_36 - 4'b 0001, // index[548] PINMUX_MIO_PAD_SLEEP_MODE_37 - 4'b 0001, // index[549] PINMUX_MIO_PAD_SLEEP_MODE_38 - 4'b 0001, // index[550] PINMUX_MIO_PAD_SLEEP_MODE_39 - 4'b 0001, // index[551] PINMUX_MIO_PAD_SLEEP_MODE_40 - 4'b 0001, // index[552] PINMUX_MIO_PAD_SLEEP_MODE_41 - 4'b 0001, // index[553] PINMUX_MIO_PAD_SLEEP_MODE_42 - 4'b 0001, // index[554] PINMUX_MIO_PAD_SLEEP_MODE_43 - 4'b 0001, // index[555] PINMUX_MIO_PAD_SLEEP_MODE_44 - 4'b 0001, // index[556] PINMUX_MIO_PAD_SLEEP_MODE_45 - 4'b 0001, // index[557] PINMUX_MIO_PAD_SLEEP_MODE_46 - 4'b 0001, // index[558] PINMUX_MIO_PAD_SLEEP_MODE_47 - 4'b 0001, // index[559] PINMUX_MIO_PAD_SLEEP_MODE_48 - 4'b 0001, // index[560] PINMUX_MIO_PAD_SLEEP_MODE_49 - 4'b 0001, // index[561] PINMUX_MIO_PAD_SLEEP_MODE_50 - 4'b 0001, // index[562] PINMUX_MIO_PAD_SLEEP_MODE_51 - 4'b 0001, // index[563] PINMUX_MIO_PAD_SLEEP_MODE_52 - 4'b 1111, // index[564] PINMUX_DIO_PAD_SLEEP_STATUS_0 - 4'b 0001, // index[565] PINMUX_DIO_PAD_SLEEP_STATUS_1 - 4'b 0001, // index[566] PINMUX_DIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[567] PINMUX_DIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[568] PINMUX_DIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[569] PINMUX_DIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[570] PINMUX_DIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[571] PINMUX_DIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[572] PINMUX_DIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[573] PINMUX_DIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[574] PINMUX_DIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[575] PINMUX_DIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[576] PINMUX_DIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[577] PINMUX_DIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[578] PINMUX_DIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[579] PINMUX_DIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[580] PINMUX_DIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[581] PINMUX_DIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[582] PINMUX_DIO_PAD_SLEEP_REGWEN_16 - 4'b 0001, // index[583] PINMUX_DIO_PAD_SLEEP_REGWEN_17 - 4'b 0001, // index[584] PINMUX_DIO_PAD_SLEEP_REGWEN_18 - 4'b 0001, // index[585] PINMUX_DIO_PAD_SLEEP_REGWEN_19 - 4'b 0001, // index[586] PINMUX_DIO_PAD_SLEEP_REGWEN_20 - 4'b 0001, // index[587] PINMUX_DIO_PAD_SLEEP_REGWEN_21 - 4'b 0001, // index[588] PINMUX_DIO_PAD_SLEEP_REGWEN_22 - 4'b 0001, // index[589] PINMUX_DIO_PAD_SLEEP_REGWEN_23 - 4'b 0001, // index[590] PINMUX_DIO_PAD_SLEEP_REGWEN_24 - 4'b 0001, // index[591] PINMUX_DIO_PAD_SLEEP_REGWEN_25 - 4'b 0001, // index[592] PINMUX_DIO_PAD_SLEEP_REGWEN_26 - 4'b 0001, // index[593] PINMUX_DIO_PAD_SLEEP_REGWEN_27 - 4'b 0001, // index[594] PINMUX_DIO_PAD_SLEEP_REGWEN_28 - 4'b 0001, // index[595] PINMUX_DIO_PAD_SLEEP_REGWEN_29 - 4'b 0001, // index[596] PINMUX_DIO_PAD_SLEEP_REGWEN_30 - 4'b 0001, // index[597] PINMUX_DIO_PAD_SLEEP_REGWEN_31 - 4'b 0001, // index[598] PINMUX_DIO_PAD_SLEEP_REGWEN_32 - 4'b 0001, // index[599] PINMUX_DIO_PAD_SLEEP_REGWEN_33 - 4'b 0001, // index[600] PINMUX_DIO_PAD_SLEEP_REGWEN_34 - 4'b 0001, // index[601] PINMUX_DIO_PAD_SLEEP_REGWEN_35 - 4'b 0001, // index[602] PINMUX_DIO_PAD_SLEEP_REGWEN_36 - 4'b 0001, // index[603] PINMUX_DIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[604] PINMUX_DIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[605] PINMUX_DIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[606] PINMUX_DIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[607] PINMUX_DIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[608] PINMUX_DIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[609] PINMUX_DIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[610] PINMUX_DIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[611] PINMUX_DIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[612] PINMUX_DIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[613] PINMUX_DIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[614] PINMUX_DIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[615] PINMUX_DIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[616] PINMUX_DIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[617] PINMUX_DIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[618] PINMUX_DIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[619] PINMUX_DIO_PAD_SLEEP_EN_16 - 4'b 0001, // index[620] PINMUX_DIO_PAD_SLEEP_EN_17 - 4'b 0001, // index[621] PINMUX_DIO_PAD_SLEEP_EN_18 - 4'b 0001, // index[622] PINMUX_DIO_PAD_SLEEP_EN_19 - 4'b 0001, // index[623] PINMUX_DIO_PAD_SLEEP_EN_20 - 4'b 0001, // index[624] PINMUX_DIO_PAD_SLEEP_EN_21 - 4'b 0001, // index[625] PINMUX_DIO_PAD_SLEEP_EN_22 - 4'b 0001, // index[626] PINMUX_DIO_PAD_SLEEP_EN_23 - 4'b 0001, // index[627] PINMUX_DIO_PAD_SLEEP_EN_24 - 4'b 0001, // index[628] PINMUX_DIO_PAD_SLEEP_EN_25 - 4'b 0001, // index[629] PINMUX_DIO_PAD_SLEEP_EN_26 - 4'b 0001, // index[630] PINMUX_DIO_PAD_SLEEP_EN_27 - 4'b 0001, // index[631] PINMUX_DIO_PAD_SLEEP_EN_28 - 4'b 0001, // index[632] PINMUX_DIO_PAD_SLEEP_EN_29 - 4'b 0001, // index[633] PINMUX_DIO_PAD_SLEEP_EN_30 - 4'b 0001, // index[634] PINMUX_DIO_PAD_SLEEP_EN_31 - 4'b 0001, // index[635] PINMUX_DIO_PAD_SLEEP_EN_32 - 4'b 0001, // index[636] PINMUX_DIO_PAD_SLEEP_EN_33 - 4'b 0001, // index[637] PINMUX_DIO_PAD_SLEEP_EN_34 - 4'b 0001, // index[638] PINMUX_DIO_PAD_SLEEP_EN_35 - 4'b 0001, // index[639] PINMUX_DIO_PAD_SLEEP_EN_36 - 4'b 0001, // index[640] PINMUX_DIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[641] PINMUX_DIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[642] PINMUX_DIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[643] PINMUX_DIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[644] PINMUX_DIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[645] PINMUX_DIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[646] PINMUX_DIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[647] PINMUX_DIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[648] PINMUX_DIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[649] PINMUX_DIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[650] PINMUX_DIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[651] PINMUX_DIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[652] PINMUX_DIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[653] PINMUX_DIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[654] PINMUX_DIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[655] PINMUX_DIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[656] PINMUX_DIO_PAD_SLEEP_MODE_16 - 4'b 0001, // index[657] PINMUX_DIO_PAD_SLEEP_MODE_17 - 4'b 0001, // index[658] PINMUX_DIO_PAD_SLEEP_MODE_18 - 4'b 0001, // index[659] PINMUX_DIO_PAD_SLEEP_MODE_19 - 4'b 0001, // index[660] PINMUX_DIO_PAD_SLEEP_MODE_20 - 4'b 0001, // index[661] PINMUX_DIO_PAD_SLEEP_MODE_21 - 4'b 0001, // index[662] PINMUX_DIO_PAD_SLEEP_MODE_22 - 4'b 0001, // index[663] PINMUX_DIO_PAD_SLEEP_MODE_23 - 4'b 0001, // index[664] PINMUX_DIO_PAD_SLEEP_MODE_24 - 4'b 0001, // index[665] PINMUX_DIO_PAD_SLEEP_MODE_25 - 4'b 0001, // index[666] PINMUX_DIO_PAD_SLEEP_MODE_26 - 4'b 0001, // index[667] PINMUX_DIO_PAD_SLEEP_MODE_27 - 4'b 0001, // index[668] PINMUX_DIO_PAD_SLEEP_MODE_28 - 4'b 0001, // index[669] PINMUX_DIO_PAD_SLEEP_MODE_29 - 4'b 0001, // index[670] PINMUX_DIO_PAD_SLEEP_MODE_30 - 4'b 0001, // index[671] PINMUX_DIO_PAD_SLEEP_MODE_31 - 4'b 0001, // index[672] PINMUX_DIO_PAD_SLEEP_MODE_32 - 4'b 0001, // index[673] PINMUX_DIO_PAD_SLEEP_MODE_33 - 4'b 0001, // index[674] PINMUX_DIO_PAD_SLEEP_MODE_34 - 4'b 0001, // index[675] PINMUX_DIO_PAD_SLEEP_MODE_35 - 4'b 0001, // index[676] PINMUX_DIO_PAD_SLEEP_MODE_36 - 4'b 0001, // index[677] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[678] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[679] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[680] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[681] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[682] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[683] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[684] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[685] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[686] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[687] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[688] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[689] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[690] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[691] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[692] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[693] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[694] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[695] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[696] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[697] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[698] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[699] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[700] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[701] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[702] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[703] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[704] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[705] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[706] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[707] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[708] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[709] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[710] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[711] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[712] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[713] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[714] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[715] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[716] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[717] PINMUX_WKUP_CAUSE + 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_4 + 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_5 + 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_6 + 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_7 + 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_8 + 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_9 + 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_10 + 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_11 + 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_12 + 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_13 + 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_14 + 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_15 + 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_16 + 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_17 + 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_18 + 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_19 + 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_20 + 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_21 + 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_22 + 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_23 + 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_24 + 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_25 + 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_26 + 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_27 + 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_28 + 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_29 + 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_30 + 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_31 + 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_32 + 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_33 + 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_34 + 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_35 + 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_36 + 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_37 + 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_38 + 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_39 + 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_40 + 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_41 + 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_42 + 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_43 + 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_44 + 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_45 + 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_46 + 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_47 + 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_48 + 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_49 + 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_50 + 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_51 + 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_52 + 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_53 + 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_54 + 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_55 + 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_56 + 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_12 + 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_13 + 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_14 + 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_15 + 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_16 + 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_17 + 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_18 + 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_19 + 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_20 + 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_21 + 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_22 + 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_23 + 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_24 + 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_25 + 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_26 + 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_27 + 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_28 + 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_29 + 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_30 + 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_31 + 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_32 + 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_33 + 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_34 + 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_35 + 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_36 + 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_37 + 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_38 + 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_39 + 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_40 + 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_41 + 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_42 + 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_43 + 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_44 + 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_45 + 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_46 + 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_12 + 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_13 + 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_14 + 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_15 + 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_16 + 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_17 + 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_18 + 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_19 + 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_20 + 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_21 + 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_22 + 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_23 + 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_24 + 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_25 + 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_26 + 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_27 + 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_28 + 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_29 + 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_30 + 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_31 + 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_32 + 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_33 + 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_34 + 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_35 + 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_36 + 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_37 + 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_38 + 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_39 + 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_40 + 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_41 + 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_42 + 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_43 + 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_44 + 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_45 + 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_46 + 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_46 + 4'b 0111, // index[256] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[257] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[258] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[259] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[260] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[261] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_11 + 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_12 + 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_13 + 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_14 + 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_15 + 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_16 + 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_17 + 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_18 + 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_19 + 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_20 + 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_21 + 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_22 + 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_23 + 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_24 + 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_25 + 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_26 + 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_27 + 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_28 + 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_29 + 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_30 + 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_31 + 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_32 + 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_33 + 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_34 + 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_35 + 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_36 + 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_37 + 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_38 + 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_39 + 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_40 + 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_41 + 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_42 + 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_43 + 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_44 + 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_45 + 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_46 + 4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[323] PINMUX_DIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[324] PINMUX_DIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[325] PINMUX_DIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[326] PINMUX_DIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[327] PINMUX_DIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[328] PINMUX_DIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[329] PINMUX_DIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[330] PINMUX_DIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[331] PINMUX_DIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[332] PINMUX_DIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[333] PINMUX_DIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[334] PINMUX_DIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[335] PINMUX_DIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[336] PINMUX_DIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[337] PINMUX_DIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[338] PINMUX_DIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[339] PINMUX_DIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[340] PINMUX_DIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[341] PINMUX_DIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[342] PINMUX_DIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[343] PINMUX_DIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[344] PINMUX_DIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[345] PINMUX_DIO_PAD_ATTR_REGWEN_42 + 4'b 0111, // index[346] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[347] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[348] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[349] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[350] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[351] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[352] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[353] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[354] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[355] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[356] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[357] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[358] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[359] PINMUX_DIO_PAD_ATTR_13 + 4'b 0111, // index[360] PINMUX_DIO_PAD_ATTR_14 + 4'b 0111, // index[361] PINMUX_DIO_PAD_ATTR_15 + 4'b 0111, // index[362] PINMUX_DIO_PAD_ATTR_16 + 4'b 0111, // index[363] PINMUX_DIO_PAD_ATTR_17 + 4'b 0111, // index[364] PINMUX_DIO_PAD_ATTR_18 + 4'b 0111, // index[365] PINMUX_DIO_PAD_ATTR_19 + 4'b 0111, // index[366] PINMUX_DIO_PAD_ATTR_20 + 4'b 0111, // index[367] PINMUX_DIO_PAD_ATTR_21 + 4'b 0111, // index[368] PINMUX_DIO_PAD_ATTR_22 + 4'b 0111, // index[369] PINMUX_DIO_PAD_ATTR_23 + 4'b 0111, // index[370] PINMUX_DIO_PAD_ATTR_24 + 4'b 0111, // index[371] PINMUX_DIO_PAD_ATTR_25 + 4'b 0111, // index[372] PINMUX_DIO_PAD_ATTR_26 + 4'b 0111, // index[373] PINMUX_DIO_PAD_ATTR_27 + 4'b 0111, // index[374] PINMUX_DIO_PAD_ATTR_28 + 4'b 0111, // index[375] PINMUX_DIO_PAD_ATTR_29 + 4'b 0111, // index[376] PINMUX_DIO_PAD_ATTR_30 + 4'b 0111, // index[377] PINMUX_DIO_PAD_ATTR_31 + 4'b 0111, // index[378] PINMUX_DIO_PAD_ATTR_32 + 4'b 0111, // index[379] PINMUX_DIO_PAD_ATTR_33 + 4'b 0111, // index[380] PINMUX_DIO_PAD_ATTR_34 + 4'b 0111, // index[381] PINMUX_DIO_PAD_ATTR_35 + 4'b 0111, // index[382] PINMUX_DIO_PAD_ATTR_36 + 4'b 0111, // index[383] PINMUX_DIO_PAD_ATTR_37 + 4'b 0111, // index[384] PINMUX_DIO_PAD_ATTR_38 + 4'b 0111, // index[385] PINMUX_DIO_PAD_ATTR_39 + 4'b 0111, // index[386] PINMUX_DIO_PAD_ATTR_40 + 4'b 0111, // index[387] PINMUX_DIO_PAD_ATTR_41 + 4'b 0111, // index[388] PINMUX_DIO_PAD_ATTR_42 + 4'b 1111, // index[389] PINMUX_MIO_PAD_SLEEP_STATUS_0 + 4'b 0011, // index[390] PINMUX_MIO_PAD_SLEEP_STATUS_1 + 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[484] PINMUX_MIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[485] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[486] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[487] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[488] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[489] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[490] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[491] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[492] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[493] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[494] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[495] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[496] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[497] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[498] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[499] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[500] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[501] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[502] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[503] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[504] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[505] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[506] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[507] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[508] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[509] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[510] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[511] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[512] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[513] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[514] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[515] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[516] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[517] PINMUX_MIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[518] PINMUX_MIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[519] PINMUX_MIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[520] PINMUX_MIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[521] PINMUX_MIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[522] PINMUX_MIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[523] PINMUX_MIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[524] PINMUX_MIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[525] PINMUX_MIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[526] PINMUX_MIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[527] PINMUX_MIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[528] PINMUX_MIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[529] PINMUX_MIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[530] PINMUX_MIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[531] PINMUX_MIO_PAD_SLEEP_MODE_46 + 4'b 1111, // index[532] PINMUX_DIO_PAD_SLEEP_STATUS_0 + 4'b 0011, // index[533] PINMUX_DIO_PAD_SLEEP_STATUS_1 + 4'b 0001, // index[534] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[535] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[536] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[537] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[538] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[539] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[540] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[541] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[542] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[543] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[544] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[545] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[546] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[547] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[548] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[549] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[550] PINMUX_DIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[551] PINMUX_DIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[552] PINMUX_DIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[553] PINMUX_DIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[554] PINMUX_DIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[555] PINMUX_DIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[556] PINMUX_DIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[557] PINMUX_DIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[558] PINMUX_DIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[559] PINMUX_DIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[560] PINMUX_DIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[561] PINMUX_DIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[562] PINMUX_DIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[563] PINMUX_DIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[564] PINMUX_DIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[565] PINMUX_DIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[566] PINMUX_DIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[567] PINMUX_DIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[568] PINMUX_DIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[569] PINMUX_DIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[570] PINMUX_DIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[571] PINMUX_DIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[572] PINMUX_DIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[573] PINMUX_DIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[574] PINMUX_DIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[575] PINMUX_DIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[576] PINMUX_DIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[577] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[578] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[579] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[580] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[581] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[582] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[583] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[584] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[585] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[586] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[587] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[588] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[589] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[590] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[591] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[592] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[593] PINMUX_DIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[594] PINMUX_DIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[595] PINMUX_DIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[596] PINMUX_DIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[597] PINMUX_DIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[598] PINMUX_DIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[599] PINMUX_DIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[600] PINMUX_DIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[601] PINMUX_DIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[602] PINMUX_DIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[603] PINMUX_DIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[604] PINMUX_DIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[605] PINMUX_DIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[606] PINMUX_DIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[607] PINMUX_DIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[608] PINMUX_DIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[609] PINMUX_DIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[610] PINMUX_DIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[611] PINMUX_DIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[612] PINMUX_DIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[613] PINMUX_DIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[614] PINMUX_DIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[615] PINMUX_DIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[616] PINMUX_DIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[617] PINMUX_DIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[618] PINMUX_DIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[619] PINMUX_DIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[620] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[621] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[622] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[623] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[624] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[625] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[626] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[627] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[628] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[629] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[630] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[631] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[632] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[633] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[634] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[635] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[636] PINMUX_DIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[637] PINMUX_DIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[638] PINMUX_DIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[639] PINMUX_DIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[640] PINMUX_DIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[641] PINMUX_DIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[642] PINMUX_DIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[643] PINMUX_DIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[644] PINMUX_DIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[645] PINMUX_DIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[646] PINMUX_DIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[647] PINMUX_DIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[648] PINMUX_DIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[649] PINMUX_DIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[650] PINMUX_DIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[651] PINMUX_DIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[652] PINMUX_DIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[653] PINMUX_DIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[654] PINMUX_DIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[655] PINMUX_DIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[656] PINMUX_DIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[657] PINMUX_DIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[658] PINMUX_DIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[659] PINMUX_DIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[660] PINMUX_DIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[661] PINMUX_DIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[662] PINMUX_DIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[663] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[664] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[665] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[666] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[667] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[668] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[669] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[670] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[671] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[672] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[673] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[674] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[675] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[676] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[677] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[678] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[679] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[680] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[681] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[682] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[683] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[684] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[685] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[686] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[687] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[688] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[689] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[690] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[691] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[692] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[693] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[694] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[695] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[696] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[697] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[698] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[699] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[700] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[701] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[702] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[703] PINMUX_WKUP_CAUSE }; endpackage
diff --git a/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv index 59e1004..7b1d282 100644 --- a/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv +++ b/hw/top_matcha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -57,9 +57,9 @@ // also check for spurious write enables logic reg_we_err; - logic [717:0] reg_we_check; + logic [703:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(718) + .OneHotWidth(704) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -299,9 +299,6 @@ logic mio_periph_insel_regwen_56_we; logic mio_periph_insel_regwen_56_qs; logic mio_periph_insel_regwen_56_wd; - logic mio_periph_insel_regwen_57_we; - logic mio_periph_insel_regwen_57_qs; - logic mio_periph_insel_regwen_57_wd; logic mio_periph_insel_0_we; logic [5:0] mio_periph_insel_0_qs; logic [5:0] mio_periph_insel_0_wd; @@ -473,9 +470,6 @@ logic mio_periph_insel_56_we; logic [5:0] mio_periph_insel_56_qs; logic [5:0] mio_periph_insel_56_wd; - logic mio_periph_insel_57_we; - logic [5:0] mio_periph_insel_57_qs; - logic [5:0] mio_periph_insel_57_wd; logic mio_outsel_regwen_0_we; logic mio_outsel_regwen_0_qs; logic mio_outsel_regwen_0_wd; @@ -617,24 +611,6 @@ logic mio_outsel_regwen_46_we; logic mio_outsel_regwen_46_qs; logic mio_outsel_regwen_46_wd; - logic mio_outsel_regwen_47_we; - logic mio_outsel_regwen_47_qs; - logic mio_outsel_regwen_47_wd; - logic mio_outsel_regwen_48_we; - logic mio_outsel_regwen_48_qs; - logic mio_outsel_regwen_48_wd; - logic mio_outsel_regwen_49_we; - logic mio_outsel_regwen_49_qs; - logic mio_outsel_regwen_49_wd; - logic mio_outsel_regwen_50_we; - logic mio_outsel_regwen_50_qs; - logic mio_outsel_regwen_50_wd; - logic mio_outsel_regwen_51_we; - logic mio_outsel_regwen_51_qs; - logic mio_outsel_regwen_51_wd; - logic mio_outsel_regwen_52_we; - logic mio_outsel_regwen_52_qs; - logic mio_outsel_regwen_52_wd; logic mio_outsel_0_we; logic [6:0] mio_outsel_0_qs; logic [6:0] mio_outsel_0_wd; @@ -776,24 +752,6 @@ logic mio_outsel_46_we; logic [6:0] mio_outsel_46_qs; logic [6:0] mio_outsel_46_wd; - logic mio_outsel_47_we; - logic [6:0] mio_outsel_47_qs; - logic [6:0] mio_outsel_47_wd; - logic mio_outsel_48_we; - logic [6:0] mio_outsel_48_qs; - logic [6:0] mio_outsel_48_wd; - logic mio_outsel_49_we; - logic [6:0] mio_outsel_49_qs; - logic [6:0] mio_outsel_49_wd; - logic mio_outsel_50_we; - logic [6:0] mio_outsel_50_qs; - logic [6:0] mio_outsel_50_wd; - logic mio_outsel_51_we; - logic [6:0] mio_outsel_51_qs; - logic [6:0] mio_outsel_51_wd; - logic mio_outsel_52_we; - logic [6:0] mio_outsel_52_qs; - logic [6:0] mio_outsel_52_wd; logic mio_pad_attr_regwen_0_we; logic mio_pad_attr_regwen_0_qs; logic mio_pad_attr_regwen_0_wd; @@ -935,24 +893,6 @@ logic mio_pad_attr_regwen_46_we; logic mio_pad_attr_regwen_46_qs; logic mio_pad_attr_regwen_46_wd; - logic mio_pad_attr_regwen_47_we; - logic mio_pad_attr_regwen_47_qs; - logic mio_pad_attr_regwen_47_wd; - logic mio_pad_attr_regwen_48_we; - logic mio_pad_attr_regwen_48_qs; - logic mio_pad_attr_regwen_48_wd; - logic mio_pad_attr_regwen_49_we; - logic mio_pad_attr_regwen_49_qs; - logic mio_pad_attr_regwen_49_wd; - logic mio_pad_attr_regwen_50_we; - logic mio_pad_attr_regwen_50_qs; - logic mio_pad_attr_regwen_50_wd; - logic mio_pad_attr_regwen_51_we; - logic mio_pad_attr_regwen_51_qs; - logic mio_pad_attr_regwen_51_wd; - logic mio_pad_attr_regwen_52_we; - logic mio_pad_attr_regwen_52_qs; - logic mio_pad_attr_regwen_52_wd; logic mio_pad_attr_0_re; logic mio_pad_attr_0_we; logic mio_pad_attr_0_invert_0_qs; @@ -1893,126 +1833,6 @@ logic [1:0] mio_pad_attr_46_slew_rate_46_wd; logic [3:0] mio_pad_attr_46_drive_strength_46_qs; logic [3:0] mio_pad_attr_46_drive_strength_46_wd; - logic mio_pad_attr_47_re; - logic mio_pad_attr_47_we; - logic mio_pad_attr_47_invert_47_qs; - logic mio_pad_attr_47_invert_47_wd; - logic mio_pad_attr_47_virtual_od_en_47_qs; - logic mio_pad_attr_47_virtual_od_en_47_wd; - logic mio_pad_attr_47_pull_en_47_qs; - logic mio_pad_attr_47_pull_en_47_wd; - logic mio_pad_attr_47_pull_select_47_qs; - logic mio_pad_attr_47_pull_select_47_wd; - logic mio_pad_attr_47_keeper_en_47_qs; - logic mio_pad_attr_47_keeper_en_47_wd; - logic mio_pad_attr_47_schmitt_en_47_qs; - logic mio_pad_attr_47_schmitt_en_47_wd; - logic mio_pad_attr_47_od_en_47_qs; - logic mio_pad_attr_47_od_en_47_wd; - logic [1:0] mio_pad_attr_47_slew_rate_47_qs; - logic [1:0] mio_pad_attr_47_slew_rate_47_wd; - logic [3:0] mio_pad_attr_47_drive_strength_47_qs; - logic [3:0] mio_pad_attr_47_drive_strength_47_wd; - logic mio_pad_attr_48_re; - logic mio_pad_attr_48_we; - logic mio_pad_attr_48_invert_48_qs; - logic mio_pad_attr_48_invert_48_wd; - logic mio_pad_attr_48_virtual_od_en_48_qs; - logic mio_pad_attr_48_virtual_od_en_48_wd; - logic mio_pad_attr_48_pull_en_48_qs; - logic mio_pad_attr_48_pull_en_48_wd; - logic mio_pad_attr_48_pull_select_48_qs; - logic mio_pad_attr_48_pull_select_48_wd; - logic mio_pad_attr_48_keeper_en_48_qs; - logic mio_pad_attr_48_keeper_en_48_wd; - logic mio_pad_attr_48_schmitt_en_48_qs; - logic mio_pad_attr_48_schmitt_en_48_wd; - logic mio_pad_attr_48_od_en_48_qs; - logic mio_pad_attr_48_od_en_48_wd; - logic [1:0] mio_pad_attr_48_slew_rate_48_qs; - logic [1:0] mio_pad_attr_48_slew_rate_48_wd; - logic [3:0] mio_pad_attr_48_drive_strength_48_qs; - logic [3:0] mio_pad_attr_48_drive_strength_48_wd; - logic mio_pad_attr_49_re; - logic mio_pad_attr_49_we; - logic mio_pad_attr_49_invert_49_qs; - logic mio_pad_attr_49_invert_49_wd; - logic mio_pad_attr_49_virtual_od_en_49_qs; - logic mio_pad_attr_49_virtual_od_en_49_wd; - logic mio_pad_attr_49_pull_en_49_qs; - logic mio_pad_attr_49_pull_en_49_wd; - logic mio_pad_attr_49_pull_select_49_qs; - logic mio_pad_attr_49_pull_select_49_wd; - logic mio_pad_attr_49_keeper_en_49_qs; - logic mio_pad_attr_49_keeper_en_49_wd; - logic mio_pad_attr_49_schmitt_en_49_qs; - logic mio_pad_attr_49_schmitt_en_49_wd; - logic mio_pad_attr_49_od_en_49_qs; - logic mio_pad_attr_49_od_en_49_wd; - logic [1:0] mio_pad_attr_49_slew_rate_49_qs; - logic [1:0] mio_pad_attr_49_slew_rate_49_wd; - logic [3:0] mio_pad_attr_49_drive_strength_49_qs; - logic [3:0] mio_pad_attr_49_drive_strength_49_wd; - logic mio_pad_attr_50_re; - logic mio_pad_attr_50_we; - logic mio_pad_attr_50_invert_50_qs; - logic mio_pad_attr_50_invert_50_wd; - logic mio_pad_attr_50_virtual_od_en_50_qs; - logic mio_pad_attr_50_virtual_od_en_50_wd; - logic mio_pad_attr_50_pull_en_50_qs; - logic mio_pad_attr_50_pull_en_50_wd; - logic mio_pad_attr_50_pull_select_50_qs; - logic mio_pad_attr_50_pull_select_50_wd; - logic mio_pad_attr_50_keeper_en_50_qs; - logic mio_pad_attr_50_keeper_en_50_wd; - logic mio_pad_attr_50_schmitt_en_50_qs; - logic mio_pad_attr_50_schmitt_en_50_wd; - logic mio_pad_attr_50_od_en_50_qs; - logic mio_pad_attr_50_od_en_50_wd; - logic [1:0] mio_pad_attr_50_slew_rate_50_qs; - logic [1:0] mio_pad_attr_50_slew_rate_50_wd; - logic [3:0] mio_pad_attr_50_drive_strength_50_qs; - logic [3:0] mio_pad_attr_50_drive_strength_50_wd; - logic mio_pad_attr_51_re; - logic mio_pad_attr_51_we; - logic mio_pad_attr_51_invert_51_qs; - logic mio_pad_attr_51_invert_51_wd; - logic mio_pad_attr_51_virtual_od_en_51_qs; - logic mio_pad_attr_51_virtual_od_en_51_wd; - logic mio_pad_attr_51_pull_en_51_qs; - logic mio_pad_attr_51_pull_en_51_wd; - logic mio_pad_attr_51_pull_select_51_qs; - logic mio_pad_attr_51_pull_select_51_wd; - logic mio_pad_attr_51_keeper_en_51_qs; - logic mio_pad_attr_51_keeper_en_51_wd; - logic mio_pad_attr_51_schmitt_en_51_qs; - logic mio_pad_attr_51_schmitt_en_51_wd; - logic mio_pad_attr_51_od_en_51_qs; - logic mio_pad_attr_51_od_en_51_wd; - logic [1:0] mio_pad_attr_51_slew_rate_51_qs; - logic [1:0] mio_pad_attr_51_slew_rate_51_wd; - logic [3:0] mio_pad_attr_51_drive_strength_51_qs; - logic [3:0] mio_pad_attr_51_drive_strength_51_wd; - logic mio_pad_attr_52_re; - logic mio_pad_attr_52_we; - logic mio_pad_attr_52_invert_52_qs; - logic mio_pad_attr_52_invert_52_wd; - logic mio_pad_attr_52_virtual_od_en_52_qs; - logic mio_pad_attr_52_virtual_od_en_52_wd; - logic mio_pad_attr_52_pull_en_52_qs; - logic mio_pad_attr_52_pull_en_52_wd; - logic mio_pad_attr_52_pull_select_52_qs; - logic mio_pad_attr_52_pull_select_52_wd; - logic mio_pad_attr_52_keeper_en_52_qs; - logic mio_pad_attr_52_keeper_en_52_wd; - logic mio_pad_attr_52_schmitt_en_52_qs; - logic mio_pad_attr_52_schmitt_en_52_wd; - logic mio_pad_attr_52_od_en_52_qs; - logic mio_pad_attr_52_od_en_52_wd; - logic [1:0] mio_pad_attr_52_slew_rate_52_qs; - logic [1:0] mio_pad_attr_52_slew_rate_52_wd; - logic [3:0] mio_pad_attr_52_drive_strength_52_qs; - logic [3:0] mio_pad_attr_52_drive_strength_52_wd; logic dio_pad_attr_regwen_0_we; logic dio_pad_attr_regwen_0_qs; logic dio_pad_attr_regwen_0_wd; @@ -2124,6 +1944,24 @@ logic dio_pad_attr_regwen_36_we; logic dio_pad_attr_regwen_36_qs; logic dio_pad_attr_regwen_36_wd; + logic dio_pad_attr_regwen_37_we; + logic dio_pad_attr_regwen_37_qs; + logic dio_pad_attr_regwen_37_wd; + logic dio_pad_attr_regwen_38_we; + logic dio_pad_attr_regwen_38_qs; + logic dio_pad_attr_regwen_38_wd; + logic dio_pad_attr_regwen_39_we; + logic dio_pad_attr_regwen_39_qs; + logic dio_pad_attr_regwen_39_wd; + logic dio_pad_attr_regwen_40_we; + logic dio_pad_attr_regwen_40_qs; + logic dio_pad_attr_regwen_40_wd; + logic dio_pad_attr_regwen_41_we; + logic dio_pad_attr_regwen_41_qs; + logic dio_pad_attr_regwen_41_wd; + logic dio_pad_attr_regwen_42_we; + logic dio_pad_attr_regwen_42_qs; + logic dio_pad_attr_regwen_42_wd; logic dio_pad_attr_0_re; logic dio_pad_attr_0_we; logic dio_pad_attr_0_invert_0_qs; @@ -2864,6 +2702,126 @@ logic [1:0] dio_pad_attr_36_slew_rate_36_wd; logic [3:0] dio_pad_attr_36_drive_strength_36_qs; logic [3:0] dio_pad_attr_36_drive_strength_36_wd; + logic dio_pad_attr_37_re; + logic dio_pad_attr_37_we; + logic dio_pad_attr_37_invert_37_qs; + logic dio_pad_attr_37_invert_37_wd; + logic dio_pad_attr_37_virtual_od_en_37_qs; + logic dio_pad_attr_37_virtual_od_en_37_wd; + logic dio_pad_attr_37_pull_en_37_qs; + logic dio_pad_attr_37_pull_en_37_wd; + logic dio_pad_attr_37_pull_select_37_qs; + logic dio_pad_attr_37_pull_select_37_wd; + logic dio_pad_attr_37_keeper_en_37_qs; + logic dio_pad_attr_37_keeper_en_37_wd; + logic dio_pad_attr_37_schmitt_en_37_qs; + logic dio_pad_attr_37_schmitt_en_37_wd; + logic dio_pad_attr_37_od_en_37_qs; + logic dio_pad_attr_37_od_en_37_wd; + logic [1:0] dio_pad_attr_37_slew_rate_37_qs; + logic [1:0] dio_pad_attr_37_slew_rate_37_wd; + logic [3:0] dio_pad_attr_37_drive_strength_37_qs; + logic [3:0] dio_pad_attr_37_drive_strength_37_wd; + logic dio_pad_attr_38_re; + logic dio_pad_attr_38_we; + logic dio_pad_attr_38_invert_38_qs; + logic dio_pad_attr_38_invert_38_wd; + logic dio_pad_attr_38_virtual_od_en_38_qs; + logic dio_pad_attr_38_virtual_od_en_38_wd; + logic dio_pad_attr_38_pull_en_38_qs; + logic dio_pad_attr_38_pull_en_38_wd; + logic dio_pad_attr_38_pull_select_38_qs; + logic dio_pad_attr_38_pull_select_38_wd; + logic dio_pad_attr_38_keeper_en_38_qs; + logic dio_pad_attr_38_keeper_en_38_wd; + logic dio_pad_attr_38_schmitt_en_38_qs; + logic dio_pad_attr_38_schmitt_en_38_wd; + logic dio_pad_attr_38_od_en_38_qs; + logic dio_pad_attr_38_od_en_38_wd; + logic [1:0] dio_pad_attr_38_slew_rate_38_qs; + logic [1:0] dio_pad_attr_38_slew_rate_38_wd; + logic [3:0] dio_pad_attr_38_drive_strength_38_qs; + logic [3:0] dio_pad_attr_38_drive_strength_38_wd; + logic dio_pad_attr_39_re; + logic dio_pad_attr_39_we; + logic dio_pad_attr_39_invert_39_qs; + logic dio_pad_attr_39_invert_39_wd; + logic dio_pad_attr_39_virtual_od_en_39_qs; + logic dio_pad_attr_39_virtual_od_en_39_wd; + logic dio_pad_attr_39_pull_en_39_qs; + logic dio_pad_attr_39_pull_en_39_wd; + logic dio_pad_attr_39_pull_select_39_qs; + logic dio_pad_attr_39_pull_select_39_wd; + logic dio_pad_attr_39_keeper_en_39_qs; + logic dio_pad_attr_39_keeper_en_39_wd; + logic dio_pad_attr_39_schmitt_en_39_qs; + logic dio_pad_attr_39_schmitt_en_39_wd; + logic dio_pad_attr_39_od_en_39_qs; + logic dio_pad_attr_39_od_en_39_wd; + logic [1:0] dio_pad_attr_39_slew_rate_39_qs; + logic [1:0] dio_pad_attr_39_slew_rate_39_wd; + logic [3:0] dio_pad_attr_39_drive_strength_39_qs; + logic [3:0] dio_pad_attr_39_drive_strength_39_wd; + logic dio_pad_attr_40_re; + logic dio_pad_attr_40_we; + logic dio_pad_attr_40_invert_40_qs; + logic dio_pad_attr_40_invert_40_wd; + logic dio_pad_attr_40_virtual_od_en_40_qs; + logic dio_pad_attr_40_virtual_od_en_40_wd; + logic dio_pad_attr_40_pull_en_40_qs; + logic dio_pad_attr_40_pull_en_40_wd; + logic dio_pad_attr_40_pull_select_40_qs; + logic dio_pad_attr_40_pull_select_40_wd; + logic dio_pad_attr_40_keeper_en_40_qs; + logic dio_pad_attr_40_keeper_en_40_wd; + logic dio_pad_attr_40_schmitt_en_40_qs; + logic dio_pad_attr_40_schmitt_en_40_wd; + logic dio_pad_attr_40_od_en_40_qs; + logic dio_pad_attr_40_od_en_40_wd; + logic [1:0] dio_pad_attr_40_slew_rate_40_qs; + logic [1:0] dio_pad_attr_40_slew_rate_40_wd; + logic [3:0] dio_pad_attr_40_drive_strength_40_qs; + logic [3:0] dio_pad_attr_40_drive_strength_40_wd; + logic dio_pad_attr_41_re; + logic dio_pad_attr_41_we; + logic dio_pad_attr_41_invert_41_qs; + logic dio_pad_attr_41_invert_41_wd; + logic dio_pad_attr_41_virtual_od_en_41_qs; + logic dio_pad_attr_41_virtual_od_en_41_wd; + logic dio_pad_attr_41_pull_en_41_qs; + logic dio_pad_attr_41_pull_en_41_wd; + logic dio_pad_attr_41_pull_select_41_qs; + logic dio_pad_attr_41_pull_select_41_wd; + logic dio_pad_attr_41_keeper_en_41_qs; + logic dio_pad_attr_41_keeper_en_41_wd; + logic dio_pad_attr_41_schmitt_en_41_qs; + logic dio_pad_attr_41_schmitt_en_41_wd; + logic dio_pad_attr_41_od_en_41_qs; + logic dio_pad_attr_41_od_en_41_wd; + logic [1:0] dio_pad_attr_41_slew_rate_41_qs; + logic [1:0] dio_pad_attr_41_slew_rate_41_wd; + logic [3:0] dio_pad_attr_41_drive_strength_41_qs; + logic [3:0] dio_pad_attr_41_drive_strength_41_wd; + logic dio_pad_attr_42_re; + logic dio_pad_attr_42_we; + logic dio_pad_attr_42_invert_42_qs; + logic dio_pad_attr_42_invert_42_wd; + logic dio_pad_attr_42_virtual_od_en_42_qs; + logic dio_pad_attr_42_virtual_od_en_42_wd; + logic dio_pad_attr_42_pull_en_42_qs; + logic dio_pad_attr_42_pull_en_42_wd; + logic dio_pad_attr_42_pull_select_42_qs; + logic dio_pad_attr_42_pull_select_42_wd; + logic dio_pad_attr_42_keeper_en_42_qs; + logic dio_pad_attr_42_keeper_en_42_wd; + logic dio_pad_attr_42_schmitt_en_42_qs; + logic dio_pad_attr_42_schmitt_en_42_wd; + logic dio_pad_attr_42_od_en_42_qs; + logic dio_pad_attr_42_od_en_42_wd; + logic [1:0] dio_pad_attr_42_slew_rate_42_qs; + logic [1:0] dio_pad_attr_42_slew_rate_42_wd; + logic [3:0] dio_pad_attr_42_drive_strength_42_qs; + logic [3:0] dio_pad_attr_42_drive_strength_42_wd; logic mio_pad_sleep_status_0_we; logic mio_pad_sleep_status_0_en_0_qs; logic mio_pad_sleep_status_0_en_0_wd; @@ -2960,18 +2918,6 @@ logic mio_pad_sleep_status_1_en_45_wd; logic mio_pad_sleep_status_1_en_46_qs; logic mio_pad_sleep_status_1_en_46_wd; - logic mio_pad_sleep_status_1_en_47_qs; - logic mio_pad_sleep_status_1_en_47_wd; - logic mio_pad_sleep_status_1_en_48_qs; - logic mio_pad_sleep_status_1_en_48_wd; - logic mio_pad_sleep_status_1_en_49_qs; - logic mio_pad_sleep_status_1_en_49_wd; - logic mio_pad_sleep_status_1_en_50_qs; - logic mio_pad_sleep_status_1_en_50_wd; - logic mio_pad_sleep_status_1_en_51_qs; - logic mio_pad_sleep_status_1_en_51_wd; - logic mio_pad_sleep_status_1_en_52_qs; - logic mio_pad_sleep_status_1_en_52_wd; logic mio_pad_sleep_regwen_0_we; logic mio_pad_sleep_regwen_0_qs; logic mio_pad_sleep_regwen_0_wd; @@ -3113,24 +3059,6 @@ logic mio_pad_sleep_regwen_46_we; logic mio_pad_sleep_regwen_46_qs; logic mio_pad_sleep_regwen_46_wd; - logic mio_pad_sleep_regwen_47_we; - logic mio_pad_sleep_regwen_47_qs; - logic mio_pad_sleep_regwen_47_wd; - logic mio_pad_sleep_regwen_48_we; - logic mio_pad_sleep_regwen_48_qs; - logic mio_pad_sleep_regwen_48_wd; - logic mio_pad_sleep_regwen_49_we; - logic mio_pad_sleep_regwen_49_qs; - logic mio_pad_sleep_regwen_49_wd; - logic mio_pad_sleep_regwen_50_we; - logic mio_pad_sleep_regwen_50_qs; - logic mio_pad_sleep_regwen_50_wd; - logic mio_pad_sleep_regwen_51_we; - logic mio_pad_sleep_regwen_51_qs; - logic mio_pad_sleep_regwen_51_wd; - logic mio_pad_sleep_regwen_52_we; - logic mio_pad_sleep_regwen_52_qs; - logic mio_pad_sleep_regwen_52_wd; logic mio_pad_sleep_en_0_we; logic mio_pad_sleep_en_0_qs; logic mio_pad_sleep_en_0_wd; @@ -3272,24 +3200,6 @@ logic mio_pad_sleep_en_46_we; logic mio_pad_sleep_en_46_qs; logic mio_pad_sleep_en_46_wd; - logic mio_pad_sleep_en_47_we; - logic mio_pad_sleep_en_47_qs; - logic mio_pad_sleep_en_47_wd; - logic mio_pad_sleep_en_48_we; - logic mio_pad_sleep_en_48_qs; - logic mio_pad_sleep_en_48_wd; - logic mio_pad_sleep_en_49_we; - logic mio_pad_sleep_en_49_qs; - logic mio_pad_sleep_en_49_wd; - logic mio_pad_sleep_en_50_we; - logic mio_pad_sleep_en_50_qs; - logic mio_pad_sleep_en_50_wd; - logic mio_pad_sleep_en_51_we; - logic mio_pad_sleep_en_51_qs; - logic mio_pad_sleep_en_51_wd; - logic mio_pad_sleep_en_52_we; - logic mio_pad_sleep_en_52_qs; - logic mio_pad_sleep_en_52_wd; logic mio_pad_sleep_mode_0_we; logic [1:0] mio_pad_sleep_mode_0_qs; logic [1:0] mio_pad_sleep_mode_0_wd; @@ -3431,24 +3341,6 @@ logic mio_pad_sleep_mode_46_we; logic [1:0] mio_pad_sleep_mode_46_qs; logic [1:0] mio_pad_sleep_mode_46_wd; - logic mio_pad_sleep_mode_47_we; - logic [1:0] mio_pad_sleep_mode_47_qs; - logic [1:0] mio_pad_sleep_mode_47_wd; - logic mio_pad_sleep_mode_48_we; - logic [1:0] mio_pad_sleep_mode_48_qs; - logic [1:0] mio_pad_sleep_mode_48_wd; - logic mio_pad_sleep_mode_49_we; - logic [1:0] mio_pad_sleep_mode_49_qs; - logic [1:0] mio_pad_sleep_mode_49_wd; - logic mio_pad_sleep_mode_50_we; - logic [1:0] mio_pad_sleep_mode_50_qs; - logic [1:0] mio_pad_sleep_mode_50_wd; - logic mio_pad_sleep_mode_51_we; - logic [1:0] mio_pad_sleep_mode_51_qs; - logic [1:0] mio_pad_sleep_mode_51_wd; - logic mio_pad_sleep_mode_52_we; - logic [1:0] mio_pad_sleep_mode_52_qs; - logic [1:0] mio_pad_sleep_mode_52_wd; logic dio_pad_sleep_status_0_we; logic dio_pad_sleep_status_0_en_0_qs; logic dio_pad_sleep_status_0_en_0_wd; @@ -3525,6 +3417,18 @@ logic dio_pad_sleep_status_1_en_35_wd; logic dio_pad_sleep_status_1_en_36_qs; logic dio_pad_sleep_status_1_en_36_wd; + logic dio_pad_sleep_status_1_en_37_qs; + logic dio_pad_sleep_status_1_en_37_wd; + logic dio_pad_sleep_status_1_en_38_qs; + logic dio_pad_sleep_status_1_en_38_wd; + logic dio_pad_sleep_status_1_en_39_qs; + logic dio_pad_sleep_status_1_en_39_wd; + logic dio_pad_sleep_status_1_en_40_qs; + logic dio_pad_sleep_status_1_en_40_wd; + logic dio_pad_sleep_status_1_en_41_qs; + logic dio_pad_sleep_status_1_en_41_wd; + logic dio_pad_sleep_status_1_en_42_qs; + logic dio_pad_sleep_status_1_en_42_wd; logic dio_pad_sleep_regwen_0_we; logic dio_pad_sleep_regwen_0_qs; logic dio_pad_sleep_regwen_0_wd; @@ -3636,6 +3540,24 @@ logic dio_pad_sleep_regwen_36_we; logic dio_pad_sleep_regwen_36_qs; logic dio_pad_sleep_regwen_36_wd; + logic dio_pad_sleep_regwen_37_we; + logic dio_pad_sleep_regwen_37_qs; + logic dio_pad_sleep_regwen_37_wd; + logic dio_pad_sleep_regwen_38_we; + logic dio_pad_sleep_regwen_38_qs; + logic dio_pad_sleep_regwen_38_wd; + logic dio_pad_sleep_regwen_39_we; + logic dio_pad_sleep_regwen_39_qs; + logic dio_pad_sleep_regwen_39_wd; + logic dio_pad_sleep_regwen_40_we; + logic dio_pad_sleep_regwen_40_qs; + logic dio_pad_sleep_regwen_40_wd; + logic dio_pad_sleep_regwen_41_we; + logic dio_pad_sleep_regwen_41_qs; + logic dio_pad_sleep_regwen_41_wd; + logic dio_pad_sleep_regwen_42_we; + logic dio_pad_sleep_regwen_42_qs; + logic dio_pad_sleep_regwen_42_wd; logic dio_pad_sleep_en_0_we; logic dio_pad_sleep_en_0_qs; logic dio_pad_sleep_en_0_wd; @@ -3747,6 +3669,24 @@ logic dio_pad_sleep_en_36_we; logic dio_pad_sleep_en_36_qs; logic dio_pad_sleep_en_36_wd; + logic dio_pad_sleep_en_37_we; + logic dio_pad_sleep_en_37_qs; + logic dio_pad_sleep_en_37_wd; + logic dio_pad_sleep_en_38_we; + logic dio_pad_sleep_en_38_qs; + logic dio_pad_sleep_en_38_wd; + logic dio_pad_sleep_en_39_we; + logic dio_pad_sleep_en_39_qs; + logic dio_pad_sleep_en_39_wd; + logic dio_pad_sleep_en_40_we; + logic dio_pad_sleep_en_40_qs; + logic dio_pad_sleep_en_40_wd; + logic dio_pad_sleep_en_41_we; + logic dio_pad_sleep_en_41_qs; + logic dio_pad_sleep_en_41_wd; + logic dio_pad_sleep_en_42_we; + logic dio_pad_sleep_en_42_qs; + logic dio_pad_sleep_en_42_wd; logic dio_pad_sleep_mode_0_we; logic [1:0] dio_pad_sleep_mode_0_qs; logic [1:0] dio_pad_sleep_mode_0_wd; @@ -3858,6 +3798,24 @@ logic dio_pad_sleep_mode_36_we; logic [1:0] dio_pad_sleep_mode_36_qs; logic [1:0] dio_pad_sleep_mode_36_wd; + logic dio_pad_sleep_mode_37_we; + logic [1:0] dio_pad_sleep_mode_37_qs; + logic [1:0] dio_pad_sleep_mode_37_wd; + logic dio_pad_sleep_mode_38_we; + logic [1:0] dio_pad_sleep_mode_38_qs; + logic [1:0] dio_pad_sleep_mode_38_wd; + logic dio_pad_sleep_mode_39_we; + logic [1:0] dio_pad_sleep_mode_39_qs; + logic [1:0] dio_pad_sleep_mode_39_wd; + logic dio_pad_sleep_mode_40_we; + logic [1:0] dio_pad_sleep_mode_40_qs; + logic [1:0] dio_pad_sleep_mode_40_wd; + logic dio_pad_sleep_mode_41_we; + logic [1:0] dio_pad_sleep_mode_41_qs; + logic [1:0] dio_pad_sleep_mode_41_wd; + logic dio_pad_sleep_mode_42_we; + logic [1:0] dio_pad_sleep_mode_42_qs; + logic [1:0] dio_pad_sleep_mode_42_wd; logic wkup_detector_regwen_0_we; logic wkup_detector_regwen_0_qs; logic wkup_detector_regwen_0_wd; @@ -6640,34 +6598,6 @@ ); - // Subregister 57 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_57]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_periph_insel_regwen_57 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_57_we), - .wd (mio_periph_insel_regwen_57_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_57_qs) - ); - - // Subregister 0 of Multireg mio_periph_insel // R[mio_periph_insel_0]: V(False) // Create REGWEN-gated WE signal @@ -8435,37 +8365,6 @@ ); - // Subregister 57 of Multireg mio_periph_insel - // R[mio_periph_insel_57]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_57_gated_we; - assign mio_periph_insel_57_gated_we = mio_periph_insel_57_we & mio_periph_insel_regwen_57_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0) - ) u_mio_periph_insel_57 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_57_gated_we), - .wd (mio_periph_insel_57_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[57].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_57_qs) - ); - - // Subregister 0 of Multireg mio_outsel_regwen // R[mio_outsel_regwen_0]: V(False) prim_subreg #( @@ -9782,174 +9681,6 @@ ); - // Subregister 47 of Multireg mio_outsel_regwen - // R[mio_outsel_regwen_47]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_outsel_regwen_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_regwen_47_we), - .wd (mio_outsel_regwen_47_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_outsel_regwen_47_qs) - ); - - - // Subregister 48 of Multireg mio_outsel_regwen - // R[mio_outsel_regwen_48]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_outsel_regwen_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_regwen_48_we), - .wd (mio_outsel_regwen_48_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_outsel_regwen_48_qs) - ); - - - // Subregister 49 of Multireg mio_outsel_regwen - // R[mio_outsel_regwen_49]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_outsel_regwen_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_regwen_49_we), - .wd (mio_outsel_regwen_49_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_outsel_regwen_49_qs) - ); - - - // Subregister 50 of Multireg mio_outsel_regwen - // R[mio_outsel_regwen_50]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_outsel_regwen_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_regwen_50_we), - .wd (mio_outsel_regwen_50_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_outsel_regwen_50_qs) - ); - - - // Subregister 51 of Multireg mio_outsel_regwen - // R[mio_outsel_regwen_51]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_outsel_regwen_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_regwen_51_we), - .wd (mio_outsel_regwen_51_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_outsel_regwen_51_qs) - ); - - - // Subregister 52 of Multireg mio_outsel_regwen - // R[mio_outsel_regwen_52]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_outsel_regwen_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_regwen_52_we), - .wd (mio_outsel_regwen_52_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_outsel_regwen_52_qs) - ); - - // Subregister 0 of Multireg mio_outsel // R[mio_outsel_0]: V(False) // Create REGWEN-gated WE signal @@ -11407,192 +11138,6 @@ ); - // Subregister 47 of Multireg mio_outsel - // R[mio_outsel_47]: V(False) - // Create REGWEN-gated WE signal - logic mio_outsel_47_gated_we; - assign mio_outsel_47_gated_we = mio_outsel_47_we & mio_outsel_regwen_47_qs; - prim_subreg #( - .DW (7), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (7'h2) - ) u_mio_outsel_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_47_gated_we), - .wd (mio_outsel_47_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_outsel[47].q), - .ds (), - - // to register interface (read) - .qs (mio_outsel_47_qs) - ); - - - // Subregister 48 of Multireg mio_outsel - // R[mio_outsel_48]: V(False) - // Create REGWEN-gated WE signal - logic mio_outsel_48_gated_we; - assign mio_outsel_48_gated_we = mio_outsel_48_we & mio_outsel_regwen_48_qs; - prim_subreg #( - .DW (7), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (7'h2) - ) u_mio_outsel_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_48_gated_we), - .wd (mio_outsel_48_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_outsel[48].q), - .ds (), - - // to register interface (read) - .qs (mio_outsel_48_qs) - ); - - - // Subregister 49 of Multireg mio_outsel - // R[mio_outsel_49]: V(False) - // Create REGWEN-gated WE signal - logic mio_outsel_49_gated_we; - assign mio_outsel_49_gated_we = mio_outsel_49_we & mio_outsel_regwen_49_qs; - prim_subreg #( - .DW (7), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (7'h2) - ) u_mio_outsel_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_49_gated_we), - .wd (mio_outsel_49_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_outsel[49].q), - .ds (), - - // to register interface (read) - .qs (mio_outsel_49_qs) - ); - - - // Subregister 50 of Multireg mio_outsel - // R[mio_outsel_50]: V(False) - // Create REGWEN-gated WE signal - logic mio_outsel_50_gated_we; - assign mio_outsel_50_gated_we = mio_outsel_50_we & mio_outsel_regwen_50_qs; - prim_subreg #( - .DW (7), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (7'h2) - ) u_mio_outsel_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_50_gated_we), - .wd (mio_outsel_50_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_outsel[50].q), - .ds (), - - // to register interface (read) - .qs (mio_outsel_50_qs) - ); - - - // Subregister 51 of Multireg mio_outsel - // R[mio_outsel_51]: V(False) - // Create REGWEN-gated WE signal - logic mio_outsel_51_gated_we; - assign mio_outsel_51_gated_we = mio_outsel_51_we & mio_outsel_regwen_51_qs; - prim_subreg #( - .DW (7), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (7'h2) - ) u_mio_outsel_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_51_gated_we), - .wd (mio_outsel_51_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_outsel[51].q), - .ds (), - - // to register interface (read) - .qs (mio_outsel_51_qs) - ); - - - // Subregister 52 of Multireg mio_outsel - // R[mio_outsel_52]: V(False) - // Create REGWEN-gated WE signal - logic mio_outsel_52_gated_we; - assign mio_outsel_52_gated_we = mio_outsel_52_we & mio_outsel_regwen_52_qs; - prim_subreg #( - .DW (7), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (7'h2) - ) u_mio_outsel_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_outsel_52_gated_we), - .wd (mio_outsel_52_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_outsel[52].q), - .ds (), - - // to register interface (read) - .qs (mio_outsel_52_qs) - ); - - // Subregister 0 of Multireg mio_pad_attr_regwen // R[mio_pad_attr_regwen_0]: V(False) prim_subreg #( @@ -12909,174 +12454,6 @@ ); - // Subregister 47 of Multireg mio_pad_attr_regwen - // R[mio_pad_attr_regwen_47]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_attr_regwen_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_attr_regwen_47_we), - .wd (mio_pad_attr_regwen_47_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_attr_regwen_47_qs) - ); - - - // Subregister 48 of Multireg mio_pad_attr_regwen - // R[mio_pad_attr_regwen_48]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_attr_regwen_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_attr_regwen_48_we), - .wd (mio_pad_attr_regwen_48_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_attr_regwen_48_qs) - ); - - - // Subregister 49 of Multireg mio_pad_attr_regwen - // R[mio_pad_attr_regwen_49]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_attr_regwen_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_attr_regwen_49_we), - .wd (mio_pad_attr_regwen_49_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_attr_regwen_49_qs) - ); - - - // Subregister 50 of Multireg mio_pad_attr_regwen - // R[mio_pad_attr_regwen_50]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_attr_regwen_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_attr_regwen_50_we), - .wd (mio_pad_attr_regwen_50_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_attr_regwen_50_qs) - ); - - - // Subregister 51 of Multireg mio_pad_attr_regwen - // R[mio_pad_attr_regwen_51]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_attr_regwen_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_attr_regwen_51_we), - .wd (mio_pad_attr_regwen_51_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_attr_regwen_51_qs) - ); - - - // Subregister 52 of Multireg mio_pad_attr_regwen - // R[mio_pad_attr_regwen_52]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_attr_regwen_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_attr_regwen_52_we), - .wd (mio_pad_attr_regwen_52_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_attr_regwen_52_qs) - ); - - // Subregister 0 of Multireg mio_pad_attr // R[mio_pad_attr_0]: V(True) logic mio_pad_attr_0_qe; @@ -20268,924 +19645,6 @@ assign reg2hw.mio_pad_attr[46].drive_strength.qe = mio_pad_attr_46_qe; - // Subregister 47 of Multireg mio_pad_attr - // R[mio_pad_attr_47]: V(True) - logic mio_pad_attr_47_qe; - logic [8:0] mio_pad_attr_47_flds_we; - assign mio_pad_attr_47_qe = &mio_pad_attr_47_flds_we; - // Create REGWEN-gated WE signal - logic mio_pad_attr_47_gated_we; - assign mio_pad_attr_47_gated_we = mio_pad_attr_47_we & mio_pad_attr_regwen_47_qs; - // F[invert_47]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_invert_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_invert_47_wd), - .d (hw2reg.mio_pad_attr[47].invert.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[0]), - .q (reg2hw.mio_pad_attr[47].invert.q), - .ds (), - .qs (mio_pad_attr_47_invert_47_qs) - ); - assign reg2hw.mio_pad_attr[47].invert.qe = mio_pad_attr_47_qe; - - // F[virtual_od_en_47]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_virtual_od_en_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_virtual_od_en_47_wd), - .d (hw2reg.mio_pad_attr[47].virtual_od_en.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[1]), - .q (reg2hw.mio_pad_attr[47].virtual_od_en.q), - .ds (), - .qs (mio_pad_attr_47_virtual_od_en_47_qs) - ); - assign reg2hw.mio_pad_attr[47].virtual_od_en.qe = mio_pad_attr_47_qe; - - // F[pull_en_47]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_pull_en_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_pull_en_47_wd), - .d (hw2reg.mio_pad_attr[47].pull_en.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[2]), - .q (reg2hw.mio_pad_attr[47].pull_en.q), - .ds (), - .qs (mio_pad_attr_47_pull_en_47_qs) - ); - assign reg2hw.mio_pad_attr[47].pull_en.qe = mio_pad_attr_47_qe; - - // F[pull_select_47]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_pull_select_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_pull_select_47_wd), - .d (hw2reg.mio_pad_attr[47].pull_select.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[3]), - .q (reg2hw.mio_pad_attr[47].pull_select.q), - .ds (), - .qs (mio_pad_attr_47_pull_select_47_qs) - ); - assign reg2hw.mio_pad_attr[47].pull_select.qe = mio_pad_attr_47_qe; - - // F[keeper_en_47]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_keeper_en_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_keeper_en_47_wd), - .d (hw2reg.mio_pad_attr[47].keeper_en.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[4]), - .q (reg2hw.mio_pad_attr[47].keeper_en.q), - .ds (), - .qs (mio_pad_attr_47_keeper_en_47_qs) - ); - assign reg2hw.mio_pad_attr[47].keeper_en.qe = mio_pad_attr_47_qe; - - // F[schmitt_en_47]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_schmitt_en_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_schmitt_en_47_wd), - .d (hw2reg.mio_pad_attr[47].schmitt_en.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[5]), - .q (reg2hw.mio_pad_attr[47].schmitt_en.q), - .ds (), - .qs (mio_pad_attr_47_schmitt_en_47_qs) - ); - assign reg2hw.mio_pad_attr[47].schmitt_en.qe = mio_pad_attr_47_qe; - - // F[od_en_47]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_47_od_en_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_od_en_47_wd), - .d (hw2reg.mio_pad_attr[47].od_en.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[6]), - .q (reg2hw.mio_pad_attr[47].od_en.q), - .ds (), - .qs (mio_pad_attr_47_od_en_47_qs) - ); - assign reg2hw.mio_pad_attr[47].od_en.qe = mio_pad_attr_47_qe; - - // F[slew_rate_47]: 17:16 - prim_subreg_ext #( - .DW (2) - ) u_mio_pad_attr_47_slew_rate_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_slew_rate_47_wd), - .d (hw2reg.mio_pad_attr[47].slew_rate.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[7]), - .q (reg2hw.mio_pad_attr[47].slew_rate.q), - .ds (), - .qs (mio_pad_attr_47_slew_rate_47_qs) - ); - assign reg2hw.mio_pad_attr[47].slew_rate.qe = mio_pad_attr_47_qe; - - // F[drive_strength_47]: 23:20 - prim_subreg_ext #( - .DW (4) - ) u_mio_pad_attr_47_drive_strength_47 ( - .re (mio_pad_attr_47_re), - .we (mio_pad_attr_47_gated_we), - .wd (mio_pad_attr_47_drive_strength_47_wd), - .d (hw2reg.mio_pad_attr[47].drive_strength.d), - .qre (), - .qe (mio_pad_attr_47_flds_we[8]), - .q (reg2hw.mio_pad_attr[47].drive_strength.q), - .ds (), - .qs (mio_pad_attr_47_drive_strength_47_qs) - ); - assign reg2hw.mio_pad_attr[47].drive_strength.qe = mio_pad_attr_47_qe; - - - // Subregister 48 of Multireg mio_pad_attr - // R[mio_pad_attr_48]: V(True) - logic mio_pad_attr_48_qe; - logic [8:0] mio_pad_attr_48_flds_we; - assign mio_pad_attr_48_qe = &mio_pad_attr_48_flds_we; - // Create REGWEN-gated WE signal - logic mio_pad_attr_48_gated_we; - assign mio_pad_attr_48_gated_we = mio_pad_attr_48_we & mio_pad_attr_regwen_48_qs; - // F[invert_48]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_invert_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_invert_48_wd), - .d (hw2reg.mio_pad_attr[48].invert.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[0]), - .q (reg2hw.mio_pad_attr[48].invert.q), - .ds (), - .qs (mio_pad_attr_48_invert_48_qs) - ); - assign reg2hw.mio_pad_attr[48].invert.qe = mio_pad_attr_48_qe; - - // F[virtual_od_en_48]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_virtual_od_en_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_virtual_od_en_48_wd), - .d (hw2reg.mio_pad_attr[48].virtual_od_en.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[1]), - .q (reg2hw.mio_pad_attr[48].virtual_od_en.q), - .ds (), - .qs (mio_pad_attr_48_virtual_od_en_48_qs) - ); - assign reg2hw.mio_pad_attr[48].virtual_od_en.qe = mio_pad_attr_48_qe; - - // F[pull_en_48]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_pull_en_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_pull_en_48_wd), - .d (hw2reg.mio_pad_attr[48].pull_en.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[2]), - .q (reg2hw.mio_pad_attr[48].pull_en.q), - .ds (), - .qs (mio_pad_attr_48_pull_en_48_qs) - ); - assign reg2hw.mio_pad_attr[48].pull_en.qe = mio_pad_attr_48_qe; - - // F[pull_select_48]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_pull_select_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_pull_select_48_wd), - .d (hw2reg.mio_pad_attr[48].pull_select.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[3]), - .q (reg2hw.mio_pad_attr[48].pull_select.q), - .ds (), - .qs (mio_pad_attr_48_pull_select_48_qs) - ); - assign reg2hw.mio_pad_attr[48].pull_select.qe = mio_pad_attr_48_qe; - - // F[keeper_en_48]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_keeper_en_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_keeper_en_48_wd), - .d (hw2reg.mio_pad_attr[48].keeper_en.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[4]), - .q (reg2hw.mio_pad_attr[48].keeper_en.q), - .ds (), - .qs (mio_pad_attr_48_keeper_en_48_qs) - ); - assign reg2hw.mio_pad_attr[48].keeper_en.qe = mio_pad_attr_48_qe; - - // F[schmitt_en_48]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_schmitt_en_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_schmitt_en_48_wd), - .d (hw2reg.mio_pad_attr[48].schmitt_en.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[5]), - .q (reg2hw.mio_pad_attr[48].schmitt_en.q), - .ds (), - .qs (mio_pad_attr_48_schmitt_en_48_qs) - ); - assign reg2hw.mio_pad_attr[48].schmitt_en.qe = mio_pad_attr_48_qe; - - // F[od_en_48]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_48_od_en_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_od_en_48_wd), - .d (hw2reg.mio_pad_attr[48].od_en.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[6]), - .q (reg2hw.mio_pad_attr[48].od_en.q), - .ds (), - .qs (mio_pad_attr_48_od_en_48_qs) - ); - assign reg2hw.mio_pad_attr[48].od_en.qe = mio_pad_attr_48_qe; - - // F[slew_rate_48]: 17:16 - prim_subreg_ext #( - .DW (2) - ) u_mio_pad_attr_48_slew_rate_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_slew_rate_48_wd), - .d (hw2reg.mio_pad_attr[48].slew_rate.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[7]), - .q (reg2hw.mio_pad_attr[48].slew_rate.q), - .ds (), - .qs (mio_pad_attr_48_slew_rate_48_qs) - ); - assign reg2hw.mio_pad_attr[48].slew_rate.qe = mio_pad_attr_48_qe; - - // F[drive_strength_48]: 23:20 - prim_subreg_ext #( - .DW (4) - ) u_mio_pad_attr_48_drive_strength_48 ( - .re (mio_pad_attr_48_re), - .we (mio_pad_attr_48_gated_we), - .wd (mio_pad_attr_48_drive_strength_48_wd), - .d (hw2reg.mio_pad_attr[48].drive_strength.d), - .qre (), - .qe (mio_pad_attr_48_flds_we[8]), - .q (reg2hw.mio_pad_attr[48].drive_strength.q), - .ds (), - .qs (mio_pad_attr_48_drive_strength_48_qs) - ); - assign reg2hw.mio_pad_attr[48].drive_strength.qe = mio_pad_attr_48_qe; - - - // Subregister 49 of Multireg mio_pad_attr - // R[mio_pad_attr_49]: V(True) - logic mio_pad_attr_49_qe; - logic [8:0] mio_pad_attr_49_flds_we; - assign mio_pad_attr_49_qe = &mio_pad_attr_49_flds_we; - // Create REGWEN-gated WE signal - logic mio_pad_attr_49_gated_we; - assign mio_pad_attr_49_gated_we = mio_pad_attr_49_we & mio_pad_attr_regwen_49_qs; - // F[invert_49]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_invert_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_invert_49_wd), - .d (hw2reg.mio_pad_attr[49].invert.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[0]), - .q (reg2hw.mio_pad_attr[49].invert.q), - .ds (), - .qs (mio_pad_attr_49_invert_49_qs) - ); - assign reg2hw.mio_pad_attr[49].invert.qe = mio_pad_attr_49_qe; - - // F[virtual_od_en_49]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_virtual_od_en_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_virtual_od_en_49_wd), - .d (hw2reg.mio_pad_attr[49].virtual_od_en.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[1]), - .q (reg2hw.mio_pad_attr[49].virtual_od_en.q), - .ds (), - .qs (mio_pad_attr_49_virtual_od_en_49_qs) - ); - assign reg2hw.mio_pad_attr[49].virtual_od_en.qe = mio_pad_attr_49_qe; - - // F[pull_en_49]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_pull_en_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_pull_en_49_wd), - .d (hw2reg.mio_pad_attr[49].pull_en.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[2]), - .q (reg2hw.mio_pad_attr[49].pull_en.q), - .ds (), - .qs (mio_pad_attr_49_pull_en_49_qs) - ); - assign reg2hw.mio_pad_attr[49].pull_en.qe = mio_pad_attr_49_qe; - - // F[pull_select_49]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_pull_select_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_pull_select_49_wd), - .d (hw2reg.mio_pad_attr[49].pull_select.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[3]), - .q (reg2hw.mio_pad_attr[49].pull_select.q), - .ds (), - .qs (mio_pad_attr_49_pull_select_49_qs) - ); - assign reg2hw.mio_pad_attr[49].pull_select.qe = mio_pad_attr_49_qe; - - // F[keeper_en_49]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_keeper_en_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_keeper_en_49_wd), - .d (hw2reg.mio_pad_attr[49].keeper_en.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[4]), - .q (reg2hw.mio_pad_attr[49].keeper_en.q), - .ds (), - .qs (mio_pad_attr_49_keeper_en_49_qs) - ); - assign reg2hw.mio_pad_attr[49].keeper_en.qe = mio_pad_attr_49_qe; - - // F[schmitt_en_49]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_schmitt_en_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_schmitt_en_49_wd), - .d (hw2reg.mio_pad_attr[49].schmitt_en.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[5]), - .q (reg2hw.mio_pad_attr[49].schmitt_en.q), - .ds (), - .qs (mio_pad_attr_49_schmitt_en_49_qs) - ); - assign reg2hw.mio_pad_attr[49].schmitt_en.qe = mio_pad_attr_49_qe; - - // F[od_en_49]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_49_od_en_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_od_en_49_wd), - .d (hw2reg.mio_pad_attr[49].od_en.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[6]), - .q (reg2hw.mio_pad_attr[49].od_en.q), - .ds (), - .qs (mio_pad_attr_49_od_en_49_qs) - ); - assign reg2hw.mio_pad_attr[49].od_en.qe = mio_pad_attr_49_qe; - - // F[slew_rate_49]: 17:16 - prim_subreg_ext #( - .DW (2) - ) u_mio_pad_attr_49_slew_rate_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_slew_rate_49_wd), - .d (hw2reg.mio_pad_attr[49].slew_rate.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[7]), - .q (reg2hw.mio_pad_attr[49].slew_rate.q), - .ds (), - .qs (mio_pad_attr_49_slew_rate_49_qs) - ); - assign reg2hw.mio_pad_attr[49].slew_rate.qe = mio_pad_attr_49_qe; - - // F[drive_strength_49]: 23:20 - prim_subreg_ext #( - .DW (4) - ) u_mio_pad_attr_49_drive_strength_49 ( - .re (mio_pad_attr_49_re), - .we (mio_pad_attr_49_gated_we), - .wd (mio_pad_attr_49_drive_strength_49_wd), - .d (hw2reg.mio_pad_attr[49].drive_strength.d), - .qre (), - .qe (mio_pad_attr_49_flds_we[8]), - .q (reg2hw.mio_pad_attr[49].drive_strength.q), - .ds (), - .qs (mio_pad_attr_49_drive_strength_49_qs) - ); - assign reg2hw.mio_pad_attr[49].drive_strength.qe = mio_pad_attr_49_qe; - - - // Subregister 50 of Multireg mio_pad_attr - // R[mio_pad_attr_50]: V(True) - logic mio_pad_attr_50_qe; - logic [8:0] mio_pad_attr_50_flds_we; - assign mio_pad_attr_50_qe = &mio_pad_attr_50_flds_we; - // Create REGWEN-gated WE signal - logic mio_pad_attr_50_gated_we; - assign mio_pad_attr_50_gated_we = mio_pad_attr_50_we & mio_pad_attr_regwen_50_qs; - // F[invert_50]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_invert_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_invert_50_wd), - .d (hw2reg.mio_pad_attr[50].invert.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[0]), - .q (reg2hw.mio_pad_attr[50].invert.q), - .ds (), - .qs (mio_pad_attr_50_invert_50_qs) - ); - assign reg2hw.mio_pad_attr[50].invert.qe = mio_pad_attr_50_qe; - - // F[virtual_od_en_50]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_virtual_od_en_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_virtual_od_en_50_wd), - .d (hw2reg.mio_pad_attr[50].virtual_od_en.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[1]), - .q (reg2hw.mio_pad_attr[50].virtual_od_en.q), - .ds (), - .qs (mio_pad_attr_50_virtual_od_en_50_qs) - ); - assign reg2hw.mio_pad_attr[50].virtual_od_en.qe = mio_pad_attr_50_qe; - - // F[pull_en_50]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_pull_en_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_pull_en_50_wd), - .d (hw2reg.mio_pad_attr[50].pull_en.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[2]), - .q (reg2hw.mio_pad_attr[50].pull_en.q), - .ds (), - .qs (mio_pad_attr_50_pull_en_50_qs) - ); - assign reg2hw.mio_pad_attr[50].pull_en.qe = mio_pad_attr_50_qe; - - // F[pull_select_50]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_pull_select_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_pull_select_50_wd), - .d (hw2reg.mio_pad_attr[50].pull_select.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[3]), - .q (reg2hw.mio_pad_attr[50].pull_select.q), - .ds (), - .qs (mio_pad_attr_50_pull_select_50_qs) - ); - assign reg2hw.mio_pad_attr[50].pull_select.qe = mio_pad_attr_50_qe; - - // F[keeper_en_50]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_keeper_en_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_keeper_en_50_wd), - .d (hw2reg.mio_pad_attr[50].keeper_en.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[4]), - .q (reg2hw.mio_pad_attr[50].keeper_en.q), - .ds (), - .qs (mio_pad_attr_50_keeper_en_50_qs) - ); - assign reg2hw.mio_pad_attr[50].keeper_en.qe = mio_pad_attr_50_qe; - - // F[schmitt_en_50]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_schmitt_en_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_schmitt_en_50_wd), - .d (hw2reg.mio_pad_attr[50].schmitt_en.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[5]), - .q (reg2hw.mio_pad_attr[50].schmitt_en.q), - .ds (), - .qs (mio_pad_attr_50_schmitt_en_50_qs) - ); - assign reg2hw.mio_pad_attr[50].schmitt_en.qe = mio_pad_attr_50_qe; - - // F[od_en_50]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_50_od_en_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_od_en_50_wd), - .d (hw2reg.mio_pad_attr[50].od_en.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[6]), - .q (reg2hw.mio_pad_attr[50].od_en.q), - .ds (), - .qs (mio_pad_attr_50_od_en_50_qs) - ); - assign reg2hw.mio_pad_attr[50].od_en.qe = mio_pad_attr_50_qe; - - // F[slew_rate_50]: 17:16 - prim_subreg_ext #( - .DW (2) - ) u_mio_pad_attr_50_slew_rate_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_slew_rate_50_wd), - .d (hw2reg.mio_pad_attr[50].slew_rate.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[7]), - .q (reg2hw.mio_pad_attr[50].slew_rate.q), - .ds (), - .qs (mio_pad_attr_50_slew_rate_50_qs) - ); - assign reg2hw.mio_pad_attr[50].slew_rate.qe = mio_pad_attr_50_qe; - - // F[drive_strength_50]: 23:20 - prim_subreg_ext #( - .DW (4) - ) u_mio_pad_attr_50_drive_strength_50 ( - .re (mio_pad_attr_50_re), - .we (mio_pad_attr_50_gated_we), - .wd (mio_pad_attr_50_drive_strength_50_wd), - .d (hw2reg.mio_pad_attr[50].drive_strength.d), - .qre (), - .qe (mio_pad_attr_50_flds_we[8]), - .q (reg2hw.mio_pad_attr[50].drive_strength.q), - .ds (), - .qs (mio_pad_attr_50_drive_strength_50_qs) - ); - assign reg2hw.mio_pad_attr[50].drive_strength.qe = mio_pad_attr_50_qe; - - - // Subregister 51 of Multireg mio_pad_attr - // R[mio_pad_attr_51]: V(True) - logic mio_pad_attr_51_qe; - logic [8:0] mio_pad_attr_51_flds_we; - assign mio_pad_attr_51_qe = &mio_pad_attr_51_flds_we; - // Create REGWEN-gated WE signal - logic mio_pad_attr_51_gated_we; - assign mio_pad_attr_51_gated_we = mio_pad_attr_51_we & mio_pad_attr_regwen_51_qs; - // F[invert_51]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_invert_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_invert_51_wd), - .d (hw2reg.mio_pad_attr[51].invert.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[0]), - .q (reg2hw.mio_pad_attr[51].invert.q), - .ds (), - .qs (mio_pad_attr_51_invert_51_qs) - ); - assign reg2hw.mio_pad_attr[51].invert.qe = mio_pad_attr_51_qe; - - // F[virtual_od_en_51]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_virtual_od_en_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_virtual_od_en_51_wd), - .d (hw2reg.mio_pad_attr[51].virtual_od_en.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[1]), - .q (reg2hw.mio_pad_attr[51].virtual_od_en.q), - .ds (), - .qs (mio_pad_attr_51_virtual_od_en_51_qs) - ); - assign reg2hw.mio_pad_attr[51].virtual_od_en.qe = mio_pad_attr_51_qe; - - // F[pull_en_51]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_pull_en_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_pull_en_51_wd), - .d (hw2reg.mio_pad_attr[51].pull_en.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[2]), - .q (reg2hw.mio_pad_attr[51].pull_en.q), - .ds (), - .qs (mio_pad_attr_51_pull_en_51_qs) - ); - assign reg2hw.mio_pad_attr[51].pull_en.qe = mio_pad_attr_51_qe; - - // F[pull_select_51]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_pull_select_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_pull_select_51_wd), - .d (hw2reg.mio_pad_attr[51].pull_select.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[3]), - .q (reg2hw.mio_pad_attr[51].pull_select.q), - .ds (), - .qs (mio_pad_attr_51_pull_select_51_qs) - ); - assign reg2hw.mio_pad_attr[51].pull_select.qe = mio_pad_attr_51_qe; - - // F[keeper_en_51]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_keeper_en_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_keeper_en_51_wd), - .d (hw2reg.mio_pad_attr[51].keeper_en.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[4]), - .q (reg2hw.mio_pad_attr[51].keeper_en.q), - .ds (), - .qs (mio_pad_attr_51_keeper_en_51_qs) - ); - assign reg2hw.mio_pad_attr[51].keeper_en.qe = mio_pad_attr_51_qe; - - // F[schmitt_en_51]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_schmitt_en_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_schmitt_en_51_wd), - .d (hw2reg.mio_pad_attr[51].schmitt_en.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[5]), - .q (reg2hw.mio_pad_attr[51].schmitt_en.q), - .ds (), - .qs (mio_pad_attr_51_schmitt_en_51_qs) - ); - assign reg2hw.mio_pad_attr[51].schmitt_en.qe = mio_pad_attr_51_qe; - - // F[od_en_51]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_51_od_en_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_od_en_51_wd), - .d (hw2reg.mio_pad_attr[51].od_en.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[6]), - .q (reg2hw.mio_pad_attr[51].od_en.q), - .ds (), - .qs (mio_pad_attr_51_od_en_51_qs) - ); - assign reg2hw.mio_pad_attr[51].od_en.qe = mio_pad_attr_51_qe; - - // F[slew_rate_51]: 17:16 - prim_subreg_ext #( - .DW (2) - ) u_mio_pad_attr_51_slew_rate_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_slew_rate_51_wd), - .d (hw2reg.mio_pad_attr[51].slew_rate.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[7]), - .q (reg2hw.mio_pad_attr[51].slew_rate.q), - .ds (), - .qs (mio_pad_attr_51_slew_rate_51_qs) - ); - assign reg2hw.mio_pad_attr[51].slew_rate.qe = mio_pad_attr_51_qe; - - // F[drive_strength_51]: 23:20 - prim_subreg_ext #( - .DW (4) - ) u_mio_pad_attr_51_drive_strength_51 ( - .re (mio_pad_attr_51_re), - .we (mio_pad_attr_51_gated_we), - .wd (mio_pad_attr_51_drive_strength_51_wd), - .d (hw2reg.mio_pad_attr[51].drive_strength.d), - .qre (), - .qe (mio_pad_attr_51_flds_we[8]), - .q (reg2hw.mio_pad_attr[51].drive_strength.q), - .ds (), - .qs (mio_pad_attr_51_drive_strength_51_qs) - ); - assign reg2hw.mio_pad_attr[51].drive_strength.qe = mio_pad_attr_51_qe; - - - // Subregister 52 of Multireg mio_pad_attr - // R[mio_pad_attr_52]: V(True) - logic mio_pad_attr_52_qe; - logic [8:0] mio_pad_attr_52_flds_we; - assign mio_pad_attr_52_qe = &mio_pad_attr_52_flds_we; - // Create REGWEN-gated WE signal - logic mio_pad_attr_52_gated_we; - assign mio_pad_attr_52_gated_we = mio_pad_attr_52_we & mio_pad_attr_regwen_52_qs; - // F[invert_52]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_invert_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_invert_52_wd), - .d (hw2reg.mio_pad_attr[52].invert.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[0]), - .q (reg2hw.mio_pad_attr[52].invert.q), - .ds (), - .qs (mio_pad_attr_52_invert_52_qs) - ); - assign reg2hw.mio_pad_attr[52].invert.qe = mio_pad_attr_52_qe; - - // F[virtual_od_en_52]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_virtual_od_en_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_virtual_od_en_52_wd), - .d (hw2reg.mio_pad_attr[52].virtual_od_en.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[1]), - .q (reg2hw.mio_pad_attr[52].virtual_od_en.q), - .ds (), - .qs (mio_pad_attr_52_virtual_od_en_52_qs) - ); - assign reg2hw.mio_pad_attr[52].virtual_od_en.qe = mio_pad_attr_52_qe; - - // F[pull_en_52]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_pull_en_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_pull_en_52_wd), - .d (hw2reg.mio_pad_attr[52].pull_en.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[2]), - .q (reg2hw.mio_pad_attr[52].pull_en.q), - .ds (), - .qs (mio_pad_attr_52_pull_en_52_qs) - ); - assign reg2hw.mio_pad_attr[52].pull_en.qe = mio_pad_attr_52_qe; - - // F[pull_select_52]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_pull_select_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_pull_select_52_wd), - .d (hw2reg.mio_pad_attr[52].pull_select.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[3]), - .q (reg2hw.mio_pad_attr[52].pull_select.q), - .ds (), - .qs (mio_pad_attr_52_pull_select_52_qs) - ); - assign reg2hw.mio_pad_attr[52].pull_select.qe = mio_pad_attr_52_qe; - - // F[keeper_en_52]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_keeper_en_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_keeper_en_52_wd), - .d (hw2reg.mio_pad_attr[52].keeper_en.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[4]), - .q (reg2hw.mio_pad_attr[52].keeper_en.q), - .ds (), - .qs (mio_pad_attr_52_keeper_en_52_qs) - ); - assign reg2hw.mio_pad_attr[52].keeper_en.qe = mio_pad_attr_52_qe; - - // F[schmitt_en_52]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_schmitt_en_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_schmitt_en_52_wd), - .d (hw2reg.mio_pad_attr[52].schmitt_en.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[5]), - .q (reg2hw.mio_pad_attr[52].schmitt_en.q), - .ds (), - .qs (mio_pad_attr_52_schmitt_en_52_qs) - ); - assign reg2hw.mio_pad_attr[52].schmitt_en.qe = mio_pad_attr_52_qe; - - // F[od_en_52]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_mio_pad_attr_52_od_en_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_od_en_52_wd), - .d (hw2reg.mio_pad_attr[52].od_en.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[6]), - .q (reg2hw.mio_pad_attr[52].od_en.q), - .ds (), - .qs (mio_pad_attr_52_od_en_52_qs) - ); - assign reg2hw.mio_pad_attr[52].od_en.qe = mio_pad_attr_52_qe; - - // F[slew_rate_52]: 17:16 - prim_subreg_ext #( - .DW (2) - ) u_mio_pad_attr_52_slew_rate_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_slew_rate_52_wd), - .d (hw2reg.mio_pad_attr[52].slew_rate.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[7]), - .q (reg2hw.mio_pad_attr[52].slew_rate.q), - .ds (), - .qs (mio_pad_attr_52_slew_rate_52_qs) - ); - assign reg2hw.mio_pad_attr[52].slew_rate.qe = mio_pad_attr_52_qe; - - // F[drive_strength_52]: 23:20 - prim_subreg_ext #( - .DW (4) - ) u_mio_pad_attr_52_drive_strength_52 ( - .re (mio_pad_attr_52_re), - .we (mio_pad_attr_52_gated_we), - .wd (mio_pad_attr_52_drive_strength_52_wd), - .d (hw2reg.mio_pad_attr[52].drive_strength.d), - .qre (), - .qe (mio_pad_attr_52_flds_we[8]), - .q (reg2hw.mio_pad_attr[52].drive_strength.q), - .ds (), - .qs (mio_pad_attr_52_drive_strength_52_qs) - ); - assign reg2hw.mio_pad_attr[52].drive_strength.qe = mio_pad_attr_52_qe; - - // Subregister 0 of Multireg dio_pad_attr_regwen // R[dio_pad_attr_regwen_0]: V(False) prim_subreg #( @@ -22222,6 +20681,174 @@ ); + // Subregister 37 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_37_we), + .wd (dio_pad_attr_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_38_we), + .wd (dio_pad_attr_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_39_we), + .wd (dio_pad_attr_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_40_we), + .wd (dio_pad_attr_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_41_we), + .wd (dio_pad_attr_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_attr_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_42_we), + .wd (dio_pad_attr_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_42_qs) + ); + + // Subregister 0 of Multireg dio_pad_attr // R[dio_pad_attr_0]: V(True) logic dio_pad_attr_0_qe; @@ -27883,6 +26510,924 @@ assign reg2hw.dio_pad_attr[36].drive_strength.qe = dio_pad_attr_36_qe; + // Subregister 37 of Multireg dio_pad_attr + // R[dio_pad_attr_37]: V(True) + logic dio_pad_attr_37_qe; + logic [8:0] dio_pad_attr_37_flds_we; + assign dio_pad_attr_37_qe = &dio_pad_attr_37_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_37_gated_we; + assign dio_pad_attr_37_gated_we = dio_pad_attr_37_we & dio_pad_attr_regwen_37_qs; + // F[invert_37]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_invert_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_invert_37_wd), + .d (hw2reg.dio_pad_attr[37].invert.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[0]), + .q (reg2hw.dio_pad_attr[37].invert.q), + .ds (), + .qs (dio_pad_attr_37_invert_37_qs) + ); + assign reg2hw.dio_pad_attr[37].invert.qe = dio_pad_attr_37_qe; + + // F[virtual_od_en_37]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_virtual_od_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_virtual_od_en_37_wd), + .d (hw2reg.dio_pad_attr[37].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[1]), + .q (reg2hw.dio_pad_attr[37].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_37_virtual_od_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].virtual_od_en.qe = dio_pad_attr_37_qe; + + // F[pull_en_37]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_pull_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_pull_en_37_wd), + .d (hw2reg.dio_pad_attr[37].pull_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[2]), + .q (reg2hw.dio_pad_attr[37].pull_en.q), + .ds (), + .qs (dio_pad_attr_37_pull_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].pull_en.qe = dio_pad_attr_37_qe; + + // F[pull_select_37]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_pull_select_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_pull_select_37_wd), + .d (hw2reg.dio_pad_attr[37].pull_select.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[3]), + .q (reg2hw.dio_pad_attr[37].pull_select.q), + .ds (), + .qs (dio_pad_attr_37_pull_select_37_qs) + ); + assign reg2hw.dio_pad_attr[37].pull_select.qe = dio_pad_attr_37_qe; + + // F[keeper_en_37]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_keeper_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_keeper_en_37_wd), + .d (hw2reg.dio_pad_attr[37].keeper_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[4]), + .q (reg2hw.dio_pad_attr[37].keeper_en.q), + .ds (), + .qs (dio_pad_attr_37_keeper_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].keeper_en.qe = dio_pad_attr_37_qe; + + // F[schmitt_en_37]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_schmitt_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_schmitt_en_37_wd), + .d (hw2reg.dio_pad_attr[37].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[5]), + .q (reg2hw.dio_pad_attr[37].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_37_schmitt_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].schmitt_en.qe = dio_pad_attr_37_qe; + + // F[od_en_37]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_od_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_od_en_37_wd), + .d (hw2reg.dio_pad_attr[37].od_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[6]), + .q (reg2hw.dio_pad_attr[37].od_en.q), + .ds (), + .qs (dio_pad_attr_37_od_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].od_en.qe = dio_pad_attr_37_qe; + + // F[slew_rate_37]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_37_slew_rate_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_slew_rate_37_wd), + .d (hw2reg.dio_pad_attr[37].slew_rate.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[7]), + .q (reg2hw.dio_pad_attr[37].slew_rate.q), + .ds (), + .qs (dio_pad_attr_37_slew_rate_37_qs) + ); + assign reg2hw.dio_pad_attr[37].slew_rate.qe = dio_pad_attr_37_qe; + + // F[drive_strength_37]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_37_drive_strength_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_drive_strength_37_wd), + .d (hw2reg.dio_pad_attr[37].drive_strength.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[8]), + .q (reg2hw.dio_pad_attr[37].drive_strength.q), + .ds (), + .qs (dio_pad_attr_37_drive_strength_37_qs) + ); + assign reg2hw.dio_pad_attr[37].drive_strength.qe = dio_pad_attr_37_qe; + + + // Subregister 38 of Multireg dio_pad_attr + // R[dio_pad_attr_38]: V(True) + logic dio_pad_attr_38_qe; + logic [8:0] dio_pad_attr_38_flds_we; + assign dio_pad_attr_38_qe = &dio_pad_attr_38_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_38_gated_we; + assign dio_pad_attr_38_gated_we = dio_pad_attr_38_we & dio_pad_attr_regwen_38_qs; + // F[invert_38]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_invert_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_invert_38_wd), + .d (hw2reg.dio_pad_attr[38].invert.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[0]), + .q (reg2hw.dio_pad_attr[38].invert.q), + .ds (), + .qs (dio_pad_attr_38_invert_38_qs) + ); + assign reg2hw.dio_pad_attr[38].invert.qe = dio_pad_attr_38_qe; + + // F[virtual_od_en_38]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_virtual_od_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_virtual_od_en_38_wd), + .d (hw2reg.dio_pad_attr[38].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[1]), + .q (reg2hw.dio_pad_attr[38].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_38_virtual_od_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].virtual_od_en.qe = dio_pad_attr_38_qe; + + // F[pull_en_38]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_pull_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_pull_en_38_wd), + .d (hw2reg.dio_pad_attr[38].pull_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[2]), + .q (reg2hw.dio_pad_attr[38].pull_en.q), + .ds (), + .qs (dio_pad_attr_38_pull_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].pull_en.qe = dio_pad_attr_38_qe; + + // F[pull_select_38]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_pull_select_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_pull_select_38_wd), + .d (hw2reg.dio_pad_attr[38].pull_select.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[3]), + .q (reg2hw.dio_pad_attr[38].pull_select.q), + .ds (), + .qs (dio_pad_attr_38_pull_select_38_qs) + ); + assign reg2hw.dio_pad_attr[38].pull_select.qe = dio_pad_attr_38_qe; + + // F[keeper_en_38]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_keeper_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_keeper_en_38_wd), + .d (hw2reg.dio_pad_attr[38].keeper_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[4]), + .q (reg2hw.dio_pad_attr[38].keeper_en.q), + .ds (), + .qs (dio_pad_attr_38_keeper_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].keeper_en.qe = dio_pad_attr_38_qe; + + // F[schmitt_en_38]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_schmitt_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_schmitt_en_38_wd), + .d (hw2reg.dio_pad_attr[38].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[5]), + .q (reg2hw.dio_pad_attr[38].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_38_schmitt_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].schmitt_en.qe = dio_pad_attr_38_qe; + + // F[od_en_38]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_od_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_od_en_38_wd), + .d (hw2reg.dio_pad_attr[38].od_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[6]), + .q (reg2hw.dio_pad_attr[38].od_en.q), + .ds (), + .qs (dio_pad_attr_38_od_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].od_en.qe = dio_pad_attr_38_qe; + + // F[slew_rate_38]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_38_slew_rate_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_slew_rate_38_wd), + .d (hw2reg.dio_pad_attr[38].slew_rate.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[7]), + .q (reg2hw.dio_pad_attr[38].slew_rate.q), + .ds (), + .qs (dio_pad_attr_38_slew_rate_38_qs) + ); + assign reg2hw.dio_pad_attr[38].slew_rate.qe = dio_pad_attr_38_qe; + + // F[drive_strength_38]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_38_drive_strength_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_drive_strength_38_wd), + .d (hw2reg.dio_pad_attr[38].drive_strength.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[8]), + .q (reg2hw.dio_pad_attr[38].drive_strength.q), + .ds (), + .qs (dio_pad_attr_38_drive_strength_38_qs) + ); + assign reg2hw.dio_pad_attr[38].drive_strength.qe = dio_pad_attr_38_qe; + + + // Subregister 39 of Multireg dio_pad_attr + // R[dio_pad_attr_39]: V(True) + logic dio_pad_attr_39_qe; + logic [8:0] dio_pad_attr_39_flds_we; + assign dio_pad_attr_39_qe = &dio_pad_attr_39_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_39_gated_we; + assign dio_pad_attr_39_gated_we = dio_pad_attr_39_we & dio_pad_attr_regwen_39_qs; + // F[invert_39]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_invert_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_invert_39_wd), + .d (hw2reg.dio_pad_attr[39].invert.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[0]), + .q (reg2hw.dio_pad_attr[39].invert.q), + .ds (), + .qs (dio_pad_attr_39_invert_39_qs) + ); + assign reg2hw.dio_pad_attr[39].invert.qe = dio_pad_attr_39_qe; + + // F[virtual_od_en_39]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_virtual_od_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_virtual_od_en_39_wd), + .d (hw2reg.dio_pad_attr[39].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[1]), + .q (reg2hw.dio_pad_attr[39].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_39_virtual_od_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].virtual_od_en.qe = dio_pad_attr_39_qe; + + // F[pull_en_39]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_pull_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_pull_en_39_wd), + .d (hw2reg.dio_pad_attr[39].pull_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[2]), + .q (reg2hw.dio_pad_attr[39].pull_en.q), + .ds (), + .qs (dio_pad_attr_39_pull_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].pull_en.qe = dio_pad_attr_39_qe; + + // F[pull_select_39]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_pull_select_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_pull_select_39_wd), + .d (hw2reg.dio_pad_attr[39].pull_select.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[3]), + .q (reg2hw.dio_pad_attr[39].pull_select.q), + .ds (), + .qs (dio_pad_attr_39_pull_select_39_qs) + ); + assign reg2hw.dio_pad_attr[39].pull_select.qe = dio_pad_attr_39_qe; + + // F[keeper_en_39]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_keeper_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_keeper_en_39_wd), + .d (hw2reg.dio_pad_attr[39].keeper_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[4]), + .q (reg2hw.dio_pad_attr[39].keeper_en.q), + .ds (), + .qs (dio_pad_attr_39_keeper_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].keeper_en.qe = dio_pad_attr_39_qe; + + // F[schmitt_en_39]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_schmitt_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_schmitt_en_39_wd), + .d (hw2reg.dio_pad_attr[39].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[5]), + .q (reg2hw.dio_pad_attr[39].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_39_schmitt_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].schmitt_en.qe = dio_pad_attr_39_qe; + + // F[od_en_39]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_od_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_od_en_39_wd), + .d (hw2reg.dio_pad_attr[39].od_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[6]), + .q (reg2hw.dio_pad_attr[39].od_en.q), + .ds (), + .qs (dio_pad_attr_39_od_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].od_en.qe = dio_pad_attr_39_qe; + + // F[slew_rate_39]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_39_slew_rate_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_slew_rate_39_wd), + .d (hw2reg.dio_pad_attr[39].slew_rate.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[7]), + .q (reg2hw.dio_pad_attr[39].slew_rate.q), + .ds (), + .qs (dio_pad_attr_39_slew_rate_39_qs) + ); + assign reg2hw.dio_pad_attr[39].slew_rate.qe = dio_pad_attr_39_qe; + + // F[drive_strength_39]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_39_drive_strength_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_drive_strength_39_wd), + .d (hw2reg.dio_pad_attr[39].drive_strength.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[8]), + .q (reg2hw.dio_pad_attr[39].drive_strength.q), + .ds (), + .qs (dio_pad_attr_39_drive_strength_39_qs) + ); + assign reg2hw.dio_pad_attr[39].drive_strength.qe = dio_pad_attr_39_qe; + + + // Subregister 40 of Multireg dio_pad_attr + // R[dio_pad_attr_40]: V(True) + logic dio_pad_attr_40_qe; + logic [8:0] dio_pad_attr_40_flds_we; + assign dio_pad_attr_40_qe = &dio_pad_attr_40_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_40_gated_we; + assign dio_pad_attr_40_gated_we = dio_pad_attr_40_we & dio_pad_attr_regwen_40_qs; + // F[invert_40]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_invert_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_invert_40_wd), + .d (hw2reg.dio_pad_attr[40].invert.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[0]), + .q (reg2hw.dio_pad_attr[40].invert.q), + .ds (), + .qs (dio_pad_attr_40_invert_40_qs) + ); + assign reg2hw.dio_pad_attr[40].invert.qe = dio_pad_attr_40_qe; + + // F[virtual_od_en_40]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_virtual_od_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_virtual_od_en_40_wd), + .d (hw2reg.dio_pad_attr[40].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[1]), + .q (reg2hw.dio_pad_attr[40].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_40_virtual_od_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].virtual_od_en.qe = dio_pad_attr_40_qe; + + // F[pull_en_40]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_pull_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_pull_en_40_wd), + .d (hw2reg.dio_pad_attr[40].pull_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[2]), + .q (reg2hw.dio_pad_attr[40].pull_en.q), + .ds (), + .qs (dio_pad_attr_40_pull_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].pull_en.qe = dio_pad_attr_40_qe; + + // F[pull_select_40]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_pull_select_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_pull_select_40_wd), + .d (hw2reg.dio_pad_attr[40].pull_select.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[3]), + .q (reg2hw.dio_pad_attr[40].pull_select.q), + .ds (), + .qs (dio_pad_attr_40_pull_select_40_qs) + ); + assign reg2hw.dio_pad_attr[40].pull_select.qe = dio_pad_attr_40_qe; + + // F[keeper_en_40]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_keeper_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_keeper_en_40_wd), + .d (hw2reg.dio_pad_attr[40].keeper_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[4]), + .q (reg2hw.dio_pad_attr[40].keeper_en.q), + .ds (), + .qs (dio_pad_attr_40_keeper_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].keeper_en.qe = dio_pad_attr_40_qe; + + // F[schmitt_en_40]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_schmitt_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_schmitt_en_40_wd), + .d (hw2reg.dio_pad_attr[40].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[5]), + .q (reg2hw.dio_pad_attr[40].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_40_schmitt_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].schmitt_en.qe = dio_pad_attr_40_qe; + + // F[od_en_40]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_od_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_od_en_40_wd), + .d (hw2reg.dio_pad_attr[40].od_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[6]), + .q (reg2hw.dio_pad_attr[40].od_en.q), + .ds (), + .qs (dio_pad_attr_40_od_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].od_en.qe = dio_pad_attr_40_qe; + + // F[slew_rate_40]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_40_slew_rate_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_slew_rate_40_wd), + .d (hw2reg.dio_pad_attr[40].slew_rate.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[7]), + .q (reg2hw.dio_pad_attr[40].slew_rate.q), + .ds (), + .qs (dio_pad_attr_40_slew_rate_40_qs) + ); + assign reg2hw.dio_pad_attr[40].slew_rate.qe = dio_pad_attr_40_qe; + + // F[drive_strength_40]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_40_drive_strength_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_drive_strength_40_wd), + .d (hw2reg.dio_pad_attr[40].drive_strength.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[8]), + .q (reg2hw.dio_pad_attr[40].drive_strength.q), + .ds (), + .qs (dio_pad_attr_40_drive_strength_40_qs) + ); + assign reg2hw.dio_pad_attr[40].drive_strength.qe = dio_pad_attr_40_qe; + + + // Subregister 41 of Multireg dio_pad_attr + // R[dio_pad_attr_41]: V(True) + logic dio_pad_attr_41_qe; + logic [8:0] dio_pad_attr_41_flds_we; + assign dio_pad_attr_41_qe = &dio_pad_attr_41_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_41_gated_we; + assign dio_pad_attr_41_gated_we = dio_pad_attr_41_we & dio_pad_attr_regwen_41_qs; + // F[invert_41]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_invert_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_invert_41_wd), + .d (hw2reg.dio_pad_attr[41].invert.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[0]), + .q (reg2hw.dio_pad_attr[41].invert.q), + .ds (), + .qs (dio_pad_attr_41_invert_41_qs) + ); + assign reg2hw.dio_pad_attr[41].invert.qe = dio_pad_attr_41_qe; + + // F[virtual_od_en_41]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_virtual_od_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_virtual_od_en_41_wd), + .d (hw2reg.dio_pad_attr[41].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[1]), + .q (reg2hw.dio_pad_attr[41].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_41_virtual_od_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].virtual_od_en.qe = dio_pad_attr_41_qe; + + // F[pull_en_41]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_pull_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_pull_en_41_wd), + .d (hw2reg.dio_pad_attr[41].pull_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[2]), + .q (reg2hw.dio_pad_attr[41].pull_en.q), + .ds (), + .qs (dio_pad_attr_41_pull_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].pull_en.qe = dio_pad_attr_41_qe; + + // F[pull_select_41]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_pull_select_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_pull_select_41_wd), + .d (hw2reg.dio_pad_attr[41].pull_select.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[3]), + .q (reg2hw.dio_pad_attr[41].pull_select.q), + .ds (), + .qs (dio_pad_attr_41_pull_select_41_qs) + ); + assign reg2hw.dio_pad_attr[41].pull_select.qe = dio_pad_attr_41_qe; + + // F[keeper_en_41]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_keeper_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_keeper_en_41_wd), + .d (hw2reg.dio_pad_attr[41].keeper_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[4]), + .q (reg2hw.dio_pad_attr[41].keeper_en.q), + .ds (), + .qs (dio_pad_attr_41_keeper_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].keeper_en.qe = dio_pad_attr_41_qe; + + // F[schmitt_en_41]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_schmitt_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_schmitt_en_41_wd), + .d (hw2reg.dio_pad_attr[41].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[5]), + .q (reg2hw.dio_pad_attr[41].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_41_schmitt_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].schmitt_en.qe = dio_pad_attr_41_qe; + + // F[od_en_41]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_od_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_od_en_41_wd), + .d (hw2reg.dio_pad_attr[41].od_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[6]), + .q (reg2hw.dio_pad_attr[41].od_en.q), + .ds (), + .qs (dio_pad_attr_41_od_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].od_en.qe = dio_pad_attr_41_qe; + + // F[slew_rate_41]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_41_slew_rate_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_slew_rate_41_wd), + .d (hw2reg.dio_pad_attr[41].slew_rate.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[7]), + .q (reg2hw.dio_pad_attr[41].slew_rate.q), + .ds (), + .qs (dio_pad_attr_41_slew_rate_41_qs) + ); + assign reg2hw.dio_pad_attr[41].slew_rate.qe = dio_pad_attr_41_qe; + + // F[drive_strength_41]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_41_drive_strength_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_drive_strength_41_wd), + .d (hw2reg.dio_pad_attr[41].drive_strength.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[8]), + .q (reg2hw.dio_pad_attr[41].drive_strength.q), + .ds (), + .qs (dio_pad_attr_41_drive_strength_41_qs) + ); + assign reg2hw.dio_pad_attr[41].drive_strength.qe = dio_pad_attr_41_qe; + + + // Subregister 42 of Multireg dio_pad_attr + // R[dio_pad_attr_42]: V(True) + logic dio_pad_attr_42_qe; + logic [8:0] dio_pad_attr_42_flds_we; + assign dio_pad_attr_42_qe = &dio_pad_attr_42_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_42_gated_we; + assign dio_pad_attr_42_gated_we = dio_pad_attr_42_we & dio_pad_attr_regwen_42_qs; + // F[invert_42]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_invert_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_invert_42_wd), + .d (hw2reg.dio_pad_attr[42].invert.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[0]), + .q (reg2hw.dio_pad_attr[42].invert.q), + .ds (), + .qs (dio_pad_attr_42_invert_42_qs) + ); + assign reg2hw.dio_pad_attr[42].invert.qe = dio_pad_attr_42_qe; + + // F[virtual_od_en_42]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_virtual_od_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_virtual_od_en_42_wd), + .d (hw2reg.dio_pad_attr[42].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[1]), + .q (reg2hw.dio_pad_attr[42].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_42_virtual_od_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].virtual_od_en.qe = dio_pad_attr_42_qe; + + // F[pull_en_42]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_pull_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_pull_en_42_wd), + .d (hw2reg.dio_pad_attr[42].pull_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[2]), + .q (reg2hw.dio_pad_attr[42].pull_en.q), + .ds (), + .qs (dio_pad_attr_42_pull_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].pull_en.qe = dio_pad_attr_42_qe; + + // F[pull_select_42]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_pull_select_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_pull_select_42_wd), + .d (hw2reg.dio_pad_attr[42].pull_select.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[3]), + .q (reg2hw.dio_pad_attr[42].pull_select.q), + .ds (), + .qs (dio_pad_attr_42_pull_select_42_qs) + ); + assign reg2hw.dio_pad_attr[42].pull_select.qe = dio_pad_attr_42_qe; + + // F[keeper_en_42]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_keeper_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_keeper_en_42_wd), + .d (hw2reg.dio_pad_attr[42].keeper_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[4]), + .q (reg2hw.dio_pad_attr[42].keeper_en.q), + .ds (), + .qs (dio_pad_attr_42_keeper_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].keeper_en.qe = dio_pad_attr_42_qe; + + // F[schmitt_en_42]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_schmitt_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_schmitt_en_42_wd), + .d (hw2reg.dio_pad_attr[42].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[5]), + .q (reg2hw.dio_pad_attr[42].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_42_schmitt_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].schmitt_en.qe = dio_pad_attr_42_qe; + + // F[od_en_42]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_od_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_od_en_42_wd), + .d (hw2reg.dio_pad_attr[42].od_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[6]), + .q (reg2hw.dio_pad_attr[42].od_en.q), + .ds (), + .qs (dio_pad_attr_42_od_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].od_en.qe = dio_pad_attr_42_qe; + + // F[slew_rate_42]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_42_slew_rate_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_slew_rate_42_wd), + .d (hw2reg.dio_pad_attr[42].slew_rate.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[7]), + .q (reg2hw.dio_pad_attr[42].slew_rate.q), + .ds (), + .qs (dio_pad_attr_42_slew_rate_42_qs) + ); + assign reg2hw.dio_pad_attr[42].slew_rate.qe = dio_pad_attr_42_qe; + + // F[drive_strength_42]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_42_drive_strength_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_drive_strength_42_wd), + .d (hw2reg.dio_pad_attr[42].drive_strength.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[8]), + .q (reg2hw.dio_pad_attr[42].drive_strength.q), + .ds (), + .qs (dio_pad_attr_42_drive_strength_42_qs) + ); + assign reg2hw.dio_pad_attr[42].drive_strength.qe = dio_pad_attr_42_qe; + + // Subregister 0 of Multireg mio_pad_sleep_status // R[mio_pad_sleep_status_0]: V(False) // F[en_0]: 0:0 @@ -29110,162 +28655,6 @@ .qs (mio_pad_sleep_status_1_en_46_qs) ); - // F[en_47]: 15:15 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h0) - ) u_mio_pad_sleep_status_1_en_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_status_1_we), - .wd (mio_pad_sleep_status_1_en_47_wd), - - // from internal hardware - .de (hw2reg.mio_pad_sleep_status[47].de), - .d (hw2reg.mio_pad_sleep_status[47].d), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_status[47].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_status_1_en_47_qs) - ); - - // F[en_48]: 16:16 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h0) - ) u_mio_pad_sleep_status_1_en_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_status_1_we), - .wd (mio_pad_sleep_status_1_en_48_wd), - - // from internal hardware - .de (hw2reg.mio_pad_sleep_status[48].de), - .d (hw2reg.mio_pad_sleep_status[48].d), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_status[48].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_status_1_en_48_qs) - ); - - // F[en_49]: 17:17 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h0) - ) u_mio_pad_sleep_status_1_en_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_status_1_we), - .wd (mio_pad_sleep_status_1_en_49_wd), - - // from internal hardware - .de (hw2reg.mio_pad_sleep_status[49].de), - .d (hw2reg.mio_pad_sleep_status[49].d), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_status[49].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_status_1_en_49_qs) - ); - - // F[en_50]: 18:18 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h0) - ) u_mio_pad_sleep_status_1_en_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_status_1_we), - .wd (mio_pad_sleep_status_1_en_50_wd), - - // from internal hardware - .de (hw2reg.mio_pad_sleep_status[50].de), - .d (hw2reg.mio_pad_sleep_status[50].d), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_status[50].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_status_1_en_50_qs) - ); - - // F[en_51]: 19:19 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h0) - ) u_mio_pad_sleep_status_1_en_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_status_1_we), - .wd (mio_pad_sleep_status_1_en_51_wd), - - // from internal hardware - .de (hw2reg.mio_pad_sleep_status[51].de), - .d (hw2reg.mio_pad_sleep_status[51].d), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_status[51].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_status_1_en_51_qs) - ); - - // F[en_52]: 20:20 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h0) - ) u_mio_pad_sleep_status_1_en_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_status_1_we), - .wd (mio_pad_sleep_status_1_en_52_wd), - - // from internal hardware - .de (hw2reg.mio_pad_sleep_status[52].de), - .d (hw2reg.mio_pad_sleep_status[52].d), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_status[52].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_status_1_en_52_qs) - ); - // Subregister 0 of Multireg mio_pad_sleep_regwen // R[mio_pad_sleep_regwen_0]: V(False) @@ -30583,174 +29972,6 @@ ); - // Subregister 47 of Multireg mio_pad_sleep_regwen - // R[mio_pad_sleep_regwen_47]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_sleep_regwen_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_regwen_47_we), - .wd (mio_pad_sleep_regwen_47_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_regwen_47_qs) - ); - - - // Subregister 48 of Multireg mio_pad_sleep_regwen - // R[mio_pad_sleep_regwen_48]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_sleep_regwen_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_regwen_48_we), - .wd (mio_pad_sleep_regwen_48_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_regwen_48_qs) - ); - - - // Subregister 49 of Multireg mio_pad_sleep_regwen - // R[mio_pad_sleep_regwen_49]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_sleep_regwen_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_regwen_49_we), - .wd (mio_pad_sleep_regwen_49_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_regwen_49_qs) - ); - - - // Subregister 50 of Multireg mio_pad_sleep_regwen - // R[mio_pad_sleep_regwen_50]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_sleep_regwen_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_regwen_50_we), - .wd (mio_pad_sleep_regwen_50_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_regwen_50_qs) - ); - - - // Subregister 51 of Multireg mio_pad_sleep_regwen - // R[mio_pad_sleep_regwen_51]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_sleep_regwen_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_regwen_51_we), - .wd (mio_pad_sleep_regwen_51_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_regwen_51_qs) - ); - - - // Subregister 52 of Multireg mio_pad_sleep_regwen - // R[mio_pad_sleep_regwen_52]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1) - ) u_mio_pad_sleep_regwen_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_regwen_52_we), - .wd (mio_pad_sleep_regwen_52_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_regwen_52_qs) - ); - - // Subregister 0 of Multireg mio_pad_sleep_en // R[mio_pad_sleep_en_0]: V(False) // Create REGWEN-gated WE signal @@ -32208,192 +31429,6 @@ ); - // Subregister 47 of Multireg mio_pad_sleep_en - // R[mio_pad_sleep_en_47]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_en_47_gated_we; - assign mio_pad_sleep_en_47_gated_we = mio_pad_sleep_en_47_we & mio_pad_sleep_regwen_47_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0) - ) u_mio_pad_sleep_en_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_en_47_gated_we), - .wd (mio_pad_sleep_en_47_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_en[47].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_en_47_qs) - ); - - - // Subregister 48 of Multireg mio_pad_sleep_en - // R[mio_pad_sleep_en_48]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_en_48_gated_we; - assign mio_pad_sleep_en_48_gated_we = mio_pad_sleep_en_48_we & mio_pad_sleep_regwen_48_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0) - ) u_mio_pad_sleep_en_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_en_48_gated_we), - .wd (mio_pad_sleep_en_48_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_en[48].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_en_48_qs) - ); - - - // Subregister 49 of Multireg mio_pad_sleep_en - // R[mio_pad_sleep_en_49]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_en_49_gated_we; - assign mio_pad_sleep_en_49_gated_we = mio_pad_sleep_en_49_we & mio_pad_sleep_regwen_49_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0) - ) u_mio_pad_sleep_en_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_en_49_gated_we), - .wd (mio_pad_sleep_en_49_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_en[49].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_en_49_qs) - ); - - - // Subregister 50 of Multireg mio_pad_sleep_en - // R[mio_pad_sleep_en_50]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_en_50_gated_we; - assign mio_pad_sleep_en_50_gated_we = mio_pad_sleep_en_50_we & mio_pad_sleep_regwen_50_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0) - ) u_mio_pad_sleep_en_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_en_50_gated_we), - .wd (mio_pad_sleep_en_50_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_en[50].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_en_50_qs) - ); - - - // Subregister 51 of Multireg mio_pad_sleep_en - // R[mio_pad_sleep_en_51]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_en_51_gated_we; - assign mio_pad_sleep_en_51_gated_we = mio_pad_sleep_en_51_we & mio_pad_sleep_regwen_51_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0) - ) u_mio_pad_sleep_en_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_en_51_gated_we), - .wd (mio_pad_sleep_en_51_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_en[51].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_en_51_qs) - ); - - - // Subregister 52 of Multireg mio_pad_sleep_en - // R[mio_pad_sleep_en_52]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_en_52_gated_we; - assign mio_pad_sleep_en_52_gated_we = mio_pad_sleep_en_52_we & mio_pad_sleep_regwen_52_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0) - ) u_mio_pad_sleep_en_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_en_52_gated_we), - .wd (mio_pad_sleep_en_52_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_en[52].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_en_52_qs) - ); - - // Subregister 0 of Multireg mio_pad_sleep_mode // R[mio_pad_sleep_mode_0]: V(False) // Create REGWEN-gated WE signal @@ -33851,192 +32886,6 @@ ); - // Subregister 47 of Multireg mio_pad_sleep_mode - // R[mio_pad_sleep_mode_47]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_mode_47_gated_we; - assign mio_pad_sleep_mode_47_gated_we = mio_pad_sleep_mode_47_we & mio_pad_sleep_regwen_47_qs; - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h2) - ) u_mio_pad_sleep_mode_47 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_mode_47_gated_we), - .wd (mio_pad_sleep_mode_47_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_mode[47].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_mode_47_qs) - ); - - - // Subregister 48 of Multireg mio_pad_sleep_mode - // R[mio_pad_sleep_mode_48]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_mode_48_gated_we; - assign mio_pad_sleep_mode_48_gated_we = mio_pad_sleep_mode_48_we & mio_pad_sleep_regwen_48_qs; - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h2) - ) u_mio_pad_sleep_mode_48 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_mode_48_gated_we), - .wd (mio_pad_sleep_mode_48_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_mode[48].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_mode_48_qs) - ); - - - // Subregister 49 of Multireg mio_pad_sleep_mode - // R[mio_pad_sleep_mode_49]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_mode_49_gated_we; - assign mio_pad_sleep_mode_49_gated_we = mio_pad_sleep_mode_49_we & mio_pad_sleep_regwen_49_qs; - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h2) - ) u_mio_pad_sleep_mode_49 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_mode_49_gated_we), - .wd (mio_pad_sleep_mode_49_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_mode[49].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_mode_49_qs) - ); - - - // Subregister 50 of Multireg mio_pad_sleep_mode - // R[mio_pad_sleep_mode_50]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_mode_50_gated_we; - assign mio_pad_sleep_mode_50_gated_we = mio_pad_sleep_mode_50_we & mio_pad_sleep_regwen_50_qs; - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h2) - ) u_mio_pad_sleep_mode_50 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_mode_50_gated_we), - .wd (mio_pad_sleep_mode_50_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_mode[50].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_mode_50_qs) - ); - - - // Subregister 51 of Multireg mio_pad_sleep_mode - // R[mio_pad_sleep_mode_51]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_mode_51_gated_we; - assign mio_pad_sleep_mode_51_gated_we = mio_pad_sleep_mode_51_we & mio_pad_sleep_regwen_51_qs; - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h2) - ) u_mio_pad_sleep_mode_51 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_mode_51_gated_we), - .wd (mio_pad_sleep_mode_51_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_mode[51].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_mode_51_qs) - ); - - - // Subregister 52 of Multireg mio_pad_sleep_mode - // R[mio_pad_sleep_mode_52]: V(False) - // Create REGWEN-gated WE signal - logic mio_pad_sleep_mode_52_gated_we; - assign mio_pad_sleep_mode_52_gated_we = mio_pad_sleep_mode_52_we & mio_pad_sleep_regwen_52_qs; - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h2) - ) u_mio_pad_sleep_mode_52 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_pad_sleep_mode_52_gated_we), - .wd (mio_pad_sleep_mode_52_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_pad_sleep_mode[52].q), - .ds (), - - // to register interface (read) - .qs (mio_pad_sleep_mode_52_qs) - ); - - // Subregister 0 of Multireg dio_pad_sleep_status // R[dio_pad_sleep_status_0]: V(False) // F[en_0]: 0:0 @@ -35004,6 +33853,162 @@ .qs (dio_pad_sleep_status_1_en_36_qs) ); + // F[en_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_1_en_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_37_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[37].de), + .d (hw2reg.dio_pad_sleep_status[37].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_37_qs) + ); + + // F[en_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_1_en_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_38_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[38].de), + .d (hw2reg.dio_pad_sleep_status[38].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_38_qs) + ); + + // F[en_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_1_en_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_39_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[39].de), + .d (hw2reg.dio_pad_sleep_status[39].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_39_qs) + ); + + // F[en_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_1_en_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_40_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[40].de), + .d (hw2reg.dio_pad_sleep_status[40].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_40_qs) + ); + + // F[en_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_1_en_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_41_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[41].de), + .d (hw2reg.dio_pad_sleep_status[41].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_41_qs) + ); + + // F[en_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0) + ) u_dio_pad_sleep_status_1_en_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_42_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[42].de), + .d (hw2reg.dio_pad_sleep_status[42].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_42_qs) + ); + // Subregister 0 of Multireg dio_pad_sleep_regwen // R[dio_pad_sleep_regwen_0]: V(False) @@ -36041,6 +35046,174 @@ ); + // Subregister 37 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_37_we), + .wd (dio_pad_sleep_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_38_we), + .wd (dio_pad_sleep_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_39_we), + .wd (dio_pad_sleep_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_40_we), + .wd (dio_pad_sleep_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_41_we), + .wd (dio_pad_sleep_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_dio_pad_sleep_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_42_we), + .wd (dio_pad_sleep_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_42_qs) + ); + + // Subregister 0 of Multireg dio_pad_sleep_en // R[dio_pad_sleep_en_0]: V(False) // Create REGWEN-gated WE signal @@ -37188,6 +36361,192 @@ ); + // Subregister 37 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_37]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_37_gated_we; + assign dio_pad_sleep_en_37_gated_we = dio_pad_sleep_en_37_we & dio_pad_sleep_regwen_37_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_37_gated_we), + .wd (dio_pad_sleep_en_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_38]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_38_gated_we; + assign dio_pad_sleep_en_38_gated_we = dio_pad_sleep_en_38_we & dio_pad_sleep_regwen_38_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_38_gated_we), + .wd (dio_pad_sleep_en_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_39]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_39_gated_we; + assign dio_pad_sleep_en_39_gated_we = dio_pad_sleep_en_39_we & dio_pad_sleep_regwen_39_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_39_gated_we), + .wd (dio_pad_sleep_en_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_40]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_40_gated_we; + assign dio_pad_sleep_en_40_gated_we = dio_pad_sleep_en_40_we & dio_pad_sleep_regwen_40_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_40_gated_we), + .wd (dio_pad_sleep_en_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_41]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_41_gated_we; + assign dio_pad_sleep_en_41_gated_we = dio_pad_sleep_en_41_we & dio_pad_sleep_regwen_41_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_41_gated_we), + .wd (dio_pad_sleep_en_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_42]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_42_gated_we; + assign dio_pad_sleep_en_42_gated_we = dio_pad_sleep_en_42_we & dio_pad_sleep_regwen_42_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0) + ) u_dio_pad_sleep_en_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_42_gated_we), + .wd (dio_pad_sleep_en_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_42_qs) + ); + + // Subregister 0 of Multireg dio_pad_sleep_mode // R[dio_pad_sleep_mode_0]: V(False) // Create REGWEN-gated WE signal @@ -38335,6 +37694,192 @@ ); + // Subregister 37 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_37]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_37_gated_we; + assign dio_pad_sleep_mode_37_gated_we = dio_pad_sleep_mode_37_we & dio_pad_sleep_regwen_37_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_37_gated_we), + .wd (dio_pad_sleep_mode_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_38]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_38_gated_we; + assign dio_pad_sleep_mode_38_gated_we = dio_pad_sleep_mode_38_we & dio_pad_sleep_regwen_38_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_38_gated_we), + .wd (dio_pad_sleep_mode_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_39]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_39_gated_we; + assign dio_pad_sleep_mode_39_gated_we = dio_pad_sleep_mode_39_we & dio_pad_sleep_regwen_39_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_39_gated_we), + .wd (dio_pad_sleep_mode_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_40]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_40_gated_we; + assign dio_pad_sleep_mode_40_gated_we = dio_pad_sleep_mode_40_we & dio_pad_sleep_regwen_40_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_40_gated_we), + .wd (dio_pad_sleep_mode_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_41]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_41_gated_we; + assign dio_pad_sleep_mode_41_gated_we = dio_pad_sleep_mode_41_we & dio_pad_sleep_regwen_41_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_41_gated_we), + .wd (dio_pad_sleep_mode_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_42]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_42_gated_we; + assign dio_pad_sleep_mode_42_gated_we = dio_pad_sleep_mode_42_we & dio_pad_sleep_regwen_42_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2) + ) u_dio_pad_sleep_mode_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_42_gated_we), + .wd (dio_pad_sleep_mode_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_42_qs) + ); + + // Subregister 0 of Multireg wkup_detector_regwen // R[wkup_detector_regwen_0]: V(False) prim_subreg #( @@ -40205,7 +39750,7 @@ - logic [717:0] addr_hit; + logic [703:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); @@ -40266,666 +39811,652 @@ addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET); addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET); addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET); - addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET); - addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); - addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); - addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); - addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); - addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); - addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); - addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); - addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); - addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); - addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); - addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); - addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); - addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); - addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); - addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); - addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); - addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); - addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); - addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); - addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); - addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); - addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); - addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); - addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); - addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); - addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); - addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); - addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); - addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); - addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); - addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); - addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); - addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); - addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); - addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); - addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); - addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); - addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); - addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); - addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); - addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); - addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); - addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); - addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); - addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); - addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); - addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); - addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); - addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); - addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); - addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); - addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); - addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); - addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); - addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); - addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); - addr_hit[115] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); - addr_hit[116] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_57_OFFSET); - addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); - addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); - addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); - addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); - addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); - addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); - addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); - addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); - addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); - addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); - addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); - addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); - addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); - addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); - addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); - addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); - addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); - addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); - addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); - addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); - addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); - addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); - addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); - addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); - addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); - addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); - addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); - addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); - addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_47_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_48_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_49_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_50_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_51_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_52_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_MIO_OUTSEL_47_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_MIO_OUTSEL_48_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_MIO_OUTSEL_49_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_MIO_OUTSEL_50_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_MIO_OUTSEL_51_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_MIO_OUTSEL_52_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); - addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); - addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); - addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); - addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_47_OFFSET); - addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_48_OFFSET); - addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_49_OFFSET); - addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_50_OFFSET); - addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_51_OFFSET); - addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_52_OFFSET); - addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); - addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); - addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); - addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); - addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); - addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); - addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); - addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); - addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); - addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); - addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); - addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); - addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); - addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); - addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); - addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); - addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); - addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); - addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); - addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); - addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); - addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); - addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); - addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); - addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); - addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); - addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); - addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); - addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); - addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); - addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); - addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); - addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); - addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); - addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); - addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); - addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); - addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); - addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); - addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); - addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); - addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); - addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); - addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); - addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); - addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); - addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); - addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_ATTR_47_OFFSET); - addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_ATTR_48_OFFSET); - addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_ATTR_49_OFFSET); - addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_ATTR_50_OFFSET); - addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_ATTR_51_OFFSET); - addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_ATTR_52_OFFSET); - addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET); - addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET); - addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET); - addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET); - addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET); - addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET); - addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET); - addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET); - addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET); - addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET); - addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET); - addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET); - addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET); - addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET); - addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET); - addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET); - addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET); - addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET); - addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET); - addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET); - addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET); - addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); - addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); - addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); - addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); - addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); - addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); - addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); - addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); - addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); - addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); - addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); - addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); - addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); - addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); - addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); - addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); - addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET); - addr_hit[383] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET); - addr_hit[384] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET); - addr_hit[385] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET); - addr_hit[386] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET); - addr_hit[387] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET); - addr_hit[388] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET); - addr_hit[389] = (reg_addr == PINMUX_DIO_PAD_ATTR_23_OFFSET); - addr_hit[390] = (reg_addr == PINMUX_DIO_PAD_ATTR_24_OFFSET); - addr_hit[391] = (reg_addr == PINMUX_DIO_PAD_ATTR_25_OFFSET); - addr_hit[392] = (reg_addr == PINMUX_DIO_PAD_ATTR_26_OFFSET); - addr_hit[393] = (reg_addr == PINMUX_DIO_PAD_ATTR_27_OFFSET); - addr_hit[394] = (reg_addr == PINMUX_DIO_PAD_ATTR_28_OFFSET); - addr_hit[395] = (reg_addr == PINMUX_DIO_PAD_ATTR_29_OFFSET); - addr_hit[396] = (reg_addr == PINMUX_DIO_PAD_ATTR_30_OFFSET); - addr_hit[397] = (reg_addr == PINMUX_DIO_PAD_ATTR_31_OFFSET); - addr_hit[398] = (reg_addr == PINMUX_DIO_PAD_ATTR_32_OFFSET); - addr_hit[399] = (reg_addr == PINMUX_DIO_PAD_ATTR_33_OFFSET); - addr_hit[400] = (reg_addr == PINMUX_DIO_PAD_ATTR_34_OFFSET); - addr_hit[401] = (reg_addr == PINMUX_DIO_PAD_ATTR_35_OFFSET); - addr_hit[402] = (reg_addr == PINMUX_DIO_PAD_ATTR_36_OFFSET); - addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); - addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); - addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); - addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); - addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); - addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); - addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); - addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); - addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); - addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); - addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); - addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); - addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); - addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); - addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); - addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); - addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); - addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); - addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); - addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); - addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); - addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); - addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); - addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); - addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); - addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); - addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); - addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); - addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); - addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); - addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); - addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); - addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); - addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_47_OFFSET); - addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_48_OFFSET); - addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_49_OFFSET); - addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_50_OFFSET); - addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_51_OFFSET); - addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_52_OFFSET); - addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); - addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); - addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); - addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); - addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); - addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); - addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); - addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); - addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); - addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); - addr_hit[484] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); - addr_hit[485] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); - addr_hit[486] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); - addr_hit[487] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); - addr_hit[488] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); - addr_hit[489] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); - addr_hit[490] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); - addr_hit[491] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); - addr_hit[492] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); - addr_hit[493] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); - addr_hit[494] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); - addr_hit[495] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); - addr_hit[496] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); - addr_hit[497] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); - addr_hit[498] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); - addr_hit[499] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); - addr_hit[500] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); - addr_hit[501] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); - addr_hit[502] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); - addr_hit[503] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); - addr_hit[504] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); - addr_hit[505] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_47_OFFSET); - addr_hit[506] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_48_OFFSET); - addr_hit[507] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_49_OFFSET); - addr_hit[508] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_50_OFFSET); - addr_hit[509] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_51_OFFSET); - addr_hit[510] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_52_OFFSET); - addr_hit[511] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[512] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[513] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[514] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[515] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[516] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[517] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[518] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[519] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[520] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[521] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[522] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[523] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[524] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[525] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[526] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[527] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); - addr_hit[528] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); - addr_hit[529] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); - addr_hit[530] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); - addr_hit[531] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); - addr_hit[532] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); - addr_hit[533] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); - addr_hit[534] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); - addr_hit[535] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); - addr_hit[536] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); - addr_hit[537] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); - addr_hit[538] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); - addr_hit[539] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); - addr_hit[540] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); - addr_hit[541] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); - addr_hit[542] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); - addr_hit[543] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); - addr_hit[544] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); - addr_hit[545] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); - addr_hit[546] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); - addr_hit[547] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); - addr_hit[548] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); - addr_hit[549] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); - addr_hit[550] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); - addr_hit[551] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); - addr_hit[552] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); - addr_hit[553] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); - addr_hit[554] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); - addr_hit[555] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); - addr_hit[556] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); - addr_hit[557] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); - addr_hit[558] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_47_OFFSET); - addr_hit[559] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_48_OFFSET); - addr_hit[560] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_49_OFFSET); - addr_hit[561] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_50_OFFSET); - addr_hit[562] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_51_OFFSET); - addr_hit[563] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_52_OFFSET); - addr_hit[564] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET); - addr_hit[565] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET); - addr_hit[566] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[567] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[568] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[569] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[570] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[571] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[572] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[573] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[574] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[575] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[576] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[577] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[578] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[579] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[580] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[581] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[582] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET); - addr_hit[583] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET); - addr_hit[584] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET); - addr_hit[585] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET); - addr_hit[586] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET); - addr_hit[587] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET); - addr_hit[588] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET); - addr_hit[589] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET); - addr_hit[590] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET); - addr_hit[591] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET); - addr_hit[592] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET); - addr_hit[593] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET); - addr_hit[594] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET); - addr_hit[595] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET); - addr_hit[596] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET); - addr_hit[597] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET); - addr_hit[598] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET); - addr_hit[599] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET); - addr_hit[600] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET); - addr_hit[601] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET); - addr_hit[602] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET); - addr_hit[603] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[604] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[605] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[606] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[607] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[608] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[609] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[610] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[611] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[612] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[613] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[614] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[615] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[616] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[617] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[618] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[619] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET); - addr_hit[620] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET); - addr_hit[621] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET); - addr_hit[622] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET); - addr_hit[623] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET); - addr_hit[624] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET); - addr_hit[625] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET); - addr_hit[626] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET); - addr_hit[627] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET); - addr_hit[628] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET); - addr_hit[629] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET); - addr_hit[630] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET); - addr_hit[631] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET); - addr_hit[632] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET); - addr_hit[633] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET); - addr_hit[634] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET); - addr_hit[635] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET); - addr_hit[636] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET); - addr_hit[637] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET); - addr_hit[638] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET); - addr_hit[639] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET); - addr_hit[640] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[641] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[642] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[643] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[644] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[645] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[646] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[647] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[648] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[649] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[650] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[651] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[652] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[653] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[654] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[655] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[656] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET); - addr_hit[657] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET); - addr_hit[658] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET); - addr_hit[659] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET); - addr_hit[660] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET); - addr_hit[661] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET); - addr_hit[662] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET); - addr_hit[663] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET); - addr_hit[664] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET); - addr_hit[665] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET); - addr_hit[666] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET); - addr_hit[667] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET); - addr_hit[668] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET); - addr_hit[669] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET); - addr_hit[670] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET); - addr_hit[671] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET); - addr_hit[672] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET); - addr_hit[673] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET); - addr_hit[674] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET); - addr_hit[675] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET); - addr_hit[676] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET); - addr_hit[677] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[678] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[679] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[680] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[681] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[682] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[683] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[684] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[685] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[686] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[687] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[688] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[689] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[690] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[691] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[692] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[693] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[694] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[695] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[696] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[697] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[698] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[699] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[700] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[701] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[702] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[703] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[704] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[705] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[706] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[707] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[708] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[709] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[710] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[711] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[712] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[713] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[714] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[715] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[716] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[717] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_ATTR_23_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_ATTR_24_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_ATTR_25_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_ATTR_26_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_ATTR_27_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_ATTR_28_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_ATTR_29_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_ATTR_30_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_ATTR_31_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_ATTR_32_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_ATTR_33_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_ATTR_34_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_ATTR_35_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_ATTR_36_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_DIO_PAD_ATTR_37_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_DIO_PAD_ATTR_38_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_DIO_PAD_ATTR_39_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_DIO_PAD_ATTR_40_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_DIO_PAD_ATTR_41_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_DIO_PAD_ATTR_42_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[503] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[504] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[505] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[506] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[507] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[508] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[509] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[510] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[511] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[512] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[513] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[514] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[515] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[516] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[517] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[518] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[519] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[520] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[521] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[522] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[523] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[524] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[525] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[526] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[527] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[528] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[529] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[530] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[531] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[533] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[534] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[535] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[536] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[537] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[538] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[539] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[540] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[541] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[542] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[543] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[544] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[545] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[546] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[547] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[548] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[549] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[550] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[551] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[552] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[553] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[554] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[555] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[556] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[557] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[558] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[559] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[560] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[561] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[562] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[563] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[564] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[565] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[566] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[567] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[568] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[569] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[570] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[571] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[572] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[573] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[574] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[575] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[576] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[577] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[578] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[579] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[580] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[581] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[582] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[583] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[584] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[585] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[586] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[587] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[588] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[589] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[590] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[591] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[592] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[593] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[594] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[595] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[596] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[597] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[598] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[599] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[600] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[601] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[602] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[603] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[604] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[605] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[606] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[607] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[608] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[609] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[610] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[611] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[612] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[613] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[614] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[615] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[616] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[617] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[618] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[619] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[620] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[621] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[622] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[623] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[624] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[625] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[626] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[627] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[628] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[629] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[630] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[631] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[632] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[633] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[634] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[635] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[636] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[637] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[638] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[639] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[640] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[641] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[642] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[643] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[644] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[645] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[646] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[647] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[648] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[649] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[650] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[651] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[652] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[653] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[654] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[655] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[656] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[657] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[658] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[659] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[660] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[661] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[662] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[663] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[664] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[665] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[666] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[667] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[668] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[669] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[670] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[671] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[672] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[673] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[674] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[675] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[676] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[677] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[678] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[679] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[680] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[681] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[682] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[683] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[684] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[685] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[686] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[687] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[688] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[689] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[690] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[691] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[692] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[693] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[694] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[695] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[696] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[697] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[698] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[699] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[700] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[701] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[702] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[703] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -41636,21 +41167,7 @@ (addr_hit[700] & (|(PINMUX_PERMIT[700] & ~reg_be))) | (addr_hit[701] & (|(PINMUX_PERMIT[701] & ~reg_be))) | (addr_hit[702] & (|(PINMUX_PERMIT[702] & ~reg_be))) | - (addr_hit[703] & (|(PINMUX_PERMIT[703] & ~reg_be))) | - (addr_hit[704] & (|(PINMUX_PERMIT[704] & ~reg_be))) | - (addr_hit[705] & (|(PINMUX_PERMIT[705] & ~reg_be))) | - (addr_hit[706] & (|(PINMUX_PERMIT[706] & ~reg_be))) | - (addr_hit[707] & (|(PINMUX_PERMIT[707] & ~reg_be))) | - (addr_hit[708] & (|(PINMUX_PERMIT[708] & ~reg_be))) | - (addr_hit[709] & (|(PINMUX_PERMIT[709] & ~reg_be))) | - (addr_hit[710] & (|(PINMUX_PERMIT[710] & ~reg_be))) | - (addr_hit[711] & (|(PINMUX_PERMIT[711] & ~reg_be))) | - (addr_hit[712] & (|(PINMUX_PERMIT[712] & ~reg_be))) | - (addr_hit[713] & (|(PINMUX_PERMIT[713] & ~reg_be))) | - (addr_hit[714] & (|(PINMUX_PERMIT[714] & ~reg_be))) | - (addr_hit[715] & (|(PINMUX_PERMIT[715] & ~reg_be))) | - (addr_hit[716] & (|(PINMUX_PERMIT[716] & ~reg_be))) | - (addr_hit[717] & (|(PINMUX_PERMIT[717] & ~reg_be))))); + (addr_hit[703] & (|(PINMUX_PERMIT[703] & ~reg_be))))); end // Generate write-enables @@ -41828,662 +41345,602 @@ assign mio_periph_insel_regwen_56_we = addr_hit[57] & reg_we & !reg_error; assign mio_periph_insel_regwen_56_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_57_we = addr_hit[58] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_57_wd = reg_wdata[0]; - assign mio_periph_insel_0_we = addr_hit[59] & reg_we & !reg_error; + assign mio_periph_insel_0_we = addr_hit[58] & reg_we & !reg_error; assign mio_periph_insel_0_wd = reg_wdata[5:0]; - assign mio_periph_insel_1_we = addr_hit[60] & reg_we & !reg_error; + assign mio_periph_insel_1_we = addr_hit[59] & reg_we & !reg_error; assign mio_periph_insel_1_wd = reg_wdata[5:0]; - assign mio_periph_insel_2_we = addr_hit[61] & reg_we & !reg_error; + assign mio_periph_insel_2_we = addr_hit[60] & reg_we & !reg_error; assign mio_periph_insel_2_wd = reg_wdata[5:0]; - assign mio_periph_insel_3_we = addr_hit[62] & reg_we & !reg_error; + assign mio_periph_insel_3_we = addr_hit[61] & reg_we & !reg_error; assign mio_periph_insel_3_wd = reg_wdata[5:0]; - assign mio_periph_insel_4_we = addr_hit[63] & reg_we & !reg_error; + assign mio_periph_insel_4_we = addr_hit[62] & reg_we & !reg_error; assign mio_periph_insel_4_wd = reg_wdata[5:0]; - assign mio_periph_insel_5_we = addr_hit[64] & reg_we & !reg_error; + assign mio_periph_insel_5_we = addr_hit[63] & reg_we & !reg_error; assign mio_periph_insel_5_wd = reg_wdata[5:0]; - assign mio_periph_insel_6_we = addr_hit[65] & reg_we & !reg_error; + assign mio_periph_insel_6_we = addr_hit[64] & reg_we & !reg_error; assign mio_periph_insel_6_wd = reg_wdata[5:0]; - assign mio_periph_insel_7_we = addr_hit[66] & reg_we & !reg_error; + assign mio_periph_insel_7_we = addr_hit[65] & reg_we & !reg_error; assign mio_periph_insel_7_wd = reg_wdata[5:0]; - assign mio_periph_insel_8_we = addr_hit[67] & reg_we & !reg_error; + assign mio_periph_insel_8_we = addr_hit[66] & reg_we & !reg_error; assign mio_periph_insel_8_wd = reg_wdata[5:0]; - assign mio_periph_insel_9_we = addr_hit[68] & reg_we & !reg_error; + assign mio_periph_insel_9_we = addr_hit[67] & reg_we & !reg_error; assign mio_periph_insel_9_wd = reg_wdata[5:0]; - assign mio_periph_insel_10_we = addr_hit[69] & reg_we & !reg_error; + assign mio_periph_insel_10_we = addr_hit[68] & reg_we & !reg_error; assign mio_periph_insel_10_wd = reg_wdata[5:0]; - assign mio_periph_insel_11_we = addr_hit[70] & reg_we & !reg_error; + assign mio_periph_insel_11_we = addr_hit[69] & reg_we & !reg_error; assign mio_periph_insel_11_wd = reg_wdata[5:0]; - assign mio_periph_insel_12_we = addr_hit[71] & reg_we & !reg_error; + assign mio_periph_insel_12_we = addr_hit[70] & reg_we & !reg_error; assign mio_periph_insel_12_wd = reg_wdata[5:0]; - assign mio_periph_insel_13_we = addr_hit[72] & reg_we & !reg_error; + assign mio_periph_insel_13_we = addr_hit[71] & reg_we & !reg_error; assign mio_periph_insel_13_wd = reg_wdata[5:0]; - assign mio_periph_insel_14_we = addr_hit[73] & reg_we & !reg_error; + assign mio_periph_insel_14_we = addr_hit[72] & reg_we & !reg_error; assign mio_periph_insel_14_wd = reg_wdata[5:0]; - assign mio_periph_insel_15_we = addr_hit[74] & reg_we & !reg_error; + assign mio_periph_insel_15_we = addr_hit[73] & reg_we & !reg_error; assign mio_periph_insel_15_wd = reg_wdata[5:0]; - assign mio_periph_insel_16_we = addr_hit[75] & reg_we & !reg_error; + assign mio_periph_insel_16_we = addr_hit[74] & reg_we & !reg_error; assign mio_periph_insel_16_wd = reg_wdata[5:0]; - assign mio_periph_insel_17_we = addr_hit[76] & reg_we & !reg_error; + assign mio_periph_insel_17_we = addr_hit[75] & reg_we & !reg_error; assign mio_periph_insel_17_wd = reg_wdata[5:0]; - assign mio_periph_insel_18_we = addr_hit[77] & reg_we & !reg_error; + assign mio_periph_insel_18_we = addr_hit[76] & reg_we & !reg_error; assign mio_periph_insel_18_wd = reg_wdata[5:0]; - assign mio_periph_insel_19_we = addr_hit[78] & reg_we & !reg_error; + assign mio_periph_insel_19_we = addr_hit[77] & reg_we & !reg_error; assign mio_periph_insel_19_wd = reg_wdata[5:0]; - assign mio_periph_insel_20_we = addr_hit[79] & reg_we & !reg_error; + assign mio_periph_insel_20_we = addr_hit[78] & reg_we & !reg_error; assign mio_periph_insel_20_wd = reg_wdata[5:0]; - assign mio_periph_insel_21_we = addr_hit[80] & reg_we & !reg_error; + assign mio_periph_insel_21_we = addr_hit[79] & reg_we & !reg_error; assign mio_periph_insel_21_wd = reg_wdata[5:0]; - assign mio_periph_insel_22_we = addr_hit[81] & reg_we & !reg_error; + assign mio_periph_insel_22_we = addr_hit[80] & reg_we & !reg_error; assign mio_periph_insel_22_wd = reg_wdata[5:0]; - assign mio_periph_insel_23_we = addr_hit[82] & reg_we & !reg_error; + assign mio_periph_insel_23_we = addr_hit[81] & reg_we & !reg_error; assign mio_periph_insel_23_wd = reg_wdata[5:0]; - assign mio_periph_insel_24_we = addr_hit[83] & reg_we & !reg_error; + assign mio_periph_insel_24_we = addr_hit[82] & reg_we & !reg_error; assign mio_periph_insel_24_wd = reg_wdata[5:0]; - assign mio_periph_insel_25_we = addr_hit[84] & reg_we & !reg_error; + assign mio_periph_insel_25_we = addr_hit[83] & reg_we & !reg_error; assign mio_periph_insel_25_wd = reg_wdata[5:0]; - assign mio_periph_insel_26_we = addr_hit[85] & reg_we & !reg_error; + assign mio_periph_insel_26_we = addr_hit[84] & reg_we & !reg_error; assign mio_periph_insel_26_wd = reg_wdata[5:0]; - assign mio_periph_insel_27_we = addr_hit[86] & reg_we & !reg_error; + assign mio_periph_insel_27_we = addr_hit[85] & reg_we & !reg_error; assign mio_periph_insel_27_wd = reg_wdata[5:0]; - assign mio_periph_insel_28_we = addr_hit[87] & reg_we & !reg_error; + assign mio_periph_insel_28_we = addr_hit[86] & reg_we & !reg_error; assign mio_periph_insel_28_wd = reg_wdata[5:0]; - assign mio_periph_insel_29_we = addr_hit[88] & reg_we & !reg_error; + assign mio_periph_insel_29_we = addr_hit[87] & reg_we & !reg_error; assign mio_periph_insel_29_wd = reg_wdata[5:0]; - assign mio_periph_insel_30_we = addr_hit[89] & reg_we & !reg_error; + assign mio_periph_insel_30_we = addr_hit[88] & reg_we & !reg_error; assign mio_periph_insel_30_wd = reg_wdata[5:0]; - assign mio_periph_insel_31_we = addr_hit[90] & reg_we & !reg_error; + assign mio_periph_insel_31_we = addr_hit[89] & reg_we & !reg_error; assign mio_periph_insel_31_wd = reg_wdata[5:0]; - assign mio_periph_insel_32_we = addr_hit[91] & reg_we & !reg_error; + assign mio_periph_insel_32_we = addr_hit[90] & reg_we & !reg_error; assign mio_periph_insel_32_wd = reg_wdata[5:0]; - assign mio_periph_insel_33_we = addr_hit[92] & reg_we & !reg_error; + assign mio_periph_insel_33_we = addr_hit[91] & reg_we & !reg_error; assign mio_periph_insel_33_wd = reg_wdata[5:0]; - assign mio_periph_insel_34_we = addr_hit[93] & reg_we & !reg_error; + assign mio_periph_insel_34_we = addr_hit[92] & reg_we & !reg_error; assign mio_periph_insel_34_wd = reg_wdata[5:0]; - assign mio_periph_insel_35_we = addr_hit[94] & reg_we & !reg_error; + assign mio_periph_insel_35_we = addr_hit[93] & reg_we & !reg_error; assign mio_periph_insel_35_wd = reg_wdata[5:0]; - assign mio_periph_insel_36_we = addr_hit[95] & reg_we & !reg_error; + assign mio_periph_insel_36_we = addr_hit[94] & reg_we & !reg_error; assign mio_periph_insel_36_wd = reg_wdata[5:0]; - assign mio_periph_insel_37_we = addr_hit[96] & reg_we & !reg_error; + assign mio_periph_insel_37_we = addr_hit[95] & reg_we & !reg_error; assign mio_periph_insel_37_wd = reg_wdata[5:0]; - assign mio_periph_insel_38_we = addr_hit[97] & reg_we & !reg_error; + assign mio_periph_insel_38_we = addr_hit[96] & reg_we & !reg_error; assign mio_periph_insel_38_wd = reg_wdata[5:0]; - assign mio_periph_insel_39_we = addr_hit[98] & reg_we & !reg_error; + assign mio_periph_insel_39_we = addr_hit[97] & reg_we & !reg_error; assign mio_periph_insel_39_wd = reg_wdata[5:0]; - assign mio_periph_insel_40_we = addr_hit[99] & reg_we & !reg_error; + assign mio_periph_insel_40_we = addr_hit[98] & reg_we & !reg_error; assign mio_periph_insel_40_wd = reg_wdata[5:0]; - assign mio_periph_insel_41_we = addr_hit[100] & reg_we & !reg_error; + assign mio_periph_insel_41_we = addr_hit[99] & reg_we & !reg_error; assign mio_periph_insel_41_wd = reg_wdata[5:0]; - assign mio_periph_insel_42_we = addr_hit[101] & reg_we & !reg_error; + assign mio_periph_insel_42_we = addr_hit[100] & reg_we & !reg_error; assign mio_periph_insel_42_wd = reg_wdata[5:0]; - assign mio_periph_insel_43_we = addr_hit[102] & reg_we & !reg_error; + assign mio_periph_insel_43_we = addr_hit[101] & reg_we & !reg_error; assign mio_periph_insel_43_wd = reg_wdata[5:0]; - assign mio_periph_insel_44_we = addr_hit[103] & reg_we & !reg_error; + assign mio_periph_insel_44_we = addr_hit[102] & reg_we & !reg_error; assign mio_periph_insel_44_wd = reg_wdata[5:0]; - assign mio_periph_insel_45_we = addr_hit[104] & reg_we & !reg_error; + assign mio_periph_insel_45_we = addr_hit[103] & reg_we & !reg_error; assign mio_periph_insel_45_wd = reg_wdata[5:0]; - assign mio_periph_insel_46_we = addr_hit[105] & reg_we & !reg_error; + assign mio_periph_insel_46_we = addr_hit[104] & reg_we & !reg_error; assign mio_periph_insel_46_wd = reg_wdata[5:0]; - assign mio_periph_insel_47_we = addr_hit[106] & reg_we & !reg_error; + assign mio_periph_insel_47_we = addr_hit[105] & reg_we & !reg_error; assign mio_periph_insel_47_wd = reg_wdata[5:0]; - assign mio_periph_insel_48_we = addr_hit[107] & reg_we & !reg_error; + assign mio_periph_insel_48_we = addr_hit[106] & reg_we & !reg_error; assign mio_periph_insel_48_wd = reg_wdata[5:0]; - assign mio_periph_insel_49_we = addr_hit[108] & reg_we & !reg_error; + assign mio_periph_insel_49_we = addr_hit[107] & reg_we & !reg_error; assign mio_periph_insel_49_wd = reg_wdata[5:0]; - assign mio_periph_insel_50_we = addr_hit[109] & reg_we & !reg_error; + assign mio_periph_insel_50_we = addr_hit[108] & reg_we & !reg_error; assign mio_periph_insel_50_wd = reg_wdata[5:0]; - assign mio_periph_insel_51_we = addr_hit[110] & reg_we & !reg_error; + assign mio_periph_insel_51_we = addr_hit[109] & reg_we & !reg_error; assign mio_periph_insel_51_wd = reg_wdata[5:0]; - assign mio_periph_insel_52_we = addr_hit[111] & reg_we & !reg_error; + assign mio_periph_insel_52_we = addr_hit[110] & reg_we & !reg_error; assign mio_periph_insel_52_wd = reg_wdata[5:0]; - assign mio_periph_insel_53_we = addr_hit[112] & reg_we & !reg_error; + assign mio_periph_insel_53_we = addr_hit[111] & reg_we & !reg_error; assign mio_periph_insel_53_wd = reg_wdata[5:0]; - assign mio_periph_insel_54_we = addr_hit[113] & reg_we & !reg_error; + assign mio_periph_insel_54_we = addr_hit[112] & reg_we & !reg_error; assign mio_periph_insel_54_wd = reg_wdata[5:0]; - assign mio_periph_insel_55_we = addr_hit[114] & reg_we & !reg_error; + assign mio_periph_insel_55_we = addr_hit[113] & reg_we & !reg_error; assign mio_periph_insel_55_wd = reg_wdata[5:0]; - assign mio_periph_insel_56_we = addr_hit[115] & reg_we & !reg_error; + assign mio_periph_insel_56_we = addr_hit[114] & reg_we & !reg_error; assign mio_periph_insel_56_wd = reg_wdata[5:0]; - assign mio_periph_insel_57_we = addr_hit[116] & reg_we & !reg_error; - - assign mio_periph_insel_57_wd = reg_wdata[5:0]; - assign mio_outsel_regwen_0_we = addr_hit[117] & reg_we & !reg_error; + assign mio_outsel_regwen_0_we = addr_hit[115] & reg_we & !reg_error; assign mio_outsel_regwen_0_wd = reg_wdata[0]; - assign mio_outsel_regwen_1_we = addr_hit[118] & reg_we & !reg_error; + assign mio_outsel_regwen_1_we = addr_hit[116] & reg_we & !reg_error; assign mio_outsel_regwen_1_wd = reg_wdata[0]; - assign mio_outsel_regwen_2_we = addr_hit[119] & reg_we & !reg_error; + assign mio_outsel_regwen_2_we = addr_hit[117] & reg_we & !reg_error; assign mio_outsel_regwen_2_wd = reg_wdata[0]; - assign mio_outsel_regwen_3_we = addr_hit[120] & reg_we & !reg_error; + assign mio_outsel_regwen_3_we = addr_hit[118] & reg_we & !reg_error; assign mio_outsel_regwen_3_wd = reg_wdata[0]; - assign mio_outsel_regwen_4_we = addr_hit[121] & reg_we & !reg_error; + assign mio_outsel_regwen_4_we = addr_hit[119] & reg_we & !reg_error; assign mio_outsel_regwen_4_wd = reg_wdata[0]; - assign mio_outsel_regwen_5_we = addr_hit[122] & reg_we & !reg_error; + assign mio_outsel_regwen_5_we = addr_hit[120] & reg_we & !reg_error; assign mio_outsel_regwen_5_wd = reg_wdata[0]; - assign mio_outsel_regwen_6_we = addr_hit[123] & reg_we & !reg_error; + assign mio_outsel_regwen_6_we = addr_hit[121] & reg_we & !reg_error; assign mio_outsel_regwen_6_wd = reg_wdata[0]; - assign mio_outsel_regwen_7_we = addr_hit[124] & reg_we & !reg_error; + assign mio_outsel_regwen_7_we = addr_hit[122] & reg_we & !reg_error; assign mio_outsel_regwen_7_wd = reg_wdata[0]; - assign mio_outsel_regwen_8_we = addr_hit[125] & reg_we & !reg_error; + assign mio_outsel_regwen_8_we = addr_hit[123] & reg_we & !reg_error; assign mio_outsel_regwen_8_wd = reg_wdata[0]; - assign mio_outsel_regwen_9_we = addr_hit[126] & reg_we & !reg_error; + assign mio_outsel_regwen_9_we = addr_hit[124] & reg_we & !reg_error; assign mio_outsel_regwen_9_wd = reg_wdata[0]; - assign mio_outsel_regwen_10_we = addr_hit[127] & reg_we & !reg_error; + assign mio_outsel_regwen_10_we = addr_hit[125] & reg_we & !reg_error; assign mio_outsel_regwen_10_wd = reg_wdata[0]; - assign mio_outsel_regwen_11_we = addr_hit[128] & reg_we & !reg_error; + assign mio_outsel_regwen_11_we = addr_hit[126] & reg_we & !reg_error; assign mio_outsel_regwen_11_wd = reg_wdata[0]; - assign mio_outsel_regwen_12_we = addr_hit[129] & reg_we & !reg_error; + assign mio_outsel_regwen_12_we = addr_hit[127] & reg_we & !reg_error; assign mio_outsel_regwen_12_wd = reg_wdata[0]; - assign mio_outsel_regwen_13_we = addr_hit[130] & reg_we & !reg_error; + assign mio_outsel_regwen_13_we = addr_hit[128] & reg_we & !reg_error; assign mio_outsel_regwen_13_wd = reg_wdata[0]; - assign mio_outsel_regwen_14_we = addr_hit[131] & reg_we & !reg_error; + assign mio_outsel_regwen_14_we = addr_hit[129] & reg_we & !reg_error; assign mio_outsel_regwen_14_wd = reg_wdata[0]; - assign mio_outsel_regwen_15_we = addr_hit[132] & reg_we & !reg_error; + assign mio_outsel_regwen_15_we = addr_hit[130] & reg_we & !reg_error; assign mio_outsel_regwen_15_wd = reg_wdata[0]; - assign mio_outsel_regwen_16_we = addr_hit[133] & reg_we & !reg_error; + assign mio_outsel_regwen_16_we = addr_hit[131] & reg_we & !reg_error; assign mio_outsel_regwen_16_wd = reg_wdata[0]; - assign mio_outsel_regwen_17_we = addr_hit[134] & reg_we & !reg_error; + assign mio_outsel_regwen_17_we = addr_hit[132] & reg_we & !reg_error; assign mio_outsel_regwen_17_wd = reg_wdata[0]; - assign mio_outsel_regwen_18_we = addr_hit[135] & reg_we & !reg_error; + assign mio_outsel_regwen_18_we = addr_hit[133] & reg_we & !reg_error; assign mio_outsel_regwen_18_wd = reg_wdata[0]; - assign mio_outsel_regwen_19_we = addr_hit[136] & reg_we & !reg_error; + assign mio_outsel_regwen_19_we = addr_hit[134] & reg_we & !reg_error; assign mio_outsel_regwen_19_wd = reg_wdata[0]; - assign mio_outsel_regwen_20_we = addr_hit[137] & reg_we & !reg_error; + assign mio_outsel_regwen_20_we = addr_hit[135] & reg_we & !reg_error; assign mio_outsel_regwen_20_wd = reg_wdata[0]; - assign mio_outsel_regwen_21_we = addr_hit[138] & reg_we & !reg_error; + assign mio_outsel_regwen_21_we = addr_hit[136] & reg_we & !reg_error; assign mio_outsel_regwen_21_wd = reg_wdata[0]; - assign mio_outsel_regwen_22_we = addr_hit[139] & reg_we & !reg_error; + assign mio_outsel_regwen_22_we = addr_hit[137] & reg_we & !reg_error; assign mio_outsel_regwen_22_wd = reg_wdata[0]; - assign mio_outsel_regwen_23_we = addr_hit[140] & reg_we & !reg_error; + assign mio_outsel_regwen_23_we = addr_hit[138] & reg_we & !reg_error; assign mio_outsel_regwen_23_wd = reg_wdata[0]; - assign mio_outsel_regwen_24_we = addr_hit[141] & reg_we & !reg_error; + assign mio_outsel_regwen_24_we = addr_hit[139] & reg_we & !reg_error; assign mio_outsel_regwen_24_wd = reg_wdata[0]; - assign mio_outsel_regwen_25_we = addr_hit[142] & reg_we & !reg_error; + assign mio_outsel_regwen_25_we = addr_hit[140] & reg_we & !reg_error; assign mio_outsel_regwen_25_wd = reg_wdata[0]; - assign mio_outsel_regwen_26_we = addr_hit[143] & reg_we & !reg_error; + assign mio_outsel_regwen_26_we = addr_hit[141] & reg_we & !reg_error; assign mio_outsel_regwen_26_wd = reg_wdata[0]; - assign mio_outsel_regwen_27_we = addr_hit[144] & reg_we & !reg_error; + assign mio_outsel_regwen_27_we = addr_hit[142] & reg_we & !reg_error; assign mio_outsel_regwen_27_wd = reg_wdata[0]; - assign mio_outsel_regwen_28_we = addr_hit[145] & reg_we & !reg_error; + assign mio_outsel_regwen_28_we = addr_hit[143] & reg_we & !reg_error; assign mio_outsel_regwen_28_wd = reg_wdata[0]; - assign mio_outsel_regwen_29_we = addr_hit[146] & reg_we & !reg_error; + assign mio_outsel_regwen_29_we = addr_hit[144] & reg_we & !reg_error; assign mio_outsel_regwen_29_wd = reg_wdata[0]; - assign mio_outsel_regwen_30_we = addr_hit[147] & reg_we & !reg_error; + assign mio_outsel_regwen_30_we = addr_hit[145] & reg_we & !reg_error; assign mio_outsel_regwen_30_wd = reg_wdata[0]; - assign mio_outsel_regwen_31_we = addr_hit[148] & reg_we & !reg_error; + assign mio_outsel_regwen_31_we = addr_hit[146] & reg_we & !reg_error; assign mio_outsel_regwen_31_wd = reg_wdata[0]; - assign mio_outsel_regwen_32_we = addr_hit[149] & reg_we & !reg_error; + assign mio_outsel_regwen_32_we = addr_hit[147] & reg_we & !reg_error; assign mio_outsel_regwen_32_wd = reg_wdata[0]; - assign mio_outsel_regwen_33_we = addr_hit[150] & reg_we & !reg_error; + assign mio_outsel_regwen_33_we = addr_hit[148] & reg_we & !reg_error; assign mio_outsel_regwen_33_wd = reg_wdata[0]; - assign mio_outsel_regwen_34_we = addr_hit[151] & reg_we & !reg_error; + assign mio_outsel_regwen_34_we = addr_hit[149] & reg_we & !reg_error; assign mio_outsel_regwen_34_wd = reg_wdata[0]; - assign mio_outsel_regwen_35_we = addr_hit[152] & reg_we & !reg_error; + assign mio_outsel_regwen_35_we = addr_hit[150] & reg_we & !reg_error; assign mio_outsel_regwen_35_wd = reg_wdata[0]; - assign mio_outsel_regwen_36_we = addr_hit[153] & reg_we & !reg_error; + assign mio_outsel_regwen_36_we = addr_hit[151] & reg_we & !reg_error; assign mio_outsel_regwen_36_wd = reg_wdata[0]; - assign mio_outsel_regwen_37_we = addr_hit[154] & reg_we & !reg_error; + assign mio_outsel_regwen_37_we = addr_hit[152] & reg_we & !reg_error; assign mio_outsel_regwen_37_wd = reg_wdata[0]; - assign mio_outsel_regwen_38_we = addr_hit[155] & reg_we & !reg_error; + assign mio_outsel_regwen_38_we = addr_hit[153] & reg_we & !reg_error; assign mio_outsel_regwen_38_wd = reg_wdata[0]; - assign mio_outsel_regwen_39_we = addr_hit[156] & reg_we & !reg_error; + assign mio_outsel_regwen_39_we = addr_hit[154] & reg_we & !reg_error; assign mio_outsel_regwen_39_wd = reg_wdata[0]; - assign mio_outsel_regwen_40_we = addr_hit[157] & reg_we & !reg_error; + assign mio_outsel_regwen_40_we = addr_hit[155] & reg_we & !reg_error; assign mio_outsel_regwen_40_wd = reg_wdata[0]; - assign mio_outsel_regwen_41_we = addr_hit[158] & reg_we & !reg_error; + assign mio_outsel_regwen_41_we = addr_hit[156] & reg_we & !reg_error; assign mio_outsel_regwen_41_wd = reg_wdata[0]; - assign mio_outsel_regwen_42_we = addr_hit[159] & reg_we & !reg_error; + assign mio_outsel_regwen_42_we = addr_hit[157] & reg_we & !reg_error; assign mio_outsel_regwen_42_wd = reg_wdata[0]; - assign mio_outsel_regwen_43_we = addr_hit[160] & reg_we & !reg_error; + assign mio_outsel_regwen_43_we = addr_hit[158] & reg_we & !reg_error; assign mio_outsel_regwen_43_wd = reg_wdata[0]; - assign mio_outsel_regwen_44_we = addr_hit[161] & reg_we & !reg_error; + assign mio_outsel_regwen_44_we = addr_hit[159] & reg_we & !reg_error; assign mio_outsel_regwen_44_wd = reg_wdata[0]; - assign mio_outsel_regwen_45_we = addr_hit[162] & reg_we & !reg_error; + assign mio_outsel_regwen_45_we = addr_hit[160] & reg_we & !reg_error; assign mio_outsel_regwen_45_wd = reg_wdata[0]; - assign mio_outsel_regwen_46_we = addr_hit[163] & reg_we & !reg_error; + assign mio_outsel_regwen_46_we = addr_hit[161] & reg_we & !reg_error; assign mio_outsel_regwen_46_wd = reg_wdata[0]; - assign mio_outsel_regwen_47_we = addr_hit[164] & reg_we & !reg_error; - - assign mio_outsel_regwen_47_wd = reg_wdata[0]; - assign mio_outsel_regwen_48_we = addr_hit[165] & reg_we & !reg_error; - - assign mio_outsel_regwen_48_wd = reg_wdata[0]; - assign mio_outsel_regwen_49_we = addr_hit[166] & reg_we & !reg_error; - - assign mio_outsel_regwen_49_wd = reg_wdata[0]; - assign mio_outsel_regwen_50_we = addr_hit[167] & reg_we & !reg_error; - - assign mio_outsel_regwen_50_wd = reg_wdata[0]; - assign mio_outsel_regwen_51_we = addr_hit[168] & reg_we & !reg_error; - - assign mio_outsel_regwen_51_wd = reg_wdata[0]; - assign mio_outsel_regwen_52_we = addr_hit[169] & reg_we & !reg_error; - - assign mio_outsel_regwen_52_wd = reg_wdata[0]; - assign mio_outsel_0_we = addr_hit[170] & reg_we & !reg_error; + assign mio_outsel_0_we = addr_hit[162] & reg_we & !reg_error; assign mio_outsel_0_wd = reg_wdata[6:0]; - assign mio_outsel_1_we = addr_hit[171] & reg_we & !reg_error; + assign mio_outsel_1_we = addr_hit[163] & reg_we & !reg_error; assign mio_outsel_1_wd = reg_wdata[6:0]; - assign mio_outsel_2_we = addr_hit[172] & reg_we & !reg_error; + assign mio_outsel_2_we = addr_hit[164] & reg_we & !reg_error; assign mio_outsel_2_wd = reg_wdata[6:0]; - assign mio_outsel_3_we = addr_hit[173] & reg_we & !reg_error; + assign mio_outsel_3_we = addr_hit[165] & reg_we & !reg_error; assign mio_outsel_3_wd = reg_wdata[6:0]; - assign mio_outsel_4_we = addr_hit[174] & reg_we & !reg_error; + assign mio_outsel_4_we = addr_hit[166] & reg_we & !reg_error; assign mio_outsel_4_wd = reg_wdata[6:0]; - assign mio_outsel_5_we = addr_hit[175] & reg_we & !reg_error; + assign mio_outsel_5_we = addr_hit[167] & reg_we & !reg_error; assign mio_outsel_5_wd = reg_wdata[6:0]; - assign mio_outsel_6_we = addr_hit[176] & reg_we & !reg_error; + assign mio_outsel_6_we = addr_hit[168] & reg_we & !reg_error; assign mio_outsel_6_wd = reg_wdata[6:0]; - assign mio_outsel_7_we = addr_hit[177] & reg_we & !reg_error; + assign mio_outsel_7_we = addr_hit[169] & reg_we & !reg_error; assign mio_outsel_7_wd = reg_wdata[6:0]; - assign mio_outsel_8_we = addr_hit[178] & reg_we & !reg_error; + assign mio_outsel_8_we = addr_hit[170] & reg_we & !reg_error; assign mio_outsel_8_wd = reg_wdata[6:0]; - assign mio_outsel_9_we = addr_hit[179] & reg_we & !reg_error; + assign mio_outsel_9_we = addr_hit[171] & reg_we & !reg_error; assign mio_outsel_9_wd = reg_wdata[6:0]; - assign mio_outsel_10_we = addr_hit[180] & reg_we & !reg_error; + assign mio_outsel_10_we = addr_hit[172] & reg_we & !reg_error; assign mio_outsel_10_wd = reg_wdata[6:0]; - assign mio_outsel_11_we = addr_hit[181] & reg_we & !reg_error; + assign mio_outsel_11_we = addr_hit[173] & reg_we & !reg_error; assign mio_outsel_11_wd = reg_wdata[6:0]; - assign mio_outsel_12_we = addr_hit[182] & reg_we & !reg_error; + assign mio_outsel_12_we = addr_hit[174] & reg_we & !reg_error; assign mio_outsel_12_wd = reg_wdata[6:0]; - assign mio_outsel_13_we = addr_hit[183] & reg_we & !reg_error; + assign mio_outsel_13_we = addr_hit[175] & reg_we & !reg_error; assign mio_outsel_13_wd = reg_wdata[6:0]; - assign mio_outsel_14_we = addr_hit[184] & reg_we & !reg_error; + assign mio_outsel_14_we = addr_hit[176] & reg_we & !reg_error; assign mio_outsel_14_wd = reg_wdata[6:0]; - assign mio_outsel_15_we = addr_hit[185] & reg_we & !reg_error; + assign mio_outsel_15_we = addr_hit[177] & reg_we & !reg_error; assign mio_outsel_15_wd = reg_wdata[6:0]; - assign mio_outsel_16_we = addr_hit[186] & reg_we & !reg_error; + assign mio_outsel_16_we = addr_hit[178] & reg_we & !reg_error; assign mio_outsel_16_wd = reg_wdata[6:0]; - assign mio_outsel_17_we = addr_hit[187] & reg_we & !reg_error; + assign mio_outsel_17_we = addr_hit[179] & reg_we & !reg_error; assign mio_outsel_17_wd = reg_wdata[6:0]; - assign mio_outsel_18_we = addr_hit[188] & reg_we & !reg_error; + assign mio_outsel_18_we = addr_hit[180] & reg_we & !reg_error; assign mio_outsel_18_wd = reg_wdata[6:0]; - assign mio_outsel_19_we = addr_hit[189] & reg_we & !reg_error; + assign mio_outsel_19_we = addr_hit[181] & reg_we & !reg_error; assign mio_outsel_19_wd = reg_wdata[6:0]; - assign mio_outsel_20_we = addr_hit[190] & reg_we & !reg_error; + assign mio_outsel_20_we = addr_hit[182] & reg_we & !reg_error; assign mio_outsel_20_wd = reg_wdata[6:0]; - assign mio_outsel_21_we = addr_hit[191] & reg_we & !reg_error; + assign mio_outsel_21_we = addr_hit[183] & reg_we & !reg_error; assign mio_outsel_21_wd = reg_wdata[6:0]; - assign mio_outsel_22_we = addr_hit[192] & reg_we & !reg_error; + assign mio_outsel_22_we = addr_hit[184] & reg_we & !reg_error; assign mio_outsel_22_wd = reg_wdata[6:0]; - assign mio_outsel_23_we = addr_hit[193] & reg_we & !reg_error; + assign mio_outsel_23_we = addr_hit[185] & reg_we & !reg_error; assign mio_outsel_23_wd = reg_wdata[6:0]; - assign mio_outsel_24_we = addr_hit[194] & reg_we & !reg_error; + assign mio_outsel_24_we = addr_hit[186] & reg_we & !reg_error; assign mio_outsel_24_wd = reg_wdata[6:0]; - assign mio_outsel_25_we = addr_hit[195] & reg_we & !reg_error; + assign mio_outsel_25_we = addr_hit[187] & reg_we & !reg_error; assign mio_outsel_25_wd = reg_wdata[6:0]; - assign mio_outsel_26_we = addr_hit[196] & reg_we & !reg_error; + assign mio_outsel_26_we = addr_hit[188] & reg_we & !reg_error; assign mio_outsel_26_wd = reg_wdata[6:0]; - assign mio_outsel_27_we = addr_hit[197] & reg_we & !reg_error; + assign mio_outsel_27_we = addr_hit[189] & reg_we & !reg_error; assign mio_outsel_27_wd = reg_wdata[6:0]; - assign mio_outsel_28_we = addr_hit[198] & reg_we & !reg_error; + assign mio_outsel_28_we = addr_hit[190] & reg_we & !reg_error; assign mio_outsel_28_wd = reg_wdata[6:0]; - assign mio_outsel_29_we = addr_hit[199] & reg_we & !reg_error; + assign mio_outsel_29_we = addr_hit[191] & reg_we & !reg_error; assign mio_outsel_29_wd = reg_wdata[6:0]; - assign mio_outsel_30_we = addr_hit[200] & reg_we & !reg_error; + assign mio_outsel_30_we = addr_hit[192] & reg_we & !reg_error; assign mio_outsel_30_wd = reg_wdata[6:0]; - assign mio_outsel_31_we = addr_hit[201] & reg_we & !reg_error; + assign mio_outsel_31_we = addr_hit[193] & reg_we & !reg_error; assign mio_outsel_31_wd = reg_wdata[6:0]; - assign mio_outsel_32_we = addr_hit[202] & reg_we & !reg_error; + assign mio_outsel_32_we = addr_hit[194] & reg_we & !reg_error; assign mio_outsel_32_wd = reg_wdata[6:0]; - assign mio_outsel_33_we = addr_hit[203] & reg_we & !reg_error; + assign mio_outsel_33_we = addr_hit[195] & reg_we & !reg_error; assign mio_outsel_33_wd = reg_wdata[6:0]; - assign mio_outsel_34_we = addr_hit[204] & reg_we & !reg_error; + assign mio_outsel_34_we = addr_hit[196] & reg_we & !reg_error; assign mio_outsel_34_wd = reg_wdata[6:0]; - assign mio_outsel_35_we = addr_hit[205] & reg_we & !reg_error; + assign mio_outsel_35_we = addr_hit[197] & reg_we & !reg_error; assign mio_outsel_35_wd = reg_wdata[6:0]; - assign mio_outsel_36_we = addr_hit[206] & reg_we & !reg_error; + assign mio_outsel_36_we = addr_hit[198] & reg_we & !reg_error; assign mio_outsel_36_wd = reg_wdata[6:0]; - assign mio_outsel_37_we = addr_hit[207] & reg_we & !reg_error; + assign mio_outsel_37_we = addr_hit[199] & reg_we & !reg_error; assign mio_outsel_37_wd = reg_wdata[6:0]; - assign mio_outsel_38_we = addr_hit[208] & reg_we & !reg_error; + assign mio_outsel_38_we = addr_hit[200] & reg_we & !reg_error; assign mio_outsel_38_wd = reg_wdata[6:0]; - assign mio_outsel_39_we = addr_hit[209] & reg_we & !reg_error; + assign mio_outsel_39_we = addr_hit[201] & reg_we & !reg_error; assign mio_outsel_39_wd = reg_wdata[6:0]; - assign mio_outsel_40_we = addr_hit[210] & reg_we & !reg_error; + assign mio_outsel_40_we = addr_hit[202] & reg_we & !reg_error; assign mio_outsel_40_wd = reg_wdata[6:0]; - assign mio_outsel_41_we = addr_hit[211] & reg_we & !reg_error; + assign mio_outsel_41_we = addr_hit[203] & reg_we & !reg_error; assign mio_outsel_41_wd = reg_wdata[6:0]; - assign mio_outsel_42_we = addr_hit[212] & reg_we & !reg_error; + assign mio_outsel_42_we = addr_hit[204] & reg_we & !reg_error; assign mio_outsel_42_wd = reg_wdata[6:0]; - assign mio_outsel_43_we = addr_hit[213] & reg_we & !reg_error; + assign mio_outsel_43_we = addr_hit[205] & reg_we & !reg_error; assign mio_outsel_43_wd = reg_wdata[6:0]; - assign mio_outsel_44_we = addr_hit[214] & reg_we & !reg_error; + assign mio_outsel_44_we = addr_hit[206] & reg_we & !reg_error; assign mio_outsel_44_wd = reg_wdata[6:0]; - assign mio_outsel_45_we = addr_hit[215] & reg_we & !reg_error; + assign mio_outsel_45_we = addr_hit[207] & reg_we & !reg_error; assign mio_outsel_45_wd = reg_wdata[6:0]; - assign mio_outsel_46_we = addr_hit[216] & reg_we & !reg_error; + assign mio_outsel_46_we = addr_hit[208] & reg_we & !reg_error; assign mio_outsel_46_wd = reg_wdata[6:0]; - assign mio_outsel_47_we = addr_hit[217] & reg_we & !reg_error; - - assign mio_outsel_47_wd = reg_wdata[6:0]; - assign mio_outsel_48_we = addr_hit[218] & reg_we & !reg_error; - - assign mio_outsel_48_wd = reg_wdata[6:0]; - assign mio_outsel_49_we = addr_hit[219] & reg_we & !reg_error; - - assign mio_outsel_49_wd = reg_wdata[6:0]; - assign mio_outsel_50_we = addr_hit[220] & reg_we & !reg_error; - - assign mio_outsel_50_wd = reg_wdata[6:0]; - assign mio_outsel_51_we = addr_hit[221] & reg_we & !reg_error; - - assign mio_outsel_51_wd = reg_wdata[6:0]; - assign mio_outsel_52_we = addr_hit[222] & reg_we & !reg_error; - - assign mio_outsel_52_wd = reg_wdata[6:0]; - assign mio_pad_attr_regwen_0_we = addr_hit[223] & reg_we & !reg_error; + assign mio_pad_attr_regwen_0_we = addr_hit[209] & reg_we & !reg_error; assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_1_we = addr_hit[224] & reg_we & !reg_error; + assign mio_pad_attr_regwen_1_we = addr_hit[210] & reg_we & !reg_error; assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_2_we = addr_hit[225] & reg_we & !reg_error; + assign mio_pad_attr_regwen_2_we = addr_hit[211] & reg_we & !reg_error; assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_3_we = addr_hit[226] & reg_we & !reg_error; + assign mio_pad_attr_regwen_3_we = addr_hit[212] & reg_we & !reg_error; assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_4_we = addr_hit[227] & reg_we & !reg_error; + assign mio_pad_attr_regwen_4_we = addr_hit[213] & reg_we & !reg_error; assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_5_we = addr_hit[228] & reg_we & !reg_error; + assign mio_pad_attr_regwen_5_we = addr_hit[214] & reg_we & !reg_error; assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_6_we = addr_hit[229] & reg_we & !reg_error; + assign mio_pad_attr_regwen_6_we = addr_hit[215] & reg_we & !reg_error; assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_7_we = addr_hit[230] & reg_we & !reg_error; + assign mio_pad_attr_regwen_7_we = addr_hit[216] & reg_we & !reg_error; assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_8_we = addr_hit[231] & reg_we & !reg_error; + assign mio_pad_attr_regwen_8_we = addr_hit[217] & reg_we & !reg_error; assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_9_we = addr_hit[232] & reg_we & !reg_error; + assign mio_pad_attr_regwen_9_we = addr_hit[218] & reg_we & !reg_error; assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_10_we = addr_hit[233] & reg_we & !reg_error; + assign mio_pad_attr_regwen_10_we = addr_hit[219] & reg_we & !reg_error; assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_11_we = addr_hit[234] & reg_we & !reg_error; + assign mio_pad_attr_regwen_11_we = addr_hit[220] & reg_we & !reg_error; assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_12_we = addr_hit[235] & reg_we & !reg_error; + assign mio_pad_attr_regwen_12_we = addr_hit[221] & reg_we & !reg_error; assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_13_we = addr_hit[236] & reg_we & !reg_error; + assign mio_pad_attr_regwen_13_we = addr_hit[222] & reg_we & !reg_error; assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_14_we = addr_hit[237] & reg_we & !reg_error; + assign mio_pad_attr_regwen_14_we = addr_hit[223] & reg_we & !reg_error; assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_15_we = addr_hit[238] & reg_we & !reg_error; + assign mio_pad_attr_regwen_15_we = addr_hit[224] & reg_we & !reg_error; assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_16_we = addr_hit[239] & reg_we & !reg_error; + assign mio_pad_attr_regwen_16_we = addr_hit[225] & reg_we & !reg_error; assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_17_we = addr_hit[240] & reg_we & !reg_error; + assign mio_pad_attr_regwen_17_we = addr_hit[226] & reg_we & !reg_error; assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_18_we = addr_hit[241] & reg_we & !reg_error; + assign mio_pad_attr_regwen_18_we = addr_hit[227] & reg_we & !reg_error; assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_19_we = addr_hit[242] & reg_we & !reg_error; + assign mio_pad_attr_regwen_19_we = addr_hit[228] & reg_we & !reg_error; assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_20_we = addr_hit[243] & reg_we & !reg_error; + assign mio_pad_attr_regwen_20_we = addr_hit[229] & reg_we & !reg_error; assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_21_we = addr_hit[244] & reg_we & !reg_error; + assign mio_pad_attr_regwen_21_we = addr_hit[230] & reg_we & !reg_error; assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_22_we = addr_hit[245] & reg_we & !reg_error; + assign mio_pad_attr_regwen_22_we = addr_hit[231] & reg_we & !reg_error; assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_23_we = addr_hit[246] & reg_we & !reg_error; + assign mio_pad_attr_regwen_23_we = addr_hit[232] & reg_we & !reg_error; assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_24_we = addr_hit[247] & reg_we & !reg_error; + assign mio_pad_attr_regwen_24_we = addr_hit[233] & reg_we & !reg_error; assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_25_we = addr_hit[248] & reg_we & !reg_error; + assign mio_pad_attr_regwen_25_we = addr_hit[234] & reg_we & !reg_error; assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_26_we = addr_hit[249] & reg_we & !reg_error; + assign mio_pad_attr_regwen_26_we = addr_hit[235] & reg_we & !reg_error; assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_27_we = addr_hit[250] & reg_we & !reg_error; + assign mio_pad_attr_regwen_27_we = addr_hit[236] & reg_we & !reg_error; assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_28_we = addr_hit[251] & reg_we & !reg_error; + assign mio_pad_attr_regwen_28_we = addr_hit[237] & reg_we & !reg_error; assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_29_we = addr_hit[252] & reg_we & !reg_error; + assign mio_pad_attr_regwen_29_we = addr_hit[238] & reg_we & !reg_error; assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_30_we = addr_hit[253] & reg_we & !reg_error; + assign mio_pad_attr_regwen_30_we = addr_hit[239] & reg_we & !reg_error; assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_31_we = addr_hit[254] & reg_we & !reg_error; + assign mio_pad_attr_regwen_31_we = addr_hit[240] & reg_we & !reg_error; assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_32_we = addr_hit[255] & reg_we & !reg_error; + assign mio_pad_attr_regwen_32_we = addr_hit[241] & reg_we & !reg_error; assign mio_pad_attr_regwen_32_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_33_we = addr_hit[256] & reg_we & !reg_error; + assign mio_pad_attr_regwen_33_we = addr_hit[242] & reg_we & !reg_error; assign mio_pad_attr_regwen_33_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_34_we = addr_hit[257] & reg_we & !reg_error; + assign mio_pad_attr_regwen_34_we = addr_hit[243] & reg_we & !reg_error; assign mio_pad_attr_regwen_34_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_35_we = addr_hit[258] & reg_we & !reg_error; + assign mio_pad_attr_regwen_35_we = addr_hit[244] & reg_we & !reg_error; assign mio_pad_attr_regwen_35_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_36_we = addr_hit[259] & reg_we & !reg_error; + assign mio_pad_attr_regwen_36_we = addr_hit[245] & reg_we & !reg_error; assign mio_pad_attr_regwen_36_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_37_we = addr_hit[260] & reg_we & !reg_error; + assign mio_pad_attr_regwen_37_we = addr_hit[246] & reg_we & !reg_error; assign mio_pad_attr_regwen_37_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_38_we = addr_hit[261] & reg_we & !reg_error; + assign mio_pad_attr_regwen_38_we = addr_hit[247] & reg_we & !reg_error; assign mio_pad_attr_regwen_38_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_39_we = addr_hit[262] & reg_we & !reg_error; + assign mio_pad_attr_regwen_39_we = addr_hit[248] & reg_we & !reg_error; assign mio_pad_attr_regwen_39_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_40_we = addr_hit[263] & reg_we & !reg_error; + assign mio_pad_attr_regwen_40_we = addr_hit[249] & reg_we & !reg_error; assign mio_pad_attr_regwen_40_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_41_we = addr_hit[264] & reg_we & !reg_error; + assign mio_pad_attr_regwen_41_we = addr_hit[250] & reg_we & !reg_error; assign mio_pad_attr_regwen_41_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_42_we = addr_hit[265] & reg_we & !reg_error; + assign mio_pad_attr_regwen_42_we = addr_hit[251] & reg_we & !reg_error; assign mio_pad_attr_regwen_42_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_43_we = addr_hit[266] & reg_we & !reg_error; + assign mio_pad_attr_regwen_43_we = addr_hit[252] & reg_we & !reg_error; assign mio_pad_attr_regwen_43_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_44_we = addr_hit[267] & reg_we & !reg_error; + assign mio_pad_attr_regwen_44_we = addr_hit[253] & reg_we & !reg_error; assign mio_pad_attr_regwen_44_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_45_we = addr_hit[268] & reg_we & !reg_error; + assign mio_pad_attr_regwen_45_we = addr_hit[254] & reg_we & !reg_error; assign mio_pad_attr_regwen_45_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_46_we = addr_hit[269] & reg_we & !reg_error; + assign mio_pad_attr_regwen_46_we = addr_hit[255] & reg_we & !reg_error; assign mio_pad_attr_regwen_46_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_47_we = addr_hit[270] & reg_we & !reg_error; - - assign mio_pad_attr_regwen_47_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_48_we = addr_hit[271] & reg_we & !reg_error; - - assign mio_pad_attr_regwen_48_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_49_we = addr_hit[272] & reg_we & !reg_error; - - assign mio_pad_attr_regwen_49_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_50_we = addr_hit[273] & reg_we & !reg_error; - - assign mio_pad_attr_regwen_50_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_51_we = addr_hit[274] & reg_we & !reg_error; - - assign mio_pad_attr_regwen_51_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_52_we = addr_hit[275] & reg_we & !reg_error; - - assign mio_pad_attr_regwen_52_wd = reg_wdata[0]; - assign mio_pad_attr_0_re = addr_hit[276] & reg_re & !reg_error; - assign mio_pad_attr_0_we = addr_hit[276] & reg_we & !reg_error; + assign mio_pad_attr_0_re = addr_hit[256] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[256] & reg_we & !reg_error; assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -42502,8 +41959,8 @@ assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign mio_pad_attr_1_re = addr_hit[277] & reg_re & !reg_error; - assign mio_pad_attr_1_we = addr_hit[277] & reg_we & !reg_error; + assign mio_pad_attr_1_re = addr_hit[257] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[257] & reg_we & !reg_error; assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -42522,8 +41979,8 @@ assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign mio_pad_attr_2_re = addr_hit[278] & reg_re & !reg_error; - assign mio_pad_attr_2_we = addr_hit[278] & reg_we & !reg_error; + assign mio_pad_attr_2_re = addr_hit[258] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[258] & reg_we & !reg_error; assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -42542,8 +41999,8 @@ assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign mio_pad_attr_3_re = addr_hit[279] & reg_re & !reg_error; - assign mio_pad_attr_3_we = addr_hit[279] & reg_we & !reg_error; + assign mio_pad_attr_3_re = addr_hit[259] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[259] & reg_we & !reg_error; assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -42562,8 +42019,8 @@ assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign mio_pad_attr_4_re = addr_hit[280] & reg_re & !reg_error; - assign mio_pad_attr_4_we = addr_hit[280] & reg_we & !reg_error; + assign mio_pad_attr_4_re = addr_hit[260] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[260] & reg_we & !reg_error; assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -42582,8 +42039,8 @@ assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign mio_pad_attr_5_re = addr_hit[281] & reg_re & !reg_error; - assign mio_pad_attr_5_we = addr_hit[281] & reg_we & !reg_error; + assign mio_pad_attr_5_re = addr_hit[261] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[261] & reg_we & !reg_error; assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -42602,8 +42059,8 @@ assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign mio_pad_attr_6_re = addr_hit[282] & reg_re & !reg_error; - assign mio_pad_attr_6_we = addr_hit[282] & reg_we & !reg_error; + assign mio_pad_attr_6_re = addr_hit[262] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[262] & reg_we & !reg_error; assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -42622,8 +42079,8 @@ assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign mio_pad_attr_7_re = addr_hit[283] & reg_re & !reg_error; - assign mio_pad_attr_7_we = addr_hit[283] & reg_we & !reg_error; + assign mio_pad_attr_7_re = addr_hit[263] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[263] & reg_we & !reg_error; assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -42642,8 +42099,8 @@ assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign mio_pad_attr_8_re = addr_hit[284] & reg_re & !reg_error; - assign mio_pad_attr_8_we = addr_hit[284] & reg_we & !reg_error; + assign mio_pad_attr_8_re = addr_hit[264] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[264] & reg_we & !reg_error; assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -42662,8 +42119,8 @@ assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign mio_pad_attr_9_re = addr_hit[285] & reg_re & !reg_error; - assign mio_pad_attr_9_we = addr_hit[285] & reg_we & !reg_error; + assign mio_pad_attr_9_re = addr_hit[265] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[265] & reg_we & !reg_error; assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -42682,8 +42139,8 @@ assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign mio_pad_attr_10_re = addr_hit[286] & reg_re & !reg_error; - assign mio_pad_attr_10_we = addr_hit[286] & reg_we & !reg_error; + assign mio_pad_attr_10_re = addr_hit[266] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[266] & reg_we & !reg_error; assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -42702,8 +42159,8 @@ assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign mio_pad_attr_11_re = addr_hit[287] & reg_re & !reg_error; - assign mio_pad_attr_11_we = addr_hit[287] & reg_we & !reg_error; + assign mio_pad_attr_11_re = addr_hit[267] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[267] & reg_we & !reg_error; assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -42722,8 +42179,8 @@ assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign mio_pad_attr_12_re = addr_hit[288] & reg_re & !reg_error; - assign mio_pad_attr_12_we = addr_hit[288] & reg_we & !reg_error; + assign mio_pad_attr_12_re = addr_hit[268] & reg_re & !reg_error; + assign mio_pad_attr_12_we = addr_hit[268] & reg_we & !reg_error; assign mio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -42742,8 +42199,8 @@ assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign mio_pad_attr_13_re = addr_hit[289] & reg_re & !reg_error; - assign mio_pad_attr_13_we = addr_hit[289] & reg_we & !reg_error; + assign mio_pad_attr_13_re = addr_hit[269] & reg_re & !reg_error; + assign mio_pad_attr_13_we = addr_hit[269] & reg_we & !reg_error; assign mio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -42762,8 +42219,8 @@ assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign mio_pad_attr_14_re = addr_hit[290] & reg_re & !reg_error; - assign mio_pad_attr_14_we = addr_hit[290] & reg_we & !reg_error; + assign mio_pad_attr_14_re = addr_hit[270] & reg_re & !reg_error; + assign mio_pad_attr_14_we = addr_hit[270] & reg_we & !reg_error; assign mio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -42782,8 +42239,8 @@ assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign mio_pad_attr_15_re = addr_hit[291] & reg_re & !reg_error; - assign mio_pad_attr_15_we = addr_hit[291] & reg_we & !reg_error; + assign mio_pad_attr_15_re = addr_hit[271] & reg_re & !reg_error; + assign mio_pad_attr_15_we = addr_hit[271] & reg_we & !reg_error; assign mio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -42802,8 +42259,8 @@ assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_attr_16_re = addr_hit[292] & reg_re & !reg_error; - assign mio_pad_attr_16_we = addr_hit[292] & reg_we & !reg_error; + assign mio_pad_attr_16_re = addr_hit[272] & reg_re & !reg_error; + assign mio_pad_attr_16_we = addr_hit[272] & reg_we & !reg_error; assign mio_pad_attr_16_invert_16_wd = reg_wdata[0]; @@ -42822,8 +42279,8 @@ assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; - assign mio_pad_attr_17_re = addr_hit[293] & reg_re & !reg_error; - assign mio_pad_attr_17_we = addr_hit[293] & reg_we & !reg_error; + assign mio_pad_attr_17_re = addr_hit[273] & reg_re & !reg_error; + assign mio_pad_attr_17_we = addr_hit[273] & reg_we & !reg_error; assign mio_pad_attr_17_invert_17_wd = reg_wdata[0]; @@ -42842,8 +42299,8 @@ assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; - assign mio_pad_attr_18_re = addr_hit[294] & reg_re & !reg_error; - assign mio_pad_attr_18_we = addr_hit[294] & reg_we & !reg_error; + assign mio_pad_attr_18_re = addr_hit[274] & reg_re & !reg_error; + assign mio_pad_attr_18_we = addr_hit[274] & reg_we & !reg_error; assign mio_pad_attr_18_invert_18_wd = reg_wdata[0]; @@ -42862,8 +42319,8 @@ assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; - assign mio_pad_attr_19_re = addr_hit[295] & reg_re & !reg_error; - assign mio_pad_attr_19_we = addr_hit[295] & reg_we & !reg_error; + assign mio_pad_attr_19_re = addr_hit[275] & reg_re & !reg_error; + assign mio_pad_attr_19_we = addr_hit[275] & reg_we & !reg_error; assign mio_pad_attr_19_invert_19_wd = reg_wdata[0]; @@ -42882,8 +42339,8 @@ assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; - assign mio_pad_attr_20_re = addr_hit[296] & reg_re & !reg_error; - assign mio_pad_attr_20_we = addr_hit[296] & reg_we & !reg_error; + assign mio_pad_attr_20_re = addr_hit[276] & reg_re & !reg_error; + assign mio_pad_attr_20_we = addr_hit[276] & reg_we & !reg_error; assign mio_pad_attr_20_invert_20_wd = reg_wdata[0]; @@ -42902,8 +42359,8 @@ assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; - assign mio_pad_attr_21_re = addr_hit[297] & reg_re & !reg_error; - assign mio_pad_attr_21_we = addr_hit[297] & reg_we & !reg_error; + assign mio_pad_attr_21_re = addr_hit[277] & reg_re & !reg_error; + assign mio_pad_attr_21_we = addr_hit[277] & reg_we & !reg_error; assign mio_pad_attr_21_invert_21_wd = reg_wdata[0]; @@ -42922,8 +42379,8 @@ assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; - assign mio_pad_attr_22_re = addr_hit[298] & reg_re & !reg_error; - assign mio_pad_attr_22_we = addr_hit[298] & reg_we & !reg_error; + assign mio_pad_attr_22_re = addr_hit[278] & reg_re & !reg_error; + assign mio_pad_attr_22_we = addr_hit[278] & reg_we & !reg_error; assign mio_pad_attr_22_invert_22_wd = reg_wdata[0]; @@ -42942,8 +42399,8 @@ assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; - assign mio_pad_attr_23_re = addr_hit[299] & reg_re & !reg_error; - assign mio_pad_attr_23_we = addr_hit[299] & reg_we & !reg_error; + assign mio_pad_attr_23_re = addr_hit[279] & reg_re & !reg_error; + assign mio_pad_attr_23_we = addr_hit[279] & reg_we & !reg_error; assign mio_pad_attr_23_invert_23_wd = reg_wdata[0]; @@ -42962,8 +42419,8 @@ assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; - assign mio_pad_attr_24_re = addr_hit[300] & reg_re & !reg_error; - assign mio_pad_attr_24_we = addr_hit[300] & reg_we & !reg_error; + assign mio_pad_attr_24_re = addr_hit[280] & reg_re & !reg_error; + assign mio_pad_attr_24_we = addr_hit[280] & reg_we & !reg_error; assign mio_pad_attr_24_invert_24_wd = reg_wdata[0]; @@ -42982,8 +42439,8 @@ assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; - assign mio_pad_attr_25_re = addr_hit[301] & reg_re & !reg_error; - assign mio_pad_attr_25_we = addr_hit[301] & reg_we & !reg_error; + assign mio_pad_attr_25_re = addr_hit[281] & reg_re & !reg_error; + assign mio_pad_attr_25_we = addr_hit[281] & reg_we & !reg_error; assign mio_pad_attr_25_invert_25_wd = reg_wdata[0]; @@ -43002,8 +42459,8 @@ assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; - assign mio_pad_attr_26_re = addr_hit[302] & reg_re & !reg_error; - assign mio_pad_attr_26_we = addr_hit[302] & reg_we & !reg_error; + assign mio_pad_attr_26_re = addr_hit[282] & reg_re & !reg_error; + assign mio_pad_attr_26_we = addr_hit[282] & reg_we & !reg_error; assign mio_pad_attr_26_invert_26_wd = reg_wdata[0]; @@ -43022,8 +42479,8 @@ assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; - assign mio_pad_attr_27_re = addr_hit[303] & reg_re & !reg_error; - assign mio_pad_attr_27_we = addr_hit[303] & reg_we & !reg_error; + assign mio_pad_attr_27_re = addr_hit[283] & reg_re & !reg_error; + assign mio_pad_attr_27_we = addr_hit[283] & reg_we & !reg_error; assign mio_pad_attr_27_invert_27_wd = reg_wdata[0]; @@ -43042,8 +42499,8 @@ assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; - assign mio_pad_attr_28_re = addr_hit[304] & reg_re & !reg_error; - assign mio_pad_attr_28_we = addr_hit[304] & reg_we & !reg_error; + assign mio_pad_attr_28_re = addr_hit[284] & reg_re & !reg_error; + assign mio_pad_attr_28_we = addr_hit[284] & reg_we & !reg_error; assign mio_pad_attr_28_invert_28_wd = reg_wdata[0]; @@ -43062,8 +42519,8 @@ assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; - assign mio_pad_attr_29_re = addr_hit[305] & reg_re & !reg_error; - assign mio_pad_attr_29_we = addr_hit[305] & reg_we & !reg_error; + assign mio_pad_attr_29_re = addr_hit[285] & reg_re & !reg_error; + assign mio_pad_attr_29_we = addr_hit[285] & reg_we & !reg_error; assign mio_pad_attr_29_invert_29_wd = reg_wdata[0]; @@ -43082,8 +42539,8 @@ assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; - assign mio_pad_attr_30_re = addr_hit[306] & reg_re & !reg_error; - assign mio_pad_attr_30_we = addr_hit[306] & reg_we & !reg_error; + assign mio_pad_attr_30_re = addr_hit[286] & reg_re & !reg_error; + assign mio_pad_attr_30_we = addr_hit[286] & reg_we & !reg_error; assign mio_pad_attr_30_invert_30_wd = reg_wdata[0]; @@ -43102,8 +42559,8 @@ assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; - assign mio_pad_attr_31_re = addr_hit[307] & reg_re & !reg_error; - assign mio_pad_attr_31_we = addr_hit[307] & reg_we & !reg_error; + assign mio_pad_attr_31_re = addr_hit[287] & reg_re & !reg_error; + assign mio_pad_attr_31_we = addr_hit[287] & reg_we & !reg_error; assign mio_pad_attr_31_invert_31_wd = reg_wdata[0]; @@ -43122,8 +42579,8 @@ assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; - assign mio_pad_attr_32_re = addr_hit[308] & reg_re & !reg_error; - assign mio_pad_attr_32_we = addr_hit[308] & reg_we & !reg_error; + assign mio_pad_attr_32_re = addr_hit[288] & reg_re & !reg_error; + assign mio_pad_attr_32_we = addr_hit[288] & reg_we & !reg_error; assign mio_pad_attr_32_invert_32_wd = reg_wdata[0]; @@ -43142,8 +42599,8 @@ assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; - assign mio_pad_attr_33_re = addr_hit[309] & reg_re & !reg_error; - assign mio_pad_attr_33_we = addr_hit[309] & reg_we & !reg_error; + assign mio_pad_attr_33_re = addr_hit[289] & reg_re & !reg_error; + assign mio_pad_attr_33_we = addr_hit[289] & reg_we & !reg_error; assign mio_pad_attr_33_invert_33_wd = reg_wdata[0]; @@ -43162,8 +42619,8 @@ assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; - assign mio_pad_attr_34_re = addr_hit[310] & reg_re & !reg_error; - assign mio_pad_attr_34_we = addr_hit[310] & reg_we & !reg_error; + assign mio_pad_attr_34_re = addr_hit[290] & reg_re & !reg_error; + assign mio_pad_attr_34_we = addr_hit[290] & reg_we & !reg_error; assign mio_pad_attr_34_invert_34_wd = reg_wdata[0]; @@ -43182,8 +42639,8 @@ assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; - assign mio_pad_attr_35_re = addr_hit[311] & reg_re & !reg_error; - assign mio_pad_attr_35_we = addr_hit[311] & reg_we & !reg_error; + assign mio_pad_attr_35_re = addr_hit[291] & reg_re & !reg_error; + assign mio_pad_attr_35_we = addr_hit[291] & reg_we & !reg_error; assign mio_pad_attr_35_invert_35_wd = reg_wdata[0]; @@ -43202,8 +42659,8 @@ assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; - assign mio_pad_attr_36_re = addr_hit[312] & reg_re & !reg_error; - assign mio_pad_attr_36_we = addr_hit[312] & reg_we & !reg_error; + assign mio_pad_attr_36_re = addr_hit[292] & reg_re & !reg_error; + assign mio_pad_attr_36_we = addr_hit[292] & reg_we & !reg_error; assign mio_pad_attr_36_invert_36_wd = reg_wdata[0]; @@ -43222,8 +42679,8 @@ assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; - assign mio_pad_attr_37_re = addr_hit[313] & reg_re & !reg_error; - assign mio_pad_attr_37_we = addr_hit[313] & reg_we & !reg_error; + assign mio_pad_attr_37_re = addr_hit[293] & reg_re & !reg_error; + assign mio_pad_attr_37_we = addr_hit[293] & reg_we & !reg_error; assign mio_pad_attr_37_invert_37_wd = reg_wdata[0]; @@ -43242,8 +42699,8 @@ assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; - assign mio_pad_attr_38_re = addr_hit[314] & reg_re & !reg_error; - assign mio_pad_attr_38_we = addr_hit[314] & reg_we & !reg_error; + assign mio_pad_attr_38_re = addr_hit[294] & reg_re & !reg_error; + assign mio_pad_attr_38_we = addr_hit[294] & reg_we & !reg_error; assign mio_pad_attr_38_invert_38_wd = reg_wdata[0]; @@ -43262,8 +42719,8 @@ assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; - assign mio_pad_attr_39_re = addr_hit[315] & reg_re & !reg_error; - assign mio_pad_attr_39_we = addr_hit[315] & reg_we & !reg_error; + assign mio_pad_attr_39_re = addr_hit[295] & reg_re & !reg_error; + assign mio_pad_attr_39_we = addr_hit[295] & reg_we & !reg_error; assign mio_pad_attr_39_invert_39_wd = reg_wdata[0]; @@ -43282,8 +42739,8 @@ assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; - assign mio_pad_attr_40_re = addr_hit[316] & reg_re & !reg_error; - assign mio_pad_attr_40_we = addr_hit[316] & reg_we & !reg_error; + assign mio_pad_attr_40_re = addr_hit[296] & reg_re & !reg_error; + assign mio_pad_attr_40_we = addr_hit[296] & reg_we & !reg_error; assign mio_pad_attr_40_invert_40_wd = reg_wdata[0]; @@ -43302,8 +42759,8 @@ assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; - assign mio_pad_attr_41_re = addr_hit[317] & reg_re & !reg_error; - assign mio_pad_attr_41_we = addr_hit[317] & reg_we & !reg_error; + assign mio_pad_attr_41_re = addr_hit[297] & reg_re & !reg_error; + assign mio_pad_attr_41_we = addr_hit[297] & reg_we & !reg_error; assign mio_pad_attr_41_invert_41_wd = reg_wdata[0]; @@ -43322,8 +42779,8 @@ assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; - assign mio_pad_attr_42_re = addr_hit[318] & reg_re & !reg_error; - assign mio_pad_attr_42_we = addr_hit[318] & reg_we & !reg_error; + assign mio_pad_attr_42_re = addr_hit[298] & reg_re & !reg_error; + assign mio_pad_attr_42_we = addr_hit[298] & reg_we & !reg_error; assign mio_pad_attr_42_invert_42_wd = reg_wdata[0]; @@ -43342,8 +42799,8 @@ assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; - assign mio_pad_attr_43_re = addr_hit[319] & reg_re & !reg_error; - assign mio_pad_attr_43_we = addr_hit[319] & reg_we & !reg_error; + assign mio_pad_attr_43_re = addr_hit[299] & reg_re & !reg_error; + assign mio_pad_attr_43_we = addr_hit[299] & reg_we & !reg_error; assign mio_pad_attr_43_invert_43_wd = reg_wdata[0]; @@ -43362,8 +42819,8 @@ assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; - assign mio_pad_attr_44_re = addr_hit[320] & reg_re & !reg_error; - assign mio_pad_attr_44_we = addr_hit[320] & reg_we & !reg_error; + assign mio_pad_attr_44_re = addr_hit[300] & reg_re & !reg_error; + assign mio_pad_attr_44_we = addr_hit[300] & reg_we & !reg_error; assign mio_pad_attr_44_invert_44_wd = reg_wdata[0]; @@ -43382,8 +42839,8 @@ assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; - assign mio_pad_attr_45_re = addr_hit[321] & reg_re & !reg_error; - assign mio_pad_attr_45_we = addr_hit[321] & reg_we & !reg_error; + assign mio_pad_attr_45_re = addr_hit[301] & reg_re & !reg_error; + assign mio_pad_attr_45_we = addr_hit[301] & reg_we & !reg_error; assign mio_pad_attr_45_invert_45_wd = reg_wdata[0]; @@ -43402,8 +42859,8 @@ assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; - assign mio_pad_attr_46_re = addr_hit[322] & reg_re & !reg_error; - assign mio_pad_attr_46_we = addr_hit[322] & reg_we & !reg_error; + assign mio_pad_attr_46_re = addr_hit[302] & reg_re & !reg_error; + assign mio_pad_attr_46_we = addr_hit[302] & reg_we & !reg_error; assign mio_pad_attr_46_invert_46_wd = reg_wdata[0]; @@ -43422,239 +42879,137 @@ assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; - assign mio_pad_attr_47_re = addr_hit[323] & reg_re & !reg_error; - assign mio_pad_attr_47_we = addr_hit[323] & reg_we & !reg_error; - - assign mio_pad_attr_47_invert_47_wd = reg_wdata[0]; - - assign mio_pad_attr_47_virtual_od_en_47_wd = reg_wdata[1]; - - assign mio_pad_attr_47_pull_en_47_wd = reg_wdata[2]; - - assign mio_pad_attr_47_pull_select_47_wd = reg_wdata[3]; - - assign mio_pad_attr_47_keeper_en_47_wd = reg_wdata[4]; - - assign mio_pad_attr_47_schmitt_en_47_wd = reg_wdata[5]; - - assign mio_pad_attr_47_od_en_47_wd = reg_wdata[6]; - - assign mio_pad_attr_47_slew_rate_47_wd = reg_wdata[17:16]; - - assign mio_pad_attr_47_drive_strength_47_wd = reg_wdata[23:20]; - assign mio_pad_attr_48_re = addr_hit[324] & reg_re & !reg_error; - assign mio_pad_attr_48_we = addr_hit[324] & reg_we & !reg_error; - - assign mio_pad_attr_48_invert_48_wd = reg_wdata[0]; - - assign mio_pad_attr_48_virtual_od_en_48_wd = reg_wdata[1]; - - assign mio_pad_attr_48_pull_en_48_wd = reg_wdata[2]; - - assign mio_pad_attr_48_pull_select_48_wd = reg_wdata[3]; - - assign mio_pad_attr_48_keeper_en_48_wd = reg_wdata[4]; - - assign mio_pad_attr_48_schmitt_en_48_wd = reg_wdata[5]; - - assign mio_pad_attr_48_od_en_48_wd = reg_wdata[6]; - - assign mio_pad_attr_48_slew_rate_48_wd = reg_wdata[17:16]; - - assign mio_pad_attr_48_drive_strength_48_wd = reg_wdata[23:20]; - assign mio_pad_attr_49_re = addr_hit[325] & reg_re & !reg_error; - assign mio_pad_attr_49_we = addr_hit[325] & reg_we & !reg_error; - - assign mio_pad_attr_49_invert_49_wd = reg_wdata[0]; - - assign mio_pad_attr_49_virtual_od_en_49_wd = reg_wdata[1]; - - assign mio_pad_attr_49_pull_en_49_wd = reg_wdata[2]; - - assign mio_pad_attr_49_pull_select_49_wd = reg_wdata[3]; - - assign mio_pad_attr_49_keeper_en_49_wd = reg_wdata[4]; - - assign mio_pad_attr_49_schmitt_en_49_wd = reg_wdata[5]; - - assign mio_pad_attr_49_od_en_49_wd = reg_wdata[6]; - - assign mio_pad_attr_49_slew_rate_49_wd = reg_wdata[17:16]; - - assign mio_pad_attr_49_drive_strength_49_wd = reg_wdata[23:20]; - assign mio_pad_attr_50_re = addr_hit[326] & reg_re & !reg_error; - assign mio_pad_attr_50_we = addr_hit[326] & reg_we & !reg_error; - - assign mio_pad_attr_50_invert_50_wd = reg_wdata[0]; - - assign mio_pad_attr_50_virtual_od_en_50_wd = reg_wdata[1]; - - assign mio_pad_attr_50_pull_en_50_wd = reg_wdata[2]; - - assign mio_pad_attr_50_pull_select_50_wd = reg_wdata[3]; - - assign mio_pad_attr_50_keeper_en_50_wd = reg_wdata[4]; - - assign mio_pad_attr_50_schmitt_en_50_wd = reg_wdata[5]; - - assign mio_pad_attr_50_od_en_50_wd = reg_wdata[6]; - - assign mio_pad_attr_50_slew_rate_50_wd = reg_wdata[17:16]; - - assign mio_pad_attr_50_drive_strength_50_wd = reg_wdata[23:20]; - assign mio_pad_attr_51_re = addr_hit[327] & reg_re & !reg_error; - assign mio_pad_attr_51_we = addr_hit[327] & reg_we & !reg_error; - - assign mio_pad_attr_51_invert_51_wd = reg_wdata[0]; - - assign mio_pad_attr_51_virtual_od_en_51_wd = reg_wdata[1]; - - assign mio_pad_attr_51_pull_en_51_wd = reg_wdata[2]; - - assign mio_pad_attr_51_pull_select_51_wd = reg_wdata[3]; - - assign mio_pad_attr_51_keeper_en_51_wd = reg_wdata[4]; - - assign mio_pad_attr_51_schmitt_en_51_wd = reg_wdata[5]; - - assign mio_pad_attr_51_od_en_51_wd = reg_wdata[6]; - - assign mio_pad_attr_51_slew_rate_51_wd = reg_wdata[17:16]; - - assign mio_pad_attr_51_drive_strength_51_wd = reg_wdata[23:20]; - assign mio_pad_attr_52_re = addr_hit[328] & reg_re & !reg_error; - assign mio_pad_attr_52_we = addr_hit[328] & reg_we & !reg_error; - - assign mio_pad_attr_52_invert_52_wd = reg_wdata[0]; - - assign mio_pad_attr_52_virtual_od_en_52_wd = reg_wdata[1]; - - assign mio_pad_attr_52_pull_en_52_wd = reg_wdata[2]; - - assign mio_pad_attr_52_pull_select_52_wd = reg_wdata[3]; - - assign mio_pad_attr_52_keeper_en_52_wd = reg_wdata[4]; - - assign mio_pad_attr_52_schmitt_en_52_wd = reg_wdata[5]; - - assign mio_pad_attr_52_od_en_52_wd = reg_wdata[6]; - - assign mio_pad_attr_52_slew_rate_52_wd = reg_wdata[17:16]; - - assign mio_pad_attr_52_drive_strength_52_wd = reg_wdata[23:20]; - assign dio_pad_attr_regwen_0_we = addr_hit[329] & reg_we & !reg_error; + assign dio_pad_attr_regwen_0_we = addr_hit[303] & reg_we & !reg_error; assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_1_we = addr_hit[330] & reg_we & !reg_error; + assign dio_pad_attr_regwen_1_we = addr_hit[304] & reg_we & !reg_error; assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_2_we = addr_hit[331] & reg_we & !reg_error; + assign dio_pad_attr_regwen_2_we = addr_hit[305] & reg_we & !reg_error; assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_3_we = addr_hit[332] & reg_we & !reg_error; + assign dio_pad_attr_regwen_3_we = addr_hit[306] & reg_we & !reg_error; assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_4_we = addr_hit[333] & reg_we & !reg_error; + assign dio_pad_attr_regwen_4_we = addr_hit[307] & reg_we & !reg_error; assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_5_we = addr_hit[334] & reg_we & !reg_error; + assign dio_pad_attr_regwen_5_we = addr_hit[308] & reg_we & !reg_error; assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_6_we = addr_hit[335] & reg_we & !reg_error; + assign dio_pad_attr_regwen_6_we = addr_hit[309] & reg_we & !reg_error; assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_7_we = addr_hit[336] & reg_we & !reg_error; + assign dio_pad_attr_regwen_7_we = addr_hit[310] & reg_we & !reg_error; assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_8_we = addr_hit[337] & reg_we & !reg_error; + assign dio_pad_attr_regwen_8_we = addr_hit[311] & reg_we & !reg_error; assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_9_we = addr_hit[338] & reg_we & !reg_error; + assign dio_pad_attr_regwen_9_we = addr_hit[312] & reg_we & !reg_error; assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_10_we = addr_hit[339] & reg_we & !reg_error; + assign dio_pad_attr_regwen_10_we = addr_hit[313] & reg_we & !reg_error; assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_11_we = addr_hit[340] & reg_we & !reg_error; + assign dio_pad_attr_regwen_11_we = addr_hit[314] & reg_we & !reg_error; assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_12_we = addr_hit[341] & reg_we & !reg_error; + assign dio_pad_attr_regwen_12_we = addr_hit[315] & reg_we & !reg_error; assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_13_we = addr_hit[342] & reg_we & !reg_error; + assign dio_pad_attr_regwen_13_we = addr_hit[316] & reg_we & !reg_error; assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_14_we = addr_hit[343] & reg_we & !reg_error; + assign dio_pad_attr_regwen_14_we = addr_hit[317] & reg_we & !reg_error; assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_15_we = addr_hit[344] & reg_we & !reg_error; + assign dio_pad_attr_regwen_15_we = addr_hit[318] & reg_we & !reg_error; assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_16_we = addr_hit[345] & reg_we & !reg_error; + assign dio_pad_attr_regwen_16_we = addr_hit[319] & reg_we & !reg_error; assign dio_pad_attr_regwen_16_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_17_we = addr_hit[346] & reg_we & !reg_error; + assign dio_pad_attr_regwen_17_we = addr_hit[320] & reg_we & !reg_error; assign dio_pad_attr_regwen_17_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_18_we = addr_hit[347] & reg_we & !reg_error; + assign dio_pad_attr_regwen_18_we = addr_hit[321] & reg_we & !reg_error; assign dio_pad_attr_regwen_18_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_19_we = addr_hit[348] & reg_we & !reg_error; + assign dio_pad_attr_regwen_19_we = addr_hit[322] & reg_we & !reg_error; assign dio_pad_attr_regwen_19_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_20_we = addr_hit[349] & reg_we & !reg_error; + assign dio_pad_attr_regwen_20_we = addr_hit[323] & reg_we & !reg_error; assign dio_pad_attr_regwen_20_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_21_we = addr_hit[350] & reg_we & !reg_error; + assign dio_pad_attr_regwen_21_we = addr_hit[324] & reg_we & !reg_error; assign dio_pad_attr_regwen_21_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_22_we = addr_hit[351] & reg_we & !reg_error; + assign dio_pad_attr_regwen_22_we = addr_hit[325] & reg_we & !reg_error; assign dio_pad_attr_regwen_22_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_23_we = addr_hit[352] & reg_we & !reg_error; + assign dio_pad_attr_regwen_23_we = addr_hit[326] & reg_we & !reg_error; assign dio_pad_attr_regwen_23_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_24_we = addr_hit[353] & reg_we & !reg_error; + assign dio_pad_attr_regwen_24_we = addr_hit[327] & reg_we & !reg_error; assign dio_pad_attr_regwen_24_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_25_we = addr_hit[354] & reg_we & !reg_error; + assign dio_pad_attr_regwen_25_we = addr_hit[328] & reg_we & !reg_error; assign dio_pad_attr_regwen_25_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_26_we = addr_hit[355] & reg_we & !reg_error; + assign dio_pad_attr_regwen_26_we = addr_hit[329] & reg_we & !reg_error; assign dio_pad_attr_regwen_26_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_27_we = addr_hit[356] & reg_we & !reg_error; + assign dio_pad_attr_regwen_27_we = addr_hit[330] & reg_we & !reg_error; assign dio_pad_attr_regwen_27_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_28_we = addr_hit[357] & reg_we & !reg_error; + assign dio_pad_attr_regwen_28_we = addr_hit[331] & reg_we & !reg_error; assign dio_pad_attr_regwen_28_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_29_we = addr_hit[358] & reg_we & !reg_error; + assign dio_pad_attr_regwen_29_we = addr_hit[332] & reg_we & !reg_error; assign dio_pad_attr_regwen_29_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_30_we = addr_hit[359] & reg_we & !reg_error; + assign dio_pad_attr_regwen_30_we = addr_hit[333] & reg_we & !reg_error; assign dio_pad_attr_regwen_30_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_31_we = addr_hit[360] & reg_we & !reg_error; + assign dio_pad_attr_regwen_31_we = addr_hit[334] & reg_we & !reg_error; assign dio_pad_attr_regwen_31_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_32_we = addr_hit[361] & reg_we & !reg_error; + assign dio_pad_attr_regwen_32_we = addr_hit[335] & reg_we & !reg_error; assign dio_pad_attr_regwen_32_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_33_we = addr_hit[362] & reg_we & !reg_error; + assign dio_pad_attr_regwen_33_we = addr_hit[336] & reg_we & !reg_error; assign dio_pad_attr_regwen_33_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_34_we = addr_hit[363] & reg_we & !reg_error; + assign dio_pad_attr_regwen_34_we = addr_hit[337] & reg_we & !reg_error; assign dio_pad_attr_regwen_34_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_35_we = addr_hit[364] & reg_we & !reg_error; + assign dio_pad_attr_regwen_35_we = addr_hit[338] & reg_we & !reg_error; assign dio_pad_attr_regwen_35_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_36_we = addr_hit[365] & reg_we & !reg_error; + assign dio_pad_attr_regwen_36_we = addr_hit[339] & reg_we & !reg_error; assign dio_pad_attr_regwen_36_wd = reg_wdata[0]; - assign dio_pad_attr_0_re = addr_hit[366] & reg_re & !reg_error; - assign dio_pad_attr_0_we = addr_hit[366] & reg_we & !reg_error; + assign dio_pad_attr_regwen_37_we = addr_hit[340] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_37_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_38_we = addr_hit[341] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_38_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_39_we = addr_hit[342] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_39_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_40_we = addr_hit[343] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_40_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_41_we = addr_hit[344] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_41_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_42_we = addr_hit[345] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_42_wd = reg_wdata[0]; + assign dio_pad_attr_0_re = addr_hit[346] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[346] & reg_we & !reg_error; assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -43673,8 +43028,8 @@ assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign dio_pad_attr_1_re = addr_hit[367] & reg_re & !reg_error; - assign dio_pad_attr_1_we = addr_hit[367] & reg_we & !reg_error; + assign dio_pad_attr_1_re = addr_hit[347] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[347] & reg_we & !reg_error; assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -43693,8 +43048,8 @@ assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign dio_pad_attr_2_re = addr_hit[368] & reg_re & !reg_error; - assign dio_pad_attr_2_we = addr_hit[368] & reg_we & !reg_error; + assign dio_pad_attr_2_re = addr_hit[348] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[348] & reg_we & !reg_error; assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -43713,8 +43068,8 @@ assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign dio_pad_attr_3_re = addr_hit[369] & reg_re & !reg_error; - assign dio_pad_attr_3_we = addr_hit[369] & reg_we & !reg_error; + assign dio_pad_attr_3_re = addr_hit[349] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[349] & reg_we & !reg_error; assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -43733,8 +43088,8 @@ assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign dio_pad_attr_4_re = addr_hit[370] & reg_re & !reg_error; - assign dio_pad_attr_4_we = addr_hit[370] & reg_we & !reg_error; + assign dio_pad_attr_4_re = addr_hit[350] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[350] & reg_we & !reg_error; assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -43753,8 +43108,8 @@ assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign dio_pad_attr_5_re = addr_hit[371] & reg_re & !reg_error; - assign dio_pad_attr_5_we = addr_hit[371] & reg_we & !reg_error; + assign dio_pad_attr_5_re = addr_hit[351] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[351] & reg_we & !reg_error; assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -43773,8 +43128,8 @@ assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign dio_pad_attr_6_re = addr_hit[372] & reg_re & !reg_error; - assign dio_pad_attr_6_we = addr_hit[372] & reg_we & !reg_error; + assign dio_pad_attr_6_re = addr_hit[352] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[352] & reg_we & !reg_error; assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -43793,8 +43148,8 @@ assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign dio_pad_attr_7_re = addr_hit[373] & reg_re & !reg_error; - assign dio_pad_attr_7_we = addr_hit[373] & reg_we & !reg_error; + assign dio_pad_attr_7_re = addr_hit[353] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[353] & reg_we & !reg_error; assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -43813,8 +43168,8 @@ assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign dio_pad_attr_8_re = addr_hit[374] & reg_re & !reg_error; - assign dio_pad_attr_8_we = addr_hit[374] & reg_we & !reg_error; + assign dio_pad_attr_8_re = addr_hit[354] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[354] & reg_we & !reg_error; assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -43833,8 +43188,8 @@ assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign dio_pad_attr_9_re = addr_hit[375] & reg_re & !reg_error; - assign dio_pad_attr_9_we = addr_hit[375] & reg_we & !reg_error; + assign dio_pad_attr_9_re = addr_hit[355] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[355] & reg_we & !reg_error; assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -43853,8 +43208,8 @@ assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign dio_pad_attr_10_re = addr_hit[376] & reg_re & !reg_error; - assign dio_pad_attr_10_we = addr_hit[376] & reg_we & !reg_error; + assign dio_pad_attr_10_re = addr_hit[356] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[356] & reg_we & !reg_error; assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -43873,8 +43228,8 @@ assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign dio_pad_attr_11_re = addr_hit[377] & reg_re & !reg_error; - assign dio_pad_attr_11_we = addr_hit[377] & reg_we & !reg_error; + assign dio_pad_attr_11_re = addr_hit[357] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[357] & reg_we & !reg_error; assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -43893,8 +43248,8 @@ assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign dio_pad_attr_12_re = addr_hit[378] & reg_re & !reg_error; - assign dio_pad_attr_12_we = addr_hit[378] & reg_we & !reg_error; + assign dio_pad_attr_12_re = addr_hit[358] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[358] & reg_we & !reg_error; assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -43913,8 +43268,8 @@ assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign dio_pad_attr_13_re = addr_hit[379] & reg_re & !reg_error; - assign dio_pad_attr_13_we = addr_hit[379] & reg_we & !reg_error; + assign dio_pad_attr_13_re = addr_hit[359] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[359] & reg_we & !reg_error; assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -43933,8 +43288,8 @@ assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign dio_pad_attr_14_re = addr_hit[380] & reg_re & !reg_error; - assign dio_pad_attr_14_we = addr_hit[380] & reg_we & !reg_error; + assign dio_pad_attr_14_re = addr_hit[360] & reg_re & !reg_error; + assign dio_pad_attr_14_we = addr_hit[360] & reg_we & !reg_error; assign dio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -43953,8 +43308,8 @@ assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign dio_pad_attr_15_re = addr_hit[381] & reg_re & !reg_error; - assign dio_pad_attr_15_we = addr_hit[381] & reg_we & !reg_error; + assign dio_pad_attr_15_re = addr_hit[361] & reg_re & !reg_error; + assign dio_pad_attr_15_we = addr_hit[361] & reg_we & !reg_error; assign dio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -43973,8 +43328,8 @@ assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign dio_pad_attr_16_re = addr_hit[382] & reg_re & !reg_error; - assign dio_pad_attr_16_we = addr_hit[382] & reg_we & !reg_error; + assign dio_pad_attr_16_re = addr_hit[362] & reg_re & !reg_error; + assign dio_pad_attr_16_we = addr_hit[362] & reg_we & !reg_error; assign dio_pad_attr_16_invert_16_wd = reg_wdata[0]; @@ -43993,8 +43348,8 @@ assign dio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; assign dio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; - assign dio_pad_attr_17_re = addr_hit[383] & reg_re & !reg_error; - assign dio_pad_attr_17_we = addr_hit[383] & reg_we & !reg_error; + assign dio_pad_attr_17_re = addr_hit[363] & reg_re & !reg_error; + assign dio_pad_attr_17_we = addr_hit[363] & reg_we & !reg_error; assign dio_pad_attr_17_invert_17_wd = reg_wdata[0]; @@ -44013,8 +43368,8 @@ assign dio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; assign dio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; - assign dio_pad_attr_18_re = addr_hit[384] & reg_re & !reg_error; - assign dio_pad_attr_18_we = addr_hit[384] & reg_we & !reg_error; + assign dio_pad_attr_18_re = addr_hit[364] & reg_re & !reg_error; + assign dio_pad_attr_18_we = addr_hit[364] & reg_we & !reg_error; assign dio_pad_attr_18_invert_18_wd = reg_wdata[0]; @@ -44033,8 +43388,8 @@ assign dio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; assign dio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; - assign dio_pad_attr_19_re = addr_hit[385] & reg_re & !reg_error; - assign dio_pad_attr_19_we = addr_hit[385] & reg_we & !reg_error; + assign dio_pad_attr_19_re = addr_hit[365] & reg_re & !reg_error; + assign dio_pad_attr_19_we = addr_hit[365] & reg_we & !reg_error; assign dio_pad_attr_19_invert_19_wd = reg_wdata[0]; @@ -44053,8 +43408,8 @@ assign dio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; assign dio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; - assign dio_pad_attr_20_re = addr_hit[386] & reg_re & !reg_error; - assign dio_pad_attr_20_we = addr_hit[386] & reg_we & !reg_error; + assign dio_pad_attr_20_re = addr_hit[366] & reg_re & !reg_error; + assign dio_pad_attr_20_we = addr_hit[366] & reg_we & !reg_error; assign dio_pad_attr_20_invert_20_wd = reg_wdata[0]; @@ -44073,8 +43428,8 @@ assign dio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; assign dio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; - assign dio_pad_attr_21_re = addr_hit[387] & reg_re & !reg_error; - assign dio_pad_attr_21_we = addr_hit[387] & reg_we & !reg_error; + assign dio_pad_attr_21_re = addr_hit[367] & reg_re & !reg_error; + assign dio_pad_attr_21_we = addr_hit[367] & reg_we & !reg_error; assign dio_pad_attr_21_invert_21_wd = reg_wdata[0]; @@ -44093,8 +43448,8 @@ assign dio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; assign dio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; - assign dio_pad_attr_22_re = addr_hit[388] & reg_re & !reg_error; - assign dio_pad_attr_22_we = addr_hit[388] & reg_we & !reg_error; + assign dio_pad_attr_22_re = addr_hit[368] & reg_re & !reg_error; + assign dio_pad_attr_22_we = addr_hit[368] & reg_we & !reg_error; assign dio_pad_attr_22_invert_22_wd = reg_wdata[0]; @@ -44113,8 +43468,8 @@ assign dio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; assign dio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; - assign dio_pad_attr_23_re = addr_hit[389] & reg_re & !reg_error; - assign dio_pad_attr_23_we = addr_hit[389] & reg_we & !reg_error; + assign dio_pad_attr_23_re = addr_hit[369] & reg_re & !reg_error; + assign dio_pad_attr_23_we = addr_hit[369] & reg_we & !reg_error; assign dio_pad_attr_23_invert_23_wd = reg_wdata[0]; @@ -44133,8 +43488,8 @@ assign dio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; assign dio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; - assign dio_pad_attr_24_re = addr_hit[390] & reg_re & !reg_error; - assign dio_pad_attr_24_we = addr_hit[390] & reg_we & !reg_error; + assign dio_pad_attr_24_re = addr_hit[370] & reg_re & !reg_error; + assign dio_pad_attr_24_we = addr_hit[370] & reg_we & !reg_error; assign dio_pad_attr_24_invert_24_wd = reg_wdata[0]; @@ -44153,8 +43508,8 @@ assign dio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; assign dio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; - assign dio_pad_attr_25_re = addr_hit[391] & reg_re & !reg_error; - assign dio_pad_attr_25_we = addr_hit[391] & reg_we & !reg_error; + assign dio_pad_attr_25_re = addr_hit[371] & reg_re & !reg_error; + assign dio_pad_attr_25_we = addr_hit[371] & reg_we & !reg_error; assign dio_pad_attr_25_invert_25_wd = reg_wdata[0]; @@ -44173,8 +43528,8 @@ assign dio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; assign dio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; - assign dio_pad_attr_26_re = addr_hit[392] & reg_re & !reg_error; - assign dio_pad_attr_26_we = addr_hit[392] & reg_we & !reg_error; + assign dio_pad_attr_26_re = addr_hit[372] & reg_re & !reg_error; + assign dio_pad_attr_26_we = addr_hit[372] & reg_we & !reg_error; assign dio_pad_attr_26_invert_26_wd = reg_wdata[0]; @@ -44193,8 +43548,8 @@ assign dio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; assign dio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; - assign dio_pad_attr_27_re = addr_hit[393] & reg_re & !reg_error; - assign dio_pad_attr_27_we = addr_hit[393] & reg_we & !reg_error; + assign dio_pad_attr_27_re = addr_hit[373] & reg_re & !reg_error; + assign dio_pad_attr_27_we = addr_hit[373] & reg_we & !reg_error; assign dio_pad_attr_27_invert_27_wd = reg_wdata[0]; @@ -44213,8 +43568,8 @@ assign dio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; assign dio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; - assign dio_pad_attr_28_re = addr_hit[394] & reg_re & !reg_error; - assign dio_pad_attr_28_we = addr_hit[394] & reg_we & !reg_error; + assign dio_pad_attr_28_re = addr_hit[374] & reg_re & !reg_error; + assign dio_pad_attr_28_we = addr_hit[374] & reg_we & !reg_error; assign dio_pad_attr_28_invert_28_wd = reg_wdata[0]; @@ -44233,8 +43588,8 @@ assign dio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; assign dio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; - assign dio_pad_attr_29_re = addr_hit[395] & reg_re & !reg_error; - assign dio_pad_attr_29_we = addr_hit[395] & reg_we & !reg_error; + assign dio_pad_attr_29_re = addr_hit[375] & reg_re & !reg_error; + assign dio_pad_attr_29_we = addr_hit[375] & reg_we & !reg_error; assign dio_pad_attr_29_invert_29_wd = reg_wdata[0]; @@ -44253,8 +43608,8 @@ assign dio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; assign dio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; - assign dio_pad_attr_30_re = addr_hit[396] & reg_re & !reg_error; - assign dio_pad_attr_30_we = addr_hit[396] & reg_we & !reg_error; + assign dio_pad_attr_30_re = addr_hit[376] & reg_re & !reg_error; + assign dio_pad_attr_30_we = addr_hit[376] & reg_we & !reg_error; assign dio_pad_attr_30_invert_30_wd = reg_wdata[0]; @@ -44273,8 +43628,8 @@ assign dio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; assign dio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; - assign dio_pad_attr_31_re = addr_hit[397] & reg_re & !reg_error; - assign dio_pad_attr_31_we = addr_hit[397] & reg_we & !reg_error; + assign dio_pad_attr_31_re = addr_hit[377] & reg_re & !reg_error; + assign dio_pad_attr_31_we = addr_hit[377] & reg_we & !reg_error; assign dio_pad_attr_31_invert_31_wd = reg_wdata[0]; @@ -44293,8 +43648,8 @@ assign dio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; assign dio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; - assign dio_pad_attr_32_re = addr_hit[398] & reg_re & !reg_error; - assign dio_pad_attr_32_we = addr_hit[398] & reg_we & !reg_error; + assign dio_pad_attr_32_re = addr_hit[378] & reg_re & !reg_error; + assign dio_pad_attr_32_we = addr_hit[378] & reg_we & !reg_error; assign dio_pad_attr_32_invert_32_wd = reg_wdata[0]; @@ -44313,8 +43668,8 @@ assign dio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; assign dio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; - assign dio_pad_attr_33_re = addr_hit[399] & reg_re & !reg_error; - assign dio_pad_attr_33_we = addr_hit[399] & reg_we & !reg_error; + assign dio_pad_attr_33_re = addr_hit[379] & reg_re & !reg_error; + assign dio_pad_attr_33_we = addr_hit[379] & reg_we & !reg_error; assign dio_pad_attr_33_invert_33_wd = reg_wdata[0]; @@ -44333,8 +43688,8 @@ assign dio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; assign dio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; - assign dio_pad_attr_34_re = addr_hit[400] & reg_re & !reg_error; - assign dio_pad_attr_34_we = addr_hit[400] & reg_we & !reg_error; + assign dio_pad_attr_34_re = addr_hit[380] & reg_re & !reg_error; + assign dio_pad_attr_34_we = addr_hit[380] & reg_we & !reg_error; assign dio_pad_attr_34_invert_34_wd = reg_wdata[0]; @@ -44353,8 +43708,8 @@ assign dio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; assign dio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; - assign dio_pad_attr_35_re = addr_hit[401] & reg_re & !reg_error; - assign dio_pad_attr_35_we = addr_hit[401] & reg_we & !reg_error; + assign dio_pad_attr_35_re = addr_hit[381] & reg_re & !reg_error; + assign dio_pad_attr_35_we = addr_hit[381] & reg_we & !reg_error; assign dio_pad_attr_35_invert_35_wd = reg_wdata[0]; @@ -44373,8 +43728,8 @@ assign dio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; assign dio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; - assign dio_pad_attr_36_re = addr_hit[402] & reg_re & !reg_error; - assign dio_pad_attr_36_we = addr_hit[402] & reg_we & !reg_error; + assign dio_pad_attr_36_re = addr_hit[382] & reg_re & !reg_error; + assign dio_pad_attr_36_we = addr_hit[382] & reg_we & !reg_error; assign dio_pad_attr_36_invert_36_wd = reg_wdata[0]; @@ -44393,7 +43748,127 @@ assign dio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; assign dio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; - assign mio_pad_sleep_status_0_we = addr_hit[403] & reg_we & !reg_error; + assign dio_pad_attr_37_re = addr_hit[383] & reg_re & !reg_error; + assign dio_pad_attr_37_we = addr_hit[383] & reg_we & !reg_error; + + assign dio_pad_attr_37_invert_37_wd = reg_wdata[0]; + + assign dio_pad_attr_37_virtual_od_en_37_wd = reg_wdata[1]; + + assign dio_pad_attr_37_pull_en_37_wd = reg_wdata[2]; + + assign dio_pad_attr_37_pull_select_37_wd = reg_wdata[3]; + + assign dio_pad_attr_37_keeper_en_37_wd = reg_wdata[4]; + + assign dio_pad_attr_37_schmitt_en_37_wd = reg_wdata[5]; + + assign dio_pad_attr_37_od_en_37_wd = reg_wdata[6]; + + assign dio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; + + assign dio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; + assign dio_pad_attr_38_re = addr_hit[384] & reg_re & !reg_error; + assign dio_pad_attr_38_we = addr_hit[384] & reg_we & !reg_error; + + assign dio_pad_attr_38_invert_38_wd = reg_wdata[0]; + + assign dio_pad_attr_38_virtual_od_en_38_wd = reg_wdata[1]; + + assign dio_pad_attr_38_pull_en_38_wd = reg_wdata[2]; + + assign dio_pad_attr_38_pull_select_38_wd = reg_wdata[3]; + + assign dio_pad_attr_38_keeper_en_38_wd = reg_wdata[4]; + + assign dio_pad_attr_38_schmitt_en_38_wd = reg_wdata[5]; + + assign dio_pad_attr_38_od_en_38_wd = reg_wdata[6]; + + assign dio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; + + assign dio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; + assign dio_pad_attr_39_re = addr_hit[385] & reg_re & !reg_error; + assign dio_pad_attr_39_we = addr_hit[385] & reg_we & !reg_error; + + assign dio_pad_attr_39_invert_39_wd = reg_wdata[0]; + + assign dio_pad_attr_39_virtual_od_en_39_wd = reg_wdata[1]; + + assign dio_pad_attr_39_pull_en_39_wd = reg_wdata[2]; + + assign dio_pad_attr_39_pull_select_39_wd = reg_wdata[3]; + + assign dio_pad_attr_39_keeper_en_39_wd = reg_wdata[4]; + + assign dio_pad_attr_39_schmitt_en_39_wd = reg_wdata[5]; + + assign dio_pad_attr_39_od_en_39_wd = reg_wdata[6]; + + assign dio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; + + assign dio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; + assign dio_pad_attr_40_re = addr_hit[386] & reg_re & !reg_error; + assign dio_pad_attr_40_we = addr_hit[386] & reg_we & !reg_error; + + assign dio_pad_attr_40_invert_40_wd = reg_wdata[0]; + + assign dio_pad_attr_40_virtual_od_en_40_wd = reg_wdata[1]; + + assign dio_pad_attr_40_pull_en_40_wd = reg_wdata[2]; + + assign dio_pad_attr_40_pull_select_40_wd = reg_wdata[3]; + + assign dio_pad_attr_40_keeper_en_40_wd = reg_wdata[4]; + + assign dio_pad_attr_40_schmitt_en_40_wd = reg_wdata[5]; + + assign dio_pad_attr_40_od_en_40_wd = reg_wdata[6]; + + assign dio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; + + assign dio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; + assign dio_pad_attr_41_re = addr_hit[387] & reg_re & !reg_error; + assign dio_pad_attr_41_we = addr_hit[387] & reg_we & !reg_error; + + assign dio_pad_attr_41_invert_41_wd = reg_wdata[0]; + + assign dio_pad_attr_41_virtual_od_en_41_wd = reg_wdata[1]; + + assign dio_pad_attr_41_pull_en_41_wd = reg_wdata[2]; + + assign dio_pad_attr_41_pull_select_41_wd = reg_wdata[3]; + + assign dio_pad_attr_41_keeper_en_41_wd = reg_wdata[4]; + + assign dio_pad_attr_41_schmitt_en_41_wd = reg_wdata[5]; + + assign dio_pad_attr_41_od_en_41_wd = reg_wdata[6]; + + assign dio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; + + assign dio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; + assign dio_pad_attr_42_re = addr_hit[388] & reg_re & !reg_error; + assign dio_pad_attr_42_we = addr_hit[388] & reg_we & !reg_error; + + assign dio_pad_attr_42_invert_42_wd = reg_wdata[0]; + + assign dio_pad_attr_42_virtual_od_en_42_wd = reg_wdata[1]; + + assign dio_pad_attr_42_pull_en_42_wd = reg_wdata[2]; + + assign dio_pad_attr_42_pull_select_42_wd = reg_wdata[3]; + + assign dio_pad_attr_42_keeper_en_42_wd = reg_wdata[4]; + + assign dio_pad_attr_42_schmitt_en_42_wd = reg_wdata[5]; + + assign dio_pad_attr_42_od_en_42_wd = reg_wdata[6]; + + assign dio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; + + assign dio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; + assign mio_pad_sleep_status_0_we = addr_hit[389] & reg_we & !reg_error; assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; @@ -44458,7 +43933,7 @@ assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; - assign mio_pad_sleep_status_1_we = addr_hit[404] & reg_we & !reg_error; + assign mio_pad_sleep_status_1_we = addr_hit[390] & reg_we & !reg_error; assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; @@ -44489,496 +43964,430 @@ assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; - - assign mio_pad_sleep_status_1_en_47_wd = reg_wdata[15]; - - assign mio_pad_sleep_status_1_en_48_wd = reg_wdata[16]; - - assign mio_pad_sleep_status_1_en_49_wd = reg_wdata[17]; - - assign mio_pad_sleep_status_1_en_50_wd = reg_wdata[18]; - - assign mio_pad_sleep_status_1_en_51_wd = reg_wdata[19]; - - assign mio_pad_sleep_status_1_en_52_wd = reg_wdata[20]; - assign mio_pad_sleep_regwen_0_we = addr_hit[405] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_0_we = addr_hit[391] & reg_we & !reg_error; assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_1_we = addr_hit[406] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_1_we = addr_hit[392] & reg_we & !reg_error; assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_2_we = addr_hit[407] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_2_we = addr_hit[393] & reg_we & !reg_error; assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_3_we = addr_hit[408] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_3_we = addr_hit[394] & reg_we & !reg_error; assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_4_we = addr_hit[409] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_4_we = addr_hit[395] & reg_we & !reg_error; assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_5_we = addr_hit[410] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_5_we = addr_hit[396] & reg_we & !reg_error; assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_6_we = addr_hit[411] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_6_we = addr_hit[397] & reg_we & !reg_error; assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_7_we = addr_hit[412] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_7_we = addr_hit[398] & reg_we & !reg_error; assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_8_we = addr_hit[413] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_8_we = addr_hit[399] & reg_we & !reg_error; assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_9_we = addr_hit[414] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_9_we = addr_hit[400] & reg_we & !reg_error; assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_10_we = addr_hit[415] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_10_we = addr_hit[401] & reg_we & !reg_error; assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_11_we = addr_hit[416] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_11_we = addr_hit[402] & reg_we & !reg_error; assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_12_we = addr_hit[417] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_12_we = addr_hit[403] & reg_we & !reg_error; assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_13_we = addr_hit[418] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_13_we = addr_hit[404] & reg_we & !reg_error; assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_14_we = addr_hit[419] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_14_we = addr_hit[405] & reg_we & !reg_error; assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_15_we = addr_hit[420] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_15_we = addr_hit[406] & reg_we & !reg_error; assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_16_we = addr_hit[421] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_16_we = addr_hit[407] & reg_we & !reg_error; assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_17_we = addr_hit[422] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_17_we = addr_hit[408] & reg_we & !reg_error; assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_18_we = addr_hit[423] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_18_we = addr_hit[409] & reg_we & !reg_error; assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_19_we = addr_hit[424] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_19_we = addr_hit[410] & reg_we & !reg_error; assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_20_we = addr_hit[425] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_20_we = addr_hit[411] & reg_we & !reg_error; assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_21_we = addr_hit[426] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_21_we = addr_hit[412] & reg_we & !reg_error; assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_22_we = addr_hit[427] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_22_we = addr_hit[413] & reg_we & !reg_error; assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_23_we = addr_hit[428] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_23_we = addr_hit[414] & reg_we & !reg_error; assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_24_we = addr_hit[429] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_24_we = addr_hit[415] & reg_we & !reg_error; assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_25_we = addr_hit[430] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_25_we = addr_hit[416] & reg_we & !reg_error; assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_26_we = addr_hit[431] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_26_we = addr_hit[417] & reg_we & !reg_error; assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_27_we = addr_hit[432] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_27_we = addr_hit[418] & reg_we & !reg_error; assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_28_we = addr_hit[433] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_28_we = addr_hit[419] & reg_we & !reg_error; assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_29_we = addr_hit[434] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_29_we = addr_hit[420] & reg_we & !reg_error; assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_30_we = addr_hit[435] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_30_we = addr_hit[421] & reg_we & !reg_error; assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_31_we = addr_hit[436] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_31_we = addr_hit[422] & reg_we & !reg_error; assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_32_we = addr_hit[437] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_32_we = addr_hit[423] & reg_we & !reg_error; assign mio_pad_sleep_regwen_32_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_33_we = addr_hit[438] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_33_we = addr_hit[424] & reg_we & !reg_error; assign mio_pad_sleep_regwen_33_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_34_we = addr_hit[439] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_34_we = addr_hit[425] & reg_we & !reg_error; assign mio_pad_sleep_regwen_34_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_35_we = addr_hit[440] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_35_we = addr_hit[426] & reg_we & !reg_error; assign mio_pad_sleep_regwen_35_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_36_we = addr_hit[441] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_36_we = addr_hit[427] & reg_we & !reg_error; assign mio_pad_sleep_regwen_36_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_37_we = addr_hit[442] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_37_we = addr_hit[428] & reg_we & !reg_error; assign mio_pad_sleep_regwen_37_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_38_we = addr_hit[443] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_38_we = addr_hit[429] & reg_we & !reg_error; assign mio_pad_sleep_regwen_38_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_39_we = addr_hit[444] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_39_we = addr_hit[430] & reg_we & !reg_error; assign mio_pad_sleep_regwen_39_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_40_we = addr_hit[445] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_40_we = addr_hit[431] & reg_we & !reg_error; assign mio_pad_sleep_regwen_40_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_41_we = addr_hit[446] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_41_we = addr_hit[432] & reg_we & !reg_error; assign mio_pad_sleep_regwen_41_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_42_we = addr_hit[447] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_42_we = addr_hit[433] & reg_we & !reg_error; assign mio_pad_sleep_regwen_42_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_43_we = addr_hit[448] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_43_we = addr_hit[434] & reg_we & !reg_error; assign mio_pad_sleep_regwen_43_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_44_we = addr_hit[449] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_44_we = addr_hit[435] & reg_we & !reg_error; assign mio_pad_sleep_regwen_44_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_45_we = addr_hit[450] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_45_we = addr_hit[436] & reg_we & !reg_error; assign mio_pad_sleep_regwen_45_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_46_we = addr_hit[451] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_46_we = addr_hit[437] & reg_we & !reg_error; assign mio_pad_sleep_regwen_46_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_47_we = addr_hit[452] & reg_we & !reg_error; - - assign mio_pad_sleep_regwen_47_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_48_we = addr_hit[453] & reg_we & !reg_error; - - assign mio_pad_sleep_regwen_48_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_49_we = addr_hit[454] & reg_we & !reg_error; - - assign mio_pad_sleep_regwen_49_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_50_we = addr_hit[455] & reg_we & !reg_error; - - assign mio_pad_sleep_regwen_50_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_51_we = addr_hit[456] & reg_we & !reg_error; - - assign mio_pad_sleep_regwen_51_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_52_we = addr_hit[457] & reg_we & !reg_error; - - assign mio_pad_sleep_regwen_52_wd = reg_wdata[0]; - assign mio_pad_sleep_en_0_we = addr_hit[458] & reg_we & !reg_error; + assign mio_pad_sleep_en_0_we = addr_hit[438] & reg_we & !reg_error; assign mio_pad_sleep_en_0_wd = reg_wdata[0]; - assign mio_pad_sleep_en_1_we = addr_hit[459] & reg_we & !reg_error; + assign mio_pad_sleep_en_1_we = addr_hit[439] & reg_we & !reg_error; assign mio_pad_sleep_en_1_wd = reg_wdata[0]; - assign mio_pad_sleep_en_2_we = addr_hit[460] & reg_we & !reg_error; + assign mio_pad_sleep_en_2_we = addr_hit[440] & reg_we & !reg_error; assign mio_pad_sleep_en_2_wd = reg_wdata[0]; - assign mio_pad_sleep_en_3_we = addr_hit[461] & reg_we & !reg_error; + assign mio_pad_sleep_en_3_we = addr_hit[441] & reg_we & !reg_error; assign mio_pad_sleep_en_3_wd = reg_wdata[0]; - assign mio_pad_sleep_en_4_we = addr_hit[462] & reg_we & !reg_error; + assign mio_pad_sleep_en_4_we = addr_hit[442] & reg_we & !reg_error; assign mio_pad_sleep_en_4_wd = reg_wdata[0]; - assign mio_pad_sleep_en_5_we = addr_hit[463] & reg_we & !reg_error; + assign mio_pad_sleep_en_5_we = addr_hit[443] & reg_we & !reg_error; assign mio_pad_sleep_en_5_wd = reg_wdata[0]; - assign mio_pad_sleep_en_6_we = addr_hit[464] & reg_we & !reg_error; + assign mio_pad_sleep_en_6_we = addr_hit[444] & reg_we & !reg_error; assign mio_pad_sleep_en_6_wd = reg_wdata[0]; - assign mio_pad_sleep_en_7_we = addr_hit[465] & reg_we & !reg_error; + assign mio_pad_sleep_en_7_we = addr_hit[445] & reg_we & !reg_error; assign mio_pad_sleep_en_7_wd = reg_wdata[0]; - assign mio_pad_sleep_en_8_we = addr_hit[466] & reg_we & !reg_error; + assign mio_pad_sleep_en_8_we = addr_hit[446] & reg_we & !reg_error; assign mio_pad_sleep_en_8_wd = reg_wdata[0]; - assign mio_pad_sleep_en_9_we = addr_hit[467] & reg_we & !reg_error; + assign mio_pad_sleep_en_9_we = addr_hit[447] & reg_we & !reg_error; assign mio_pad_sleep_en_9_wd = reg_wdata[0]; - assign mio_pad_sleep_en_10_we = addr_hit[468] & reg_we & !reg_error; + assign mio_pad_sleep_en_10_we = addr_hit[448] & reg_we & !reg_error; assign mio_pad_sleep_en_10_wd = reg_wdata[0]; - assign mio_pad_sleep_en_11_we = addr_hit[469] & reg_we & !reg_error; + assign mio_pad_sleep_en_11_we = addr_hit[449] & reg_we & !reg_error; assign mio_pad_sleep_en_11_wd = reg_wdata[0]; - assign mio_pad_sleep_en_12_we = addr_hit[470] & reg_we & !reg_error; + assign mio_pad_sleep_en_12_we = addr_hit[450] & reg_we & !reg_error; assign mio_pad_sleep_en_12_wd = reg_wdata[0]; - assign mio_pad_sleep_en_13_we = addr_hit[471] & reg_we & !reg_error; + assign mio_pad_sleep_en_13_we = addr_hit[451] & reg_we & !reg_error; assign mio_pad_sleep_en_13_wd = reg_wdata[0]; - assign mio_pad_sleep_en_14_we = addr_hit[472] & reg_we & !reg_error; + assign mio_pad_sleep_en_14_we = addr_hit[452] & reg_we & !reg_error; assign mio_pad_sleep_en_14_wd = reg_wdata[0]; - assign mio_pad_sleep_en_15_we = addr_hit[473] & reg_we & !reg_error; + assign mio_pad_sleep_en_15_we = addr_hit[453] & reg_we & !reg_error; assign mio_pad_sleep_en_15_wd = reg_wdata[0]; - assign mio_pad_sleep_en_16_we = addr_hit[474] & reg_we & !reg_error; + assign mio_pad_sleep_en_16_we = addr_hit[454] & reg_we & !reg_error; assign mio_pad_sleep_en_16_wd = reg_wdata[0]; - assign mio_pad_sleep_en_17_we = addr_hit[475] & reg_we & !reg_error; + assign mio_pad_sleep_en_17_we = addr_hit[455] & reg_we & !reg_error; assign mio_pad_sleep_en_17_wd = reg_wdata[0]; - assign mio_pad_sleep_en_18_we = addr_hit[476] & reg_we & !reg_error; + assign mio_pad_sleep_en_18_we = addr_hit[456] & reg_we & !reg_error; assign mio_pad_sleep_en_18_wd = reg_wdata[0]; - assign mio_pad_sleep_en_19_we = addr_hit[477] & reg_we & !reg_error; + assign mio_pad_sleep_en_19_we = addr_hit[457] & reg_we & !reg_error; assign mio_pad_sleep_en_19_wd = reg_wdata[0]; - assign mio_pad_sleep_en_20_we = addr_hit[478] & reg_we & !reg_error; + assign mio_pad_sleep_en_20_we = addr_hit[458] & reg_we & !reg_error; assign mio_pad_sleep_en_20_wd = reg_wdata[0]; - assign mio_pad_sleep_en_21_we = addr_hit[479] & reg_we & !reg_error; + assign mio_pad_sleep_en_21_we = addr_hit[459] & reg_we & !reg_error; assign mio_pad_sleep_en_21_wd = reg_wdata[0]; - assign mio_pad_sleep_en_22_we = addr_hit[480] & reg_we & !reg_error; + assign mio_pad_sleep_en_22_we = addr_hit[460] & reg_we & !reg_error; assign mio_pad_sleep_en_22_wd = reg_wdata[0]; - assign mio_pad_sleep_en_23_we = addr_hit[481] & reg_we & !reg_error; + assign mio_pad_sleep_en_23_we = addr_hit[461] & reg_we & !reg_error; assign mio_pad_sleep_en_23_wd = reg_wdata[0]; - assign mio_pad_sleep_en_24_we = addr_hit[482] & reg_we & !reg_error; + assign mio_pad_sleep_en_24_we = addr_hit[462] & reg_we & !reg_error; assign mio_pad_sleep_en_24_wd = reg_wdata[0]; - assign mio_pad_sleep_en_25_we = addr_hit[483] & reg_we & !reg_error; + assign mio_pad_sleep_en_25_we = addr_hit[463] & reg_we & !reg_error; assign mio_pad_sleep_en_25_wd = reg_wdata[0]; - assign mio_pad_sleep_en_26_we = addr_hit[484] & reg_we & !reg_error; + assign mio_pad_sleep_en_26_we = addr_hit[464] & reg_we & !reg_error; assign mio_pad_sleep_en_26_wd = reg_wdata[0]; - assign mio_pad_sleep_en_27_we = addr_hit[485] & reg_we & !reg_error; + assign mio_pad_sleep_en_27_we = addr_hit[465] & reg_we & !reg_error; assign mio_pad_sleep_en_27_wd = reg_wdata[0]; - assign mio_pad_sleep_en_28_we = addr_hit[486] & reg_we & !reg_error; + assign mio_pad_sleep_en_28_we = addr_hit[466] & reg_we & !reg_error; assign mio_pad_sleep_en_28_wd = reg_wdata[0]; - assign mio_pad_sleep_en_29_we = addr_hit[487] & reg_we & !reg_error; + assign mio_pad_sleep_en_29_we = addr_hit[467] & reg_we & !reg_error; assign mio_pad_sleep_en_29_wd = reg_wdata[0]; - assign mio_pad_sleep_en_30_we = addr_hit[488] & reg_we & !reg_error; + assign mio_pad_sleep_en_30_we = addr_hit[468] & reg_we & !reg_error; assign mio_pad_sleep_en_30_wd = reg_wdata[0]; - assign mio_pad_sleep_en_31_we = addr_hit[489] & reg_we & !reg_error; + assign mio_pad_sleep_en_31_we = addr_hit[469] & reg_we & !reg_error; assign mio_pad_sleep_en_31_wd = reg_wdata[0]; - assign mio_pad_sleep_en_32_we = addr_hit[490] & reg_we & !reg_error; + assign mio_pad_sleep_en_32_we = addr_hit[470] & reg_we & !reg_error; assign mio_pad_sleep_en_32_wd = reg_wdata[0]; - assign mio_pad_sleep_en_33_we = addr_hit[491] & reg_we & !reg_error; + assign mio_pad_sleep_en_33_we = addr_hit[471] & reg_we & !reg_error; assign mio_pad_sleep_en_33_wd = reg_wdata[0]; - assign mio_pad_sleep_en_34_we = addr_hit[492] & reg_we & !reg_error; + assign mio_pad_sleep_en_34_we = addr_hit[472] & reg_we & !reg_error; assign mio_pad_sleep_en_34_wd = reg_wdata[0]; - assign mio_pad_sleep_en_35_we = addr_hit[493] & reg_we & !reg_error; + assign mio_pad_sleep_en_35_we = addr_hit[473] & reg_we & !reg_error; assign mio_pad_sleep_en_35_wd = reg_wdata[0]; - assign mio_pad_sleep_en_36_we = addr_hit[494] & reg_we & !reg_error; + assign mio_pad_sleep_en_36_we = addr_hit[474] & reg_we & !reg_error; assign mio_pad_sleep_en_36_wd = reg_wdata[0]; - assign mio_pad_sleep_en_37_we = addr_hit[495] & reg_we & !reg_error; + assign mio_pad_sleep_en_37_we = addr_hit[475] & reg_we & !reg_error; assign mio_pad_sleep_en_37_wd = reg_wdata[0]; - assign mio_pad_sleep_en_38_we = addr_hit[496] & reg_we & !reg_error; + assign mio_pad_sleep_en_38_we = addr_hit[476] & reg_we & !reg_error; assign mio_pad_sleep_en_38_wd = reg_wdata[0]; - assign mio_pad_sleep_en_39_we = addr_hit[497] & reg_we & !reg_error; + assign mio_pad_sleep_en_39_we = addr_hit[477] & reg_we & !reg_error; assign mio_pad_sleep_en_39_wd = reg_wdata[0]; - assign mio_pad_sleep_en_40_we = addr_hit[498] & reg_we & !reg_error; + assign mio_pad_sleep_en_40_we = addr_hit[478] & reg_we & !reg_error; assign mio_pad_sleep_en_40_wd = reg_wdata[0]; - assign mio_pad_sleep_en_41_we = addr_hit[499] & reg_we & !reg_error; + assign mio_pad_sleep_en_41_we = addr_hit[479] & reg_we & !reg_error; assign mio_pad_sleep_en_41_wd = reg_wdata[0]; - assign mio_pad_sleep_en_42_we = addr_hit[500] & reg_we & !reg_error; + assign mio_pad_sleep_en_42_we = addr_hit[480] & reg_we & !reg_error; assign mio_pad_sleep_en_42_wd = reg_wdata[0]; - assign mio_pad_sleep_en_43_we = addr_hit[501] & reg_we & !reg_error; + assign mio_pad_sleep_en_43_we = addr_hit[481] & reg_we & !reg_error; assign mio_pad_sleep_en_43_wd = reg_wdata[0]; - assign mio_pad_sleep_en_44_we = addr_hit[502] & reg_we & !reg_error; + assign mio_pad_sleep_en_44_we = addr_hit[482] & reg_we & !reg_error; assign mio_pad_sleep_en_44_wd = reg_wdata[0]; - assign mio_pad_sleep_en_45_we = addr_hit[503] & reg_we & !reg_error; + assign mio_pad_sleep_en_45_we = addr_hit[483] & reg_we & !reg_error; assign mio_pad_sleep_en_45_wd = reg_wdata[0]; - assign mio_pad_sleep_en_46_we = addr_hit[504] & reg_we & !reg_error; + assign mio_pad_sleep_en_46_we = addr_hit[484] & reg_we & !reg_error; assign mio_pad_sleep_en_46_wd = reg_wdata[0]; - assign mio_pad_sleep_en_47_we = addr_hit[505] & reg_we & !reg_error; - - assign mio_pad_sleep_en_47_wd = reg_wdata[0]; - assign mio_pad_sleep_en_48_we = addr_hit[506] & reg_we & !reg_error; - - assign mio_pad_sleep_en_48_wd = reg_wdata[0]; - assign mio_pad_sleep_en_49_we = addr_hit[507] & reg_we & !reg_error; - - assign mio_pad_sleep_en_49_wd = reg_wdata[0]; - assign mio_pad_sleep_en_50_we = addr_hit[508] & reg_we & !reg_error; - - assign mio_pad_sleep_en_50_wd = reg_wdata[0]; - assign mio_pad_sleep_en_51_we = addr_hit[509] & reg_we & !reg_error; - - assign mio_pad_sleep_en_51_wd = reg_wdata[0]; - assign mio_pad_sleep_en_52_we = addr_hit[510] & reg_we & !reg_error; - - assign mio_pad_sleep_en_52_wd = reg_wdata[0]; - assign mio_pad_sleep_mode_0_we = addr_hit[511] & reg_we & !reg_error; + assign mio_pad_sleep_mode_0_we = addr_hit[485] & reg_we & !reg_error; assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_1_we = addr_hit[512] & reg_we & !reg_error; + assign mio_pad_sleep_mode_1_we = addr_hit[486] & reg_we & !reg_error; assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_2_we = addr_hit[513] & reg_we & !reg_error; + assign mio_pad_sleep_mode_2_we = addr_hit[487] & reg_we & !reg_error; assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_3_we = addr_hit[514] & reg_we & !reg_error; + assign mio_pad_sleep_mode_3_we = addr_hit[488] & reg_we & !reg_error; assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_4_we = addr_hit[515] & reg_we & !reg_error; + assign mio_pad_sleep_mode_4_we = addr_hit[489] & reg_we & !reg_error; assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_5_we = addr_hit[516] & reg_we & !reg_error; + assign mio_pad_sleep_mode_5_we = addr_hit[490] & reg_we & !reg_error; assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_6_we = addr_hit[517] & reg_we & !reg_error; + assign mio_pad_sleep_mode_6_we = addr_hit[491] & reg_we & !reg_error; assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_7_we = addr_hit[518] & reg_we & !reg_error; + assign mio_pad_sleep_mode_7_we = addr_hit[492] & reg_we & !reg_error; assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_8_we = addr_hit[519] & reg_we & !reg_error; + assign mio_pad_sleep_mode_8_we = addr_hit[493] & reg_we & !reg_error; assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_9_we = addr_hit[520] & reg_we & !reg_error; + assign mio_pad_sleep_mode_9_we = addr_hit[494] & reg_we & !reg_error; assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_10_we = addr_hit[521] & reg_we & !reg_error; + assign mio_pad_sleep_mode_10_we = addr_hit[495] & reg_we & !reg_error; assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_11_we = addr_hit[522] & reg_we & !reg_error; + assign mio_pad_sleep_mode_11_we = addr_hit[496] & reg_we & !reg_error; assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_12_we = addr_hit[523] & reg_we & !reg_error; + assign mio_pad_sleep_mode_12_we = addr_hit[497] & reg_we & !reg_error; assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_13_we = addr_hit[524] & reg_we & !reg_error; + assign mio_pad_sleep_mode_13_we = addr_hit[498] & reg_we & !reg_error; assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_14_we = addr_hit[525] & reg_we & !reg_error; + assign mio_pad_sleep_mode_14_we = addr_hit[499] & reg_we & !reg_error; assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_15_we = addr_hit[526] & reg_we & !reg_error; + assign mio_pad_sleep_mode_15_we = addr_hit[500] & reg_we & !reg_error; assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_16_we = addr_hit[527] & reg_we & !reg_error; + assign mio_pad_sleep_mode_16_we = addr_hit[501] & reg_we & !reg_error; assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_17_we = addr_hit[528] & reg_we & !reg_error; + assign mio_pad_sleep_mode_17_we = addr_hit[502] & reg_we & !reg_error; assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_18_we = addr_hit[529] & reg_we & !reg_error; + assign mio_pad_sleep_mode_18_we = addr_hit[503] & reg_we & !reg_error; assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_19_we = addr_hit[530] & reg_we & !reg_error; + assign mio_pad_sleep_mode_19_we = addr_hit[504] & reg_we & !reg_error; assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_20_we = addr_hit[531] & reg_we & !reg_error; + assign mio_pad_sleep_mode_20_we = addr_hit[505] & reg_we & !reg_error; assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_21_we = addr_hit[532] & reg_we & !reg_error; + assign mio_pad_sleep_mode_21_we = addr_hit[506] & reg_we & !reg_error; assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_22_we = addr_hit[533] & reg_we & !reg_error; + assign mio_pad_sleep_mode_22_we = addr_hit[507] & reg_we & !reg_error; assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_23_we = addr_hit[534] & reg_we & !reg_error; + assign mio_pad_sleep_mode_23_we = addr_hit[508] & reg_we & !reg_error; assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_24_we = addr_hit[535] & reg_we & !reg_error; + assign mio_pad_sleep_mode_24_we = addr_hit[509] & reg_we & !reg_error; assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_25_we = addr_hit[536] & reg_we & !reg_error; + assign mio_pad_sleep_mode_25_we = addr_hit[510] & reg_we & !reg_error; assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_26_we = addr_hit[537] & reg_we & !reg_error; + assign mio_pad_sleep_mode_26_we = addr_hit[511] & reg_we & !reg_error; assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_27_we = addr_hit[538] & reg_we & !reg_error; + assign mio_pad_sleep_mode_27_we = addr_hit[512] & reg_we & !reg_error; assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_28_we = addr_hit[539] & reg_we & !reg_error; + assign mio_pad_sleep_mode_28_we = addr_hit[513] & reg_we & !reg_error; assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_29_we = addr_hit[540] & reg_we & !reg_error; + assign mio_pad_sleep_mode_29_we = addr_hit[514] & reg_we & !reg_error; assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_30_we = addr_hit[541] & reg_we & !reg_error; + assign mio_pad_sleep_mode_30_we = addr_hit[515] & reg_we & !reg_error; assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_31_we = addr_hit[542] & reg_we & !reg_error; + assign mio_pad_sleep_mode_31_we = addr_hit[516] & reg_we & !reg_error; assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_32_we = addr_hit[543] & reg_we & !reg_error; + assign mio_pad_sleep_mode_32_we = addr_hit[517] & reg_we & !reg_error; assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_33_we = addr_hit[544] & reg_we & !reg_error; + assign mio_pad_sleep_mode_33_we = addr_hit[518] & reg_we & !reg_error; assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_34_we = addr_hit[545] & reg_we & !reg_error; + assign mio_pad_sleep_mode_34_we = addr_hit[519] & reg_we & !reg_error; assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_35_we = addr_hit[546] & reg_we & !reg_error; + assign mio_pad_sleep_mode_35_we = addr_hit[520] & reg_we & !reg_error; assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_36_we = addr_hit[547] & reg_we & !reg_error; + assign mio_pad_sleep_mode_36_we = addr_hit[521] & reg_we & !reg_error; assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_37_we = addr_hit[548] & reg_we & !reg_error; + assign mio_pad_sleep_mode_37_we = addr_hit[522] & reg_we & !reg_error; assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_38_we = addr_hit[549] & reg_we & !reg_error; + assign mio_pad_sleep_mode_38_we = addr_hit[523] & reg_we & !reg_error; assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_39_we = addr_hit[550] & reg_we & !reg_error; + assign mio_pad_sleep_mode_39_we = addr_hit[524] & reg_we & !reg_error; assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_40_we = addr_hit[551] & reg_we & !reg_error; + assign mio_pad_sleep_mode_40_we = addr_hit[525] & reg_we & !reg_error; assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_41_we = addr_hit[552] & reg_we & !reg_error; + assign mio_pad_sleep_mode_41_we = addr_hit[526] & reg_we & !reg_error; assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_42_we = addr_hit[553] & reg_we & !reg_error; + assign mio_pad_sleep_mode_42_we = addr_hit[527] & reg_we & !reg_error; assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_43_we = addr_hit[554] & reg_we & !reg_error; + assign mio_pad_sleep_mode_43_we = addr_hit[528] & reg_we & !reg_error; assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_44_we = addr_hit[555] & reg_we & !reg_error; + assign mio_pad_sleep_mode_44_we = addr_hit[529] & reg_we & !reg_error; assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_45_we = addr_hit[556] & reg_we & !reg_error; + assign mio_pad_sleep_mode_45_we = addr_hit[530] & reg_we & !reg_error; assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_46_we = addr_hit[557] & reg_we & !reg_error; + assign mio_pad_sleep_mode_46_we = addr_hit[531] & reg_we & !reg_error; assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_47_we = addr_hit[558] & reg_we & !reg_error; - - assign mio_pad_sleep_mode_47_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_48_we = addr_hit[559] & reg_we & !reg_error; - - assign mio_pad_sleep_mode_48_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_49_we = addr_hit[560] & reg_we & !reg_error; - - assign mio_pad_sleep_mode_49_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_50_we = addr_hit[561] & reg_we & !reg_error; - - assign mio_pad_sleep_mode_50_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_51_we = addr_hit[562] & reg_we & !reg_error; - - assign mio_pad_sleep_mode_51_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_52_we = addr_hit[563] & reg_we & !reg_error; - - assign mio_pad_sleep_mode_52_wd = reg_wdata[1:0]; - assign dio_pad_sleep_status_0_we = addr_hit[564] & reg_we & !reg_error; + assign dio_pad_sleep_status_0_we = addr_hit[532] & reg_we & !reg_error; assign dio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; @@ -45043,7 +44452,7 @@ assign dio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; assign dio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; - assign dio_pad_sleep_status_1_we = addr_hit[565] & reg_we & !reg_error; + assign dio_pad_sleep_status_1_we = addr_hit[533] & reg_we & !reg_error; assign dio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; @@ -45054,452 +44463,518 @@ assign dio_pad_sleep_status_1_en_35_wd = reg_wdata[3]; assign dio_pad_sleep_status_1_en_36_wd = reg_wdata[4]; - assign dio_pad_sleep_regwen_0_we = addr_hit[566] & reg_we & !reg_error; + + assign dio_pad_sleep_status_1_en_37_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_1_en_38_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_1_en_39_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_1_en_40_wd = reg_wdata[8]; + + assign dio_pad_sleep_status_1_en_41_wd = reg_wdata[9]; + + assign dio_pad_sleep_status_1_en_42_wd = reg_wdata[10]; + assign dio_pad_sleep_regwen_0_we = addr_hit[534] & reg_we & !reg_error; assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_1_we = addr_hit[567] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_1_we = addr_hit[535] & reg_we & !reg_error; assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_2_we = addr_hit[568] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_2_we = addr_hit[536] & reg_we & !reg_error; assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_3_we = addr_hit[569] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_3_we = addr_hit[537] & reg_we & !reg_error; assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_4_we = addr_hit[570] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_4_we = addr_hit[538] & reg_we & !reg_error; assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_5_we = addr_hit[571] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_5_we = addr_hit[539] & reg_we & !reg_error; assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_6_we = addr_hit[572] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_6_we = addr_hit[540] & reg_we & !reg_error; assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_7_we = addr_hit[573] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_7_we = addr_hit[541] & reg_we & !reg_error; assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_8_we = addr_hit[574] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_8_we = addr_hit[542] & reg_we & !reg_error; assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_9_we = addr_hit[575] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_9_we = addr_hit[543] & reg_we & !reg_error; assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_10_we = addr_hit[576] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_10_we = addr_hit[544] & reg_we & !reg_error; assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_11_we = addr_hit[577] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_11_we = addr_hit[545] & reg_we & !reg_error; assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_12_we = addr_hit[578] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_12_we = addr_hit[546] & reg_we & !reg_error; assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_13_we = addr_hit[579] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_13_we = addr_hit[547] & reg_we & !reg_error; assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_14_we = addr_hit[580] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_14_we = addr_hit[548] & reg_we & !reg_error; assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_15_we = addr_hit[581] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_15_we = addr_hit[549] & reg_we & !reg_error; assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_16_we = addr_hit[582] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_16_we = addr_hit[550] & reg_we & !reg_error; assign dio_pad_sleep_regwen_16_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_17_we = addr_hit[583] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_17_we = addr_hit[551] & reg_we & !reg_error; assign dio_pad_sleep_regwen_17_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_18_we = addr_hit[584] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_18_we = addr_hit[552] & reg_we & !reg_error; assign dio_pad_sleep_regwen_18_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_19_we = addr_hit[585] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_19_we = addr_hit[553] & reg_we & !reg_error; assign dio_pad_sleep_regwen_19_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_20_we = addr_hit[586] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_20_we = addr_hit[554] & reg_we & !reg_error; assign dio_pad_sleep_regwen_20_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_21_we = addr_hit[587] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_21_we = addr_hit[555] & reg_we & !reg_error; assign dio_pad_sleep_regwen_21_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_22_we = addr_hit[588] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_22_we = addr_hit[556] & reg_we & !reg_error; assign dio_pad_sleep_regwen_22_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_23_we = addr_hit[589] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_23_we = addr_hit[557] & reg_we & !reg_error; assign dio_pad_sleep_regwen_23_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_24_we = addr_hit[590] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_24_we = addr_hit[558] & reg_we & !reg_error; assign dio_pad_sleep_regwen_24_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_25_we = addr_hit[591] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_25_we = addr_hit[559] & reg_we & !reg_error; assign dio_pad_sleep_regwen_25_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_26_we = addr_hit[592] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_26_we = addr_hit[560] & reg_we & !reg_error; assign dio_pad_sleep_regwen_26_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_27_we = addr_hit[593] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_27_we = addr_hit[561] & reg_we & !reg_error; assign dio_pad_sleep_regwen_27_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_28_we = addr_hit[594] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_28_we = addr_hit[562] & reg_we & !reg_error; assign dio_pad_sleep_regwen_28_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_29_we = addr_hit[595] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_29_we = addr_hit[563] & reg_we & !reg_error; assign dio_pad_sleep_regwen_29_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_30_we = addr_hit[596] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_30_we = addr_hit[564] & reg_we & !reg_error; assign dio_pad_sleep_regwen_30_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_31_we = addr_hit[597] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_31_we = addr_hit[565] & reg_we & !reg_error; assign dio_pad_sleep_regwen_31_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_32_we = addr_hit[598] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_32_we = addr_hit[566] & reg_we & !reg_error; assign dio_pad_sleep_regwen_32_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_33_we = addr_hit[599] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_33_we = addr_hit[567] & reg_we & !reg_error; assign dio_pad_sleep_regwen_33_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_34_we = addr_hit[600] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_34_we = addr_hit[568] & reg_we & !reg_error; assign dio_pad_sleep_regwen_34_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_35_we = addr_hit[601] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_35_we = addr_hit[569] & reg_we & !reg_error; assign dio_pad_sleep_regwen_35_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_36_we = addr_hit[602] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_36_we = addr_hit[570] & reg_we & !reg_error; assign dio_pad_sleep_regwen_36_wd = reg_wdata[0]; - assign dio_pad_sleep_en_0_we = addr_hit[603] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_37_we = addr_hit[571] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_37_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_38_we = addr_hit[572] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_38_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_39_we = addr_hit[573] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_39_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_40_we = addr_hit[574] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_40_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_41_we = addr_hit[575] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_41_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_42_we = addr_hit[576] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_42_wd = reg_wdata[0]; + assign dio_pad_sleep_en_0_we = addr_hit[577] & reg_we & !reg_error; assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_pad_sleep_en_1_we = addr_hit[604] & reg_we & !reg_error; + assign dio_pad_sleep_en_1_we = addr_hit[578] & reg_we & !reg_error; assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_pad_sleep_en_2_we = addr_hit[605] & reg_we & !reg_error; + assign dio_pad_sleep_en_2_we = addr_hit[579] & reg_we & !reg_error; assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_pad_sleep_en_3_we = addr_hit[606] & reg_we & !reg_error; + assign dio_pad_sleep_en_3_we = addr_hit[580] & reg_we & !reg_error; assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_pad_sleep_en_4_we = addr_hit[607] & reg_we & !reg_error; + assign dio_pad_sleep_en_4_we = addr_hit[581] & reg_we & !reg_error; assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_pad_sleep_en_5_we = addr_hit[608] & reg_we & !reg_error; + assign dio_pad_sleep_en_5_we = addr_hit[582] & reg_we & !reg_error; assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_pad_sleep_en_6_we = addr_hit[609] & reg_we & !reg_error; + assign dio_pad_sleep_en_6_we = addr_hit[583] & reg_we & !reg_error; assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_pad_sleep_en_7_we = addr_hit[610] & reg_we & !reg_error; + assign dio_pad_sleep_en_7_we = addr_hit[584] & reg_we & !reg_error; assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_pad_sleep_en_8_we = addr_hit[611] & reg_we & !reg_error; + assign dio_pad_sleep_en_8_we = addr_hit[585] & reg_we & !reg_error; assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_pad_sleep_en_9_we = addr_hit[612] & reg_we & !reg_error; + assign dio_pad_sleep_en_9_we = addr_hit[586] & reg_we & !reg_error; assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_pad_sleep_en_10_we = addr_hit[613] & reg_we & !reg_error; + assign dio_pad_sleep_en_10_we = addr_hit[587] & reg_we & !reg_error; assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_pad_sleep_en_11_we = addr_hit[614] & reg_we & !reg_error; + assign dio_pad_sleep_en_11_we = addr_hit[588] & reg_we & !reg_error; assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_pad_sleep_en_12_we = addr_hit[615] & reg_we & !reg_error; + assign dio_pad_sleep_en_12_we = addr_hit[589] & reg_we & !reg_error; assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_pad_sleep_en_13_we = addr_hit[616] & reg_we & !reg_error; + assign dio_pad_sleep_en_13_we = addr_hit[590] & reg_we & !reg_error; assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_pad_sleep_en_14_we = addr_hit[617] & reg_we & !reg_error; + assign dio_pad_sleep_en_14_we = addr_hit[591] & reg_we & !reg_error; assign dio_pad_sleep_en_14_wd = reg_wdata[0]; - assign dio_pad_sleep_en_15_we = addr_hit[618] & reg_we & !reg_error; + assign dio_pad_sleep_en_15_we = addr_hit[592] & reg_we & !reg_error; assign dio_pad_sleep_en_15_wd = reg_wdata[0]; - assign dio_pad_sleep_en_16_we = addr_hit[619] & reg_we & !reg_error; + assign dio_pad_sleep_en_16_we = addr_hit[593] & reg_we & !reg_error; assign dio_pad_sleep_en_16_wd = reg_wdata[0]; - assign dio_pad_sleep_en_17_we = addr_hit[620] & reg_we & !reg_error; + assign dio_pad_sleep_en_17_we = addr_hit[594] & reg_we & !reg_error; assign dio_pad_sleep_en_17_wd = reg_wdata[0]; - assign dio_pad_sleep_en_18_we = addr_hit[621] & reg_we & !reg_error; + assign dio_pad_sleep_en_18_we = addr_hit[595] & reg_we & !reg_error; assign dio_pad_sleep_en_18_wd = reg_wdata[0]; - assign dio_pad_sleep_en_19_we = addr_hit[622] & reg_we & !reg_error; + assign dio_pad_sleep_en_19_we = addr_hit[596] & reg_we & !reg_error; assign dio_pad_sleep_en_19_wd = reg_wdata[0]; - assign dio_pad_sleep_en_20_we = addr_hit[623] & reg_we & !reg_error; + assign dio_pad_sleep_en_20_we = addr_hit[597] & reg_we & !reg_error; assign dio_pad_sleep_en_20_wd = reg_wdata[0]; - assign dio_pad_sleep_en_21_we = addr_hit[624] & reg_we & !reg_error; + assign dio_pad_sleep_en_21_we = addr_hit[598] & reg_we & !reg_error; assign dio_pad_sleep_en_21_wd = reg_wdata[0]; - assign dio_pad_sleep_en_22_we = addr_hit[625] & reg_we & !reg_error; + assign dio_pad_sleep_en_22_we = addr_hit[599] & reg_we & !reg_error; assign dio_pad_sleep_en_22_wd = reg_wdata[0]; - assign dio_pad_sleep_en_23_we = addr_hit[626] & reg_we & !reg_error; + assign dio_pad_sleep_en_23_we = addr_hit[600] & reg_we & !reg_error; assign dio_pad_sleep_en_23_wd = reg_wdata[0]; - assign dio_pad_sleep_en_24_we = addr_hit[627] & reg_we & !reg_error; + assign dio_pad_sleep_en_24_we = addr_hit[601] & reg_we & !reg_error; assign dio_pad_sleep_en_24_wd = reg_wdata[0]; - assign dio_pad_sleep_en_25_we = addr_hit[628] & reg_we & !reg_error; + assign dio_pad_sleep_en_25_we = addr_hit[602] & reg_we & !reg_error; assign dio_pad_sleep_en_25_wd = reg_wdata[0]; - assign dio_pad_sleep_en_26_we = addr_hit[629] & reg_we & !reg_error; + assign dio_pad_sleep_en_26_we = addr_hit[603] & reg_we & !reg_error; assign dio_pad_sleep_en_26_wd = reg_wdata[0]; - assign dio_pad_sleep_en_27_we = addr_hit[630] & reg_we & !reg_error; + assign dio_pad_sleep_en_27_we = addr_hit[604] & reg_we & !reg_error; assign dio_pad_sleep_en_27_wd = reg_wdata[0]; - assign dio_pad_sleep_en_28_we = addr_hit[631] & reg_we & !reg_error; + assign dio_pad_sleep_en_28_we = addr_hit[605] & reg_we & !reg_error; assign dio_pad_sleep_en_28_wd = reg_wdata[0]; - assign dio_pad_sleep_en_29_we = addr_hit[632] & reg_we & !reg_error; + assign dio_pad_sleep_en_29_we = addr_hit[606] & reg_we & !reg_error; assign dio_pad_sleep_en_29_wd = reg_wdata[0]; - assign dio_pad_sleep_en_30_we = addr_hit[633] & reg_we & !reg_error; + assign dio_pad_sleep_en_30_we = addr_hit[607] & reg_we & !reg_error; assign dio_pad_sleep_en_30_wd = reg_wdata[0]; - assign dio_pad_sleep_en_31_we = addr_hit[634] & reg_we & !reg_error; + assign dio_pad_sleep_en_31_we = addr_hit[608] & reg_we & !reg_error; assign dio_pad_sleep_en_31_wd = reg_wdata[0]; - assign dio_pad_sleep_en_32_we = addr_hit[635] & reg_we & !reg_error; + assign dio_pad_sleep_en_32_we = addr_hit[609] & reg_we & !reg_error; assign dio_pad_sleep_en_32_wd = reg_wdata[0]; - assign dio_pad_sleep_en_33_we = addr_hit[636] & reg_we & !reg_error; + assign dio_pad_sleep_en_33_we = addr_hit[610] & reg_we & !reg_error; assign dio_pad_sleep_en_33_wd = reg_wdata[0]; - assign dio_pad_sleep_en_34_we = addr_hit[637] & reg_we & !reg_error; + assign dio_pad_sleep_en_34_we = addr_hit[611] & reg_we & !reg_error; assign dio_pad_sleep_en_34_wd = reg_wdata[0]; - assign dio_pad_sleep_en_35_we = addr_hit[638] & reg_we & !reg_error; + assign dio_pad_sleep_en_35_we = addr_hit[612] & reg_we & !reg_error; assign dio_pad_sleep_en_35_wd = reg_wdata[0]; - assign dio_pad_sleep_en_36_we = addr_hit[639] & reg_we & !reg_error; + assign dio_pad_sleep_en_36_we = addr_hit[613] & reg_we & !reg_error; assign dio_pad_sleep_en_36_wd = reg_wdata[0]; - assign dio_pad_sleep_mode_0_we = addr_hit[640] & reg_we & !reg_error; + assign dio_pad_sleep_en_37_we = addr_hit[614] & reg_we & !reg_error; + + assign dio_pad_sleep_en_37_wd = reg_wdata[0]; + assign dio_pad_sleep_en_38_we = addr_hit[615] & reg_we & !reg_error; + + assign dio_pad_sleep_en_38_wd = reg_wdata[0]; + assign dio_pad_sleep_en_39_we = addr_hit[616] & reg_we & !reg_error; + + assign dio_pad_sleep_en_39_wd = reg_wdata[0]; + assign dio_pad_sleep_en_40_we = addr_hit[617] & reg_we & !reg_error; + + assign dio_pad_sleep_en_40_wd = reg_wdata[0]; + assign dio_pad_sleep_en_41_we = addr_hit[618] & reg_we & !reg_error; + + assign dio_pad_sleep_en_41_wd = reg_wdata[0]; + assign dio_pad_sleep_en_42_we = addr_hit[619] & reg_we & !reg_error; + + assign dio_pad_sleep_en_42_wd = reg_wdata[0]; + assign dio_pad_sleep_mode_0_we = addr_hit[620] & reg_we & !reg_error; assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_1_we = addr_hit[641] & reg_we & !reg_error; + assign dio_pad_sleep_mode_1_we = addr_hit[621] & reg_we & !reg_error; assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_2_we = addr_hit[642] & reg_we & !reg_error; + assign dio_pad_sleep_mode_2_we = addr_hit[622] & reg_we & !reg_error; assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_3_we = addr_hit[643] & reg_we & !reg_error; + assign dio_pad_sleep_mode_3_we = addr_hit[623] & reg_we & !reg_error; assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_4_we = addr_hit[644] & reg_we & !reg_error; + assign dio_pad_sleep_mode_4_we = addr_hit[624] & reg_we & !reg_error; assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_5_we = addr_hit[645] & reg_we & !reg_error; + assign dio_pad_sleep_mode_5_we = addr_hit[625] & reg_we & !reg_error; assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_6_we = addr_hit[646] & reg_we & !reg_error; + assign dio_pad_sleep_mode_6_we = addr_hit[626] & reg_we & !reg_error; assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_7_we = addr_hit[647] & reg_we & !reg_error; + assign dio_pad_sleep_mode_7_we = addr_hit[627] & reg_we & !reg_error; assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_8_we = addr_hit[648] & reg_we & !reg_error; + assign dio_pad_sleep_mode_8_we = addr_hit[628] & reg_we & !reg_error; assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_9_we = addr_hit[649] & reg_we & !reg_error; + assign dio_pad_sleep_mode_9_we = addr_hit[629] & reg_we & !reg_error; assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_10_we = addr_hit[650] & reg_we & !reg_error; + assign dio_pad_sleep_mode_10_we = addr_hit[630] & reg_we & !reg_error; assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_11_we = addr_hit[651] & reg_we & !reg_error; + assign dio_pad_sleep_mode_11_we = addr_hit[631] & reg_we & !reg_error; assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_12_we = addr_hit[652] & reg_we & !reg_error; + assign dio_pad_sleep_mode_12_we = addr_hit[632] & reg_we & !reg_error; assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_13_we = addr_hit[653] & reg_we & !reg_error; + assign dio_pad_sleep_mode_13_we = addr_hit[633] & reg_we & !reg_error; assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_14_we = addr_hit[654] & reg_we & !reg_error; + assign dio_pad_sleep_mode_14_we = addr_hit[634] & reg_we & !reg_error; assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_15_we = addr_hit[655] & reg_we & !reg_error; + assign dio_pad_sleep_mode_15_we = addr_hit[635] & reg_we & !reg_error; assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_16_we = addr_hit[656] & reg_we & !reg_error; + assign dio_pad_sleep_mode_16_we = addr_hit[636] & reg_we & !reg_error; assign dio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_17_we = addr_hit[657] & reg_we & !reg_error; + assign dio_pad_sleep_mode_17_we = addr_hit[637] & reg_we & !reg_error; assign dio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_18_we = addr_hit[658] & reg_we & !reg_error; + assign dio_pad_sleep_mode_18_we = addr_hit[638] & reg_we & !reg_error; assign dio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_19_we = addr_hit[659] & reg_we & !reg_error; + assign dio_pad_sleep_mode_19_we = addr_hit[639] & reg_we & !reg_error; assign dio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_20_we = addr_hit[660] & reg_we & !reg_error; + assign dio_pad_sleep_mode_20_we = addr_hit[640] & reg_we & !reg_error; assign dio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_21_we = addr_hit[661] & reg_we & !reg_error; + assign dio_pad_sleep_mode_21_we = addr_hit[641] & reg_we & !reg_error; assign dio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_22_we = addr_hit[662] & reg_we & !reg_error; + assign dio_pad_sleep_mode_22_we = addr_hit[642] & reg_we & !reg_error; assign dio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_23_we = addr_hit[663] & reg_we & !reg_error; + assign dio_pad_sleep_mode_23_we = addr_hit[643] & reg_we & !reg_error; assign dio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_24_we = addr_hit[664] & reg_we & !reg_error; + assign dio_pad_sleep_mode_24_we = addr_hit[644] & reg_we & !reg_error; assign dio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_25_we = addr_hit[665] & reg_we & !reg_error; + assign dio_pad_sleep_mode_25_we = addr_hit[645] & reg_we & !reg_error; assign dio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_26_we = addr_hit[666] & reg_we & !reg_error; + assign dio_pad_sleep_mode_26_we = addr_hit[646] & reg_we & !reg_error; assign dio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_27_we = addr_hit[667] & reg_we & !reg_error; + assign dio_pad_sleep_mode_27_we = addr_hit[647] & reg_we & !reg_error; assign dio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_28_we = addr_hit[668] & reg_we & !reg_error; + assign dio_pad_sleep_mode_28_we = addr_hit[648] & reg_we & !reg_error; assign dio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_29_we = addr_hit[669] & reg_we & !reg_error; + assign dio_pad_sleep_mode_29_we = addr_hit[649] & reg_we & !reg_error; assign dio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_30_we = addr_hit[670] & reg_we & !reg_error; + assign dio_pad_sleep_mode_30_we = addr_hit[650] & reg_we & !reg_error; assign dio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_31_we = addr_hit[671] & reg_we & !reg_error; + assign dio_pad_sleep_mode_31_we = addr_hit[651] & reg_we & !reg_error; assign dio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_32_we = addr_hit[672] & reg_we & !reg_error; + assign dio_pad_sleep_mode_32_we = addr_hit[652] & reg_we & !reg_error; assign dio_pad_sleep_mode_32_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_33_we = addr_hit[673] & reg_we & !reg_error; + assign dio_pad_sleep_mode_33_we = addr_hit[653] & reg_we & !reg_error; assign dio_pad_sleep_mode_33_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_34_we = addr_hit[674] & reg_we & !reg_error; + assign dio_pad_sleep_mode_34_we = addr_hit[654] & reg_we & !reg_error; assign dio_pad_sleep_mode_34_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_35_we = addr_hit[675] & reg_we & !reg_error; + assign dio_pad_sleep_mode_35_we = addr_hit[655] & reg_we & !reg_error; assign dio_pad_sleep_mode_35_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_36_we = addr_hit[676] & reg_we & !reg_error; + assign dio_pad_sleep_mode_36_we = addr_hit[656] & reg_we & !reg_error; assign dio_pad_sleep_mode_36_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[677] & reg_we & !reg_error; + assign dio_pad_sleep_mode_37_we = addr_hit[657] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_37_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_38_we = addr_hit[658] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_38_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_39_we = addr_hit[659] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_39_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_40_we = addr_hit[660] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_40_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_41_we = addr_hit[661] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_41_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_42_we = addr_hit[662] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_42_wd = reg_wdata[1:0]; + assign wkup_detector_regwen_0_we = addr_hit[663] & reg_we & !reg_error; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[678] & reg_we & !reg_error; + assign wkup_detector_regwen_1_we = addr_hit[664] & reg_we & !reg_error; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[679] & reg_we & !reg_error; + assign wkup_detector_regwen_2_we = addr_hit[665] & reg_we & !reg_error; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[680] & reg_we & !reg_error; + assign wkup_detector_regwen_3_we = addr_hit[666] & reg_we & !reg_error; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[681] & reg_we & !reg_error; + assign wkup_detector_regwen_4_we = addr_hit[667] & reg_we & !reg_error; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[682] & reg_we & !reg_error; + assign wkup_detector_regwen_5_we = addr_hit[668] & reg_we & !reg_error; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[683] & reg_we & !reg_error; + assign wkup_detector_regwen_6_we = addr_hit[669] & reg_we & !reg_error; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[684] & reg_we & !reg_error; + assign wkup_detector_regwen_7_we = addr_hit[670] & reg_we & !reg_error; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[685] & reg_we & !reg_error; + assign wkup_detector_en_0_we = addr_hit[671] & reg_we & !reg_error; - assign wkup_detector_en_1_we = addr_hit[686] & reg_we & !reg_error; + assign wkup_detector_en_1_we = addr_hit[672] & reg_we & !reg_error; - assign wkup_detector_en_2_we = addr_hit[687] & reg_we & !reg_error; + assign wkup_detector_en_2_we = addr_hit[673] & reg_we & !reg_error; - assign wkup_detector_en_3_we = addr_hit[688] & reg_we & !reg_error; + assign wkup_detector_en_3_we = addr_hit[674] & reg_we & !reg_error; - assign wkup_detector_en_4_we = addr_hit[689] & reg_we & !reg_error; + assign wkup_detector_en_4_we = addr_hit[675] & reg_we & !reg_error; - assign wkup_detector_en_5_we = addr_hit[690] & reg_we & !reg_error; + assign wkup_detector_en_5_we = addr_hit[676] & reg_we & !reg_error; - assign wkup_detector_en_6_we = addr_hit[691] & reg_we & !reg_error; + assign wkup_detector_en_6_we = addr_hit[677] & reg_we & !reg_error; - assign wkup_detector_en_7_we = addr_hit[692] & reg_we & !reg_error; + assign wkup_detector_en_7_we = addr_hit[678] & reg_we & !reg_error; - assign wkup_detector_0_we = addr_hit[693] & reg_we & !reg_error; + assign wkup_detector_0_we = addr_hit[679] & reg_we & !reg_error; - assign wkup_detector_1_we = addr_hit[694] & reg_we & !reg_error; + assign wkup_detector_1_we = addr_hit[680] & reg_we & !reg_error; - assign wkup_detector_2_we = addr_hit[695] & reg_we & !reg_error; + assign wkup_detector_2_we = addr_hit[681] & reg_we & !reg_error; - assign wkup_detector_3_we = addr_hit[696] & reg_we & !reg_error; + assign wkup_detector_3_we = addr_hit[682] & reg_we & !reg_error; - assign wkup_detector_4_we = addr_hit[697] & reg_we & !reg_error; + assign wkup_detector_4_we = addr_hit[683] & reg_we & !reg_error; - assign wkup_detector_5_we = addr_hit[698] & reg_we & !reg_error; + assign wkup_detector_5_we = addr_hit[684] & reg_we & !reg_error; - assign wkup_detector_6_we = addr_hit[699] & reg_we & !reg_error; + assign wkup_detector_6_we = addr_hit[685] & reg_we & !reg_error; - assign wkup_detector_7_we = addr_hit[700] & reg_we & !reg_error; + assign wkup_detector_7_we = addr_hit[686] & reg_we & !reg_error; - assign wkup_detector_cnt_th_0_we = addr_hit[701] & reg_we & !reg_error; + assign wkup_detector_cnt_th_0_we = addr_hit[687] & reg_we & !reg_error; - assign wkup_detector_cnt_th_1_we = addr_hit[702] & reg_we & !reg_error; + assign wkup_detector_cnt_th_1_we = addr_hit[688] & reg_we & !reg_error; - assign wkup_detector_cnt_th_2_we = addr_hit[703] & reg_we & !reg_error; + assign wkup_detector_cnt_th_2_we = addr_hit[689] & reg_we & !reg_error; - assign wkup_detector_cnt_th_3_we = addr_hit[704] & reg_we & !reg_error; + assign wkup_detector_cnt_th_3_we = addr_hit[690] & reg_we & !reg_error; - assign wkup_detector_cnt_th_4_we = addr_hit[705] & reg_we & !reg_error; + assign wkup_detector_cnt_th_4_we = addr_hit[691] & reg_we & !reg_error; - assign wkup_detector_cnt_th_5_we = addr_hit[706] & reg_we & !reg_error; + assign wkup_detector_cnt_th_5_we = addr_hit[692] & reg_we & !reg_error; - assign wkup_detector_cnt_th_6_we = addr_hit[707] & reg_we & !reg_error; + assign wkup_detector_cnt_th_6_we = addr_hit[693] & reg_we & !reg_error; - assign wkup_detector_cnt_th_7_we = addr_hit[708] & reg_we & !reg_error; + assign wkup_detector_cnt_th_7_we = addr_hit[694] & reg_we & !reg_error; - assign wkup_detector_padsel_0_we = addr_hit[709] & reg_we & !reg_error; + assign wkup_detector_padsel_0_we = addr_hit[695] & reg_we & !reg_error; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[710] & reg_we & !reg_error; + assign wkup_detector_padsel_1_we = addr_hit[696] & reg_we & !reg_error; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[711] & reg_we & !reg_error; + assign wkup_detector_padsel_2_we = addr_hit[697] & reg_we & !reg_error; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[712] & reg_we & !reg_error; + assign wkup_detector_padsel_3_we = addr_hit[698] & reg_we & !reg_error; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[713] & reg_we & !reg_error; + assign wkup_detector_padsel_4_we = addr_hit[699] & reg_we & !reg_error; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[714] & reg_we & !reg_error; + assign wkup_detector_padsel_5_we = addr_hit[700] & reg_we & !reg_error; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[715] & reg_we & !reg_error; + assign wkup_detector_padsel_6_we = addr_hit[701] & reg_we & !reg_error; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[716] & reg_we & !reg_error; + assign wkup_detector_padsel_7_we = addr_hit[702] & reg_we & !reg_error; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_we = addr_hit[717] & reg_we & !reg_error; + assign wkup_cause_we = addr_hit[703] & reg_we & !reg_error; @@ -45570,666 +45045,652 @@ reg_we_check[55] = mio_periph_insel_regwen_54_we; reg_we_check[56] = mio_periph_insel_regwen_55_we; reg_we_check[57] = mio_periph_insel_regwen_56_we; - reg_we_check[58] = mio_periph_insel_regwen_57_we; - reg_we_check[59] = mio_periph_insel_0_gated_we; - reg_we_check[60] = mio_periph_insel_1_gated_we; - reg_we_check[61] = mio_periph_insel_2_gated_we; - reg_we_check[62] = mio_periph_insel_3_gated_we; - reg_we_check[63] = mio_periph_insel_4_gated_we; - reg_we_check[64] = mio_periph_insel_5_gated_we; - reg_we_check[65] = mio_periph_insel_6_gated_we; - reg_we_check[66] = mio_periph_insel_7_gated_we; - reg_we_check[67] = mio_periph_insel_8_gated_we; - reg_we_check[68] = mio_periph_insel_9_gated_we; - reg_we_check[69] = mio_periph_insel_10_gated_we; - reg_we_check[70] = mio_periph_insel_11_gated_we; - reg_we_check[71] = mio_periph_insel_12_gated_we; - reg_we_check[72] = mio_periph_insel_13_gated_we; - reg_we_check[73] = mio_periph_insel_14_gated_we; - reg_we_check[74] = mio_periph_insel_15_gated_we; - reg_we_check[75] = mio_periph_insel_16_gated_we; - reg_we_check[76] = mio_periph_insel_17_gated_we; - reg_we_check[77] = mio_periph_insel_18_gated_we; - reg_we_check[78] = mio_periph_insel_19_gated_we; - reg_we_check[79] = mio_periph_insel_20_gated_we; - reg_we_check[80] = mio_periph_insel_21_gated_we; - reg_we_check[81] = mio_periph_insel_22_gated_we; - reg_we_check[82] = mio_periph_insel_23_gated_we; - reg_we_check[83] = mio_periph_insel_24_gated_we; - reg_we_check[84] = mio_periph_insel_25_gated_we; - reg_we_check[85] = mio_periph_insel_26_gated_we; - reg_we_check[86] = mio_periph_insel_27_gated_we; - reg_we_check[87] = mio_periph_insel_28_gated_we; - reg_we_check[88] = mio_periph_insel_29_gated_we; - reg_we_check[89] = mio_periph_insel_30_gated_we; - reg_we_check[90] = mio_periph_insel_31_gated_we; - reg_we_check[91] = mio_periph_insel_32_gated_we; - reg_we_check[92] = mio_periph_insel_33_gated_we; - reg_we_check[93] = mio_periph_insel_34_gated_we; - reg_we_check[94] = mio_periph_insel_35_gated_we; - reg_we_check[95] = mio_periph_insel_36_gated_we; - reg_we_check[96] = mio_periph_insel_37_gated_we; - reg_we_check[97] = mio_periph_insel_38_gated_we; - reg_we_check[98] = mio_periph_insel_39_gated_we; - reg_we_check[99] = mio_periph_insel_40_gated_we; - reg_we_check[100] = mio_periph_insel_41_gated_we; - reg_we_check[101] = mio_periph_insel_42_gated_we; - reg_we_check[102] = mio_periph_insel_43_gated_we; - reg_we_check[103] = mio_periph_insel_44_gated_we; - reg_we_check[104] = mio_periph_insel_45_gated_we; - reg_we_check[105] = mio_periph_insel_46_gated_we; - reg_we_check[106] = mio_periph_insel_47_gated_we; - reg_we_check[107] = mio_periph_insel_48_gated_we; - reg_we_check[108] = mio_periph_insel_49_gated_we; - reg_we_check[109] = mio_periph_insel_50_gated_we; - reg_we_check[110] = mio_periph_insel_51_gated_we; - reg_we_check[111] = mio_periph_insel_52_gated_we; - reg_we_check[112] = mio_periph_insel_53_gated_we; - reg_we_check[113] = mio_periph_insel_54_gated_we; - reg_we_check[114] = mio_periph_insel_55_gated_we; - reg_we_check[115] = mio_periph_insel_56_gated_we; - reg_we_check[116] = mio_periph_insel_57_gated_we; - reg_we_check[117] = mio_outsel_regwen_0_we; - reg_we_check[118] = mio_outsel_regwen_1_we; - reg_we_check[119] = mio_outsel_regwen_2_we; - reg_we_check[120] = mio_outsel_regwen_3_we; - reg_we_check[121] = mio_outsel_regwen_4_we; - reg_we_check[122] = mio_outsel_regwen_5_we; - reg_we_check[123] = mio_outsel_regwen_6_we; - reg_we_check[124] = mio_outsel_regwen_7_we; - reg_we_check[125] = mio_outsel_regwen_8_we; - reg_we_check[126] = mio_outsel_regwen_9_we; - reg_we_check[127] = mio_outsel_regwen_10_we; - reg_we_check[128] = mio_outsel_regwen_11_we; - reg_we_check[129] = mio_outsel_regwen_12_we; - reg_we_check[130] = mio_outsel_regwen_13_we; - reg_we_check[131] = mio_outsel_regwen_14_we; - reg_we_check[132] = mio_outsel_regwen_15_we; - reg_we_check[133] = mio_outsel_regwen_16_we; - reg_we_check[134] = mio_outsel_regwen_17_we; - reg_we_check[135] = mio_outsel_regwen_18_we; - reg_we_check[136] = mio_outsel_regwen_19_we; - reg_we_check[137] = mio_outsel_regwen_20_we; - reg_we_check[138] = mio_outsel_regwen_21_we; - reg_we_check[139] = mio_outsel_regwen_22_we; - reg_we_check[140] = mio_outsel_regwen_23_we; - reg_we_check[141] = mio_outsel_regwen_24_we; - reg_we_check[142] = mio_outsel_regwen_25_we; - reg_we_check[143] = mio_outsel_regwen_26_we; - reg_we_check[144] = mio_outsel_regwen_27_we; - reg_we_check[145] = mio_outsel_regwen_28_we; - reg_we_check[146] = mio_outsel_regwen_29_we; - reg_we_check[147] = mio_outsel_regwen_30_we; - reg_we_check[148] = mio_outsel_regwen_31_we; - reg_we_check[149] = mio_outsel_regwen_32_we; - reg_we_check[150] = mio_outsel_regwen_33_we; - reg_we_check[151] = mio_outsel_regwen_34_we; - reg_we_check[152] = mio_outsel_regwen_35_we; - reg_we_check[153] = mio_outsel_regwen_36_we; - reg_we_check[154] = mio_outsel_regwen_37_we; - reg_we_check[155] = mio_outsel_regwen_38_we; - reg_we_check[156] = mio_outsel_regwen_39_we; - reg_we_check[157] = mio_outsel_regwen_40_we; - reg_we_check[158] = mio_outsel_regwen_41_we; - reg_we_check[159] = mio_outsel_regwen_42_we; - reg_we_check[160] = mio_outsel_regwen_43_we; - reg_we_check[161] = mio_outsel_regwen_44_we; - reg_we_check[162] = mio_outsel_regwen_45_we; - reg_we_check[163] = mio_outsel_regwen_46_we; - reg_we_check[164] = mio_outsel_regwen_47_we; - reg_we_check[165] = mio_outsel_regwen_48_we; - reg_we_check[166] = mio_outsel_regwen_49_we; - reg_we_check[167] = mio_outsel_regwen_50_we; - reg_we_check[168] = mio_outsel_regwen_51_we; - reg_we_check[169] = mio_outsel_regwen_52_we; - reg_we_check[170] = mio_outsel_0_gated_we; - reg_we_check[171] = mio_outsel_1_gated_we; - reg_we_check[172] = mio_outsel_2_gated_we; - reg_we_check[173] = mio_outsel_3_gated_we; - reg_we_check[174] = mio_outsel_4_gated_we; - reg_we_check[175] = mio_outsel_5_gated_we; - reg_we_check[176] = mio_outsel_6_gated_we; - reg_we_check[177] = mio_outsel_7_gated_we; - reg_we_check[178] = mio_outsel_8_gated_we; - reg_we_check[179] = mio_outsel_9_gated_we; - reg_we_check[180] = mio_outsel_10_gated_we; - reg_we_check[181] = mio_outsel_11_gated_we; - reg_we_check[182] = mio_outsel_12_gated_we; - reg_we_check[183] = mio_outsel_13_gated_we; - reg_we_check[184] = mio_outsel_14_gated_we; - reg_we_check[185] = mio_outsel_15_gated_we; - reg_we_check[186] = mio_outsel_16_gated_we; - reg_we_check[187] = mio_outsel_17_gated_we; - reg_we_check[188] = mio_outsel_18_gated_we; - reg_we_check[189] = mio_outsel_19_gated_we; - reg_we_check[190] = mio_outsel_20_gated_we; - reg_we_check[191] = mio_outsel_21_gated_we; - reg_we_check[192] = mio_outsel_22_gated_we; - reg_we_check[193] = mio_outsel_23_gated_we; - reg_we_check[194] = mio_outsel_24_gated_we; - reg_we_check[195] = mio_outsel_25_gated_we; - reg_we_check[196] = mio_outsel_26_gated_we; - reg_we_check[197] = mio_outsel_27_gated_we; - reg_we_check[198] = mio_outsel_28_gated_we; - reg_we_check[199] = mio_outsel_29_gated_we; - reg_we_check[200] = mio_outsel_30_gated_we; - reg_we_check[201] = mio_outsel_31_gated_we; - reg_we_check[202] = mio_outsel_32_gated_we; - reg_we_check[203] = mio_outsel_33_gated_we; - reg_we_check[204] = mio_outsel_34_gated_we; - reg_we_check[205] = mio_outsel_35_gated_we; - reg_we_check[206] = mio_outsel_36_gated_we; - reg_we_check[207] = mio_outsel_37_gated_we; - reg_we_check[208] = mio_outsel_38_gated_we; - reg_we_check[209] = mio_outsel_39_gated_we; - reg_we_check[210] = mio_outsel_40_gated_we; - reg_we_check[211] = mio_outsel_41_gated_we; - reg_we_check[212] = mio_outsel_42_gated_we; - reg_we_check[213] = mio_outsel_43_gated_we; - reg_we_check[214] = mio_outsel_44_gated_we; - reg_we_check[215] = mio_outsel_45_gated_we; - reg_we_check[216] = mio_outsel_46_gated_we; - reg_we_check[217] = mio_outsel_47_gated_we; - reg_we_check[218] = mio_outsel_48_gated_we; - reg_we_check[219] = mio_outsel_49_gated_we; - reg_we_check[220] = mio_outsel_50_gated_we; - reg_we_check[221] = mio_outsel_51_gated_we; - reg_we_check[222] = mio_outsel_52_gated_we; - reg_we_check[223] = mio_pad_attr_regwen_0_we; - reg_we_check[224] = mio_pad_attr_regwen_1_we; - reg_we_check[225] = mio_pad_attr_regwen_2_we; - reg_we_check[226] = mio_pad_attr_regwen_3_we; - reg_we_check[227] = mio_pad_attr_regwen_4_we; - reg_we_check[228] = mio_pad_attr_regwen_5_we; - reg_we_check[229] = mio_pad_attr_regwen_6_we; - reg_we_check[230] = mio_pad_attr_regwen_7_we; - reg_we_check[231] = mio_pad_attr_regwen_8_we; - reg_we_check[232] = mio_pad_attr_regwen_9_we; - reg_we_check[233] = mio_pad_attr_regwen_10_we; - reg_we_check[234] = mio_pad_attr_regwen_11_we; - reg_we_check[235] = mio_pad_attr_regwen_12_we; - reg_we_check[236] = mio_pad_attr_regwen_13_we; - reg_we_check[237] = mio_pad_attr_regwen_14_we; - reg_we_check[238] = mio_pad_attr_regwen_15_we; - reg_we_check[239] = mio_pad_attr_regwen_16_we; - reg_we_check[240] = mio_pad_attr_regwen_17_we; - reg_we_check[241] = mio_pad_attr_regwen_18_we; - reg_we_check[242] = mio_pad_attr_regwen_19_we; - reg_we_check[243] = mio_pad_attr_regwen_20_we; - reg_we_check[244] = mio_pad_attr_regwen_21_we; - reg_we_check[245] = mio_pad_attr_regwen_22_we; - reg_we_check[246] = mio_pad_attr_regwen_23_we; - reg_we_check[247] = mio_pad_attr_regwen_24_we; - reg_we_check[248] = mio_pad_attr_regwen_25_we; - reg_we_check[249] = mio_pad_attr_regwen_26_we; - reg_we_check[250] = mio_pad_attr_regwen_27_we; - reg_we_check[251] = mio_pad_attr_regwen_28_we; - reg_we_check[252] = mio_pad_attr_regwen_29_we; - reg_we_check[253] = mio_pad_attr_regwen_30_we; - reg_we_check[254] = mio_pad_attr_regwen_31_we; - reg_we_check[255] = mio_pad_attr_regwen_32_we; - reg_we_check[256] = mio_pad_attr_regwen_33_we; - reg_we_check[257] = mio_pad_attr_regwen_34_we; - reg_we_check[258] = mio_pad_attr_regwen_35_we; - reg_we_check[259] = mio_pad_attr_regwen_36_we; - reg_we_check[260] = mio_pad_attr_regwen_37_we; - reg_we_check[261] = mio_pad_attr_regwen_38_we; - reg_we_check[262] = mio_pad_attr_regwen_39_we; - reg_we_check[263] = mio_pad_attr_regwen_40_we; - reg_we_check[264] = mio_pad_attr_regwen_41_we; - reg_we_check[265] = mio_pad_attr_regwen_42_we; - reg_we_check[266] = mio_pad_attr_regwen_43_we; - reg_we_check[267] = mio_pad_attr_regwen_44_we; - reg_we_check[268] = mio_pad_attr_regwen_45_we; - reg_we_check[269] = mio_pad_attr_regwen_46_we; - reg_we_check[270] = mio_pad_attr_regwen_47_we; - reg_we_check[271] = mio_pad_attr_regwen_48_we; - reg_we_check[272] = mio_pad_attr_regwen_49_we; - reg_we_check[273] = mio_pad_attr_regwen_50_we; - reg_we_check[274] = mio_pad_attr_regwen_51_we; - reg_we_check[275] = mio_pad_attr_regwen_52_we; - reg_we_check[276] = mio_pad_attr_0_gated_we; - reg_we_check[277] = mio_pad_attr_1_gated_we; - reg_we_check[278] = mio_pad_attr_2_gated_we; - reg_we_check[279] = mio_pad_attr_3_gated_we; - reg_we_check[280] = mio_pad_attr_4_gated_we; - reg_we_check[281] = mio_pad_attr_5_gated_we; - reg_we_check[282] = mio_pad_attr_6_gated_we; - reg_we_check[283] = mio_pad_attr_7_gated_we; - reg_we_check[284] = mio_pad_attr_8_gated_we; - reg_we_check[285] = mio_pad_attr_9_gated_we; - reg_we_check[286] = mio_pad_attr_10_gated_we; - reg_we_check[287] = mio_pad_attr_11_gated_we; - reg_we_check[288] = mio_pad_attr_12_gated_we; - reg_we_check[289] = mio_pad_attr_13_gated_we; - reg_we_check[290] = mio_pad_attr_14_gated_we; - reg_we_check[291] = mio_pad_attr_15_gated_we; - reg_we_check[292] = mio_pad_attr_16_gated_we; - reg_we_check[293] = mio_pad_attr_17_gated_we; - reg_we_check[294] = mio_pad_attr_18_gated_we; - reg_we_check[295] = mio_pad_attr_19_gated_we; - reg_we_check[296] = mio_pad_attr_20_gated_we; - reg_we_check[297] = mio_pad_attr_21_gated_we; - reg_we_check[298] = mio_pad_attr_22_gated_we; - reg_we_check[299] = mio_pad_attr_23_gated_we; - reg_we_check[300] = mio_pad_attr_24_gated_we; - reg_we_check[301] = mio_pad_attr_25_gated_we; - reg_we_check[302] = mio_pad_attr_26_gated_we; - reg_we_check[303] = mio_pad_attr_27_gated_we; - reg_we_check[304] = mio_pad_attr_28_gated_we; - reg_we_check[305] = mio_pad_attr_29_gated_we; - reg_we_check[306] = mio_pad_attr_30_gated_we; - reg_we_check[307] = mio_pad_attr_31_gated_we; - reg_we_check[308] = mio_pad_attr_32_gated_we; - reg_we_check[309] = mio_pad_attr_33_gated_we; - reg_we_check[310] = mio_pad_attr_34_gated_we; - reg_we_check[311] = mio_pad_attr_35_gated_we; - reg_we_check[312] = mio_pad_attr_36_gated_we; - reg_we_check[313] = mio_pad_attr_37_gated_we; - reg_we_check[314] = mio_pad_attr_38_gated_we; - reg_we_check[315] = mio_pad_attr_39_gated_we; - reg_we_check[316] = mio_pad_attr_40_gated_we; - reg_we_check[317] = mio_pad_attr_41_gated_we; - reg_we_check[318] = mio_pad_attr_42_gated_we; - reg_we_check[319] = mio_pad_attr_43_gated_we; - reg_we_check[320] = mio_pad_attr_44_gated_we; - reg_we_check[321] = mio_pad_attr_45_gated_we; - reg_we_check[322] = mio_pad_attr_46_gated_we; - reg_we_check[323] = mio_pad_attr_47_gated_we; - reg_we_check[324] = mio_pad_attr_48_gated_we; - reg_we_check[325] = mio_pad_attr_49_gated_we; - reg_we_check[326] = mio_pad_attr_50_gated_we; - reg_we_check[327] = mio_pad_attr_51_gated_we; - reg_we_check[328] = mio_pad_attr_52_gated_we; - reg_we_check[329] = dio_pad_attr_regwen_0_we; - reg_we_check[330] = dio_pad_attr_regwen_1_we; - reg_we_check[331] = dio_pad_attr_regwen_2_we; - reg_we_check[332] = dio_pad_attr_regwen_3_we; - reg_we_check[333] = dio_pad_attr_regwen_4_we; - reg_we_check[334] = dio_pad_attr_regwen_5_we; - reg_we_check[335] = dio_pad_attr_regwen_6_we; - reg_we_check[336] = dio_pad_attr_regwen_7_we; - reg_we_check[337] = dio_pad_attr_regwen_8_we; - reg_we_check[338] = dio_pad_attr_regwen_9_we; - reg_we_check[339] = dio_pad_attr_regwen_10_we; - reg_we_check[340] = dio_pad_attr_regwen_11_we; - reg_we_check[341] = dio_pad_attr_regwen_12_we; - reg_we_check[342] = dio_pad_attr_regwen_13_we; - reg_we_check[343] = dio_pad_attr_regwen_14_we; - reg_we_check[344] = dio_pad_attr_regwen_15_we; - reg_we_check[345] = dio_pad_attr_regwen_16_we; - reg_we_check[346] = dio_pad_attr_regwen_17_we; - reg_we_check[347] = dio_pad_attr_regwen_18_we; - reg_we_check[348] = dio_pad_attr_regwen_19_we; - reg_we_check[349] = dio_pad_attr_regwen_20_we; - reg_we_check[350] = dio_pad_attr_regwen_21_we; - reg_we_check[351] = dio_pad_attr_regwen_22_we; - reg_we_check[352] = dio_pad_attr_regwen_23_we; - reg_we_check[353] = dio_pad_attr_regwen_24_we; - reg_we_check[354] = dio_pad_attr_regwen_25_we; - reg_we_check[355] = dio_pad_attr_regwen_26_we; - reg_we_check[356] = dio_pad_attr_regwen_27_we; - reg_we_check[357] = dio_pad_attr_regwen_28_we; - reg_we_check[358] = dio_pad_attr_regwen_29_we; - reg_we_check[359] = dio_pad_attr_regwen_30_we; - reg_we_check[360] = dio_pad_attr_regwen_31_we; - reg_we_check[361] = dio_pad_attr_regwen_32_we; - reg_we_check[362] = dio_pad_attr_regwen_33_we; - reg_we_check[363] = dio_pad_attr_regwen_34_we; - reg_we_check[364] = dio_pad_attr_regwen_35_we; - reg_we_check[365] = dio_pad_attr_regwen_36_we; - reg_we_check[366] = dio_pad_attr_0_gated_we; - reg_we_check[367] = dio_pad_attr_1_gated_we; - reg_we_check[368] = dio_pad_attr_2_gated_we; - reg_we_check[369] = dio_pad_attr_3_gated_we; - reg_we_check[370] = dio_pad_attr_4_gated_we; - reg_we_check[371] = dio_pad_attr_5_gated_we; - reg_we_check[372] = dio_pad_attr_6_gated_we; - reg_we_check[373] = dio_pad_attr_7_gated_we; - reg_we_check[374] = dio_pad_attr_8_gated_we; - reg_we_check[375] = dio_pad_attr_9_gated_we; - reg_we_check[376] = dio_pad_attr_10_gated_we; - reg_we_check[377] = dio_pad_attr_11_gated_we; - reg_we_check[378] = dio_pad_attr_12_gated_we; - reg_we_check[379] = dio_pad_attr_13_gated_we; - reg_we_check[380] = dio_pad_attr_14_gated_we; - reg_we_check[381] = dio_pad_attr_15_gated_we; - reg_we_check[382] = dio_pad_attr_16_gated_we; - reg_we_check[383] = dio_pad_attr_17_gated_we; - reg_we_check[384] = dio_pad_attr_18_gated_we; - reg_we_check[385] = dio_pad_attr_19_gated_we; - reg_we_check[386] = dio_pad_attr_20_gated_we; - reg_we_check[387] = dio_pad_attr_21_gated_we; - reg_we_check[388] = dio_pad_attr_22_gated_we; - reg_we_check[389] = dio_pad_attr_23_gated_we; - reg_we_check[390] = dio_pad_attr_24_gated_we; - reg_we_check[391] = dio_pad_attr_25_gated_we; - reg_we_check[392] = dio_pad_attr_26_gated_we; - reg_we_check[393] = dio_pad_attr_27_gated_we; - reg_we_check[394] = dio_pad_attr_28_gated_we; - reg_we_check[395] = dio_pad_attr_29_gated_we; - reg_we_check[396] = dio_pad_attr_30_gated_we; - reg_we_check[397] = dio_pad_attr_31_gated_we; - reg_we_check[398] = dio_pad_attr_32_gated_we; - reg_we_check[399] = dio_pad_attr_33_gated_we; - reg_we_check[400] = dio_pad_attr_34_gated_we; - reg_we_check[401] = dio_pad_attr_35_gated_we; - reg_we_check[402] = dio_pad_attr_36_gated_we; - reg_we_check[403] = mio_pad_sleep_status_0_we; - reg_we_check[404] = mio_pad_sleep_status_1_we; - reg_we_check[405] = mio_pad_sleep_regwen_0_we; - reg_we_check[406] = mio_pad_sleep_regwen_1_we; - reg_we_check[407] = mio_pad_sleep_regwen_2_we; - reg_we_check[408] = mio_pad_sleep_regwen_3_we; - reg_we_check[409] = mio_pad_sleep_regwen_4_we; - reg_we_check[410] = mio_pad_sleep_regwen_5_we; - reg_we_check[411] = mio_pad_sleep_regwen_6_we; - reg_we_check[412] = mio_pad_sleep_regwen_7_we; - reg_we_check[413] = mio_pad_sleep_regwen_8_we; - reg_we_check[414] = mio_pad_sleep_regwen_9_we; - reg_we_check[415] = mio_pad_sleep_regwen_10_we; - reg_we_check[416] = mio_pad_sleep_regwen_11_we; - reg_we_check[417] = mio_pad_sleep_regwen_12_we; - reg_we_check[418] = mio_pad_sleep_regwen_13_we; - reg_we_check[419] = mio_pad_sleep_regwen_14_we; - reg_we_check[420] = mio_pad_sleep_regwen_15_we; - reg_we_check[421] = mio_pad_sleep_regwen_16_we; - reg_we_check[422] = mio_pad_sleep_regwen_17_we; - reg_we_check[423] = mio_pad_sleep_regwen_18_we; - reg_we_check[424] = mio_pad_sleep_regwen_19_we; - reg_we_check[425] = mio_pad_sleep_regwen_20_we; - reg_we_check[426] = mio_pad_sleep_regwen_21_we; - reg_we_check[427] = mio_pad_sleep_regwen_22_we; - reg_we_check[428] = mio_pad_sleep_regwen_23_we; - reg_we_check[429] = mio_pad_sleep_regwen_24_we; - reg_we_check[430] = mio_pad_sleep_regwen_25_we; - reg_we_check[431] = mio_pad_sleep_regwen_26_we; - reg_we_check[432] = mio_pad_sleep_regwen_27_we; - reg_we_check[433] = mio_pad_sleep_regwen_28_we; - reg_we_check[434] = mio_pad_sleep_regwen_29_we; - reg_we_check[435] = mio_pad_sleep_regwen_30_we; - reg_we_check[436] = mio_pad_sleep_regwen_31_we; - reg_we_check[437] = mio_pad_sleep_regwen_32_we; - reg_we_check[438] = mio_pad_sleep_regwen_33_we; - reg_we_check[439] = mio_pad_sleep_regwen_34_we; - reg_we_check[440] = mio_pad_sleep_regwen_35_we; - reg_we_check[441] = mio_pad_sleep_regwen_36_we; - reg_we_check[442] = mio_pad_sleep_regwen_37_we; - reg_we_check[443] = mio_pad_sleep_regwen_38_we; - reg_we_check[444] = mio_pad_sleep_regwen_39_we; - reg_we_check[445] = mio_pad_sleep_regwen_40_we; - reg_we_check[446] = mio_pad_sleep_regwen_41_we; - reg_we_check[447] = mio_pad_sleep_regwen_42_we; - reg_we_check[448] = mio_pad_sleep_regwen_43_we; - reg_we_check[449] = mio_pad_sleep_regwen_44_we; - reg_we_check[450] = mio_pad_sleep_regwen_45_we; - reg_we_check[451] = mio_pad_sleep_regwen_46_we; - reg_we_check[452] = mio_pad_sleep_regwen_47_we; - reg_we_check[453] = mio_pad_sleep_regwen_48_we; - reg_we_check[454] = mio_pad_sleep_regwen_49_we; - reg_we_check[455] = mio_pad_sleep_regwen_50_we; - reg_we_check[456] = mio_pad_sleep_regwen_51_we; - reg_we_check[457] = mio_pad_sleep_regwen_52_we; - reg_we_check[458] = mio_pad_sleep_en_0_gated_we; - reg_we_check[459] = mio_pad_sleep_en_1_gated_we; - reg_we_check[460] = mio_pad_sleep_en_2_gated_we; - reg_we_check[461] = mio_pad_sleep_en_3_gated_we; - reg_we_check[462] = mio_pad_sleep_en_4_gated_we; - reg_we_check[463] = mio_pad_sleep_en_5_gated_we; - reg_we_check[464] = mio_pad_sleep_en_6_gated_we; - reg_we_check[465] = mio_pad_sleep_en_7_gated_we; - reg_we_check[466] = mio_pad_sleep_en_8_gated_we; - reg_we_check[467] = mio_pad_sleep_en_9_gated_we; - reg_we_check[468] = mio_pad_sleep_en_10_gated_we; - reg_we_check[469] = mio_pad_sleep_en_11_gated_we; - reg_we_check[470] = mio_pad_sleep_en_12_gated_we; - reg_we_check[471] = mio_pad_sleep_en_13_gated_we; - reg_we_check[472] = mio_pad_sleep_en_14_gated_we; - reg_we_check[473] = mio_pad_sleep_en_15_gated_we; - reg_we_check[474] = mio_pad_sleep_en_16_gated_we; - reg_we_check[475] = mio_pad_sleep_en_17_gated_we; - reg_we_check[476] = mio_pad_sleep_en_18_gated_we; - reg_we_check[477] = mio_pad_sleep_en_19_gated_we; - reg_we_check[478] = mio_pad_sleep_en_20_gated_we; - reg_we_check[479] = mio_pad_sleep_en_21_gated_we; - reg_we_check[480] = mio_pad_sleep_en_22_gated_we; - reg_we_check[481] = mio_pad_sleep_en_23_gated_we; - reg_we_check[482] = mio_pad_sleep_en_24_gated_we; - reg_we_check[483] = mio_pad_sleep_en_25_gated_we; - reg_we_check[484] = mio_pad_sleep_en_26_gated_we; - reg_we_check[485] = mio_pad_sleep_en_27_gated_we; - reg_we_check[486] = mio_pad_sleep_en_28_gated_we; - reg_we_check[487] = mio_pad_sleep_en_29_gated_we; - reg_we_check[488] = mio_pad_sleep_en_30_gated_we; - reg_we_check[489] = mio_pad_sleep_en_31_gated_we; - reg_we_check[490] = mio_pad_sleep_en_32_gated_we; - reg_we_check[491] = mio_pad_sleep_en_33_gated_we; - reg_we_check[492] = mio_pad_sleep_en_34_gated_we; - reg_we_check[493] = mio_pad_sleep_en_35_gated_we; - reg_we_check[494] = mio_pad_sleep_en_36_gated_we; - reg_we_check[495] = mio_pad_sleep_en_37_gated_we; - reg_we_check[496] = mio_pad_sleep_en_38_gated_we; - reg_we_check[497] = mio_pad_sleep_en_39_gated_we; - reg_we_check[498] = mio_pad_sleep_en_40_gated_we; - reg_we_check[499] = mio_pad_sleep_en_41_gated_we; - reg_we_check[500] = mio_pad_sleep_en_42_gated_we; - reg_we_check[501] = mio_pad_sleep_en_43_gated_we; - reg_we_check[502] = mio_pad_sleep_en_44_gated_we; - reg_we_check[503] = mio_pad_sleep_en_45_gated_we; - reg_we_check[504] = mio_pad_sleep_en_46_gated_we; - reg_we_check[505] = mio_pad_sleep_en_47_gated_we; - reg_we_check[506] = mio_pad_sleep_en_48_gated_we; - reg_we_check[507] = mio_pad_sleep_en_49_gated_we; - reg_we_check[508] = mio_pad_sleep_en_50_gated_we; - reg_we_check[509] = mio_pad_sleep_en_51_gated_we; - reg_we_check[510] = mio_pad_sleep_en_52_gated_we; - reg_we_check[511] = mio_pad_sleep_mode_0_gated_we; - reg_we_check[512] = mio_pad_sleep_mode_1_gated_we; - reg_we_check[513] = mio_pad_sleep_mode_2_gated_we; - reg_we_check[514] = mio_pad_sleep_mode_3_gated_we; - reg_we_check[515] = mio_pad_sleep_mode_4_gated_we; - reg_we_check[516] = mio_pad_sleep_mode_5_gated_we; - reg_we_check[517] = mio_pad_sleep_mode_6_gated_we; - reg_we_check[518] = mio_pad_sleep_mode_7_gated_we; - reg_we_check[519] = mio_pad_sleep_mode_8_gated_we; - reg_we_check[520] = mio_pad_sleep_mode_9_gated_we; - reg_we_check[521] = mio_pad_sleep_mode_10_gated_we; - reg_we_check[522] = mio_pad_sleep_mode_11_gated_we; - reg_we_check[523] = mio_pad_sleep_mode_12_gated_we; - reg_we_check[524] = mio_pad_sleep_mode_13_gated_we; - reg_we_check[525] = mio_pad_sleep_mode_14_gated_we; - reg_we_check[526] = mio_pad_sleep_mode_15_gated_we; - reg_we_check[527] = mio_pad_sleep_mode_16_gated_we; - reg_we_check[528] = mio_pad_sleep_mode_17_gated_we; - reg_we_check[529] = mio_pad_sleep_mode_18_gated_we; - reg_we_check[530] = mio_pad_sleep_mode_19_gated_we; - reg_we_check[531] = mio_pad_sleep_mode_20_gated_we; - reg_we_check[532] = mio_pad_sleep_mode_21_gated_we; - reg_we_check[533] = mio_pad_sleep_mode_22_gated_we; - reg_we_check[534] = mio_pad_sleep_mode_23_gated_we; - reg_we_check[535] = mio_pad_sleep_mode_24_gated_we; - reg_we_check[536] = mio_pad_sleep_mode_25_gated_we; - reg_we_check[537] = mio_pad_sleep_mode_26_gated_we; - reg_we_check[538] = mio_pad_sleep_mode_27_gated_we; - reg_we_check[539] = mio_pad_sleep_mode_28_gated_we; - reg_we_check[540] = mio_pad_sleep_mode_29_gated_we; - reg_we_check[541] = mio_pad_sleep_mode_30_gated_we; - reg_we_check[542] = mio_pad_sleep_mode_31_gated_we; - reg_we_check[543] = mio_pad_sleep_mode_32_gated_we; - reg_we_check[544] = mio_pad_sleep_mode_33_gated_we; - reg_we_check[545] = mio_pad_sleep_mode_34_gated_we; - reg_we_check[546] = mio_pad_sleep_mode_35_gated_we; - reg_we_check[547] = mio_pad_sleep_mode_36_gated_we; - reg_we_check[548] = mio_pad_sleep_mode_37_gated_we; - reg_we_check[549] = mio_pad_sleep_mode_38_gated_we; - reg_we_check[550] = mio_pad_sleep_mode_39_gated_we; - reg_we_check[551] = mio_pad_sleep_mode_40_gated_we; - reg_we_check[552] = mio_pad_sleep_mode_41_gated_we; - reg_we_check[553] = mio_pad_sleep_mode_42_gated_we; - reg_we_check[554] = mio_pad_sleep_mode_43_gated_we; - reg_we_check[555] = mio_pad_sleep_mode_44_gated_we; - reg_we_check[556] = mio_pad_sleep_mode_45_gated_we; - reg_we_check[557] = mio_pad_sleep_mode_46_gated_we; - reg_we_check[558] = mio_pad_sleep_mode_47_gated_we; - reg_we_check[559] = mio_pad_sleep_mode_48_gated_we; - reg_we_check[560] = mio_pad_sleep_mode_49_gated_we; - reg_we_check[561] = mio_pad_sleep_mode_50_gated_we; - reg_we_check[562] = mio_pad_sleep_mode_51_gated_we; - reg_we_check[563] = mio_pad_sleep_mode_52_gated_we; - reg_we_check[564] = dio_pad_sleep_status_0_we; - reg_we_check[565] = dio_pad_sleep_status_1_we; - reg_we_check[566] = dio_pad_sleep_regwen_0_we; - reg_we_check[567] = dio_pad_sleep_regwen_1_we; - reg_we_check[568] = dio_pad_sleep_regwen_2_we; - reg_we_check[569] = dio_pad_sleep_regwen_3_we; - reg_we_check[570] = dio_pad_sleep_regwen_4_we; - reg_we_check[571] = dio_pad_sleep_regwen_5_we; - reg_we_check[572] = dio_pad_sleep_regwen_6_we; - reg_we_check[573] = dio_pad_sleep_regwen_7_we; - reg_we_check[574] = dio_pad_sleep_regwen_8_we; - reg_we_check[575] = dio_pad_sleep_regwen_9_we; - reg_we_check[576] = dio_pad_sleep_regwen_10_we; - reg_we_check[577] = dio_pad_sleep_regwen_11_we; - reg_we_check[578] = dio_pad_sleep_regwen_12_we; - reg_we_check[579] = dio_pad_sleep_regwen_13_we; - reg_we_check[580] = dio_pad_sleep_regwen_14_we; - reg_we_check[581] = dio_pad_sleep_regwen_15_we; - reg_we_check[582] = dio_pad_sleep_regwen_16_we; - reg_we_check[583] = dio_pad_sleep_regwen_17_we; - reg_we_check[584] = dio_pad_sleep_regwen_18_we; - reg_we_check[585] = dio_pad_sleep_regwen_19_we; - reg_we_check[586] = dio_pad_sleep_regwen_20_we; - reg_we_check[587] = dio_pad_sleep_regwen_21_we; - reg_we_check[588] = dio_pad_sleep_regwen_22_we; - reg_we_check[589] = dio_pad_sleep_regwen_23_we; - reg_we_check[590] = dio_pad_sleep_regwen_24_we; - reg_we_check[591] = dio_pad_sleep_regwen_25_we; - reg_we_check[592] = dio_pad_sleep_regwen_26_we; - reg_we_check[593] = dio_pad_sleep_regwen_27_we; - reg_we_check[594] = dio_pad_sleep_regwen_28_we; - reg_we_check[595] = dio_pad_sleep_regwen_29_we; - reg_we_check[596] = dio_pad_sleep_regwen_30_we; - reg_we_check[597] = dio_pad_sleep_regwen_31_we; - reg_we_check[598] = dio_pad_sleep_regwen_32_we; - reg_we_check[599] = dio_pad_sleep_regwen_33_we; - reg_we_check[600] = dio_pad_sleep_regwen_34_we; - reg_we_check[601] = dio_pad_sleep_regwen_35_we; - reg_we_check[602] = dio_pad_sleep_regwen_36_we; - reg_we_check[603] = dio_pad_sleep_en_0_gated_we; - reg_we_check[604] = dio_pad_sleep_en_1_gated_we; - reg_we_check[605] = dio_pad_sleep_en_2_gated_we; - reg_we_check[606] = dio_pad_sleep_en_3_gated_we; - reg_we_check[607] = dio_pad_sleep_en_4_gated_we; - reg_we_check[608] = dio_pad_sleep_en_5_gated_we; - reg_we_check[609] = dio_pad_sleep_en_6_gated_we; - reg_we_check[610] = dio_pad_sleep_en_7_gated_we; - reg_we_check[611] = dio_pad_sleep_en_8_gated_we; - reg_we_check[612] = dio_pad_sleep_en_9_gated_we; - reg_we_check[613] = dio_pad_sleep_en_10_gated_we; - reg_we_check[614] = dio_pad_sleep_en_11_gated_we; - reg_we_check[615] = dio_pad_sleep_en_12_gated_we; - reg_we_check[616] = dio_pad_sleep_en_13_gated_we; - reg_we_check[617] = dio_pad_sleep_en_14_gated_we; - reg_we_check[618] = dio_pad_sleep_en_15_gated_we; - reg_we_check[619] = dio_pad_sleep_en_16_gated_we; - reg_we_check[620] = dio_pad_sleep_en_17_gated_we; - reg_we_check[621] = dio_pad_sleep_en_18_gated_we; - reg_we_check[622] = dio_pad_sleep_en_19_gated_we; - reg_we_check[623] = dio_pad_sleep_en_20_gated_we; - reg_we_check[624] = dio_pad_sleep_en_21_gated_we; - reg_we_check[625] = dio_pad_sleep_en_22_gated_we; - reg_we_check[626] = dio_pad_sleep_en_23_gated_we; - reg_we_check[627] = dio_pad_sleep_en_24_gated_we; - reg_we_check[628] = dio_pad_sleep_en_25_gated_we; - reg_we_check[629] = dio_pad_sleep_en_26_gated_we; - reg_we_check[630] = dio_pad_sleep_en_27_gated_we; - reg_we_check[631] = dio_pad_sleep_en_28_gated_we; - reg_we_check[632] = dio_pad_sleep_en_29_gated_we; - reg_we_check[633] = dio_pad_sleep_en_30_gated_we; - reg_we_check[634] = dio_pad_sleep_en_31_gated_we; - reg_we_check[635] = dio_pad_sleep_en_32_gated_we; - reg_we_check[636] = dio_pad_sleep_en_33_gated_we; - reg_we_check[637] = dio_pad_sleep_en_34_gated_we; - reg_we_check[638] = dio_pad_sleep_en_35_gated_we; - reg_we_check[639] = dio_pad_sleep_en_36_gated_we; - reg_we_check[640] = dio_pad_sleep_mode_0_gated_we; - reg_we_check[641] = dio_pad_sleep_mode_1_gated_we; - reg_we_check[642] = dio_pad_sleep_mode_2_gated_we; - reg_we_check[643] = dio_pad_sleep_mode_3_gated_we; - reg_we_check[644] = dio_pad_sleep_mode_4_gated_we; - reg_we_check[645] = dio_pad_sleep_mode_5_gated_we; - reg_we_check[646] = dio_pad_sleep_mode_6_gated_we; - reg_we_check[647] = dio_pad_sleep_mode_7_gated_we; - reg_we_check[648] = dio_pad_sleep_mode_8_gated_we; - reg_we_check[649] = dio_pad_sleep_mode_9_gated_we; - reg_we_check[650] = dio_pad_sleep_mode_10_gated_we; - reg_we_check[651] = dio_pad_sleep_mode_11_gated_we; - reg_we_check[652] = dio_pad_sleep_mode_12_gated_we; - reg_we_check[653] = dio_pad_sleep_mode_13_gated_we; - reg_we_check[654] = dio_pad_sleep_mode_14_gated_we; - reg_we_check[655] = dio_pad_sleep_mode_15_gated_we; - reg_we_check[656] = dio_pad_sleep_mode_16_gated_we; - reg_we_check[657] = dio_pad_sleep_mode_17_gated_we; - reg_we_check[658] = dio_pad_sleep_mode_18_gated_we; - reg_we_check[659] = dio_pad_sleep_mode_19_gated_we; - reg_we_check[660] = dio_pad_sleep_mode_20_gated_we; - reg_we_check[661] = dio_pad_sleep_mode_21_gated_we; - reg_we_check[662] = dio_pad_sleep_mode_22_gated_we; - reg_we_check[663] = dio_pad_sleep_mode_23_gated_we; - reg_we_check[664] = dio_pad_sleep_mode_24_gated_we; - reg_we_check[665] = dio_pad_sleep_mode_25_gated_we; - reg_we_check[666] = dio_pad_sleep_mode_26_gated_we; - reg_we_check[667] = dio_pad_sleep_mode_27_gated_we; - reg_we_check[668] = dio_pad_sleep_mode_28_gated_we; - reg_we_check[669] = dio_pad_sleep_mode_29_gated_we; - reg_we_check[670] = dio_pad_sleep_mode_30_gated_we; - reg_we_check[671] = dio_pad_sleep_mode_31_gated_we; - reg_we_check[672] = dio_pad_sleep_mode_32_gated_we; - reg_we_check[673] = dio_pad_sleep_mode_33_gated_we; - reg_we_check[674] = dio_pad_sleep_mode_34_gated_we; - reg_we_check[675] = dio_pad_sleep_mode_35_gated_we; - reg_we_check[676] = dio_pad_sleep_mode_36_gated_we; - reg_we_check[677] = wkup_detector_regwen_0_we; - reg_we_check[678] = wkup_detector_regwen_1_we; - reg_we_check[679] = wkup_detector_regwen_2_we; - reg_we_check[680] = wkup_detector_regwen_3_we; - reg_we_check[681] = wkup_detector_regwen_4_we; - reg_we_check[682] = wkup_detector_regwen_5_we; - reg_we_check[683] = wkup_detector_regwen_6_we; - reg_we_check[684] = wkup_detector_regwen_7_we; - reg_we_check[685] = wkup_detector_en_0_we; - reg_we_check[686] = wkup_detector_en_1_we; - reg_we_check[687] = wkup_detector_en_2_we; - reg_we_check[688] = wkup_detector_en_3_we; - reg_we_check[689] = wkup_detector_en_4_we; - reg_we_check[690] = wkup_detector_en_5_we; - reg_we_check[691] = wkup_detector_en_6_we; - reg_we_check[692] = wkup_detector_en_7_we; - reg_we_check[693] = wkup_detector_0_we; - reg_we_check[694] = wkup_detector_1_we; - reg_we_check[695] = wkup_detector_2_we; - reg_we_check[696] = wkup_detector_3_we; - reg_we_check[697] = wkup_detector_4_we; - reg_we_check[698] = wkup_detector_5_we; - reg_we_check[699] = wkup_detector_6_we; - reg_we_check[700] = wkup_detector_7_we; - reg_we_check[701] = wkup_detector_cnt_th_0_we; - reg_we_check[702] = wkup_detector_cnt_th_1_we; - reg_we_check[703] = wkup_detector_cnt_th_2_we; - reg_we_check[704] = wkup_detector_cnt_th_3_we; - reg_we_check[705] = wkup_detector_cnt_th_4_we; - reg_we_check[706] = wkup_detector_cnt_th_5_we; - reg_we_check[707] = wkup_detector_cnt_th_6_we; - reg_we_check[708] = wkup_detector_cnt_th_7_we; - reg_we_check[709] = wkup_detector_padsel_0_gated_we; - reg_we_check[710] = wkup_detector_padsel_1_gated_we; - reg_we_check[711] = wkup_detector_padsel_2_gated_we; - reg_we_check[712] = wkup_detector_padsel_3_gated_we; - reg_we_check[713] = wkup_detector_padsel_4_gated_we; - reg_we_check[714] = wkup_detector_padsel_5_gated_we; - reg_we_check[715] = wkup_detector_padsel_6_gated_we; - reg_we_check[716] = wkup_detector_padsel_7_gated_we; - reg_we_check[717] = wkup_cause_we; + reg_we_check[58] = mio_periph_insel_0_gated_we; + reg_we_check[59] = mio_periph_insel_1_gated_we; + reg_we_check[60] = mio_periph_insel_2_gated_we; + reg_we_check[61] = mio_periph_insel_3_gated_we; + reg_we_check[62] = mio_periph_insel_4_gated_we; + reg_we_check[63] = mio_periph_insel_5_gated_we; + reg_we_check[64] = mio_periph_insel_6_gated_we; + reg_we_check[65] = mio_periph_insel_7_gated_we; + reg_we_check[66] = mio_periph_insel_8_gated_we; + reg_we_check[67] = mio_periph_insel_9_gated_we; + reg_we_check[68] = mio_periph_insel_10_gated_we; + reg_we_check[69] = mio_periph_insel_11_gated_we; + reg_we_check[70] = mio_periph_insel_12_gated_we; + reg_we_check[71] = mio_periph_insel_13_gated_we; + reg_we_check[72] = mio_periph_insel_14_gated_we; + reg_we_check[73] = mio_periph_insel_15_gated_we; + reg_we_check[74] = mio_periph_insel_16_gated_we; + reg_we_check[75] = mio_periph_insel_17_gated_we; + reg_we_check[76] = mio_periph_insel_18_gated_we; + reg_we_check[77] = mio_periph_insel_19_gated_we; + reg_we_check[78] = mio_periph_insel_20_gated_we; + reg_we_check[79] = mio_periph_insel_21_gated_we; + reg_we_check[80] = mio_periph_insel_22_gated_we; + reg_we_check[81] = mio_periph_insel_23_gated_we; + reg_we_check[82] = mio_periph_insel_24_gated_we; + reg_we_check[83] = mio_periph_insel_25_gated_we; + reg_we_check[84] = mio_periph_insel_26_gated_we; + reg_we_check[85] = mio_periph_insel_27_gated_we; + reg_we_check[86] = mio_periph_insel_28_gated_we; + reg_we_check[87] = mio_periph_insel_29_gated_we; + reg_we_check[88] = mio_periph_insel_30_gated_we; + reg_we_check[89] = mio_periph_insel_31_gated_we; + reg_we_check[90] = mio_periph_insel_32_gated_we; + reg_we_check[91] = mio_periph_insel_33_gated_we; + reg_we_check[92] = mio_periph_insel_34_gated_we; + reg_we_check[93] = mio_periph_insel_35_gated_we; + reg_we_check[94] = mio_periph_insel_36_gated_we; + reg_we_check[95] = mio_periph_insel_37_gated_we; + reg_we_check[96] = mio_periph_insel_38_gated_we; + reg_we_check[97] = mio_periph_insel_39_gated_we; + reg_we_check[98] = mio_periph_insel_40_gated_we; + reg_we_check[99] = mio_periph_insel_41_gated_we; + reg_we_check[100] = mio_periph_insel_42_gated_we; + reg_we_check[101] = mio_periph_insel_43_gated_we; + reg_we_check[102] = mio_periph_insel_44_gated_we; + reg_we_check[103] = mio_periph_insel_45_gated_we; + reg_we_check[104] = mio_periph_insel_46_gated_we; + reg_we_check[105] = mio_periph_insel_47_gated_we; + reg_we_check[106] = mio_periph_insel_48_gated_we; + reg_we_check[107] = mio_periph_insel_49_gated_we; + reg_we_check[108] = mio_periph_insel_50_gated_we; + reg_we_check[109] = mio_periph_insel_51_gated_we; + reg_we_check[110] = mio_periph_insel_52_gated_we; + reg_we_check[111] = mio_periph_insel_53_gated_we; + reg_we_check[112] = mio_periph_insel_54_gated_we; + reg_we_check[113] = mio_periph_insel_55_gated_we; + reg_we_check[114] = mio_periph_insel_56_gated_we; + reg_we_check[115] = mio_outsel_regwen_0_we; + reg_we_check[116] = mio_outsel_regwen_1_we; + reg_we_check[117] = mio_outsel_regwen_2_we; + reg_we_check[118] = mio_outsel_regwen_3_we; + reg_we_check[119] = mio_outsel_regwen_4_we; + reg_we_check[120] = mio_outsel_regwen_5_we; + reg_we_check[121] = mio_outsel_regwen_6_we; + reg_we_check[122] = mio_outsel_regwen_7_we; + reg_we_check[123] = mio_outsel_regwen_8_we; + reg_we_check[124] = mio_outsel_regwen_9_we; + reg_we_check[125] = mio_outsel_regwen_10_we; + reg_we_check[126] = mio_outsel_regwen_11_we; + reg_we_check[127] = mio_outsel_regwen_12_we; + reg_we_check[128] = mio_outsel_regwen_13_we; + reg_we_check[129] = mio_outsel_regwen_14_we; + reg_we_check[130] = mio_outsel_regwen_15_we; + reg_we_check[131] = mio_outsel_regwen_16_we; + reg_we_check[132] = mio_outsel_regwen_17_we; + reg_we_check[133] = mio_outsel_regwen_18_we; + reg_we_check[134] = mio_outsel_regwen_19_we; + reg_we_check[135] = mio_outsel_regwen_20_we; + reg_we_check[136] = mio_outsel_regwen_21_we; + reg_we_check[137] = mio_outsel_regwen_22_we; + reg_we_check[138] = mio_outsel_regwen_23_we; + reg_we_check[139] = mio_outsel_regwen_24_we; + reg_we_check[140] = mio_outsel_regwen_25_we; + reg_we_check[141] = mio_outsel_regwen_26_we; + reg_we_check[142] = mio_outsel_regwen_27_we; + reg_we_check[143] = mio_outsel_regwen_28_we; + reg_we_check[144] = mio_outsel_regwen_29_we; + reg_we_check[145] = mio_outsel_regwen_30_we; + reg_we_check[146] = mio_outsel_regwen_31_we; + reg_we_check[147] = mio_outsel_regwen_32_we; + reg_we_check[148] = mio_outsel_regwen_33_we; + reg_we_check[149] = mio_outsel_regwen_34_we; + reg_we_check[150] = mio_outsel_regwen_35_we; + reg_we_check[151] = mio_outsel_regwen_36_we; + reg_we_check[152] = mio_outsel_regwen_37_we; + reg_we_check[153] = mio_outsel_regwen_38_we; + reg_we_check[154] = mio_outsel_regwen_39_we; + reg_we_check[155] = mio_outsel_regwen_40_we; + reg_we_check[156] = mio_outsel_regwen_41_we; + reg_we_check[157] = mio_outsel_regwen_42_we; + reg_we_check[158] = mio_outsel_regwen_43_we; + reg_we_check[159] = mio_outsel_regwen_44_we; + reg_we_check[160] = mio_outsel_regwen_45_we; + reg_we_check[161] = mio_outsel_regwen_46_we; + reg_we_check[162] = mio_outsel_0_gated_we; + reg_we_check[163] = mio_outsel_1_gated_we; + reg_we_check[164] = mio_outsel_2_gated_we; + reg_we_check[165] = mio_outsel_3_gated_we; + reg_we_check[166] = mio_outsel_4_gated_we; + reg_we_check[167] = mio_outsel_5_gated_we; + reg_we_check[168] = mio_outsel_6_gated_we; + reg_we_check[169] = mio_outsel_7_gated_we; + reg_we_check[170] = mio_outsel_8_gated_we; + reg_we_check[171] = mio_outsel_9_gated_we; + reg_we_check[172] = mio_outsel_10_gated_we; + reg_we_check[173] = mio_outsel_11_gated_we; + reg_we_check[174] = mio_outsel_12_gated_we; + reg_we_check[175] = mio_outsel_13_gated_we; + reg_we_check[176] = mio_outsel_14_gated_we; + reg_we_check[177] = mio_outsel_15_gated_we; + reg_we_check[178] = mio_outsel_16_gated_we; + reg_we_check[179] = mio_outsel_17_gated_we; + reg_we_check[180] = mio_outsel_18_gated_we; + reg_we_check[181] = mio_outsel_19_gated_we; + reg_we_check[182] = mio_outsel_20_gated_we; + reg_we_check[183] = mio_outsel_21_gated_we; + reg_we_check[184] = mio_outsel_22_gated_we; + reg_we_check[185] = mio_outsel_23_gated_we; + reg_we_check[186] = mio_outsel_24_gated_we; + reg_we_check[187] = mio_outsel_25_gated_we; + reg_we_check[188] = mio_outsel_26_gated_we; + reg_we_check[189] = mio_outsel_27_gated_we; + reg_we_check[190] = mio_outsel_28_gated_we; + reg_we_check[191] = mio_outsel_29_gated_we; + reg_we_check[192] = mio_outsel_30_gated_we; + reg_we_check[193] = mio_outsel_31_gated_we; + reg_we_check[194] = mio_outsel_32_gated_we; + reg_we_check[195] = mio_outsel_33_gated_we; + reg_we_check[196] = mio_outsel_34_gated_we; + reg_we_check[197] = mio_outsel_35_gated_we; + reg_we_check[198] = mio_outsel_36_gated_we; + reg_we_check[199] = mio_outsel_37_gated_we; + reg_we_check[200] = mio_outsel_38_gated_we; + reg_we_check[201] = mio_outsel_39_gated_we; + reg_we_check[202] = mio_outsel_40_gated_we; + reg_we_check[203] = mio_outsel_41_gated_we; + reg_we_check[204] = mio_outsel_42_gated_we; + reg_we_check[205] = mio_outsel_43_gated_we; + reg_we_check[206] = mio_outsel_44_gated_we; + reg_we_check[207] = mio_outsel_45_gated_we; + reg_we_check[208] = mio_outsel_46_gated_we; + reg_we_check[209] = mio_pad_attr_regwen_0_we; + reg_we_check[210] = mio_pad_attr_regwen_1_we; + reg_we_check[211] = mio_pad_attr_regwen_2_we; + reg_we_check[212] = mio_pad_attr_regwen_3_we; + reg_we_check[213] = mio_pad_attr_regwen_4_we; + reg_we_check[214] = mio_pad_attr_regwen_5_we; + reg_we_check[215] = mio_pad_attr_regwen_6_we; + reg_we_check[216] = mio_pad_attr_regwen_7_we; + reg_we_check[217] = mio_pad_attr_regwen_8_we; + reg_we_check[218] = mio_pad_attr_regwen_9_we; + reg_we_check[219] = mio_pad_attr_regwen_10_we; + reg_we_check[220] = mio_pad_attr_regwen_11_we; + reg_we_check[221] = mio_pad_attr_regwen_12_we; + reg_we_check[222] = mio_pad_attr_regwen_13_we; + reg_we_check[223] = mio_pad_attr_regwen_14_we; + reg_we_check[224] = mio_pad_attr_regwen_15_we; + reg_we_check[225] = mio_pad_attr_regwen_16_we; + reg_we_check[226] = mio_pad_attr_regwen_17_we; + reg_we_check[227] = mio_pad_attr_regwen_18_we; + reg_we_check[228] = mio_pad_attr_regwen_19_we; + reg_we_check[229] = mio_pad_attr_regwen_20_we; + reg_we_check[230] = mio_pad_attr_regwen_21_we; + reg_we_check[231] = mio_pad_attr_regwen_22_we; + reg_we_check[232] = mio_pad_attr_regwen_23_we; + reg_we_check[233] = mio_pad_attr_regwen_24_we; + reg_we_check[234] = mio_pad_attr_regwen_25_we; + reg_we_check[235] = mio_pad_attr_regwen_26_we; + reg_we_check[236] = mio_pad_attr_regwen_27_we; + reg_we_check[237] = mio_pad_attr_regwen_28_we; + reg_we_check[238] = mio_pad_attr_regwen_29_we; + reg_we_check[239] = mio_pad_attr_regwen_30_we; + reg_we_check[240] = mio_pad_attr_regwen_31_we; + reg_we_check[241] = mio_pad_attr_regwen_32_we; + reg_we_check[242] = mio_pad_attr_regwen_33_we; + reg_we_check[243] = mio_pad_attr_regwen_34_we; + reg_we_check[244] = mio_pad_attr_regwen_35_we; + reg_we_check[245] = mio_pad_attr_regwen_36_we; + reg_we_check[246] = mio_pad_attr_regwen_37_we; + reg_we_check[247] = mio_pad_attr_regwen_38_we; + reg_we_check[248] = mio_pad_attr_regwen_39_we; + reg_we_check[249] = mio_pad_attr_regwen_40_we; + reg_we_check[250] = mio_pad_attr_regwen_41_we; + reg_we_check[251] = mio_pad_attr_regwen_42_we; + reg_we_check[252] = mio_pad_attr_regwen_43_we; + reg_we_check[253] = mio_pad_attr_regwen_44_we; + reg_we_check[254] = mio_pad_attr_regwen_45_we; + reg_we_check[255] = mio_pad_attr_regwen_46_we; + reg_we_check[256] = mio_pad_attr_0_gated_we; + reg_we_check[257] = mio_pad_attr_1_gated_we; + reg_we_check[258] = mio_pad_attr_2_gated_we; + reg_we_check[259] = mio_pad_attr_3_gated_we; + reg_we_check[260] = mio_pad_attr_4_gated_we; + reg_we_check[261] = mio_pad_attr_5_gated_we; + reg_we_check[262] = mio_pad_attr_6_gated_we; + reg_we_check[263] = mio_pad_attr_7_gated_we; + reg_we_check[264] = mio_pad_attr_8_gated_we; + reg_we_check[265] = mio_pad_attr_9_gated_we; + reg_we_check[266] = mio_pad_attr_10_gated_we; + reg_we_check[267] = mio_pad_attr_11_gated_we; + reg_we_check[268] = mio_pad_attr_12_gated_we; + reg_we_check[269] = mio_pad_attr_13_gated_we; + reg_we_check[270] = mio_pad_attr_14_gated_we; + reg_we_check[271] = mio_pad_attr_15_gated_we; + reg_we_check[272] = mio_pad_attr_16_gated_we; + reg_we_check[273] = mio_pad_attr_17_gated_we; + reg_we_check[274] = mio_pad_attr_18_gated_we; + reg_we_check[275] = mio_pad_attr_19_gated_we; + reg_we_check[276] = mio_pad_attr_20_gated_we; + reg_we_check[277] = mio_pad_attr_21_gated_we; + reg_we_check[278] = mio_pad_attr_22_gated_we; + reg_we_check[279] = mio_pad_attr_23_gated_we; + reg_we_check[280] = mio_pad_attr_24_gated_we; + reg_we_check[281] = mio_pad_attr_25_gated_we; + reg_we_check[282] = mio_pad_attr_26_gated_we; + reg_we_check[283] = mio_pad_attr_27_gated_we; + reg_we_check[284] = mio_pad_attr_28_gated_we; + reg_we_check[285] = mio_pad_attr_29_gated_we; + reg_we_check[286] = mio_pad_attr_30_gated_we; + reg_we_check[287] = mio_pad_attr_31_gated_we; + reg_we_check[288] = mio_pad_attr_32_gated_we; + reg_we_check[289] = mio_pad_attr_33_gated_we; + reg_we_check[290] = mio_pad_attr_34_gated_we; + reg_we_check[291] = mio_pad_attr_35_gated_we; + reg_we_check[292] = mio_pad_attr_36_gated_we; + reg_we_check[293] = mio_pad_attr_37_gated_we; + reg_we_check[294] = mio_pad_attr_38_gated_we; + reg_we_check[295] = mio_pad_attr_39_gated_we; + reg_we_check[296] = mio_pad_attr_40_gated_we; + reg_we_check[297] = mio_pad_attr_41_gated_we; + reg_we_check[298] = mio_pad_attr_42_gated_we; + reg_we_check[299] = mio_pad_attr_43_gated_we; + reg_we_check[300] = mio_pad_attr_44_gated_we; + reg_we_check[301] = mio_pad_attr_45_gated_we; + reg_we_check[302] = mio_pad_attr_46_gated_we; + reg_we_check[303] = dio_pad_attr_regwen_0_we; + reg_we_check[304] = dio_pad_attr_regwen_1_we; + reg_we_check[305] = dio_pad_attr_regwen_2_we; + reg_we_check[306] = dio_pad_attr_regwen_3_we; + reg_we_check[307] = dio_pad_attr_regwen_4_we; + reg_we_check[308] = dio_pad_attr_regwen_5_we; + reg_we_check[309] = dio_pad_attr_regwen_6_we; + reg_we_check[310] = dio_pad_attr_regwen_7_we; + reg_we_check[311] = dio_pad_attr_regwen_8_we; + reg_we_check[312] = dio_pad_attr_regwen_9_we; + reg_we_check[313] = dio_pad_attr_regwen_10_we; + reg_we_check[314] = dio_pad_attr_regwen_11_we; + reg_we_check[315] = dio_pad_attr_regwen_12_we; + reg_we_check[316] = dio_pad_attr_regwen_13_we; + reg_we_check[317] = dio_pad_attr_regwen_14_we; + reg_we_check[318] = dio_pad_attr_regwen_15_we; + reg_we_check[319] = dio_pad_attr_regwen_16_we; + reg_we_check[320] = dio_pad_attr_regwen_17_we; + reg_we_check[321] = dio_pad_attr_regwen_18_we; + reg_we_check[322] = dio_pad_attr_regwen_19_we; + reg_we_check[323] = dio_pad_attr_regwen_20_we; + reg_we_check[324] = dio_pad_attr_regwen_21_we; + reg_we_check[325] = dio_pad_attr_regwen_22_we; + reg_we_check[326] = dio_pad_attr_regwen_23_we; + reg_we_check[327] = dio_pad_attr_regwen_24_we; + reg_we_check[328] = dio_pad_attr_regwen_25_we; + reg_we_check[329] = dio_pad_attr_regwen_26_we; + reg_we_check[330] = dio_pad_attr_regwen_27_we; + reg_we_check[331] = dio_pad_attr_regwen_28_we; + reg_we_check[332] = dio_pad_attr_regwen_29_we; + reg_we_check[333] = dio_pad_attr_regwen_30_we; + reg_we_check[334] = dio_pad_attr_regwen_31_we; + reg_we_check[335] = dio_pad_attr_regwen_32_we; + reg_we_check[336] = dio_pad_attr_regwen_33_we; + reg_we_check[337] = dio_pad_attr_regwen_34_we; + reg_we_check[338] = dio_pad_attr_regwen_35_we; + reg_we_check[339] = dio_pad_attr_regwen_36_we; + reg_we_check[340] = dio_pad_attr_regwen_37_we; + reg_we_check[341] = dio_pad_attr_regwen_38_we; + reg_we_check[342] = dio_pad_attr_regwen_39_we; + reg_we_check[343] = dio_pad_attr_regwen_40_we; + reg_we_check[344] = dio_pad_attr_regwen_41_we; + reg_we_check[345] = dio_pad_attr_regwen_42_we; + reg_we_check[346] = dio_pad_attr_0_gated_we; + reg_we_check[347] = dio_pad_attr_1_gated_we; + reg_we_check[348] = dio_pad_attr_2_gated_we; + reg_we_check[349] = dio_pad_attr_3_gated_we; + reg_we_check[350] = dio_pad_attr_4_gated_we; + reg_we_check[351] = dio_pad_attr_5_gated_we; + reg_we_check[352] = dio_pad_attr_6_gated_we; + reg_we_check[353] = dio_pad_attr_7_gated_we; + reg_we_check[354] = dio_pad_attr_8_gated_we; + reg_we_check[355] = dio_pad_attr_9_gated_we; + reg_we_check[356] = dio_pad_attr_10_gated_we; + reg_we_check[357] = dio_pad_attr_11_gated_we; + reg_we_check[358] = dio_pad_attr_12_gated_we; + reg_we_check[359] = dio_pad_attr_13_gated_we; + reg_we_check[360] = dio_pad_attr_14_gated_we; + reg_we_check[361] = dio_pad_attr_15_gated_we; + reg_we_check[362] = dio_pad_attr_16_gated_we; + reg_we_check[363] = dio_pad_attr_17_gated_we; + reg_we_check[364] = dio_pad_attr_18_gated_we; + reg_we_check[365] = dio_pad_attr_19_gated_we; + reg_we_check[366] = dio_pad_attr_20_gated_we; + reg_we_check[367] = dio_pad_attr_21_gated_we; + reg_we_check[368] = dio_pad_attr_22_gated_we; + reg_we_check[369] = dio_pad_attr_23_gated_we; + reg_we_check[370] = dio_pad_attr_24_gated_we; + reg_we_check[371] = dio_pad_attr_25_gated_we; + reg_we_check[372] = dio_pad_attr_26_gated_we; + reg_we_check[373] = dio_pad_attr_27_gated_we; + reg_we_check[374] = dio_pad_attr_28_gated_we; + reg_we_check[375] = dio_pad_attr_29_gated_we; + reg_we_check[376] = dio_pad_attr_30_gated_we; + reg_we_check[377] = dio_pad_attr_31_gated_we; + reg_we_check[378] = dio_pad_attr_32_gated_we; + reg_we_check[379] = dio_pad_attr_33_gated_we; + reg_we_check[380] = dio_pad_attr_34_gated_we; + reg_we_check[381] = dio_pad_attr_35_gated_we; + reg_we_check[382] = dio_pad_attr_36_gated_we; + reg_we_check[383] = dio_pad_attr_37_gated_we; + reg_we_check[384] = dio_pad_attr_38_gated_we; + reg_we_check[385] = dio_pad_attr_39_gated_we; + reg_we_check[386] = dio_pad_attr_40_gated_we; + reg_we_check[387] = dio_pad_attr_41_gated_we; + reg_we_check[388] = dio_pad_attr_42_gated_we; + reg_we_check[389] = mio_pad_sleep_status_0_we; + reg_we_check[390] = mio_pad_sleep_status_1_we; + reg_we_check[391] = mio_pad_sleep_regwen_0_we; + reg_we_check[392] = mio_pad_sleep_regwen_1_we; + reg_we_check[393] = mio_pad_sleep_regwen_2_we; + reg_we_check[394] = mio_pad_sleep_regwen_3_we; + reg_we_check[395] = mio_pad_sleep_regwen_4_we; + reg_we_check[396] = mio_pad_sleep_regwen_5_we; + reg_we_check[397] = mio_pad_sleep_regwen_6_we; + reg_we_check[398] = mio_pad_sleep_regwen_7_we; + reg_we_check[399] = mio_pad_sleep_regwen_8_we; + reg_we_check[400] = mio_pad_sleep_regwen_9_we; + reg_we_check[401] = mio_pad_sleep_regwen_10_we; + reg_we_check[402] = mio_pad_sleep_regwen_11_we; + reg_we_check[403] = mio_pad_sleep_regwen_12_we; + reg_we_check[404] = mio_pad_sleep_regwen_13_we; + reg_we_check[405] = mio_pad_sleep_regwen_14_we; + reg_we_check[406] = mio_pad_sleep_regwen_15_we; + reg_we_check[407] = mio_pad_sleep_regwen_16_we; + reg_we_check[408] = mio_pad_sleep_regwen_17_we; + reg_we_check[409] = mio_pad_sleep_regwen_18_we; + reg_we_check[410] = mio_pad_sleep_regwen_19_we; + reg_we_check[411] = mio_pad_sleep_regwen_20_we; + reg_we_check[412] = mio_pad_sleep_regwen_21_we; + reg_we_check[413] = mio_pad_sleep_regwen_22_we; + reg_we_check[414] = mio_pad_sleep_regwen_23_we; + reg_we_check[415] = mio_pad_sleep_regwen_24_we; + reg_we_check[416] = mio_pad_sleep_regwen_25_we; + reg_we_check[417] = mio_pad_sleep_regwen_26_we; + reg_we_check[418] = mio_pad_sleep_regwen_27_we; + reg_we_check[419] = mio_pad_sleep_regwen_28_we; + reg_we_check[420] = mio_pad_sleep_regwen_29_we; + reg_we_check[421] = mio_pad_sleep_regwen_30_we; + reg_we_check[422] = mio_pad_sleep_regwen_31_we; + reg_we_check[423] = mio_pad_sleep_regwen_32_we; + reg_we_check[424] = mio_pad_sleep_regwen_33_we; + reg_we_check[425] = mio_pad_sleep_regwen_34_we; + reg_we_check[426] = mio_pad_sleep_regwen_35_we; + reg_we_check[427] = mio_pad_sleep_regwen_36_we; + reg_we_check[428] = mio_pad_sleep_regwen_37_we; + reg_we_check[429] = mio_pad_sleep_regwen_38_we; + reg_we_check[430] = mio_pad_sleep_regwen_39_we; + reg_we_check[431] = mio_pad_sleep_regwen_40_we; + reg_we_check[432] = mio_pad_sleep_regwen_41_we; + reg_we_check[433] = mio_pad_sleep_regwen_42_we; + reg_we_check[434] = mio_pad_sleep_regwen_43_we; + reg_we_check[435] = mio_pad_sleep_regwen_44_we; + reg_we_check[436] = mio_pad_sleep_regwen_45_we; + reg_we_check[437] = mio_pad_sleep_regwen_46_we; + reg_we_check[438] = mio_pad_sleep_en_0_gated_we; + reg_we_check[439] = mio_pad_sleep_en_1_gated_we; + reg_we_check[440] = mio_pad_sleep_en_2_gated_we; + reg_we_check[441] = mio_pad_sleep_en_3_gated_we; + reg_we_check[442] = mio_pad_sleep_en_4_gated_we; + reg_we_check[443] = mio_pad_sleep_en_5_gated_we; + reg_we_check[444] = mio_pad_sleep_en_6_gated_we; + reg_we_check[445] = mio_pad_sleep_en_7_gated_we; + reg_we_check[446] = mio_pad_sleep_en_8_gated_we; + reg_we_check[447] = mio_pad_sleep_en_9_gated_we; + reg_we_check[448] = mio_pad_sleep_en_10_gated_we; + reg_we_check[449] = mio_pad_sleep_en_11_gated_we; + reg_we_check[450] = mio_pad_sleep_en_12_gated_we; + reg_we_check[451] = mio_pad_sleep_en_13_gated_we; + reg_we_check[452] = mio_pad_sleep_en_14_gated_we; + reg_we_check[453] = mio_pad_sleep_en_15_gated_we; + reg_we_check[454] = mio_pad_sleep_en_16_gated_we; + reg_we_check[455] = mio_pad_sleep_en_17_gated_we; + reg_we_check[456] = mio_pad_sleep_en_18_gated_we; + reg_we_check[457] = mio_pad_sleep_en_19_gated_we; + reg_we_check[458] = mio_pad_sleep_en_20_gated_we; + reg_we_check[459] = mio_pad_sleep_en_21_gated_we; + reg_we_check[460] = mio_pad_sleep_en_22_gated_we; + reg_we_check[461] = mio_pad_sleep_en_23_gated_we; + reg_we_check[462] = mio_pad_sleep_en_24_gated_we; + reg_we_check[463] = mio_pad_sleep_en_25_gated_we; + reg_we_check[464] = mio_pad_sleep_en_26_gated_we; + reg_we_check[465] = mio_pad_sleep_en_27_gated_we; + reg_we_check[466] = mio_pad_sleep_en_28_gated_we; + reg_we_check[467] = mio_pad_sleep_en_29_gated_we; + reg_we_check[468] = mio_pad_sleep_en_30_gated_we; + reg_we_check[469] = mio_pad_sleep_en_31_gated_we; + reg_we_check[470] = mio_pad_sleep_en_32_gated_we; + reg_we_check[471] = mio_pad_sleep_en_33_gated_we; + reg_we_check[472] = mio_pad_sleep_en_34_gated_we; + reg_we_check[473] = mio_pad_sleep_en_35_gated_we; + reg_we_check[474] = mio_pad_sleep_en_36_gated_we; + reg_we_check[475] = mio_pad_sleep_en_37_gated_we; + reg_we_check[476] = mio_pad_sleep_en_38_gated_we; + reg_we_check[477] = mio_pad_sleep_en_39_gated_we; + reg_we_check[478] = mio_pad_sleep_en_40_gated_we; + reg_we_check[479] = mio_pad_sleep_en_41_gated_we; + reg_we_check[480] = mio_pad_sleep_en_42_gated_we; + reg_we_check[481] = mio_pad_sleep_en_43_gated_we; + reg_we_check[482] = mio_pad_sleep_en_44_gated_we; + reg_we_check[483] = mio_pad_sleep_en_45_gated_we; + reg_we_check[484] = mio_pad_sleep_en_46_gated_we; + reg_we_check[485] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[486] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[487] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[488] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[489] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[490] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[491] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[492] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[493] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[494] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[495] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[496] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[497] = mio_pad_sleep_mode_12_gated_we; + reg_we_check[498] = mio_pad_sleep_mode_13_gated_we; + reg_we_check[499] = mio_pad_sleep_mode_14_gated_we; + reg_we_check[500] = mio_pad_sleep_mode_15_gated_we; + reg_we_check[501] = mio_pad_sleep_mode_16_gated_we; + reg_we_check[502] = mio_pad_sleep_mode_17_gated_we; + reg_we_check[503] = mio_pad_sleep_mode_18_gated_we; + reg_we_check[504] = mio_pad_sleep_mode_19_gated_we; + reg_we_check[505] = mio_pad_sleep_mode_20_gated_we; + reg_we_check[506] = mio_pad_sleep_mode_21_gated_we; + reg_we_check[507] = mio_pad_sleep_mode_22_gated_we; + reg_we_check[508] = mio_pad_sleep_mode_23_gated_we; + reg_we_check[509] = mio_pad_sleep_mode_24_gated_we; + reg_we_check[510] = mio_pad_sleep_mode_25_gated_we; + reg_we_check[511] = mio_pad_sleep_mode_26_gated_we; + reg_we_check[512] = mio_pad_sleep_mode_27_gated_we; + reg_we_check[513] = mio_pad_sleep_mode_28_gated_we; + reg_we_check[514] = mio_pad_sleep_mode_29_gated_we; + reg_we_check[515] = mio_pad_sleep_mode_30_gated_we; + reg_we_check[516] = mio_pad_sleep_mode_31_gated_we; + reg_we_check[517] = mio_pad_sleep_mode_32_gated_we; + reg_we_check[518] = mio_pad_sleep_mode_33_gated_we; + reg_we_check[519] = mio_pad_sleep_mode_34_gated_we; + reg_we_check[520] = mio_pad_sleep_mode_35_gated_we; + reg_we_check[521] = mio_pad_sleep_mode_36_gated_we; + reg_we_check[522] = mio_pad_sleep_mode_37_gated_we; + reg_we_check[523] = mio_pad_sleep_mode_38_gated_we; + reg_we_check[524] = mio_pad_sleep_mode_39_gated_we; + reg_we_check[525] = mio_pad_sleep_mode_40_gated_we; + reg_we_check[526] = mio_pad_sleep_mode_41_gated_we; + reg_we_check[527] = mio_pad_sleep_mode_42_gated_we; + reg_we_check[528] = mio_pad_sleep_mode_43_gated_we; + reg_we_check[529] = mio_pad_sleep_mode_44_gated_we; + reg_we_check[530] = mio_pad_sleep_mode_45_gated_we; + reg_we_check[531] = mio_pad_sleep_mode_46_gated_we; + reg_we_check[532] = dio_pad_sleep_status_0_we; + reg_we_check[533] = dio_pad_sleep_status_1_we; + reg_we_check[534] = dio_pad_sleep_regwen_0_we; + reg_we_check[535] = dio_pad_sleep_regwen_1_we; + reg_we_check[536] = dio_pad_sleep_regwen_2_we; + reg_we_check[537] = dio_pad_sleep_regwen_3_we; + reg_we_check[538] = dio_pad_sleep_regwen_4_we; + reg_we_check[539] = dio_pad_sleep_regwen_5_we; + reg_we_check[540] = dio_pad_sleep_regwen_6_we; + reg_we_check[541] = dio_pad_sleep_regwen_7_we; + reg_we_check[542] = dio_pad_sleep_regwen_8_we; + reg_we_check[543] = dio_pad_sleep_regwen_9_we; + reg_we_check[544] = dio_pad_sleep_regwen_10_we; + reg_we_check[545] = dio_pad_sleep_regwen_11_we; + reg_we_check[546] = dio_pad_sleep_regwen_12_we; + reg_we_check[547] = dio_pad_sleep_regwen_13_we; + reg_we_check[548] = dio_pad_sleep_regwen_14_we; + reg_we_check[549] = dio_pad_sleep_regwen_15_we; + reg_we_check[550] = dio_pad_sleep_regwen_16_we; + reg_we_check[551] = dio_pad_sleep_regwen_17_we; + reg_we_check[552] = dio_pad_sleep_regwen_18_we; + reg_we_check[553] = dio_pad_sleep_regwen_19_we; + reg_we_check[554] = dio_pad_sleep_regwen_20_we; + reg_we_check[555] = dio_pad_sleep_regwen_21_we; + reg_we_check[556] = dio_pad_sleep_regwen_22_we; + reg_we_check[557] = dio_pad_sleep_regwen_23_we; + reg_we_check[558] = dio_pad_sleep_regwen_24_we; + reg_we_check[559] = dio_pad_sleep_regwen_25_we; + reg_we_check[560] = dio_pad_sleep_regwen_26_we; + reg_we_check[561] = dio_pad_sleep_regwen_27_we; + reg_we_check[562] = dio_pad_sleep_regwen_28_we; + reg_we_check[563] = dio_pad_sleep_regwen_29_we; + reg_we_check[564] = dio_pad_sleep_regwen_30_we; + reg_we_check[565] = dio_pad_sleep_regwen_31_we; + reg_we_check[566] = dio_pad_sleep_regwen_32_we; + reg_we_check[567] = dio_pad_sleep_regwen_33_we; + reg_we_check[568] = dio_pad_sleep_regwen_34_we; + reg_we_check[569] = dio_pad_sleep_regwen_35_we; + reg_we_check[570] = dio_pad_sleep_regwen_36_we; + reg_we_check[571] = dio_pad_sleep_regwen_37_we; + reg_we_check[572] = dio_pad_sleep_regwen_38_we; + reg_we_check[573] = dio_pad_sleep_regwen_39_we; + reg_we_check[574] = dio_pad_sleep_regwen_40_we; + reg_we_check[575] = dio_pad_sleep_regwen_41_we; + reg_we_check[576] = dio_pad_sleep_regwen_42_we; + reg_we_check[577] = dio_pad_sleep_en_0_gated_we; + reg_we_check[578] = dio_pad_sleep_en_1_gated_we; + reg_we_check[579] = dio_pad_sleep_en_2_gated_we; + reg_we_check[580] = dio_pad_sleep_en_3_gated_we; + reg_we_check[581] = dio_pad_sleep_en_4_gated_we; + reg_we_check[582] = dio_pad_sleep_en_5_gated_we; + reg_we_check[583] = dio_pad_sleep_en_6_gated_we; + reg_we_check[584] = dio_pad_sleep_en_7_gated_we; + reg_we_check[585] = dio_pad_sleep_en_8_gated_we; + reg_we_check[586] = dio_pad_sleep_en_9_gated_we; + reg_we_check[587] = dio_pad_sleep_en_10_gated_we; + reg_we_check[588] = dio_pad_sleep_en_11_gated_we; + reg_we_check[589] = dio_pad_sleep_en_12_gated_we; + reg_we_check[590] = dio_pad_sleep_en_13_gated_we; + reg_we_check[591] = dio_pad_sleep_en_14_gated_we; + reg_we_check[592] = dio_pad_sleep_en_15_gated_we; + reg_we_check[593] = dio_pad_sleep_en_16_gated_we; + reg_we_check[594] = dio_pad_sleep_en_17_gated_we; + reg_we_check[595] = dio_pad_sleep_en_18_gated_we; + reg_we_check[596] = dio_pad_sleep_en_19_gated_we; + reg_we_check[597] = dio_pad_sleep_en_20_gated_we; + reg_we_check[598] = dio_pad_sleep_en_21_gated_we; + reg_we_check[599] = dio_pad_sleep_en_22_gated_we; + reg_we_check[600] = dio_pad_sleep_en_23_gated_we; + reg_we_check[601] = dio_pad_sleep_en_24_gated_we; + reg_we_check[602] = dio_pad_sleep_en_25_gated_we; + reg_we_check[603] = dio_pad_sleep_en_26_gated_we; + reg_we_check[604] = dio_pad_sleep_en_27_gated_we; + reg_we_check[605] = dio_pad_sleep_en_28_gated_we; + reg_we_check[606] = dio_pad_sleep_en_29_gated_we; + reg_we_check[607] = dio_pad_sleep_en_30_gated_we; + reg_we_check[608] = dio_pad_sleep_en_31_gated_we; + reg_we_check[609] = dio_pad_sleep_en_32_gated_we; + reg_we_check[610] = dio_pad_sleep_en_33_gated_we; + reg_we_check[611] = dio_pad_sleep_en_34_gated_we; + reg_we_check[612] = dio_pad_sleep_en_35_gated_we; + reg_we_check[613] = dio_pad_sleep_en_36_gated_we; + reg_we_check[614] = dio_pad_sleep_en_37_gated_we; + reg_we_check[615] = dio_pad_sleep_en_38_gated_we; + reg_we_check[616] = dio_pad_sleep_en_39_gated_we; + reg_we_check[617] = dio_pad_sleep_en_40_gated_we; + reg_we_check[618] = dio_pad_sleep_en_41_gated_we; + reg_we_check[619] = dio_pad_sleep_en_42_gated_we; + reg_we_check[620] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[621] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[622] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[623] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[624] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[625] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[626] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[627] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[628] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[629] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[630] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[631] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[632] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[633] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[634] = dio_pad_sleep_mode_14_gated_we; + reg_we_check[635] = dio_pad_sleep_mode_15_gated_we; + reg_we_check[636] = dio_pad_sleep_mode_16_gated_we; + reg_we_check[637] = dio_pad_sleep_mode_17_gated_we; + reg_we_check[638] = dio_pad_sleep_mode_18_gated_we; + reg_we_check[639] = dio_pad_sleep_mode_19_gated_we; + reg_we_check[640] = dio_pad_sleep_mode_20_gated_we; + reg_we_check[641] = dio_pad_sleep_mode_21_gated_we; + reg_we_check[642] = dio_pad_sleep_mode_22_gated_we; + reg_we_check[643] = dio_pad_sleep_mode_23_gated_we; + reg_we_check[644] = dio_pad_sleep_mode_24_gated_we; + reg_we_check[645] = dio_pad_sleep_mode_25_gated_we; + reg_we_check[646] = dio_pad_sleep_mode_26_gated_we; + reg_we_check[647] = dio_pad_sleep_mode_27_gated_we; + reg_we_check[648] = dio_pad_sleep_mode_28_gated_we; + reg_we_check[649] = dio_pad_sleep_mode_29_gated_we; + reg_we_check[650] = dio_pad_sleep_mode_30_gated_we; + reg_we_check[651] = dio_pad_sleep_mode_31_gated_we; + reg_we_check[652] = dio_pad_sleep_mode_32_gated_we; + reg_we_check[653] = dio_pad_sleep_mode_33_gated_we; + reg_we_check[654] = dio_pad_sleep_mode_34_gated_we; + reg_we_check[655] = dio_pad_sleep_mode_35_gated_we; + reg_we_check[656] = dio_pad_sleep_mode_36_gated_we; + reg_we_check[657] = dio_pad_sleep_mode_37_gated_we; + reg_we_check[658] = dio_pad_sleep_mode_38_gated_we; + reg_we_check[659] = dio_pad_sleep_mode_39_gated_we; + reg_we_check[660] = dio_pad_sleep_mode_40_gated_we; + reg_we_check[661] = dio_pad_sleep_mode_41_gated_we; + reg_we_check[662] = dio_pad_sleep_mode_42_gated_we; + reg_we_check[663] = wkup_detector_regwen_0_we; + reg_we_check[664] = wkup_detector_regwen_1_we; + reg_we_check[665] = wkup_detector_regwen_2_we; + reg_we_check[666] = wkup_detector_regwen_3_we; + reg_we_check[667] = wkup_detector_regwen_4_we; + reg_we_check[668] = wkup_detector_regwen_5_we; + reg_we_check[669] = wkup_detector_regwen_6_we; + reg_we_check[670] = wkup_detector_regwen_7_we; + reg_we_check[671] = wkup_detector_en_0_we; + reg_we_check[672] = wkup_detector_en_1_we; + reg_we_check[673] = wkup_detector_en_2_we; + reg_we_check[674] = wkup_detector_en_3_we; + reg_we_check[675] = wkup_detector_en_4_we; + reg_we_check[676] = wkup_detector_en_5_we; + reg_we_check[677] = wkup_detector_en_6_we; + reg_we_check[678] = wkup_detector_en_7_we; + reg_we_check[679] = wkup_detector_0_we; + reg_we_check[680] = wkup_detector_1_we; + reg_we_check[681] = wkup_detector_2_we; + reg_we_check[682] = wkup_detector_3_we; + reg_we_check[683] = wkup_detector_4_we; + reg_we_check[684] = wkup_detector_5_we; + reg_we_check[685] = wkup_detector_6_we; + reg_we_check[686] = wkup_detector_7_we; + reg_we_check[687] = wkup_detector_cnt_th_0_we; + reg_we_check[688] = wkup_detector_cnt_th_1_we; + reg_we_check[689] = wkup_detector_cnt_th_2_we; + reg_we_check[690] = wkup_detector_cnt_th_3_we; + reg_we_check[691] = wkup_detector_cnt_th_4_we; + reg_we_check[692] = wkup_detector_cnt_th_5_we; + reg_we_check[693] = wkup_detector_cnt_th_6_we; + reg_we_check[694] = wkup_detector_cnt_th_7_we; + reg_we_check[695] = wkup_detector_padsel_0_gated_we; + reg_we_check[696] = wkup_detector_padsel_1_gated_we; + reg_we_check[697] = wkup_detector_padsel_2_gated_we; + reg_we_check[698] = wkup_detector_padsel_3_gated_we; + reg_we_check[699] = wkup_detector_padsel_4_gated_we; + reg_we_check[700] = wkup_detector_padsel_5_gated_we; + reg_we_check[701] = wkup_detector_padsel_6_gated_we; + reg_we_check[702] = wkup_detector_padsel_7_gated_we; + reg_we_check[703] = wkup_cause_we; end // Read data return @@ -46469,878 +45930,798 @@ end addr_hit[58]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_57_qs; - end - - addr_hit[59]: begin reg_rdata_next[5:0] = mio_periph_insel_0_qs; end - addr_hit[60]: begin + addr_hit[59]: begin reg_rdata_next[5:0] = mio_periph_insel_1_qs; end - addr_hit[61]: begin + addr_hit[60]: begin reg_rdata_next[5:0] = mio_periph_insel_2_qs; end - addr_hit[62]: begin + addr_hit[61]: begin reg_rdata_next[5:0] = mio_periph_insel_3_qs; end - addr_hit[63]: begin + addr_hit[62]: begin reg_rdata_next[5:0] = mio_periph_insel_4_qs; end - addr_hit[64]: begin + addr_hit[63]: begin reg_rdata_next[5:0] = mio_periph_insel_5_qs; end - addr_hit[65]: begin + addr_hit[64]: begin reg_rdata_next[5:0] = mio_periph_insel_6_qs; end - addr_hit[66]: begin + addr_hit[65]: begin reg_rdata_next[5:0] = mio_periph_insel_7_qs; end - addr_hit[67]: begin + addr_hit[66]: begin reg_rdata_next[5:0] = mio_periph_insel_8_qs; end - addr_hit[68]: begin + addr_hit[67]: begin reg_rdata_next[5:0] = mio_periph_insel_9_qs; end - addr_hit[69]: begin + addr_hit[68]: begin reg_rdata_next[5:0] = mio_periph_insel_10_qs; end - addr_hit[70]: begin + addr_hit[69]: begin reg_rdata_next[5:0] = mio_periph_insel_11_qs; end - addr_hit[71]: begin + addr_hit[70]: begin reg_rdata_next[5:0] = mio_periph_insel_12_qs; end - addr_hit[72]: begin + addr_hit[71]: begin reg_rdata_next[5:0] = mio_periph_insel_13_qs; end - addr_hit[73]: begin + addr_hit[72]: begin reg_rdata_next[5:0] = mio_periph_insel_14_qs; end - addr_hit[74]: begin + addr_hit[73]: begin reg_rdata_next[5:0] = mio_periph_insel_15_qs; end - addr_hit[75]: begin + addr_hit[74]: begin reg_rdata_next[5:0] = mio_periph_insel_16_qs; end - addr_hit[76]: begin + addr_hit[75]: begin reg_rdata_next[5:0] = mio_periph_insel_17_qs; end - addr_hit[77]: begin + addr_hit[76]: begin reg_rdata_next[5:0] = mio_periph_insel_18_qs; end - addr_hit[78]: begin + addr_hit[77]: begin reg_rdata_next[5:0] = mio_periph_insel_19_qs; end - addr_hit[79]: begin + addr_hit[78]: begin reg_rdata_next[5:0] = mio_periph_insel_20_qs; end - addr_hit[80]: begin + addr_hit[79]: begin reg_rdata_next[5:0] = mio_periph_insel_21_qs; end - addr_hit[81]: begin + addr_hit[80]: begin reg_rdata_next[5:0] = mio_periph_insel_22_qs; end - addr_hit[82]: begin + addr_hit[81]: begin reg_rdata_next[5:0] = mio_periph_insel_23_qs; end - addr_hit[83]: begin + addr_hit[82]: begin reg_rdata_next[5:0] = mio_periph_insel_24_qs; end - addr_hit[84]: begin + addr_hit[83]: begin reg_rdata_next[5:0] = mio_periph_insel_25_qs; end - addr_hit[85]: begin + addr_hit[84]: begin reg_rdata_next[5:0] = mio_periph_insel_26_qs; end - addr_hit[86]: begin + addr_hit[85]: begin reg_rdata_next[5:0] = mio_periph_insel_27_qs; end - addr_hit[87]: begin + addr_hit[86]: begin reg_rdata_next[5:0] = mio_periph_insel_28_qs; end - addr_hit[88]: begin + addr_hit[87]: begin reg_rdata_next[5:0] = mio_periph_insel_29_qs; end - addr_hit[89]: begin + addr_hit[88]: begin reg_rdata_next[5:0] = mio_periph_insel_30_qs; end - addr_hit[90]: begin + addr_hit[89]: begin reg_rdata_next[5:0] = mio_periph_insel_31_qs; end - addr_hit[91]: begin + addr_hit[90]: begin reg_rdata_next[5:0] = mio_periph_insel_32_qs; end - addr_hit[92]: begin + addr_hit[91]: begin reg_rdata_next[5:0] = mio_periph_insel_33_qs; end - addr_hit[93]: begin + addr_hit[92]: begin reg_rdata_next[5:0] = mio_periph_insel_34_qs; end - addr_hit[94]: begin + addr_hit[93]: begin reg_rdata_next[5:0] = mio_periph_insel_35_qs; end - addr_hit[95]: begin + addr_hit[94]: begin reg_rdata_next[5:0] = mio_periph_insel_36_qs; end - addr_hit[96]: begin + addr_hit[95]: begin reg_rdata_next[5:0] = mio_periph_insel_37_qs; end - addr_hit[97]: begin + addr_hit[96]: begin reg_rdata_next[5:0] = mio_periph_insel_38_qs; end - addr_hit[98]: begin + addr_hit[97]: begin reg_rdata_next[5:0] = mio_periph_insel_39_qs; end - addr_hit[99]: begin + addr_hit[98]: begin reg_rdata_next[5:0] = mio_periph_insel_40_qs; end - addr_hit[100]: begin + addr_hit[99]: begin reg_rdata_next[5:0] = mio_periph_insel_41_qs; end - addr_hit[101]: begin + addr_hit[100]: begin reg_rdata_next[5:0] = mio_periph_insel_42_qs; end - addr_hit[102]: begin + addr_hit[101]: begin reg_rdata_next[5:0] = mio_periph_insel_43_qs; end - addr_hit[103]: begin + addr_hit[102]: begin reg_rdata_next[5:0] = mio_periph_insel_44_qs; end - addr_hit[104]: begin + addr_hit[103]: begin reg_rdata_next[5:0] = mio_periph_insel_45_qs; end - addr_hit[105]: begin + addr_hit[104]: begin reg_rdata_next[5:0] = mio_periph_insel_46_qs; end - addr_hit[106]: begin + addr_hit[105]: begin reg_rdata_next[5:0] = mio_periph_insel_47_qs; end - addr_hit[107]: begin + addr_hit[106]: begin reg_rdata_next[5:0] = mio_periph_insel_48_qs; end - addr_hit[108]: begin + addr_hit[107]: begin reg_rdata_next[5:0] = mio_periph_insel_49_qs; end - addr_hit[109]: begin + addr_hit[108]: begin reg_rdata_next[5:0] = mio_periph_insel_50_qs; end - addr_hit[110]: begin + addr_hit[109]: begin reg_rdata_next[5:0] = mio_periph_insel_51_qs; end - addr_hit[111]: begin + addr_hit[110]: begin reg_rdata_next[5:0] = mio_periph_insel_52_qs; end - addr_hit[112]: begin + addr_hit[111]: begin reg_rdata_next[5:0] = mio_periph_insel_53_qs; end - addr_hit[113]: begin + addr_hit[112]: begin reg_rdata_next[5:0] = mio_periph_insel_54_qs; end - addr_hit[114]: begin + addr_hit[113]: begin reg_rdata_next[5:0] = mio_periph_insel_55_qs; end - addr_hit[115]: begin + addr_hit[114]: begin reg_rdata_next[5:0] = mio_periph_insel_56_qs; end - addr_hit[116]: begin - reg_rdata_next[5:0] = mio_periph_insel_57_qs; - end - - addr_hit[117]: begin + addr_hit[115]: begin reg_rdata_next[0] = mio_outsel_regwen_0_qs; end - addr_hit[118]: begin + addr_hit[116]: begin reg_rdata_next[0] = mio_outsel_regwen_1_qs; end - addr_hit[119]: begin + addr_hit[117]: begin reg_rdata_next[0] = mio_outsel_regwen_2_qs; end - addr_hit[120]: begin + addr_hit[118]: begin reg_rdata_next[0] = mio_outsel_regwen_3_qs; end - addr_hit[121]: begin + addr_hit[119]: begin reg_rdata_next[0] = mio_outsel_regwen_4_qs; end - addr_hit[122]: begin + addr_hit[120]: begin reg_rdata_next[0] = mio_outsel_regwen_5_qs; end - addr_hit[123]: begin + addr_hit[121]: begin reg_rdata_next[0] = mio_outsel_regwen_6_qs; end - addr_hit[124]: begin + addr_hit[122]: begin reg_rdata_next[0] = mio_outsel_regwen_7_qs; end - addr_hit[125]: begin + addr_hit[123]: begin reg_rdata_next[0] = mio_outsel_regwen_8_qs; end - addr_hit[126]: begin + addr_hit[124]: begin reg_rdata_next[0] = mio_outsel_regwen_9_qs; end - addr_hit[127]: begin + addr_hit[125]: begin reg_rdata_next[0] = mio_outsel_regwen_10_qs; end - addr_hit[128]: begin + addr_hit[126]: begin reg_rdata_next[0] = mio_outsel_regwen_11_qs; end - addr_hit[129]: begin + addr_hit[127]: begin reg_rdata_next[0] = mio_outsel_regwen_12_qs; end - addr_hit[130]: begin + addr_hit[128]: begin reg_rdata_next[0] = mio_outsel_regwen_13_qs; end - addr_hit[131]: begin + addr_hit[129]: begin reg_rdata_next[0] = mio_outsel_regwen_14_qs; end - addr_hit[132]: begin + addr_hit[130]: begin reg_rdata_next[0] = mio_outsel_regwen_15_qs; end - addr_hit[133]: begin + addr_hit[131]: begin reg_rdata_next[0] = mio_outsel_regwen_16_qs; end - addr_hit[134]: begin + addr_hit[132]: begin reg_rdata_next[0] = mio_outsel_regwen_17_qs; end - addr_hit[135]: begin + addr_hit[133]: begin reg_rdata_next[0] = mio_outsel_regwen_18_qs; end - addr_hit[136]: begin + addr_hit[134]: begin reg_rdata_next[0] = mio_outsel_regwen_19_qs; end - addr_hit[137]: begin + addr_hit[135]: begin reg_rdata_next[0] = mio_outsel_regwen_20_qs; end - addr_hit[138]: begin + addr_hit[136]: begin reg_rdata_next[0] = mio_outsel_regwen_21_qs; end - addr_hit[139]: begin + addr_hit[137]: begin reg_rdata_next[0] = mio_outsel_regwen_22_qs; end - addr_hit[140]: begin + addr_hit[138]: begin reg_rdata_next[0] = mio_outsel_regwen_23_qs; end - addr_hit[141]: begin + addr_hit[139]: begin reg_rdata_next[0] = mio_outsel_regwen_24_qs; end - addr_hit[142]: begin + addr_hit[140]: begin reg_rdata_next[0] = mio_outsel_regwen_25_qs; end - addr_hit[143]: begin + addr_hit[141]: begin reg_rdata_next[0] = mio_outsel_regwen_26_qs; end - addr_hit[144]: begin + addr_hit[142]: begin reg_rdata_next[0] = mio_outsel_regwen_27_qs; end - addr_hit[145]: begin + addr_hit[143]: begin reg_rdata_next[0] = mio_outsel_regwen_28_qs; end - addr_hit[146]: begin + addr_hit[144]: begin reg_rdata_next[0] = mio_outsel_regwen_29_qs; end - addr_hit[147]: begin + addr_hit[145]: begin reg_rdata_next[0] = mio_outsel_regwen_30_qs; end - addr_hit[148]: begin + addr_hit[146]: begin reg_rdata_next[0] = mio_outsel_regwen_31_qs; end - addr_hit[149]: begin + addr_hit[147]: begin reg_rdata_next[0] = mio_outsel_regwen_32_qs; end - addr_hit[150]: begin + addr_hit[148]: begin reg_rdata_next[0] = mio_outsel_regwen_33_qs; end - addr_hit[151]: begin + addr_hit[149]: begin reg_rdata_next[0] = mio_outsel_regwen_34_qs; end - addr_hit[152]: begin + addr_hit[150]: begin reg_rdata_next[0] = mio_outsel_regwen_35_qs; end - addr_hit[153]: begin + addr_hit[151]: begin reg_rdata_next[0] = mio_outsel_regwen_36_qs; end - addr_hit[154]: begin + addr_hit[152]: begin reg_rdata_next[0] = mio_outsel_regwen_37_qs; end - addr_hit[155]: begin + addr_hit[153]: begin reg_rdata_next[0] = mio_outsel_regwen_38_qs; end - addr_hit[156]: begin + addr_hit[154]: begin reg_rdata_next[0] = mio_outsel_regwen_39_qs; end - addr_hit[157]: begin + addr_hit[155]: begin reg_rdata_next[0] = mio_outsel_regwen_40_qs; end - addr_hit[158]: begin + addr_hit[156]: begin reg_rdata_next[0] = mio_outsel_regwen_41_qs; end - addr_hit[159]: begin + addr_hit[157]: begin reg_rdata_next[0] = mio_outsel_regwen_42_qs; end - addr_hit[160]: begin + addr_hit[158]: begin reg_rdata_next[0] = mio_outsel_regwen_43_qs; end - addr_hit[161]: begin + addr_hit[159]: begin reg_rdata_next[0] = mio_outsel_regwen_44_qs; end - addr_hit[162]: begin + addr_hit[160]: begin reg_rdata_next[0] = mio_outsel_regwen_45_qs; end - addr_hit[163]: begin + addr_hit[161]: begin reg_rdata_next[0] = mio_outsel_regwen_46_qs; end - addr_hit[164]: begin - reg_rdata_next[0] = mio_outsel_regwen_47_qs; - end - - addr_hit[165]: begin - reg_rdata_next[0] = mio_outsel_regwen_48_qs; - end - - addr_hit[166]: begin - reg_rdata_next[0] = mio_outsel_regwen_49_qs; - end - - addr_hit[167]: begin - reg_rdata_next[0] = mio_outsel_regwen_50_qs; - end - - addr_hit[168]: begin - reg_rdata_next[0] = mio_outsel_regwen_51_qs; - end - - addr_hit[169]: begin - reg_rdata_next[0] = mio_outsel_regwen_52_qs; - end - - addr_hit[170]: begin + addr_hit[162]: begin reg_rdata_next[6:0] = mio_outsel_0_qs; end - addr_hit[171]: begin + addr_hit[163]: begin reg_rdata_next[6:0] = mio_outsel_1_qs; end - addr_hit[172]: begin + addr_hit[164]: begin reg_rdata_next[6:0] = mio_outsel_2_qs; end - addr_hit[173]: begin + addr_hit[165]: begin reg_rdata_next[6:0] = mio_outsel_3_qs; end - addr_hit[174]: begin + addr_hit[166]: begin reg_rdata_next[6:0] = mio_outsel_4_qs; end - addr_hit[175]: begin + addr_hit[167]: begin reg_rdata_next[6:0] = mio_outsel_5_qs; end - addr_hit[176]: begin + addr_hit[168]: begin reg_rdata_next[6:0] = mio_outsel_6_qs; end - addr_hit[177]: begin + addr_hit[169]: begin reg_rdata_next[6:0] = mio_outsel_7_qs; end - addr_hit[178]: begin + addr_hit[170]: begin reg_rdata_next[6:0] = mio_outsel_8_qs; end - addr_hit[179]: begin + addr_hit[171]: begin reg_rdata_next[6:0] = mio_outsel_9_qs; end - addr_hit[180]: begin + addr_hit[172]: begin reg_rdata_next[6:0] = mio_outsel_10_qs; end - addr_hit[181]: begin + addr_hit[173]: begin reg_rdata_next[6:0] = mio_outsel_11_qs; end - addr_hit[182]: begin + addr_hit[174]: begin reg_rdata_next[6:0] = mio_outsel_12_qs; end - addr_hit[183]: begin + addr_hit[175]: begin reg_rdata_next[6:0] = mio_outsel_13_qs; end - addr_hit[184]: begin + addr_hit[176]: begin reg_rdata_next[6:0] = mio_outsel_14_qs; end - addr_hit[185]: begin + addr_hit[177]: begin reg_rdata_next[6:0] = mio_outsel_15_qs; end - addr_hit[186]: begin + addr_hit[178]: begin reg_rdata_next[6:0] = mio_outsel_16_qs; end - addr_hit[187]: begin + addr_hit[179]: begin reg_rdata_next[6:0] = mio_outsel_17_qs; end - addr_hit[188]: begin + addr_hit[180]: begin reg_rdata_next[6:0] = mio_outsel_18_qs; end - addr_hit[189]: begin + addr_hit[181]: begin reg_rdata_next[6:0] = mio_outsel_19_qs; end - addr_hit[190]: begin + addr_hit[182]: begin reg_rdata_next[6:0] = mio_outsel_20_qs; end - addr_hit[191]: begin + addr_hit[183]: begin reg_rdata_next[6:0] = mio_outsel_21_qs; end - addr_hit[192]: begin + addr_hit[184]: begin reg_rdata_next[6:0] = mio_outsel_22_qs; end - addr_hit[193]: begin + addr_hit[185]: begin reg_rdata_next[6:0] = mio_outsel_23_qs; end - addr_hit[194]: begin + addr_hit[186]: begin reg_rdata_next[6:0] = mio_outsel_24_qs; end - addr_hit[195]: begin + addr_hit[187]: begin reg_rdata_next[6:0] = mio_outsel_25_qs; end - addr_hit[196]: begin + addr_hit[188]: begin reg_rdata_next[6:0] = mio_outsel_26_qs; end - addr_hit[197]: begin + addr_hit[189]: begin reg_rdata_next[6:0] = mio_outsel_27_qs; end - addr_hit[198]: begin + addr_hit[190]: begin reg_rdata_next[6:0] = mio_outsel_28_qs; end - addr_hit[199]: begin + addr_hit[191]: begin reg_rdata_next[6:0] = mio_outsel_29_qs; end - addr_hit[200]: begin + addr_hit[192]: begin reg_rdata_next[6:0] = mio_outsel_30_qs; end - addr_hit[201]: begin + addr_hit[193]: begin reg_rdata_next[6:0] = mio_outsel_31_qs; end - addr_hit[202]: begin + addr_hit[194]: begin reg_rdata_next[6:0] = mio_outsel_32_qs; end - addr_hit[203]: begin + addr_hit[195]: begin reg_rdata_next[6:0] = mio_outsel_33_qs; end - addr_hit[204]: begin + addr_hit[196]: begin reg_rdata_next[6:0] = mio_outsel_34_qs; end - addr_hit[205]: begin + addr_hit[197]: begin reg_rdata_next[6:0] = mio_outsel_35_qs; end - addr_hit[206]: begin + addr_hit[198]: begin reg_rdata_next[6:0] = mio_outsel_36_qs; end - addr_hit[207]: begin + addr_hit[199]: begin reg_rdata_next[6:0] = mio_outsel_37_qs; end - addr_hit[208]: begin + addr_hit[200]: begin reg_rdata_next[6:0] = mio_outsel_38_qs; end - addr_hit[209]: begin + addr_hit[201]: begin reg_rdata_next[6:0] = mio_outsel_39_qs; end - addr_hit[210]: begin + addr_hit[202]: begin reg_rdata_next[6:0] = mio_outsel_40_qs; end - addr_hit[211]: begin + addr_hit[203]: begin reg_rdata_next[6:0] = mio_outsel_41_qs; end - addr_hit[212]: begin + addr_hit[204]: begin reg_rdata_next[6:0] = mio_outsel_42_qs; end - addr_hit[213]: begin + addr_hit[205]: begin reg_rdata_next[6:0] = mio_outsel_43_qs; end - addr_hit[214]: begin + addr_hit[206]: begin reg_rdata_next[6:0] = mio_outsel_44_qs; end - addr_hit[215]: begin + addr_hit[207]: begin reg_rdata_next[6:0] = mio_outsel_45_qs; end - addr_hit[216]: begin + addr_hit[208]: begin reg_rdata_next[6:0] = mio_outsel_46_qs; end - addr_hit[217]: begin - reg_rdata_next[6:0] = mio_outsel_47_qs; - end - - addr_hit[218]: begin - reg_rdata_next[6:0] = mio_outsel_48_qs; - end - - addr_hit[219]: begin - reg_rdata_next[6:0] = mio_outsel_49_qs; - end - - addr_hit[220]: begin - reg_rdata_next[6:0] = mio_outsel_50_qs; - end - - addr_hit[221]: begin - reg_rdata_next[6:0] = mio_outsel_51_qs; - end - - addr_hit[222]: begin - reg_rdata_next[6:0] = mio_outsel_52_qs; - end - - addr_hit[223]: begin + addr_hit[209]: begin reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end - addr_hit[224]: begin + addr_hit[210]: begin reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end - addr_hit[225]: begin + addr_hit[211]: begin reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end - addr_hit[226]: begin + addr_hit[212]: begin reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end - addr_hit[227]: begin + addr_hit[213]: begin reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end - addr_hit[228]: begin + addr_hit[214]: begin reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end - addr_hit[229]: begin + addr_hit[215]: begin reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end - addr_hit[230]: begin + addr_hit[216]: begin reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end - addr_hit[231]: begin + addr_hit[217]: begin reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end - addr_hit[232]: begin + addr_hit[218]: begin reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end - addr_hit[233]: begin + addr_hit[219]: begin reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end - addr_hit[234]: begin + addr_hit[220]: begin reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end - addr_hit[235]: begin + addr_hit[221]: begin reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end - addr_hit[236]: begin + addr_hit[222]: begin reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end - addr_hit[237]: begin + addr_hit[223]: begin reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end - addr_hit[238]: begin + addr_hit[224]: begin reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end - addr_hit[239]: begin + addr_hit[225]: begin reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end - addr_hit[240]: begin + addr_hit[226]: begin reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end - addr_hit[241]: begin + addr_hit[227]: begin reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end - addr_hit[242]: begin + addr_hit[228]: begin reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end - addr_hit[243]: begin + addr_hit[229]: begin reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end - addr_hit[244]: begin + addr_hit[230]: begin reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end - addr_hit[245]: begin + addr_hit[231]: begin reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end - addr_hit[246]: begin + addr_hit[232]: begin reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end - addr_hit[247]: begin + addr_hit[233]: begin reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end - addr_hit[248]: begin + addr_hit[234]: begin reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end - addr_hit[249]: begin + addr_hit[235]: begin reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end - addr_hit[250]: begin + addr_hit[236]: begin reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end - addr_hit[251]: begin + addr_hit[237]: begin reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end - addr_hit[252]: begin + addr_hit[238]: begin reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end - addr_hit[253]: begin + addr_hit[239]: begin reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end - addr_hit[254]: begin + addr_hit[240]: begin reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end - addr_hit[255]: begin + addr_hit[241]: begin reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; end - addr_hit[256]: begin + addr_hit[242]: begin reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; end - addr_hit[257]: begin + addr_hit[243]: begin reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; end - addr_hit[258]: begin + addr_hit[244]: begin reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; end - addr_hit[259]: begin + addr_hit[245]: begin reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; end - addr_hit[260]: begin + addr_hit[246]: begin reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; end - addr_hit[261]: begin + addr_hit[247]: begin reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; end - addr_hit[262]: begin + addr_hit[248]: begin reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; end - addr_hit[263]: begin + addr_hit[249]: begin reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; end - addr_hit[264]: begin + addr_hit[250]: begin reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; end - addr_hit[265]: begin + addr_hit[251]: begin reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; end - addr_hit[266]: begin + addr_hit[252]: begin reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; end - addr_hit[267]: begin + addr_hit[253]: begin reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; end - addr_hit[268]: begin + addr_hit[254]: begin reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; end - addr_hit[269]: begin + addr_hit[255]: begin reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; end - addr_hit[270]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_47_qs; - end - - addr_hit[271]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_48_qs; - end - - addr_hit[272]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_49_qs; - end - - addr_hit[273]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_50_qs; - end - - addr_hit[274]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_51_qs; - end - - addr_hit[275]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_52_qs; - end - - addr_hit[276]: begin + addr_hit[256]: begin reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; @@ -47352,7 +46733,7 @@ reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; end - addr_hit[277]: begin + addr_hit[257]: begin reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; @@ -47364,7 +46745,7 @@ reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; end - addr_hit[278]: begin + addr_hit[258]: begin reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; @@ -47376,7 +46757,7 @@ reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; end - addr_hit[279]: begin + addr_hit[259]: begin reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; @@ -47388,7 +46769,7 @@ reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; end - addr_hit[280]: begin + addr_hit[260]: begin reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; @@ -47400,7 +46781,7 @@ reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; end - addr_hit[281]: begin + addr_hit[261]: begin reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; @@ -47412,7 +46793,7 @@ reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; end - addr_hit[282]: begin + addr_hit[262]: begin reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; @@ -47424,7 +46805,7 @@ reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; end - addr_hit[283]: begin + addr_hit[263]: begin reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; @@ -47436,7 +46817,7 @@ reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; end - addr_hit[284]: begin + addr_hit[264]: begin reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; @@ -47448,7 +46829,7 @@ reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; end - addr_hit[285]: begin + addr_hit[265]: begin reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; @@ -47460,7 +46841,7 @@ reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; end - addr_hit[286]: begin + addr_hit[266]: begin reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; @@ -47472,7 +46853,7 @@ reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; end - addr_hit[287]: begin + addr_hit[267]: begin reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; @@ -47484,7 +46865,7 @@ reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; end - addr_hit[288]: begin + addr_hit[268]: begin reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs; @@ -47496,7 +46877,7 @@ reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs; end - addr_hit[289]: begin + addr_hit[269]: begin reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs; @@ -47508,7 +46889,7 @@ reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs; end - addr_hit[290]: begin + addr_hit[270]: begin reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs; @@ -47520,7 +46901,7 @@ reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs; end - addr_hit[291]: begin + addr_hit[271]: begin reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs; @@ -47532,7 +46913,7 @@ reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs; end - addr_hit[292]: begin + addr_hit[272]: begin reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs; reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs; reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs; @@ -47544,7 +46925,7 @@ reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs; end - addr_hit[293]: begin + addr_hit[273]: begin reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs; reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs; reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs; @@ -47556,7 +46937,7 @@ reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs; end - addr_hit[294]: begin + addr_hit[274]: begin reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs; reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs; reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs; @@ -47568,7 +46949,7 @@ reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs; end - addr_hit[295]: begin + addr_hit[275]: begin reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs; reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs; reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs; @@ -47580,7 +46961,7 @@ reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs; end - addr_hit[296]: begin + addr_hit[276]: begin reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs; reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs; reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs; @@ -47592,7 +46973,7 @@ reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs; end - addr_hit[297]: begin + addr_hit[277]: begin reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs; reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs; reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs; @@ -47604,7 +46985,7 @@ reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs; end - addr_hit[298]: begin + addr_hit[278]: begin reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs; reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs; reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs; @@ -47616,7 +46997,7 @@ reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs; end - addr_hit[299]: begin + addr_hit[279]: begin reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs; reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs; reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs; @@ -47628,7 +47009,7 @@ reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs; end - addr_hit[300]: begin + addr_hit[280]: begin reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs; reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs; reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs; @@ -47640,7 +47021,7 @@ reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs; end - addr_hit[301]: begin + addr_hit[281]: begin reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs; reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs; reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs; @@ -47652,7 +47033,7 @@ reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs; end - addr_hit[302]: begin + addr_hit[282]: begin reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs; reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs; reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs; @@ -47664,7 +47045,7 @@ reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs; end - addr_hit[303]: begin + addr_hit[283]: begin reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs; reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs; reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs; @@ -47676,7 +47057,7 @@ reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs; end - addr_hit[304]: begin + addr_hit[284]: begin reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs; reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs; reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs; @@ -47688,7 +47069,7 @@ reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs; end - addr_hit[305]: begin + addr_hit[285]: begin reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs; reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs; reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs; @@ -47700,7 +47081,7 @@ reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs; end - addr_hit[306]: begin + addr_hit[286]: begin reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs; reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs; reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs; @@ -47712,7 +47093,7 @@ reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs; end - addr_hit[307]: begin + addr_hit[287]: begin reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs; reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs; reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs; @@ -47724,7 +47105,7 @@ reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs; end - addr_hit[308]: begin + addr_hit[288]: begin reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs; reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs; reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs; @@ -47736,7 +47117,7 @@ reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs; end - addr_hit[309]: begin + addr_hit[289]: begin reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs; reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs; reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs; @@ -47748,7 +47129,7 @@ reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs; end - addr_hit[310]: begin + addr_hit[290]: begin reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs; reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs; reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs; @@ -47760,7 +47141,7 @@ reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs; end - addr_hit[311]: begin + addr_hit[291]: begin reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs; reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs; reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs; @@ -47772,7 +47153,7 @@ reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs; end - addr_hit[312]: begin + addr_hit[292]: begin reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs; reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs; reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs; @@ -47784,7 +47165,7 @@ reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs; end - addr_hit[313]: begin + addr_hit[293]: begin reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs; reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs; reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs; @@ -47796,7 +47177,7 @@ reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs; end - addr_hit[314]: begin + addr_hit[294]: begin reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs; reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs; reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs; @@ -47808,7 +47189,7 @@ reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs; end - addr_hit[315]: begin + addr_hit[295]: begin reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs; reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs; reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs; @@ -47820,7 +47201,7 @@ reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs; end - addr_hit[316]: begin + addr_hit[296]: begin reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs; reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs; reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs; @@ -47832,7 +47213,7 @@ reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs; end - addr_hit[317]: begin + addr_hit[297]: begin reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs; reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs; reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs; @@ -47844,7 +47225,7 @@ reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs; end - addr_hit[318]: begin + addr_hit[298]: begin reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs; reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs; reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs; @@ -47856,7 +47237,7 @@ reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs; end - addr_hit[319]: begin + addr_hit[299]: begin reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs; reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs; reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs; @@ -47868,7 +47249,7 @@ reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs; end - addr_hit[320]: begin + addr_hit[300]: begin reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs; reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs; reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs; @@ -47880,7 +47261,7 @@ reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs; end - addr_hit[321]: begin + addr_hit[301]: begin reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs; reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs; reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs; @@ -47892,7 +47273,7 @@ reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs; end - addr_hit[322]: begin + addr_hit[302]: begin reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs; reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs; reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs; @@ -47904,227 +47285,179 @@ reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs; end - addr_hit[323]: begin - reg_rdata_next[0] = mio_pad_attr_47_invert_47_qs; - reg_rdata_next[1] = mio_pad_attr_47_virtual_od_en_47_qs; - reg_rdata_next[2] = mio_pad_attr_47_pull_en_47_qs; - reg_rdata_next[3] = mio_pad_attr_47_pull_select_47_qs; - reg_rdata_next[4] = mio_pad_attr_47_keeper_en_47_qs; - reg_rdata_next[5] = mio_pad_attr_47_schmitt_en_47_qs; - reg_rdata_next[6] = mio_pad_attr_47_od_en_47_qs; - reg_rdata_next[17:16] = mio_pad_attr_47_slew_rate_47_qs; - reg_rdata_next[23:20] = mio_pad_attr_47_drive_strength_47_qs; - end - - addr_hit[324]: begin - reg_rdata_next[0] = mio_pad_attr_48_invert_48_qs; - reg_rdata_next[1] = mio_pad_attr_48_virtual_od_en_48_qs; - reg_rdata_next[2] = mio_pad_attr_48_pull_en_48_qs; - reg_rdata_next[3] = mio_pad_attr_48_pull_select_48_qs; - reg_rdata_next[4] = mio_pad_attr_48_keeper_en_48_qs; - reg_rdata_next[5] = mio_pad_attr_48_schmitt_en_48_qs; - reg_rdata_next[6] = mio_pad_attr_48_od_en_48_qs; - reg_rdata_next[17:16] = mio_pad_attr_48_slew_rate_48_qs; - reg_rdata_next[23:20] = mio_pad_attr_48_drive_strength_48_qs; - end - - addr_hit[325]: begin - reg_rdata_next[0] = mio_pad_attr_49_invert_49_qs; - reg_rdata_next[1] = mio_pad_attr_49_virtual_od_en_49_qs; - reg_rdata_next[2] = mio_pad_attr_49_pull_en_49_qs; - reg_rdata_next[3] = mio_pad_attr_49_pull_select_49_qs; - reg_rdata_next[4] = mio_pad_attr_49_keeper_en_49_qs; - reg_rdata_next[5] = mio_pad_attr_49_schmitt_en_49_qs; - reg_rdata_next[6] = mio_pad_attr_49_od_en_49_qs; - reg_rdata_next[17:16] = mio_pad_attr_49_slew_rate_49_qs; - reg_rdata_next[23:20] = mio_pad_attr_49_drive_strength_49_qs; - end - - addr_hit[326]: begin - reg_rdata_next[0] = mio_pad_attr_50_invert_50_qs; - reg_rdata_next[1] = mio_pad_attr_50_virtual_od_en_50_qs; - reg_rdata_next[2] = mio_pad_attr_50_pull_en_50_qs; - reg_rdata_next[3] = mio_pad_attr_50_pull_select_50_qs; - reg_rdata_next[4] = mio_pad_attr_50_keeper_en_50_qs; - reg_rdata_next[5] = mio_pad_attr_50_schmitt_en_50_qs; - reg_rdata_next[6] = mio_pad_attr_50_od_en_50_qs; - reg_rdata_next[17:16] = mio_pad_attr_50_slew_rate_50_qs; - reg_rdata_next[23:20] = mio_pad_attr_50_drive_strength_50_qs; - end - - addr_hit[327]: begin - reg_rdata_next[0] = mio_pad_attr_51_invert_51_qs; - reg_rdata_next[1] = mio_pad_attr_51_virtual_od_en_51_qs; - reg_rdata_next[2] = mio_pad_attr_51_pull_en_51_qs; - reg_rdata_next[3] = mio_pad_attr_51_pull_select_51_qs; - reg_rdata_next[4] = mio_pad_attr_51_keeper_en_51_qs; - reg_rdata_next[5] = mio_pad_attr_51_schmitt_en_51_qs; - reg_rdata_next[6] = mio_pad_attr_51_od_en_51_qs; - reg_rdata_next[17:16] = mio_pad_attr_51_slew_rate_51_qs; - reg_rdata_next[23:20] = mio_pad_attr_51_drive_strength_51_qs; - end - - addr_hit[328]: begin - reg_rdata_next[0] = mio_pad_attr_52_invert_52_qs; - reg_rdata_next[1] = mio_pad_attr_52_virtual_od_en_52_qs; - reg_rdata_next[2] = mio_pad_attr_52_pull_en_52_qs; - reg_rdata_next[3] = mio_pad_attr_52_pull_select_52_qs; - reg_rdata_next[4] = mio_pad_attr_52_keeper_en_52_qs; - reg_rdata_next[5] = mio_pad_attr_52_schmitt_en_52_qs; - reg_rdata_next[6] = mio_pad_attr_52_od_en_52_qs; - reg_rdata_next[17:16] = mio_pad_attr_52_slew_rate_52_qs; - reg_rdata_next[23:20] = mio_pad_attr_52_drive_strength_52_qs; - end - - addr_hit[329]: begin + addr_hit[303]: begin reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end - addr_hit[330]: begin + addr_hit[304]: begin reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end - addr_hit[331]: begin + addr_hit[305]: begin reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end - addr_hit[332]: begin + addr_hit[306]: begin reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end - addr_hit[333]: begin + addr_hit[307]: begin reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end - addr_hit[334]: begin + addr_hit[308]: begin reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end - addr_hit[335]: begin + addr_hit[309]: begin reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end - addr_hit[336]: begin + addr_hit[310]: begin reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end - addr_hit[337]: begin + addr_hit[311]: begin reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end - addr_hit[338]: begin + addr_hit[312]: begin reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end - addr_hit[339]: begin + addr_hit[313]: begin reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end - addr_hit[340]: begin + addr_hit[314]: begin reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end - addr_hit[341]: begin + addr_hit[315]: begin reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end - addr_hit[342]: begin + addr_hit[316]: begin reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end - addr_hit[343]: begin + addr_hit[317]: begin reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; end - addr_hit[344]: begin + addr_hit[318]: begin reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; end - addr_hit[345]: begin + addr_hit[319]: begin reg_rdata_next[0] = dio_pad_attr_regwen_16_qs; end - addr_hit[346]: begin + addr_hit[320]: begin reg_rdata_next[0] = dio_pad_attr_regwen_17_qs; end - addr_hit[347]: begin + addr_hit[321]: begin reg_rdata_next[0] = dio_pad_attr_regwen_18_qs; end - addr_hit[348]: begin + addr_hit[322]: begin reg_rdata_next[0] = dio_pad_attr_regwen_19_qs; end - addr_hit[349]: begin + addr_hit[323]: begin reg_rdata_next[0] = dio_pad_attr_regwen_20_qs; end - addr_hit[350]: begin + addr_hit[324]: begin reg_rdata_next[0] = dio_pad_attr_regwen_21_qs; end - addr_hit[351]: begin + addr_hit[325]: begin reg_rdata_next[0] = dio_pad_attr_regwen_22_qs; end - addr_hit[352]: begin + addr_hit[326]: begin reg_rdata_next[0] = dio_pad_attr_regwen_23_qs; end - addr_hit[353]: begin + addr_hit[327]: begin reg_rdata_next[0] = dio_pad_attr_regwen_24_qs; end - addr_hit[354]: begin + addr_hit[328]: begin reg_rdata_next[0] = dio_pad_attr_regwen_25_qs; end - addr_hit[355]: begin + addr_hit[329]: begin reg_rdata_next[0] = dio_pad_attr_regwen_26_qs; end - addr_hit[356]: begin + addr_hit[330]: begin reg_rdata_next[0] = dio_pad_attr_regwen_27_qs; end - addr_hit[357]: begin + addr_hit[331]: begin reg_rdata_next[0] = dio_pad_attr_regwen_28_qs; end - addr_hit[358]: begin + addr_hit[332]: begin reg_rdata_next[0] = dio_pad_attr_regwen_29_qs; end - addr_hit[359]: begin + addr_hit[333]: begin reg_rdata_next[0] = dio_pad_attr_regwen_30_qs; end - addr_hit[360]: begin + addr_hit[334]: begin reg_rdata_next[0] = dio_pad_attr_regwen_31_qs; end - addr_hit[361]: begin + addr_hit[335]: begin reg_rdata_next[0] = dio_pad_attr_regwen_32_qs; end - addr_hit[362]: begin + addr_hit[336]: begin reg_rdata_next[0] = dio_pad_attr_regwen_33_qs; end - addr_hit[363]: begin + addr_hit[337]: begin reg_rdata_next[0] = dio_pad_attr_regwen_34_qs; end - addr_hit[364]: begin + addr_hit[338]: begin reg_rdata_next[0] = dio_pad_attr_regwen_35_qs; end - addr_hit[365]: begin + addr_hit[339]: begin reg_rdata_next[0] = dio_pad_attr_regwen_36_qs; end - addr_hit[366]: begin + addr_hit[340]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_37_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_38_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_39_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_40_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_41_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_42_qs; + end + + addr_hit[346]: begin reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; @@ -48136,7 +47469,7 @@ reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; end - addr_hit[367]: begin + addr_hit[347]: begin reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; @@ -48148,7 +47481,7 @@ reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; end - addr_hit[368]: begin + addr_hit[348]: begin reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; @@ -48160,7 +47493,7 @@ reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; end - addr_hit[369]: begin + addr_hit[349]: begin reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; @@ -48172,7 +47505,7 @@ reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; end - addr_hit[370]: begin + addr_hit[350]: begin reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; @@ -48184,7 +47517,7 @@ reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; end - addr_hit[371]: begin + addr_hit[351]: begin reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; @@ -48196,7 +47529,7 @@ reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; end - addr_hit[372]: begin + addr_hit[352]: begin reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; @@ -48208,7 +47541,7 @@ reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; end - addr_hit[373]: begin + addr_hit[353]: begin reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; @@ -48220,7 +47553,7 @@ reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; end - addr_hit[374]: begin + addr_hit[354]: begin reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; @@ -48232,7 +47565,7 @@ reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; end - addr_hit[375]: begin + addr_hit[355]: begin reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; @@ -48244,7 +47577,7 @@ reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; end - addr_hit[376]: begin + addr_hit[356]: begin reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; @@ -48256,7 +47589,7 @@ reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; end - addr_hit[377]: begin + addr_hit[357]: begin reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; @@ -48268,7 +47601,7 @@ reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; end - addr_hit[378]: begin + addr_hit[358]: begin reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; @@ -48280,7 +47613,7 @@ reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; end - addr_hit[379]: begin + addr_hit[359]: begin reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; @@ -48292,7 +47625,7 @@ reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; end - addr_hit[380]: begin + addr_hit[360]: begin reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs; @@ -48304,7 +47637,7 @@ reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs; end - addr_hit[381]: begin + addr_hit[361]: begin reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs; @@ -48316,7 +47649,7 @@ reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs; end - addr_hit[382]: begin + addr_hit[362]: begin reg_rdata_next[0] = dio_pad_attr_16_invert_16_qs; reg_rdata_next[1] = dio_pad_attr_16_virtual_od_en_16_qs; reg_rdata_next[2] = dio_pad_attr_16_pull_en_16_qs; @@ -48328,7 +47661,7 @@ reg_rdata_next[23:20] = dio_pad_attr_16_drive_strength_16_qs; end - addr_hit[383]: begin + addr_hit[363]: begin reg_rdata_next[0] = dio_pad_attr_17_invert_17_qs; reg_rdata_next[1] = dio_pad_attr_17_virtual_od_en_17_qs; reg_rdata_next[2] = dio_pad_attr_17_pull_en_17_qs; @@ -48340,7 +47673,7 @@ reg_rdata_next[23:20] = dio_pad_attr_17_drive_strength_17_qs; end - addr_hit[384]: begin + addr_hit[364]: begin reg_rdata_next[0] = dio_pad_attr_18_invert_18_qs; reg_rdata_next[1] = dio_pad_attr_18_virtual_od_en_18_qs; reg_rdata_next[2] = dio_pad_attr_18_pull_en_18_qs; @@ -48352,7 +47685,7 @@ reg_rdata_next[23:20] = dio_pad_attr_18_drive_strength_18_qs; end - addr_hit[385]: begin + addr_hit[365]: begin reg_rdata_next[0] = dio_pad_attr_19_invert_19_qs; reg_rdata_next[1] = dio_pad_attr_19_virtual_od_en_19_qs; reg_rdata_next[2] = dio_pad_attr_19_pull_en_19_qs; @@ -48364,7 +47697,7 @@ reg_rdata_next[23:20] = dio_pad_attr_19_drive_strength_19_qs; end - addr_hit[386]: begin + addr_hit[366]: begin reg_rdata_next[0] = dio_pad_attr_20_invert_20_qs; reg_rdata_next[1] = dio_pad_attr_20_virtual_od_en_20_qs; reg_rdata_next[2] = dio_pad_attr_20_pull_en_20_qs; @@ -48376,7 +47709,7 @@ reg_rdata_next[23:20] = dio_pad_attr_20_drive_strength_20_qs; end - addr_hit[387]: begin + addr_hit[367]: begin reg_rdata_next[0] = dio_pad_attr_21_invert_21_qs; reg_rdata_next[1] = dio_pad_attr_21_virtual_od_en_21_qs; reg_rdata_next[2] = dio_pad_attr_21_pull_en_21_qs; @@ -48388,7 +47721,7 @@ reg_rdata_next[23:20] = dio_pad_attr_21_drive_strength_21_qs; end - addr_hit[388]: begin + addr_hit[368]: begin reg_rdata_next[0] = dio_pad_attr_22_invert_22_qs; reg_rdata_next[1] = dio_pad_attr_22_virtual_od_en_22_qs; reg_rdata_next[2] = dio_pad_attr_22_pull_en_22_qs; @@ -48400,7 +47733,7 @@ reg_rdata_next[23:20] = dio_pad_attr_22_drive_strength_22_qs; end - addr_hit[389]: begin + addr_hit[369]: begin reg_rdata_next[0] = dio_pad_attr_23_invert_23_qs; reg_rdata_next[1] = dio_pad_attr_23_virtual_od_en_23_qs; reg_rdata_next[2] = dio_pad_attr_23_pull_en_23_qs; @@ -48412,7 +47745,7 @@ reg_rdata_next[23:20] = dio_pad_attr_23_drive_strength_23_qs; end - addr_hit[390]: begin + addr_hit[370]: begin reg_rdata_next[0] = dio_pad_attr_24_invert_24_qs; reg_rdata_next[1] = dio_pad_attr_24_virtual_od_en_24_qs; reg_rdata_next[2] = dio_pad_attr_24_pull_en_24_qs; @@ -48424,7 +47757,7 @@ reg_rdata_next[23:20] = dio_pad_attr_24_drive_strength_24_qs; end - addr_hit[391]: begin + addr_hit[371]: begin reg_rdata_next[0] = dio_pad_attr_25_invert_25_qs; reg_rdata_next[1] = dio_pad_attr_25_virtual_od_en_25_qs; reg_rdata_next[2] = dio_pad_attr_25_pull_en_25_qs; @@ -48436,7 +47769,7 @@ reg_rdata_next[23:20] = dio_pad_attr_25_drive_strength_25_qs; end - addr_hit[392]: begin + addr_hit[372]: begin reg_rdata_next[0] = dio_pad_attr_26_invert_26_qs; reg_rdata_next[1] = dio_pad_attr_26_virtual_od_en_26_qs; reg_rdata_next[2] = dio_pad_attr_26_pull_en_26_qs; @@ -48448,7 +47781,7 @@ reg_rdata_next[23:20] = dio_pad_attr_26_drive_strength_26_qs; end - addr_hit[393]: begin + addr_hit[373]: begin reg_rdata_next[0] = dio_pad_attr_27_invert_27_qs; reg_rdata_next[1] = dio_pad_attr_27_virtual_od_en_27_qs; reg_rdata_next[2] = dio_pad_attr_27_pull_en_27_qs; @@ -48460,7 +47793,7 @@ reg_rdata_next[23:20] = dio_pad_attr_27_drive_strength_27_qs; end - addr_hit[394]: begin + addr_hit[374]: begin reg_rdata_next[0] = dio_pad_attr_28_invert_28_qs; reg_rdata_next[1] = dio_pad_attr_28_virtual_od_en_28_qs; reg_rdata_next[2] = dio_pad_attr_28_pull_en_28_qs; @@ -48472,7 +47805,7 @@ reg_rdata_next[23:20] = dio_pad_attr_28_drive_strength_28_qs; end - addr_hit[395]: begin + addr_hit[375]: begin reg_rdata_next[0] = dio_pad_attr_29_invert_29_qs; reg_rdata_next[1] = dio_pad_attr_29_virtual_od_en_29_qs; reg_rdata_next[2] = dio_pad_attr_29_pull_en_29_qs; @@ -48484,7 +47817,7 @@ reg_rdata_next[23:20] = dio_pad_attr_29_drive_strength_29_qs; end - addr_hit[396]: begin + addr_hit[376]: begin reg_rdata_next[0] = dio_pad_attr_30_invert_30_qs; reg_rdata_next[1] = dio_pad_attr_30_virtual_od_en_30_qs; reg_rdata_next[2] = dio_pad_attr_30_pull_en_30_qs; @@ -48496,7 +47829,7 @@ reg_rdata_next[23:20] = dio_pad_attr_30_drive_strength_30_qs; end - addr_hit[397]: begin + addr_hit[377]: begin reg_rdata_next[0] = dio_pad_attr_31_invert_31_qs; reg_rdata_next[1] = dio_pad_attr_31_virtual_od_en_31_qs; reg_rdata_next[2] = dio_pad_attr_31_pull_en_31_qs; @@ -48508,7 +47841,7 @@ reg_rdata_next[23:20] = dio_pad_attr_31_drive_strength_31_qs; end - addr_hit[398]: begin + addr_hit[378]: begin reg_rdata_next[0] = dio_pad_attr_32_invert_32_qs; reg_rdata_next[1] = dio_pad_attr_32_virtual_od_en_32_qs; reg_rdata_next[2] = dio_pad_attr_32_pull_en_32_qs; @@ -48520,7 +47853,7 @@ reg_rdata_next[23:20] = dio_pad_attr_32_drive_strength_32_qs; end - addr_hit[399]: begin + addr_hit[379]: begin reg_rdata_next[0] = dio_pad_attr_33_invert_33_qs; reg_rdata_next[1] = dio_pad_attr_33_virtual_od_en_33_qs; reg_rdata_next[2] = dio_pad_attr_33_pull_en_33_qs; @@ -48532,7 +47865,7 @@ reg_rdata_next[23:20] = dio_pad_attr_33_drive_strength_33_qs; end - addr_hit[400]: begin + addr_hit[380]: begin reg_rdata_next[0] = dio_pad_attr_34_invert_34_qs; reg_rdata_next[1] = dio_pad_attr_34_virtual_od_en_34_qs; reg_rdata_next[2] = dio_pad_attr_34_pull_en_34_qs; @@ -48544,7 +47877,7 @@ reg_rdata_next[23:20] = dio_pad_attr_34_drive_strength_34_qs; end - addr_hit[401]: begin + addr_hit[381]: begin reg_rdata_next[0] = dio_pad_attr_35_invert_35_qs; reg_rdata_next[1] = dio_pad_attr_35_virtual_od_en_35_qs; reg_rdata_next[2] = dio_pad_attr_35_pull_en_35_qs; @@ -48556,7 +47889,7 @@ reg_rdata_next[23:20] = dio_pad_attr_35_drive_strength_35_qs; end - addr_hit[402]: begin + addr_hit[382]: begin reg_rdata_next[0] = dio_pad_attr_36_invert_36_qs; reg_rdata_next[1] = dio_pad_attr_36_virtual_od_en_36_qs; reg_rdata_next[2] = dio_pad_attr_36_pull_en_36_qs; @@ -48568,7 +47901,79 @@ reg_rdata_next[23:20] = dio_pad_attr_36_drive_strength_36_qs; end - addr_hit[403]: begin + addr_hit[383]: begin + reg_rdata_next[0] = dio_pad_attr_37_invert_37_qs; + reg_rdata_next[1] = dio_pad_attr_37_virtual_od_en_37_qs; + reg_rdata_next[2] = dio_pad_attr_37_pull_en_37_qs; + reg_rdata_next[3] = dio_pad_attr_37_pull_select_37_qs; + reg_rdata_next[4] = dio_pad_attr_37_keeper_en_37_qs; + reg_rdata_next[5] = dio_pad_attr_37_schmitt_en_37_qs; + reg_rdata_next[6] = dio_pad_attr_37_od_en_37_qs; + reg_rdata_next[17:16] = dio_pad_attr_37_slew_rate_37_qs; + reg_rdata_next[23:20] = dio_pad_attr_37_drive_strength_37_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = dio_pad_attr_38_invert_38_qs; + reg_rdata_next[1] = dio_pad_attr_38_virtual_od_en_38_qs; + reg_rdata_next[2] = dio_pad_attr_38_pull_en_38_qs; + reg_rdata_next[3] = dio_pad_attr_38_pull_select_38_qs; + reg_rdata_next[4] = dio_pad_attr_38_keeper_en_38_qs; + reg_rdata_next[5] = dio_pad_attr_38_schmitt_en_38_qs; + reg_rdata_next[6] = dio_pad_attr_38_od_en_38_qs; + reg_rdata_next[17:16] = dio_pad_attr_38_slew_rate_38_qs; + reg_rdata_next[23:20] = dio_pad_attr_38_drive_strength_38_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = dio_pad_attr_39_invert_39_qs; + reg_rdata_next[1] = dio_pad_attr_39_virtual_od_en_39_qs; + reg_rdata_next[2] = dio_pad_attr_39_pull_en_39_qs; + reg_rdata_next[3] = dio_pad_attr_39_pull_select_39_qs; + reg_rdata_next[4] = dio_pad_attr_39_keeper_en_39_qs; + reg_rdata_next[5] = dio_pad_attr_39_schmitt_en_39_qs; + reg_rdata_next[6] = dio_pad_attr_39_od_en_39_qs; + reg_rdata_next[17:16] = dio_pad_attr_39_slew_rate_39_qs; + reg_rdata_next[23:20] = dio_pad_attr_39_drive_strength_39_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = dio_pad_attr_40_invert_40_qs; + reg_rdata_next[1] = dio_pad_attr_40_virtual_od_en_40_qs; + reg_rdata_next[2] = dio_pad_attr_40_pull_en_40_qs; + reg_rdata_next[3] = dio_pad_attr_40_pull_select_40_qs; + reg_rdata_next[4] = dio_pad_attr_40_keeper_en_40_qs; + reg_rdata_next[5] = dio_pad_attr_40_schmitt_en_40_qs; + reg_rdata_next[6] = dio_pad_attr_40_od_en_40_qs; + reg_rdata_next[17:16] = dio_pad_attr_40_slew_rate_40_qs; + reg_rdata_next[23:20] = dio_pad_attr_40_drive_strength_40_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = dio_pad_attr_41_invert_41_qs; + reg_rdata_next[1] = dio_pad_attr_41_virtual_od_en_41_qs; + reg_rdata_next[2] = dio_pad_attr_41_pull_en_41_qs; + reg_rdata_next[3] = dio_pad_attr_41_pull_select_41_qs; + reg_rdata_next[4] = dio_pad_attr_41_keeper_en_41_qs; + reg_rdata_next[5] = dio_pad_attr_41_schmitt_en_41_qs; + reg_rdata_next[6] = dio_pad_attr_41_od_en_41_qs; + reg_rdata_next[17:16] = dio_pad_attr_41_slew_rate_41_qs; + reg_rdata_next[23:20] = dio_pad_attr_41_drive_strength_41_qs; + end + + addr_hit[388]: begin + reg_rdata_next[0] = dio_pad_attr_42_invert_42_qs; + reg_rdata_next[1] = dio_pad_attr_42_virtual_od_en_42_qs; + reg_rdata_next[2] = dio_pad_attr_42_pull_en_42_qs; + reg_rdata_next[3] = dio_pad_attr_42_pull_select_42_qs; + reg_rdata_next[4] = dio_pad_attr_42_keeper_en_42_qs; + reg_rdata_next[5] = dio_pad_attr_42_schmitt_en_42_qs; + reg_rdata_next[6] = dio_pad_attr_42_od_en_42_qs; + reg_rdata_next[17:16] = dio_pad_attr_42_slew_rate_42_qs; + reg_rdata_next[23:20] = dio_pad_attr_42_drive_strength_42_qs; + end + + addr_hit[389]: begin reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs; reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs; reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs; @@ -48603,7 +48008,7 @@ reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs; end - addr_hit[404]: begin + addr_hit[390]: begin reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs; reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs; reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs; @@ -48619,651 +48024,573 @@ reg_rdata_next[12] = mio_pad_sleep_status_1_en_44_qs; reg_rdata_next[13] = mio_pad_sleep_status_1_en_45_qs; reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs; - reg_rdata_next[15] = mio_pad_sleep_status_1_en_47_qs; - reg_rdata_next[16] = mio_pad_sleep_status_1_en_48_qs; - reg_rdata_next[17] = mio_pad_sleep_status_1_en_49_qs; - reg_rdata_next[18] = mio_pad_sleep_status_1_en_50_qs; - reg_rdata_next[19] = mio_pad_sleep_status_1_en_51_qs; - reg_rdata_next[20] = mio_pad_sleep_status_1_en_52_qs; end - addr_hit[405]: begin + addr_hit[391]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end - addr_hit[406]: begin + addr_hit[392]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end - addr_hit[407]: begin + addr_hit[393]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end - addr_hit[408]: begin + addr_hit[394]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end - addr_hit[409]: begin + addr_hit[395]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end - addr_hit[410]: begin + addr_hit[396]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end - addr_hit[411]: begin + addr_hit[397]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end - addr_hit[412]: begin + addr_hit[398]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end - addr_hit[413]: begin + addr_hit[399]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end - addr_hit[414]: begin + addr_hit[400]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end - addr_hit[415]: begin + addr_hit[401]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end - addr_hit[416]: begin + addr_hit[402]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end - addr_hit[417]: begin + addr_hit[403]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end - addr_hit[418]: begin + addr_hit[404]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end - addr_hit[419]: begin + addr_hit[405]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end - addr_hit[420]: begin + addr_hit[406]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; end - addr_hit[421]: begin + addr_hit[407]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; end - addr_hit[422]: begin + addr_hit[408]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; end - addr_hit[423]: begin + addr_hit[409]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; end - addr_hit[424]: begin + addr_hit[410]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; end - addr_hit[425]: begin + addr_hit[411]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; end - addr_hit[426]: begin + addr_hit[412]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; end - addr_hit[427]: begin + addr_hit[413]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; end - addr_hit[428]: begin + addr_hit[414]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; end - addr_hit[429]: begin + addr_hit[415]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; end - addr_hit[430]: begin + addr_hit[416]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; end - addr_hit[431]: begin + addr_hit[417]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; end - addr_hit[432]: begin + addr_hit[418]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; end - addr_hit[433]: begin + addr_hit[419]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; end - addr_hit[434]: begin + addr_hit[420]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; end - addr_hit[435]: begin + addr_hit[421]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; end - addr_hit[436]: begin + addr_hit[422]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; end - addr_hit[437]: begin + addr_hit[423]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs; end - addr_hit[438]: begin + addr_hit[424]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs; end - addr_hit[439]: begin + addr_hit[425]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs; end - addr_hit[440]: begin + addr_hit[426]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs; end - addr_hit[441]: begin + addr_hit[427]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs; end - addr_hit[442]: begin + addr_hit[428]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs; end - addr_hit[443]: begin + addr_hit[429]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs; end - addr_hit[444]: begin + addr_hit[430]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs; end - addr_hit[445]: begin + addr_hit[431]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs; end - addr_hit[446]: begin + addr_hit[432]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs; end - addr_hit[447]: begin + addr_hit[433]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs; end - addr_hit[448]: begin + addr_hit[434]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs; end - addr_hit[449]: begin + addr_hit[435]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs; end - addr_hit[450]: begin + addr_hit[436]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs; end - addr_hit[451]: begin + addr_hit[437]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs; end - addr_hit[452]: begin - reg_rdata_next[0] = mio_pad_sleep_regwen_47_qs; - end - - addr_hit[453]: begin - reg_rdata_next[0] = mio_pad_sleep_regwen_48_qs; - end - - addr_hit[454]: begin - reg_rdata_next[0] = mio_pad_sleep_regwen_49_qs; - end - - addr_hit[455]: begin - reg_rdata_next[0] = mio_pad_sleep_regwen_50_qs; - end - - addr_hit[456]: begin - reg_rdata_next[0] = mio_pad_sleep_regwen_51_qs; - end - - addr_hit[457]: begin - reg_rdata_next[0] = mio_pad_sleep_regwen_52_qs; - end - - addr_hit[458]: begin + addr_hit[438]: begin reg_rdata_next[0] = mio_pad_sleep_en_0_qs; end - addr_hit[459]: begin + addr_hit[439]: begin reg_rdata_next[0] = mio_pad_sleep_en_1_qs; end - addr_hit[460]: begin + addr_hit[440]: begin reg_rdata_next[0] = mio_pad_sleep_en_2_qs; end - addr_hit[461]: begin + addr_hit[441]: begin reg_rdata_next[0] = mio_pad_sleep_en_3_qs; end - addr_hit[462]: begin + addr_hit[442]: begin reg_rdata_next[0] = mio_pad_sleep_en_4_qs; end - addr_hit[463]: begin + addr_hit[443]: begin reg_rdata_next[0] = mio_pad_sleep_en_5_qs; end - addr_hit[464]: begin + addr_hit[444]: begin reg_rdata_next[0] = mio_pad_sleep_en_6_qs; end - addr_hit[465]: begin + addr_hit[445]: begin reg_rdata_next[0] = mio_pad_sleep_en_7_qs; end - addr_hit[466]: begin + addr_hit[446]: begin reg_rdata_next[0] = mio_pad_sleep_en_8_qs; end - addr_hit[467]: begin + addr_hit[447]: begin reg_rdata_next[0] = mio_pad_sleep_en_9_qs; end - addr_hit[468]: begin + addr_hit[448]: begin reg_rdata_next[0] = mio_pad_sleep_en_10_qs; end - addr_hit[469]: begin + addr_hit[449]: begin reg_rdata_next[0] = mio_pad_sleep_en_11_qs; end - addr_hit[470]: begin + addr_hit[450]: begin reg_rdata_next[0] = mio_pad_sleep_en_12_qs; end - addr_hit[471]: begin + addr_hit[451]: begin reg_rdata_next[0] = mio_pad_sleep_en_13_qs; end - addr_hit[472]: begin + addr_hit[452]: begin reg_rdata_next[0] = mio_pad_sleep_en_14_qs; end - addr_hit[473]: begin + addr_hit[453]: begin reg_rdata_next[0] = mio_pad_sleep_en_15_qs; end - addr_hit[474]: begin + addr_hit[454]: begin reg_rdata_next[0] = mio_pad_sleep_en_16_qs; end - addr_hit[475]: begin + addr_hit[455]: begin reg_rdata_next[0] = mio_pad_sleep_en_17_qs; end - addr_hit[476]: begin + addr_hit[456]: begin reg_rdata_next[0] = mio_pad_sleep_en_18_qs; end - addr_hit[477]: begin + addr_hit[457]: begin reg_rdata_next[0] = mio_pad_sleep_en_19_qs; end - addr_hit[478]: begin + addr_hit[458]: begin reg_rdata_next[0] = mio_pad_sleep_en_20_qs; end - addr_hit[479]: begin + addr_hit[459]: begin reg_rdata_next[0] = mio_pad_sleep_en_21_qs; end - addr_hit[480]: begin + addr_hit[460]: begin reg_rdata_next[0] = mio_pad_sleep_en_22_qs; end - addr_hit[481]: begin + addr_hit[461]: begin reg_rdata_next[0] = mio_pad_sleep_en_23_qs; end - addr_hit[482]: begin + addr_hit[462]: begin reg_rdata_next[0] = mio_pad_sleep_en_24_qs; end - addr_hit[483]: begin + addr_hit[463]: begin reg_rdata_next[0] = mio_pad_sleep_en_25_qs; end - addr_hit[484]: begin + addr_hit[464]: begin reg_rdata_next[0] = mio_pad_sleep_en_26_qs; end - addr_hit[485]: begin + addr_hit[465]: begin reg_rdata_next[0] = mio_pad_sleep_en_27_qs; end - addr_hit[486]: begin + addr_hit[466]: begin reg_rdata_next[0] = mio_pad_sleep_en_28_qs; end - addr_hit[487]: begin + addr_hit[467]: begin reg_rdata_next[0] = mio_pad_sleep_en_29_qs; end - addr_hit[488]: begin + addr_hit[468]: begin reg_rdata_next[0] = mio_pad_sleep_en_30_qs; end - addr_hit[489]: begin + addr_hit[469]: begin reg_rdata_next[0] = mio_pad_sleep_en_31_qs; end - addr_hit[490]: begin + addr_hit[470]: begin reg_rdata_next[0] = mio_pad_sleep_en_32_qs; end - addr_hit[491]: begin + addr_hit[471]: begin reg_rdata_next[0] = mio_pad_sleep_en_33_qs; end - addr_hit[492]: begin + addr_hit[472]: begin reg_rdata_next[0] = mio_pad_sleep_en_34_qs; end - addr_hit[493]: begin + addr_hit[473]: begin reg_rdata_next[0] = mio_pad_sleep_en_35_qs; end - addr_hit[494]: begin + addr_hit[474]: begin reg_rdata_next[0] = mio_pad_sleep_en_36_qs; end - addr_hit[495]: begin + addr_hit[475]: begin reg_rdata_next[0] = mio_pad_sleep_en_37_qs; end - addr_hit[496]: begin + addr_hit[476]: begin reg_rdata_next[0] = mio_pad_sleep_en_38_qs; end - addr_hit[497]: begin + addr_hit[477]: begin reg_rdata_next[0] = mio_pad_sleep_en_39_qs; end - addr_hit[498]: begin + addr_hit[478]: begin reg_rdata_next[0] = mio_pad_sleep_en_40_qs; end - addr_hit[499]: begin + addr_hit[479]: begin reg_rdata_next[0] = mio_pad_sleep_en_41_qs; end - addr_hit[500]: begin + addr_hit[480]: begin reg_rdata_next[0] = mio_pad_sleep_en_42_qs; end - addr_hit[501]: begin + addr_hit[481]: begin reg_rdata_next[0] = mio_pad_sleep_en_43_qs; end - addr_hit[502]: begin + addr_hit[482]: begin reg_rdata_next[0] = mio_pad_sleep_en_44_qs; end - addr_hit[503]: begin + addr_hit[483]: begin reg_rdata_next[0] = mio_pad_sleep_en_45_qs; end - addr_hit[504]: begin + addr_hit[484]: begin reg_rdata_next[0] = mio_pad_sleep_en_46_qs; end - addr_hit[505]: begin - reg_rdata_next[0] = mio_pad_sleep_en_47_qs; - end - - addr_hit[506]: begin - reg_rdata_next[0] = mio_pad_sleep_en_48_qs; - end - - addr_hit[507]: begin - reg_rdata_next[0] = mio_pad_sleep_en_49_qs; - end - - addr_hit[508]: begin - reg_rdata_next[0] = mio_pad_sleep_en_50_qs; - end - - addr_hit[509]: begin - reg_rdata_next[0] = mio_pad_sleep_en_51_qs; - end - - addr_hit[510]: begin - reg_rdata_next[0] = mio_pad_sleep_en_52_qs; - end - - addr_hit[511]: begin + addr_hit[485]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; end - addr_hit[512]: begin + addr_hit[486]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; end - addr_hit[513]: begin + addr_hit[487]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; end - addr_hit[514]: begin + addr_hit[488]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; end - addr_hit[515]: begin + addr_hit[489]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; end - addr_hit[516]: begin + addr_hit[490]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; end - addr_hit[517]: begin + addr_hit[491]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; end - addr_hit[518]: begin + addr_hit[492]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; end - addr_hit[519]: begin + addr_hit[493]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; end - addr_hit[520]: begin + addr_hit[494]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; end - addr_hit[521]: begin + addr_hit[495]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; end - addr_hit[522]: begin + addr_hit[496]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; end - addr_hit[523]: begin + addr_hit[497]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; end - addr_hit[524]: begin + addr_hit[498]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; end - addr_hit[525]: begin + addr_hit[499]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; end - addr_hit[526]: begin + addr_hit[500]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; end - addr_hit[527]: begin + addr_hit[501]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; end - addr_hit[528]: begin + addr_hit[502]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; end - addr_hit[529]: begin + addr_hit[503]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; end - addr_hit[530]: begin + addr_hit[504]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; end - addr_hit[531]: begin + addr_hit[505]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; end - addr_hit[532]: begin + addr_hit[506]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; end - addr_hit[533]: begin + addr_hit[507]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; end - addr_hit[534]: begin + addr_hit[508]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; end - addr_hit[535]: begin + addr_hit[509]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; end - addr_hit[536]: begin + addr_hit[510]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; end - addr_hit[537]: begin + addr_hit[511]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; end - addr_hit[538]: begin + addr_hit[512]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; end - addr_hit[539]: begin + addr_hit[513]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; end - addr_hit[540]: begin + addr_hit[514]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; end - addr_hit[541]: begin + addr_hit[515]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; end - addr_hit[542]: begin + addr_hit[516]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; end - addr_hit[543]: begin + addr_hit[517]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs; end - addr_hit[544]: begin + addr_hit[518]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs; end - addr_hit[545]: begin + addr_hit[519]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs; end - addr_hit[546]: begin + addr_hit[520]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs; end - addr_hit[547]: begin + addr_hit[521]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs; end - addr_hit[548]: begin + addr_hit[522]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs; end - addr_hit[549]: begin + addr_hit[523]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs; end - addr_hit[550]: begin + addr_hit[524]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs; end - addr_hit[551]: begin + addr_hit[525]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs; end - addr_hit[552]: begin + addr_hit[526]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs; end - addr_hit[553]: begin + addr_hit[527]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs; end - addr_hit[554]: begin + addr_hit[528]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs; end - addr_hit[555]: begin + addr_hit[529]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs; end - addr_hit[556]: begin + addr_hit[530]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs; end - addr_hit[557]: begin + addr_hit[531]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs; end - addr_hit[558]: begin - reg_rdata_next[1:0] = mio_pad_sleep_mode_47_qs; - end - - addr_hit[559]: begin - reg_rdata_next[1:0] = mio_pad_sleep_mode_48_qs; - end - - addr_hit[560]: begin - reg_rdata_next[1:0] = mio_pad_sleep_mode_49_qs; - end - - addr_hit[561]: begin - reg_rdata_next[1:0] = mio_pad_sleep_mode_50_qs; - end - - addr_hit[562]: begin - reg_rdata_next[1:0] = mio_pad_sleep_mode_51_qs; - end - - addr_hit[563]: begin - reg_rdata_next[1:0] = mio_pad_sleep_mode_52_qs; - end - - addr_hit[564]: begin + addr_hit[532]: begin reg_rdata_next[0] = dio_pad_sleep_status_0_en_0_qs; reg_rdata_next[1] = dio_pad_sleep_status_0_en_1_qs; reg_rdata_next[2] = dio_pad_sleep_status_0_en_2_qs; @@ -49298,595 +48625,673 @@ reg_rdata_next[31] = dio_pad_sleep_status_0_en_31_qs; end - addr_hit[565]: begin + addr_hit[533]: begin reg_rdata_next[0] = dio_pad_sleep_status_1_en_32_qs; reg_rdata_next[1] = dio_pad_sleep_status_1_en_33_qs; reg_rdata_next[2] = dio_pad_sleep_status_1_en_34_qs; reg_rdata_next[3] = dio_pad_sleep_status_1_en_35_qs; reg_rdata_next[4] = dio_pad_sleep_status_1_en_36_qs; + reg_rdata_next[5] = dio_pad_sleep_status_1_en_37_qs; + reg_rdata_next[6] = dio_pad_sleep_status_1_en_38_qs; + reg_rdata_next[7] = dio_pad_sleep_status_1_en_39_qs; + reg_rdata_next[8] = dio_pad_sleep_status_1_en_40_qs; + reg_rdata_next[9] = dio_pad_sleep_status_1_en_41_qs; + reg_rdata_next[10] = dio_pad_sleep_status_1_en_42_qs; end - addr_hit[566]: begin + addr_hit[534]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; end - addr_hit[567]: begin + addr_hit[535]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; end - addr_hit[568]: begin + addr_hit[536]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; end - addr_hit[569]: begin + addr_hit[537]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; end - addr_hit[570]: begin + addr_hit[538]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; end - addr_hit[571]: begin + addr_hit[539]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; end - addr_hit[572]: begin + addr_hit[540]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; end - addr_hit[573]: begin + addr_hit[541]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; end - addr_hit[574]: begin + addr_hit[542]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; end - addr_hit[575]: begin + addr_hit[543]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; end - addr_hit[576]: begin + addr_hit[544]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; end - addr_hit[577]: begin + addr_hit[545]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; end - addr_hit[578]: begin + addr_hit[546]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; end - addr_hit[579]: begin + addr_hit[547]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; end - addr_hit[580]: begin + addr_hit[548]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; end - addr_hit[581]: begin + addr_hit[549]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; end - addr_hit[582]: begin + addr_hit[550]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs; end - addr_hit[583]: begin + addr_hit[551]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs; end - addr_hit[584]: begin + addr_hit[552]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs; end - addr_hit[585]: begin + addr_hit[553]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs; end - addr_hit[586]: begin + addr_hit[554]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs; end - addr_hit[587]: begin + addr_hit[555]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_21_qs; end - addr_hit[588]: begin + addr_hit[556]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_22_qs; end - addr_hit[589]: begin + addr_hit[557]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_23_qs; end - addr_hit[590]: begin + addr_hit[558]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_24_qs; end - addr_hit[591]: begin + addr_hit[559]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_25_qs; end - addr_hit[592]: begin + addr_hit[560]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_26_qs; end - addr_hit[593]: begin + addr_hit[561]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_27_qs; end - addr_hit[594]: begin + addr_hit[562]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_28_qs; end - addr_hit[595]: begin + addr_hit[563]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_29_qs; end - addr_hit[596]: begin + addr_hit[564]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_30_qs; end - addr_hit[597]: begin + addr_hit[565]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_31_qs; end - addr_hit[598]: begin + addr_hit[566]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_32_qs; end - addr_hit[599]: begin + addr_hit[567]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_33_qs; end - addr_hit[600]: begin + addr_hit[568]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_34_qs; end - addr_hit[601]: begin + addr_hit[569]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_35_qs; end - addr_hit[602]: begin + addr_hit[570]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_36_qs; end - addr_hit[603]: begin + addr_hit[571]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_37_qs; + end + + addr_hit[572]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_38_qs; + end + + addr_hit[573]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_39_qs; + end + + addr_hit[574]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_40_qs; + end + + addr_hit[575]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_41_qs; + end + + addr_hit[576]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_42_qs; + end + + addr_hit[577]: begin reg_rdata_next[0] = dio_pad_sleep_en_0_qs; end - addr_hit[604]: begin + addr_hit[578]: begin reg_rdata_next[0] = dio_pad_sleep_en_1_qs; end - addr_hit[605]: begin + addr_hit[579]: begin reg_rdata_next[0] = dio_pad_sleep_en_2_qs; end - addr_hit[606]: begin + addr_hit[580]: begin reg_rdata_next[0] = dio_pad_sleep_en_3_qs; end - addr_hit[607]: begin + addr_hit[581]: begin reg_rdata_next[0] = dio_pad_sleep_en_4_qs; end - addr_hit[608]: begin + addr_hit[582]: begin reg_rdata_next[0] = dio_pad_sleep_en_5_qs; end - addr_hit[609]: begin + addr_hit[583]: begin reg_rdata_next[0] = dio_pad_sleep_en_6_qs; end - addr_hit[610]: begin + addr_hit[584]: begin reg_rdata_next[0] = dio_pad_sleep_en_7_qs; end - addr_hit[611]: begin + addr_hit[585]: begin reg_rdata_next[0] = dio_pad_sleep_en_8_qs; end - addr_hit[612]: begin + addr_hit[586]: begin reg_rdata_next[0] = dio_pad_sleep_en_9_qs; end - addr_hit[613]: begin + addr_hit[587]: begin reg_rdata_next[0] = dio_pad_sleep_en_10_qs; end - addr_hit[614]: begin + addr_hit[588]: begin reg_rdata_next[0] = dio_pad_sleep_en_11_qs; end - addr_hit[615]: begin + addr_hit[589]: begin reg_rdata_next[0] = dio_pad_sleep_en_12_qs; end - addr_hit[616]: begin + addr_hit[590]: begin reg_rdata_next[0] = dio_pad_sleep_en_13_qs; end - addr_hit[617]: begin + addr_hit[591]: begin reg_rdata_next[0] = dio_pad_sleep_en_14_qs; end - addr_hit[618]: begin + addr_hit[592]: begin reg_rdata_next[0] = dio_pad_sleep_en_15_qs; end - addr_hit[619]: begin + addr_hit[593]: begin reg_rdata_next[0] = dio_pad_sleep_en_16_qs; end - addr_hit[620]: begin + addr_hit[594]: begin reg_rdata_next[0] = dio_pad_sleep_en_17_qs; end - addr_hit[621]: begin + addr_hit[595]: begin reg_rdata_next[0] = dio_pad_sleep_en_18_qs; end - addr_hit[622]: begin + addr_hit[596]: begin reg_rdata_next[0] = dio_pad_sleep_en_19_qs; end - addr_hit[623]: begin + addr_hit[597]: begin reg_rdata_next[0] = dio_pad_sleep_en_20_qs; end - addr_hit[624]: begin + addr_hit[598]: begin reg_rdata_next[0] = dio_pad_sleep_en_21_qs; end - addr_hit[625]: begin + addr_hit[599]: begin reg_rdata_next[0] = dio_pad_sleep_en_22_qs; end - addr_hit[626]: begin + addr_hit[600]: begin reg_rdata_next[0] = dio_pad_sleep_en_23_qs; end - addr_hit[627]: begin + addr_hit[601]: begin reg_rdata_next[0] = dio_pad_sleep_en_24_qs; end - addr_hit[628]: begin + addr_hit[602]: begin reg_rdata_next[0] = dio_pad_sleep_en_25_qs; end - addr_hit[629]: begin + addr_hit[603]: begin reg_rdata_next[0] = dio_pad_sleep_en_26_qs; end - addr_hit[630]: begin + addr_hit[604]: begin reg_rdata_next[0] = dio_pad_sleep_en_27_qs; end - addr_hit[631]: begin + addr_hit[605]: begin reg_rdata_next[0] = dio_pad_sleep_en_28_qs; end - addr_hit[632]: begin + addr_hit[606]: begin reg_rdata_next[0] = dio_pad_sleep_en_29_qs; end - addr_hit[633]: begin + addr_hit[607]: begin reg_rdata_next[0] = dio_pad_sleep_en_30_qs; end - addr_hit[634]: begin + addr_hit[608]: begin reg_rdata_next[0] = dio_pad_sleep_en_31_qs; end - addr_hit[635]: begin + addr_hit[609]: begin reg_rdata_next[0] = dio_pad_sleep_en_32_qs; end - addr_hit[636]: begin + addr_hit[610]: begin reg_rdata_next[0] = dio_pad_sleep_en_33_qs; end - addr_hit[637]: begin + addr_hit[611]: begin reg_rdata_next[0] = dio_pad_sleep_en_34_qs; end - addr_hit[638]: begin + addr_hit[612]: begin reg_rdata_next[0] = dio_pad_sleep_en_35_qs; end - addr_hit[639]: begin + addr_hit[613]: begin reg_rdata_next[0] = dio_pad_sleep_en_36_qs; end - addr_hit[640]: begin + addr_hit[614]: begin + reg_rdata_next[0] = dio_pad_sleep_en_37_qs; + end + + addr_hit[615]: begin + reg_rdata_next[0] = dio_pad_sleep_en_38_qs; + end + + addr_hit[616]: begin + reg_rdata_next[0] = dio_pad_sleep_en_39_qs; + end + + addr_hit[617]: begin + reg_rdata_next[0] = dio_pad_sleep_en_40_qs; + end + + addr_hit[618]: begin + reg_rdata_next[0] = dio_pad_sleep_en_41_qs; + end + + addr_hit[619]: begin + reg_rdata_next[0] = dio_pad_sleep_en_42_qs; + end + + addr_hit[620]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; end - addr_hit[641]: begin + addr_hit[621]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; end - addr_hit[642]: begin + addr_hit[622]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; end - addr_hit[643]: begin + addr_hit[623]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; end - addr_hit[644]: begin + addr_hit[624]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; end - addr_hit[645]: begin + addr_hit[625]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; end - addr_hit[646]: begin + addr_hit[626]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; end - addr_hit[647]: begin + addr_hit[627]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; end - addr_hit[648]: begin + addr_hit[628]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; end - addr_hit[649]: begin + addr_hit[629]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; end - addr_hit[650]: begin + addr_hit[630]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; end - addr_hit[651]: begin + addr_hit[631]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; end - addr_hit[652]: begin + addr_hit[632]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; end - addr_hit[653]: begin + addr_hit[633]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; end - addr_hit[654]: begin + addr_hit[634]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; end - addr_hit[655]: begin + addr_hit[635]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; end - addr_hit[656]: begin + addr_hit[636]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs; end - addr_hit[657]: begin + addr_hit[637]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs; end - addr_hit[658]: begin + addr_hit[638]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs; end - addr_hit[659]: begin + addr_hit[639]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs; end - addr_hit[660]: begin + addr_hit[640]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs; end - addr_hit[661]: begin + addr_hit[641]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_21_qs; end - addr_hit[662]: begin + addr_hit[642]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_22_qs; end - addr_hit[663]: begin + addr_hit[643]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_23_qs; end - addr_hit[664]: begin + addr_hit[644]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_24_qs; end - addr_hit[665]: begin + addr_hit[645]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_25_qs; end - addr_hit[666]: begin + addr_hit[646]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_26_qs; end - addr_hit[667]: begin + addr_hit[647]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_27_qs; end - addr_hit[668]: begin + addr_hit[648]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_28_qs; end - addr_hit[669]: begin + addr_hit[649]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_29_qs; end - addr_hit[670]: begin + addr_hit[650]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_30_qs; end - addr_hit[671]: begin + addr_hit[651]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_31_qs; end - addr_hit[672]: begin + addr_hit[652]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_32_qs; end - addr_hit[673]: begin + addr_hit[653]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_33_qs; end - addr_hit[674]: begin + addr_hit[654]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_34_qs; end - addr_hit[675]: begin + addr_hit[655]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_35_qs; end - addr_hit[676]: begin + addr_hit[656]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_36_qs; end - addr_hit[677]: begin + addr_hit[657]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_37_qs; + end + + addr_hit[658]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_38_qs; + end + + addr_hit[659]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_39_qs; + end + + addr_hit[660]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_40_qs; + end + + addr_hit[661]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_41_qs; + end + + addr_hit[662]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_42_qs; + end + + addr_hit[663]: begin reg_rdata_next[0] = wkup_detector_regwen_0_qs; end - addr_hit[678]: begin + addr_hit[664]: begin reg_rdata_next[0] = wkup_detector_regwen_1_qs; end - addr_hit[679]: begin + addr_hit[665]: begin reg_rdata_next[0] = wkup_detector_regwen_2_qs; end - addr_hit[680]: begin + addr_hit[666]: begin reg_rdata_next[0] = wkup_detector_regwen_3_qs; end - addr_hit[681]: begin + addr_hit[667]: begin reg_rdata_next[0] = wkup_detector_regwen_4_qs; end - addr_hit[682]: begin + addr_hit[668]: begin reg_rdata_next[0] = wkup_detector_regwen_5_qs; end - addr_hit[683]: begin + addr_hit[669]: begin reg_rdata_next[0] = wkup_detector_regwen_6_qs; end - addr_hit[684]: begin + addr_hit[670]: begin reg_rdata_next[0] = wkup_detector_regwen_7_qs; end - addr_hit[685]: begin + addr_hit[671]: begin reg_rdata_next = DW'(wkup_detector_en_0_qs); end - addr_hit[686]: begin + addr_hit[672]: begin reg_rdata_next = DW'(wkup_detector_en_1_qs); end - addr_hit[687]: begin + addr_hit[673]: begin reg_rdata_next = DW'(wkup_detector_en_2_qs); end - addr_hit[688]: begin + addr_hit[674]: begin reg_rdata_next = DW'(wkup_detector_en_3_qs); end - addr_hit[689]: begin + addr_hit[675]: begin reg_rdata_next = DW'(wkup_detector_en_4_qs); end - addr_hit[690]: begin + addr_hit[676]: begin reg_rdata_next = DW'(wkup_detector_en_5_qs); end - addr_hit[691]: begin + addr_hit[677]: begin reg_rdata_next = DW'(wkup_detector_en_6_qs); end - addr_hit[692]: begin + addr_hit[678]: begin reg_rdata_next = DW'(wkup_detector_en_7_qs); end - addr_hit[693]: begin + addr_hit[679]: begin reg_rdata_next = DW'(wkup_detector_0_qs); end - addr_hit[694]: begin + addr_hit[680]: begin reg_rdata_next = DW'(wkup_detector_1_qs); end - addr_hit[695]: begin + addr_hit[681]: begin reg_rdata_next = DW'(wkup_detector_2_qs); end - addr_hit[696]: begin + addr_hit[682]: begin reg_rdata_next = DW'(wkup_detector_3_qs); end - addr_hit[697]: begin + addr_hit[683]: begin reg_rdata_next = DW'(wkup_detector_4_qs); end - addr_hit[698]: begin + addr_hit[684]: begin reg_rdata_next = DW'(wkup_detector_5_qs); end - addr_hit[699]: begin + addr_hit[685]: begin reg_rdata_next = DW'(wkup_detector_6_qs); end - addr_hit[700]: begin + addr_hit[686]: begin reg_rdata_next = DW'(wkup_detector_7_qs); end - addr_hit[701]: begin + addr_hit[687]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); end - addr_hit[702]: begin + addr_hit[688]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); end - addr_hit[703]: begin + addr_hit[689]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); end - addr_hit[704]: begin + addr_hit[690]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); end - addr_hit[705]: begin + addr_hit[691]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); end - addr_hit[706]: begin + addr_hit[692]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); end - addr_hit[707]: begin + addr_hit[693]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); end - addr_hit[708]: begin + addr_hit[694]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); end - addr_hit[709]: begin + addr_hit[695]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[710]: begin + addr_hit[696]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[711]: begin + addr_hit[697]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[712]: begin + addr_hit[698]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[713]: begin + addr_hit[699]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[714]: begin + addr_hit[700]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[715]: begin + addr_hit[701]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[716]: begin + addr_hit[702]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[717]: begin + addr_hit[703]: begin reg_rdata_next = DW'(wkup_cause_qs); end default: begin @@ -49905,79 +49310,79 @@ always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[685]: begin + addr_hit[671]: begin reg_busy_sel = wkup_detector_en_0_busy; end - addr_hit[686]: begin + addr_hit[672]: begin reg_busy_sel = wkup_detector_en_1_busy; end - addr_hit[687]: begin + addr_hit[673]: begin reg_busy_sel = wkup_detector_en_2_busy; end - addr_hit[688]: begin + addr_hit[674]: begin reg_busy_sel = wkup_detector_en_3_busy; end - addr_hit[689]: begin + addr_hit[675]: begin reg_busy_sel = wkup_detector_en_4_busy; end - addr_hit[690]: begin + addr_hit[676]: begin reg_busy_sel = wkup_detector_en_5_busy; end - addr_hit[691]: begin + addr_hit[677]: begin reg_busy_sel = wkup_detector_en_6_busy; end - addr_hit[692]: begin + addr_hit[678]: begin reg_busy_sel = wkup_detector_en_7_busy; end - addr_hit[693]: begin + addr_hit[679]: begin reg_busy_sel = wkup_detector_0_busy; end - addr_hit[694]: begin + addr_hit[680]: begin reg_busy_sel = wkup_detector_1_busy; end - addr_hit[695]: begin + addr_hit[681]: begin reg_busy_sel = wkup_detector_2_busy; end - addr_hit[696]: begin + addr_hit[682]: begin reg_busy_sel = wkup_detector_3_busy; end - addr_hit[697]: begin + addr_hit[683]: begin reg_busy_sel = wkup_detector_4_busy; end - addr_hit[698]: begin + addr_hit[684]: begin reg_busy_sel = wkup_detector_5_busy; end - addr_hit[699]: begin + addr_hit[685]: begin reg_busy_sel = wkup_detector_6_busy; end - addr_hit[700]: begin + addr_hit[686]: begin reg_busy_sel = wkup_detector_7_busy; end - addr_hit[701]: begin + addr_hit[687]: begin reg_busy_sel = wkup_detector_cnt_th_0_busy; end - addr_hit[702]: begin + addr_hit[688]: begin reg_busy_sel = wkup_detector_cnt_th_1_busy; end - addr_hit[703]: begin + addr_hit[689]: begin reg_busy_sel = wkup_detector_cnt_th_2_busy; end - addr_hit[704]: begin + addr_hit[690]: begin reg_busy_sel = wkup_detector_cnt_th_3_busy; end - addr_hit[705]: begin + addr_hit[691]: begin reg_busy_sel = wkup_detector_cnt_th_4_busy; end - addr_hit[706]: begin + addr_hit[692]: begin reg_busy_sel = wkup_detector_cnt_th_5_busy; end - addr_hit[707]: begin + addr_hit[693]: begin reg_busy_sel = wkup_detector_cnt_th_6_busy; end - addr_hit[708]: begin + addr_hit[694]: begin reg_busy_sel = wkup_detector_cnt_th_7_busy; end - addr_hit[717]: begin + addr_hit[703]: begin reg_busy_sel = wkup_cause_busy; end default: begin
diff --git a/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv b/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv index b713384..633994b 100644 --- a/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv +++ b/hw/top_matcha/rtl/autogen/chip_matcha_asic.sv
@@ -56,6 +56,12 @@ inout ISP_DVP_VSYNC, // Dedicated Pad for isp_wrapper_s_vsync inout CAM_TRIG, // Dedicated Pad for cam_ctrl_cam_trig inout CAM_INT, // Dedicated Pad for cam_ctrl_cam_int + inout I2S0_RX_SCLK, // Dedicated Pad for i2s0_rx_sclk + inout I2S0_RX_WS, // Dedicated Pad for i2s0_rx_ws + inout I2S0_RX_SD, // Dedicated Pad for i2s0_rx_sd + inout I2S0_TX_SCLK, // Dedicated Pad for i2s0_tx_sclk + inout I2S0_TX_WS, // Dedicated Pad for i2s0_tx_ws + inout I2S0_TX_SD, // Dedicated Pad for i2s0_tx_sd inout IOR8, // Dedicated Pad for sysrst_ctrl_aon_ec_rst_l inout IOR9, // Dedicated Pad for sysrst_ctrl_aon_flash_wp_l inout AST_MISC, // Manual Pad @@ -107,13 +113,7 @@ inout IOR10, // MIO Pad 43 inout IOR11, // MIO Pad 44 inout IOR12, // MIO Pad 45 - inout IOR13, // MIO Pad 46 - inout IOD0, // MIO Pad 47 - inout IOD1, // MIO Pad 48 - inout IOD2, // MIO Pad 49 - inout IOD3, // MIO Pad 50 - inout IOD4, // MIO Pad 51 - inout IOD5 // MIO Pad 52 + inout IOR13 // MIO Pad 46 ); import top_matcha_pkg::*; @@ -150,11 +150,17 @@ usb_sense_idx: MioInUsbdevSense, // Pad types for attribute WARL behavior dio_pad_type: { + BidirStd, // DIO i2s0_tx_sd + BidirStd, // DIO i2s0_tx_ws + BidirStd, // DIO i2s0_tx_sclk + BidirStd, // DIO i2s0_rx_ws + BidirStd, // DIO i2s0_rx_sclk BidirStd, // DIO cam_ctrl_cam_trig BidirStd, // DIO spi_host2_csb BidirStd, // DIO spi_host2_sck BidirStd, // DIO spi_host0_csb BidirStd, // DIO spi_host0_sck + BidirStd, // DIO i2s0_rx_sd InputStd, // DIO cam_ctrl_cam_int InputStd, // DIO isp_wrapper_s_vsync InputStd, // DIO isp_wrapper_s_hsync @@ -189,12 +195,6 @@ BidirStd // DIO usbdev_usb_dp }, mio_pad_type: { - BidirStd, // MIO Pad 52 - BidirStd, // MIO Pad 51 - BidirStd, // MIO Pad 50 - BidirStd, // MIO Pad 49 - BidirStd, // MIO Pad 48 - BidirStd, // MIO Pad 47 BidirOd, // MIO Pad 46 BidirOd, // MIO Pad 45 BidirOd, // MIO Pad 44 @@ -304,14 +304,20 @@ padring #( // Padring specific counts may differ from pinmux config due // to custom, stubbed or added pads. - .NDioPads(45), - .NMioPads(53), + .NDioPads(51), + .NMioPads(47), .PhysicalPads(1), .NIoBanks(int'(IoBankCount)), .DioScanRole ({ scan_role_pkg::DioPadAstMiscScanRole, scan_role_pkg::DioPadIor9ScanRole, scan_role_pkg::DioPadIor8ScanRole, + scan_role_pkg::DioPadI2s0TxSdScanRole, + scan_role_pkg::DioPadI2s0TxWsScanRole, + scan_role_pkg::DioPadI2s0TxSclkScanRole, + scan_role_pkg::DioPadI2s0RxSdScanRole, + scan_role_pkg::DioPadI2s0RxWsScanRole, + scan_role_pkg::DioPadI2s0RxSclkScanRole, scan_role_pkg::DioPadCamIntScanRole, scan_role_pkg::DioPadCamTrigScanRole, scan_role_pkg::DioPadIspDvpVsyncScanRole, @@ -356,12 +362,6 @@ scan_role_pkg::DioPadPorNScanRole }), .MioScanRole ({ - scan_role_pkg::MioPadIod5ScanRole, - scan_role_pkg::MioPadIod4ScanRole, - scan_role_pkg::MioPadIod3ScanRole, - scan_role_pkg::MioPadIod2ScanRole, - scan_role_pkg::MioPadIod1ScanRole, - scan_role_pkg::MioPadIod0ScanRole, scan_role_pkg::MioPadIor13ScanRole, scan_role_pkg::MioPadIor12ScanRole, scan_role_pkg::MioPadIor11ScanRole, @@ -414,6 +414,12 @@ IoBankVcc, // AST_MISC IoBankVcc, // IOR9 IoBankVcc, // IOR8 + IoBankVioa, // I2S0_TX_SD + IoBankVioa, // I2S0_TX_WS + IoBankVioa, // I2S0_TX_SCLK + IoBankVioa, // I2S0_RX_SD + IoBankVioa, // I2S0_RX_WS + IoBankVioa, // I2S0_RX_SCLK IoBankVioa, // CAM_INT IoBankVioa, // CAM_TRIG IoBankVioa, // ISP_DVP_VSYNC @@ -458,12 +464,6 @@ IoBankVcc // POR_N }), .MioPadBank ({ - IoBankVcc, // IOD5 - IoBankVcc, // IOD4 - IoBankVcc, // IOD3 - IoBankVcc, // IOD2 - IoBankVcc, // IOD1 - IoBankVcc, // IOD0 IoBankVcc, // IOR13 IoBankVcc, // IOR12 IoBankVcc, // IOR11 @@ -516,6 +516,12 @@ InputStd, // AST_MISC BidirOd, // IOR9 BidirOd, // IOR8 + BidirStd, // I2S0_TX_SD + BidirStd, // I2S0_TX_WS + BidirStd, // I2S0_TX_SCLK + BidirStd, // I2S0_RX_SD + BidirStd, // I2S0_RX_WS + BidirStd, // I2S0_RX_SCLK InputStd, // CAM_INT BidirStd, // CAM_TRIG InputStd, // ISP_DVP_VSYNC @@ -560,12 +566,6 @@ InputStd // POR_N }), .MioPadType ({ - BidirStd, // IOD5 - BidirStd, // IOD4 - BidirStd, // IOD3 - BidirStd, // IOD2 - BidirStd, // IOD1 - BidirStd, // IOD0 BidirOd, // IOR13 BidirOd, // IOR12 BidirOd, // IOR11 @@ -624,6 +624,12 @@ AST_MISC, IOR9, IOR8, + I2S0_TX_SD, + I2S0_TX_WS, + I2S0_TX_SCLK, + I2S0_RX_SD, + I2S0_RX_WS, + I2S0_RX_SCLK, CAM_INT, CAM_TRIG, ISP_DVP_VSYNC, @@ -677,12 +683,6 @@ }), .mio_pad_io ({ - IOD5, - IOD4, - IOD3, - IOD2, - IOD1, - IOD0, IOR13, IOR12, IOR11, @@ -745,6 +745,12 @@ manual_in_ast_misc, dio_in[DioSysrstCtrlAonFlashWpL], dio_in[DioSysrstCtrlAonEcRstL], + dio_in[DioI2s0TxSd], + dio_in[DioI2s0TxWs], + dio_in[DioI2s0TxSclk], + dio_in[DioI2s0RxSd], + dio_in[DioI2s0RxWs], + dio_in[DioI2s0RxSclk], dio_in[DioCamCtrlCamInt], dio_in[DioCamCtrlCamTrig], dio_in[DioIspWrapperSVsync], @@ -792,6 +798,12 @@ manual_out_ast_misc, dio_out[DioSysrstCtrlAonFlashWpL], dio_out[DioSysrstCtrlAonEcRstL], + dio_out[DioI2s0TxSd], + dio_out[DioI2s0TxWs], + dio_out[DioI2s0TxSclk], + dio_out[DioI2s0RxSd], + dio_out[DioI2s0RxWs], + dio_out[DioI2s0RxSclk], dio_out[DioCamCtrlCamInt], dio_out[DioCamCtrlCamTrig], dio_out[DioIspWrapperSVsync], @@ -839,6 +851,12 @@ manual_oe_ast_misc, dio_oe[DioSysrstCtrlAonFlashWpL], dio_oe[DioSysrstCtrlAonEcRstL], + dio_oe[DioI2s0TxSd], + dio_oe[DioI2s0TxWs], + dio_oe[DioI2s0TxSclk], + dio_oe[DioI2s0RxSd], + dio_oe[DioI2s0RxWs], + dio_oe[DioI2s0RxSclk], dio_oe[DioCamCtrlCamInt], dio_oe[DioCamCtrlCamTrig], dio_oe[DioIspWrapperSVsync], @@ -886,6 +904,12 @@ manual_attr_ast_misc, dio_attr[DioSysrstCtrlAonFlashWpL], dio_attr[DioSysrstCtrlAonEcRstL], + dio_attr[DioI2s0TxSd], + dio_attr[DioI2s0TxWs], + dio_attr[DioI2s0TxSclk], + dio_attr[DioI2s0RxSd], + dio_attr[DioI2s0RxWs], + dio_attr[DioI2s0RxSclk], dio_attr[DioCamCtrlCamInt], dio_attr[DioCamCtrlCamTrig], dio_attr[DioIspWrapperSVsync], @@ -930,11 +954,11 @@ manual_attr_por_n }), - .mio_in_o (mio_in[52:0]), - .mio_out_i (mio_out[52:0]), - .mio_oe_i (mio_oe[52:0]), - .mio_attr_i (mio_attr[52:0]), - .mio_in_raw_o (mio_in_raw[52:0]) + .mio_in_o (mio_in[46:0]), + .mio_out_i (mio_out[46:0]), + .mio_oe_i (mio_oe[46:0]), + .mio_attr_i (mio_attr[46:0]), + .mio_in_raw_o (mio_in_raw[46:0]) );
diff --git a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv index 67f728b..c1f38fb 100644 --- a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv +++ b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
@@ -55,6 +55,12 @@ inout ISP_DVP_VSYNC, // Dedicated Pad for isp_wrapper_s_vsync inout CAM_TRIG, // Dedicated Pad for cam_ctrl_cam_trig inout CAM_INT, // Dedicated Pad for cam_ctrl_cam_int + inout I2S0_RX_SCLK, // Dedicated Pad for i2s0_rx_sclk + inout I2S0_RX_WS, // Dedicated Pad for i2s0_rx_ws + inout I2S0_RX_SD, // Dedicated Pad for i2s0_rx_sd + inout I2S0_TX_SCLK, // Dedicated Pad for i2s0_tx_sclk + inout I2S0_TX_WS, // Dedicated Pad for i2s0_tx_ws + inout I2S0_TX_SD, // Dedicated Pad for i2s0_tx_sd inout IOR8, // Dedicated Pad for sysrst_ctrl_aon_ec_rst_l inout IOR9, // Dedicated Pad for sysrst_ctrl_aon_flash_wp_l inout IO_CLK, // Manual Pad @@ -111,13 +117,7 @@ inout IOR10, // MIO Pad 43 inout IOR11, // MIO Pad 44 inout IOR12, // MIO Pad 45 - inout IOR13, // MIO Pad 46 - inout IOD0, // MIO Pad 47 - inout IOD1, // MIO Pad 48 - inout IOD2, // MIO Pad 49 - inout IOD3, // MIO Pad 50 - inout IOD4, // MIO Pad 51 - inout IOD5 // MIO Pad 52 + inout IOR13 // MIO Pad 46 ); import top_matcha_pkg::*; @@ -154,11 +154,17 @@ usb_sense_idx: MioInUsbdevSense, // Pad types for attribute WARL behavior dio_pad_type: { + BidirStd, // DIO i2s0_tx_sd + BidirStd, // DIO i2s0_tx_ws + BidirStd, // DIO i2s0_tx_sclk + BidirStd, // DIO i2s0_rx_ws + BidirStd, // DIO i2s0_rx_sclk BidirStd, // DIO cam_ctrl_cam_trig BidirStd, // DIO spi_host2_csb BidirStd, // DIO spi_host2_sck BidirStd, // DIO spi_host0_csb BidirStd, // DIO spi_host0_sck + BidirStd, // DIO i2s0_rx_sd InputStd, // DIO cam_ctrl_cam_int InputStd, // DIO isp_wrapper_s_vsync InputStd, // DIO isp_wrapper_s_hsync @@ -193,12 +199,6 @@ BidirStd // DIO usbdev_usb_dp }, mio_pad_type: { - BidirStd, // MIO Pad 52 - BidirStd, // MIO Pad 51 - BidirStd, // MIO Pad 50 - BidirStd, // MIO Pad 49 - BidirStd, // MIO Pad 48 - BidirStd, // MIO Pad 47 BidirOd, // MIO Pad 46 BidirOd, // MIO Pad 45 BidirOd, // MIO Pad 44 @@ -309,8 +309,8 @@ padring #( // Padring specific counts may differ from pinmux config due // to custom, stubbed or added pads. - .NDioPads(44), - .NMioPads(53), + .NDioPads(50), + .NMioPads(47), .DioPadType ({ BidirStd, // IO_TRIGGER BidirStd, // IO_CLKOUT @@ -320,6 +320,12 @@ AnalogIn0, // IO_CLK BidirOd, // IOR9 BidirOd, // IOR8 + BidirStd, // I2S0_TX_SD + BidirStd, // I2S0_TX_WS + BidirStd, // I2S0_TX_SCLK + BidirStd, // I2S0_RX_SD + BidirStd, // I2S0_RX_WS + BidirStd, // I2S0_RX_SCLK InputStd, // CAM_INT BidirStd, // CAM_TRIG InputStd, // ISP_DVP_VSYNC @@ -358,12 +364,6 @@ InputStd // POR_N }), .MioPadType ({ - BidirStd, // IOD5 - BidirStd, // IOD4 - BidirStd, // IOD3 - BidirStd, // IOD2 - BidirStd, // IOD1 - BidirStd, // IOD0 BidirOd, // IOR13 BidirOd, // IOR12 BidirOd, // IOR11 @@ -427,6 +427,12 @@ IO_CLK, IOR9, IOR8, + I2S0_TX_SD, + I2S0_TX_WS, + I2S0_TX_SCLK, + I2S0_RX_SD, + I2S0_RX_WS, + I2S0_RX_SCLK, CAM_INT, CAM_TRIG, ISP_DVP_VSYNC, @@ -466,12 +472,6 @@ }), .mio_pad_io ({ - IOD5, - IOD4, - IOD3, - IOD2, - IOD1, - IOD0, IOR13, IOR12, IOR11, @@ -539,6 +539,12 @@ manual_in_io_clk, dio_in[DioSysrstCtrlAonFlashWpL], dio_in[DioSysrstCtrlAonEcRstL], + dio_in[DioI2s0TxSd], + dio_in[DioI2s0TxWs], + dio_in[DioI2s0TxSclk], + dio_in[DioI2s0RxSd], + dio_in[DioI2s0RxWs], + dio_in[DioI2s0RxSclk], dio_in[DioCamCtrlCamInt], dio_in[DioCamCtrlCamTrig], dio_in[DioIspWrapperSVsync], @@ -585,6 +591,12 @@ manual_out_io_clk, dio_out[DioSysrstCtrlAonFlashWpL], dio_out[DioSysrstCtrlAonEcRstL], + dio_out[DioI2s0TxSd], + dio_out[DioI2s0TxWs], + dio_out[DioI2s0TxSclk], + dio_out[DioI2s0RxSd], + dio_out[DioI2s0RxWs], + dio_out[DioI2s0RxSclk], dio_out[DioCamCtrlCamInt], dio_out[DioCamCtrlCamTrig], dio_out[DioIspWrapperSVsync], @@ -631,6 +643,12 @@ manual_oe_io_clk, dio_oe[DioSysrstCtrlAonFlashWpL], dio_oe[DioSysrstCtrlAonEcRstL], + dio_oe[DioI2s0TxSd], + dio_oe[DioI2s0TxWs], + dio_oe[DioI2s0TxSclk], + dio_oe[DioI2s0RxSd], + dio_oe[DioI2s0RxWs], + dio_oe[DioI2s0RxSclk], dio_oe[DioCamCtrlCamInt], dio_oe[DioCamCtrlCamTrig], dio_oe[DioIspWrapperSVsync], @@ -677,6 +695,12 @@ manual_attr_io_clk, dio_attr[DioSysrstCtrlAonFlashWpL], dio_attr[DioSysrstCtrlAonEcRstL], + dio_attr[DioI2s0TxSd], + dio_attr[DioI2s0TxWs], + dio_attr[DioI2s0TxSclk], + dio_attr[DioI2s0RxSd], + dio_attr[DioI2s0RxWs], + dio_attr[DioI2s0RxSclk], dio_attr[DioCamCtrlCamInt], dio_attr[DioCamCtrlCamTrig], dio_attr[DioIspWrapperSVsync], @@ -715,11 +739,11 @@ manual_attr_por_n }), - .mio_in_o (mio_in[52:0]), - .mio_out_i (mio_out[52:0]), - .mio_oe_i (mio_oe[52:0]), - .mio_attr_i (mio_attr[52:0]), - .mio_in_raw_o (mio_in_raw[52:0]) + .mio_in_o (mio_in[46:0]), + .mio_out_i (mio_out[46:0]), + .mio_oe_i (mio_oe[46:0]), + .mio_attr_i (mio_attr[46:0]), + .mio_in_raw_o (mio_in_raw[46:0]) );
diff --git a/hw/top_matcha/rtl/autogen/top_matcha.sv b/hw/top_matcha/rtl/autogen/top_matcha.sv index 4050556..025633c 100644 --- a/hw/top_matcha/rtl/autogen/top_matcha.sv +++ b/hw/top_matcha/rtl/autogen/top_matcha.sv
@@ -162,13 +162,13 @@ parameter int RvCoreIbexSmcASIDWidth = 9 ) ( // Multiplexed I/O - input [52:0] mio_in_i, - output logic [52:0] mio_out_o, - output logic [52:0] mio_oe_o, + input [46:0] mio_in_i, + output logic [46:0] mio_out_o, + output logic [46:0] mio_oe_o, // Dedicated I/O - input [36:0] dio_in_i, - output logic [36:0] dio_out_o, - output logic [36:0] dio_oe_o, + input [42:0] dio_in_i, + output logic [42:0] dio_out_o, + output logic [42:0] dio_oe_o, // pad attributes to padring output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o, @@ -259,12 +259,12 @@ import top_matcha_rnd_cnst_pkg::*; // Signals - logic [57:0] mio_p2d; - logic [79:0] mio_d2p; - logic [79:0] mio_en_d2p; - logic [36:0] dio_p2d; - logic [36:0] dio_d2p; - logic [36:0] dio_en_d2p; + logic [56:0] mio_p2d; + logic [74:0] mio_d2p; + logic [74:0] mio_en_d2p; + logic [42:0] dio_p2d; + logic [42:0] dio_d2p; + logic [42:0] dio_en_d2p; // uart0 logic cio_uart0_rx_p2d; logic cio_uart0_tx_d2p; @@ -4082,7 +4082,6 @@ assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck]; assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms]; assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi]; - assign cio_i2s0_rx_sd_p2d = mio_p2d[MioInI2s0RxSd]; assign cio_sysrst_ctrl_aon_ac_present_p2d = mio_p2d[MioInSysrstCtrlAonAcPresent]; assign cio_sysrst_ctrl_aon_key0_in_p2d = mio_p2d[MioInSysrstCtrlAonKey0In]; assign cio_sysrst_ctrl_aon_key1_in_p2d = mio_p2d[MioInSysrstCtrlAonKey1In]; @@ -4161,11 +4160,6 @@ assign mio_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_d2p[4]; assign mio_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_d2p[5]; assign mio_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_d2p[0]; - assign mio_d2p[MioOutI2s0RxSclk] = cio_i2s0_rx_sclk_d2p; - assign mio_d2p[MioOutI2s0RxWs] = cio_i2s0_rx_ws_d2p; - assign mio_d2p[MioOutI2s0TxSclk] = cio_i2s0_tx_sclk_d2p; - assign mio_d2p[MioOutI2s0TxWs] = cio_i2s0_tx_ws_d2p; - assign mio_d2p[MioOutI2s0TxSd] = cio_i2s0_tx_sd_d2p; assign mio_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_d2p; assign mio_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_d2p; assign mio_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_d2p; @@ -4243,11 +4237,6 @@ assign mio_en_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_en_d2p[4]; assign mio_en_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_en_d2p[5]; assign mio_en_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_en_d2p[0]; - assign mio_en_d2p[MioOutI2s0RxSclk] = cio_i2s0_rx_sclk_en_d2p; - assign mio_en_d2p[MioOutI2s0RxWs] = cio_i2s0_rx_ws_en_d2p; - assign mio_en_d2p[MioOutI2s0TxSclk] = cio_i2s0_tx_sclk_en_d2p; - assign mio_en_d2p[MioOutI2s0TxWs] = cio_i2s0_tx_ws_en_d2p; - assign mio_en_d2p[MioOutI2s0TxSd] = cio_i2s0_tx_sd_en_d2p; assign mio_en_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_en_d2p; assign mio_en_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_en_d2p; assign mio_en_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_en_d2p; @@ -4256,7 +4245,7 @@ assign mio_en_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_en_d2p; // All dedicated inputs - logic [36:0] unused_dio_p2d; + logic [42:0] unused_dio_p2d; assign unused_dio_p2d = dio_p2d; assign cio_usbdev_usb_dp_p2d = dio_p2d[DioUsbdevUsbDp]; assign cio_usbdev_usb_dn_p2d = dio_p2d[DioUsbdevUsbDn]; @@ -4290,6 +4279,7 @@ assign cio_isp_wrapper_s_hsync_p2d = dio_p2d[DioIspWrapperSHsync]; assign cio_isp_wrapper_s_vsync_p2d = dio_p2d[DioIspWrapperSVsync]; assign cio_cam_ctrl_cam_int_p2d = dio_p2d[DioCamCtrlCamInt]; + assign cio_i2s0_rx_sd_p2d = dio_p2d[DioI2s0RxSd]; // All dedicated outputs assign dio_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_d2p; @@ -4324,11 +4314,17 @@ assign dio_d2p[DioIspWrapperSHsync] = 1'b0; assign dio_d2p[DioIspWrapperSVsync] = 1'b0; assign dio_d2p[DioCamCtrlCamInt] = 1'b0; + assign dio_d2p[DioI2s0RxSd] = 1'b0; assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p; assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p; assign dio_d2p[DioSpiHost2Sck] = cio_spi_host2_sck_d2p; assign dio_d2p[DioSpiHost2Csb] = cio_spi_host2_csb_d2p; assign dio_d2p[DioCamCtrlCamTrig] = cio_cam_ctrl_cam_trig_d2p; + assign dio_d2p[DioI2s0RxSclk] = cio_i2s0_rx_sclk_d2p; + assign dio_d2p[DioI2s0RxWs] = cio_i2s0_rx_ws_d2p; + assign dio_d2p[DioI2s0TxSclk] = cio_i2s0_tx_sclk_d2p; + assign dio_d2p[DioI2s0TxWs] = cio_i2s0_tx_ws_d2p; + assign dio_d2p[DioI2s0TxSd] = cio_i2s0_tx_sd_d2p; // All dedicated output enables assign dio_en_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_en_d2p; @@ -4363,11 +4359,17 @@ assign dio_en_d2p[DioIspWrapperSHsync] = 1'b0; assign dio_en_d2p[DioIspWrapperSVsync] = 1'b0; assign dio_en_d2p[DioCamCtrlCamInt] = 1'b0; + assign dio_en_d2p[DioI2s0RxSd] = 1'b0; assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p; assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p; assign dio_en_d2p[DioSpiHost2Sck] = cio_spi_host2_sck_en_d2p; assign dio_en_d2p[DioSpiHost2Csb] = cio_spi_host2_csb_en_d2p; assign dio_en_d2p[DioCamCtrlCamTrig] = cio_cam_ctrl_cam_trig_en_d2p; + assign dio_en_d2p[DioI2s0RxSclk] = cio_i2s0_rx_sclk_en_d2p; + assign dio_en_d2p[DioI2s0RxWs] = cio_i2s0_rx_ws_en_d2p; + assign dio_en_d2p[DioI2s0TxSclk] = cio_i2s0_tx_sclk_en_d2p; + assign dio_en_d2p[DioI2s0TxWs] = cio_i2s0_tx_ws_en_d2p; + assign dio_en_d2p[DioI2s0TxSd] = cio_i2s0_tx_sd_en_d2p; // make sure scanmode_i is never X (including during reset)
diff --git a/hw/top_matcha/rtl/autogen/top_matcha_pkg.sv b/hw/top_matcha/rtl/autogen/top_matcha_pkg.sv index 981e492..e1b5f89 100644 --- a/hw/top_matcha/rtl/autogen/top_matcha_pkg.sv +++ b/hw/top_matcha/rtl/autogen/top_matcha_pkg.sv
@@ -936,15 +936,14 @@ MioInFlashCtrlTck = 47, MioInFlashCtrlTms = 48, MioInFlashCtrlTdi = 49, - MioInI2s0RxSd = 50, - MioInSysrstCtrlAonAcPresent = 51, - MioInSysrstCtrlAonKey0In = 52, - MioInSysrstCtrlAonKey1In = 53, - MioInSysrstCtrlAonKey2In = 54, - MioInSysrstCtrlAonPwrbIn = 55, - MioInSysrstCtrlAonLidOpen = 56, - MioInUsbdevSense = 57, - MioInCount = 58 + MioInSysrstCtrlAonAcPresent = 50, + MioInSysrstCtrlAonKey0In = 51, + MioInSysrstCtrlAonKey1In = 52, + MioInSysrstCtrlAonKey2In = 53, + MioInSysrstCtrlAonPwrbIn = 54, + MioInSysrstCtrlAonLidOpen = 55, + MioInUsbdevSense = 56, + MioInCount = 57 } mio_in_e; typedef enum { @@ -1017,18 +1016,13 @@ MioOutPwmAonPwm4 = 66, MioOutPwmAonPwm5 = 67, MioOutOtpCtrlTest0 = 68, - MioOutI2s0RxSclk = 69, - MioOutI2s0RxWs = 70, - MioOutI2s0TxSclk = 71, - MioOutI2s0TxWs = 72, - MioOutI2s0TxSd = 73, - MioOutSysrstCtrlAonBatDisable = 74, - MioOutSysrstCtrlAonKey0Out = 75, - MioOutSysrstCtrlAonKey1Out = 76, - MioOutSysrstCtrlAonKey2Out = 77, - MioOutSysrstCtrlAonPwrbOut = 78, - MioOutSysrstCtrlAonZ3Wakeup = 79, - MioOutCount = 80 + MioOutSysrstCtrlAonBatDisable = 69, + MioOutSysrstCtrlAonKey0Out = 70, + MioOutSysrstCtrlAonKey1Out = 71, + MioOutSysrstCtrlAonKey2Out = 72, + MioOutSysrstCtrlAonPwrbOut = 73, + MioOutSysrstCtrlAonZ3Wakeup = 74, + MioOutCount = 75 } mio_out_e; // Enumeration for DIO signals, used on both the top and chip-levels. @@ -1065,12 +1059,18 @@ DioIspWrapperSHsync = 29, DioIspWrapperSVsync = 30, DioCamCtrlCamInt = 31, - DioSpiHost0Sck = 32, - DioSpiHost0Csb = 33, - DioSpiHost2Sck = 34, - DioSpiHost2Csb = 35, - DioCamCtrlCamTrig = 36, - DioCount = 37 + DioI2s0RxSd = 32, + DioSpiHost0Sck = 33, + DioSpiHost0Csb = 34, + DioSpiHost2Sck = 35, + DioSpiHost2Csb = 36, + DioCamCtrlCamTrig = 37, + DioI2s0RxSclk = 38, + DioI2s0RxWs = 39, + DioI2s0TxSclk = 40, + DioI2s0TxWs = 41, + DioI2s0TxSd = 42, + DioCount = 43 } dio_e; // Enumeration for the types of pads. @@ -1130,12 +1130,6 @@ MioPadIor11 = 44, MioPadIor12 = 45, MioPadIor13 = 46, - MioPadIod0 = 47, - MioPadIod1 = 48, - MioPadIod2 = 49, - MioPadIod3 = 50, - MioPadIod4 = 51, - MioPadIod5 = 52, MioPadCount } mio_pad_e; @@ -1182,8 +1176,14 @@ DioPadIspDvpVsync = 39, DioPadCamTrig = 40, DioPadCamInt = 41, - DioPadIor8 = 42, - DioPadIor9 = 43, + DioPadI2s0RxSclk = 42, + DioPadI2s0RxWs = 43, + DioPadI2s0RxSd = 44, + DioPadI2s0TxSclk = 45, + DioPadI2s0TxWs = 46, + DioPadI2s0TxSd = 47, + DioPadIor8 = 48, + DioPadIor9 = 49, DioPadCount } dio_pad_e;
diff --git a/hw/top_matcha/rtl/chip_matcha_verilator.sv b/hw/top_matcha/rtl/chip_matcha_verilator.sv index 6af01d1..f51e485 100644 --- a/hw/top_matcha/rtl/chip_matcha_verilator.sv +++ b/hw/top_matcha/rtl/chip_matcha_verilator.sv
@@ -73,6 +73,8 @@ dio_in[DioSpiDeviceSd0] = cio_spi_device_sdi_p2d_i; dio_in[DioUsbdevUsbDp] = cio_usbdev_dp_p2d_i; dio_in[DioUsbdevUsbDn] = cio_usbdev_dn_p2d_i; + + dio_in[DioI2s0RxSd] = cio_i2s_rx_sd_p2d_i; end // USB @@ -101,6 +103,12 @@ assign cio_spi_device_sdo_d2p_o = dio_out[DioSpiDeviceSd1]; assign cio_spi_device_sdo_en_d2p_o = dio_oe[DioSpiDeviceSd1]; + assign cio_i2s_rx_sclk_d2p_o = dio_out[DioI2s0RxSclk]; + assign cio_i2s_rx_ws_d2p_o = dio_out[DioI2s0RxWs]; + assign cio_i2s_tx_sclk_d2p_o = dio_out[DioI2s0TxSclk]; + assign cio_i2s_tx_sd_d2p_o = dio_out[DioI2s0TxSd]; + assign cio_i2s_tx_ws_d2p_o = dio_out[DioI2s0TxWs]; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; @@ -125,9 +133,6 @@ // UART RX mio_in[MioPadIoc3] = cio_uart_rx_p2d_i; mio_in[MioPadIoc10] = cio_uart_smc_rx_p2d_i; - - //I2S - // mio_in[MioPadIod1] = cio_i2s_rx_sd_p2d_i; end // Generic GPIOs @@ -162,18 +167,6 @@ assign cio_uart_smc_tx_d2p_o = mio_out[MioPadIoc11]; assign cio_uart_smc_tx_en_d2p_o = mio_oe[MioPadIoc11]; - // I2S - assign cio_i2s_rx_sclk_d2p_o = 0; - assign cio_i2s_rx_ws_d2p_o = 0; - assign cio_i2s_tx_sclk_d2p_o = 0; - assign cio_i2s_tx_sd_d2p_o = 0; - assign cio_i2s_tx_ws_d2p_o = 0; - // assign cio_i2s_rx_sclk_d2p_o = mio_out[MioPadIod0]; - // assign cio_i2s_rx_ws_d2p_o = mio_out[MioPadIod2]; - // assign cio_i2s_tx_sclk_d2p_o = mio_out[MioPadIod3]; - // assign cio_i2s_tx_sd_d2p_o = mio_out[MioPadIod4]; - // assign cio_i2s_tx_ws_d2p_o = mio_out[MioPadIod5]; - // Note: we're collecting the `pull_en` and `pull_select` signals together // so that the GPIO DPI functions can simulate weak and strong GPIO // inputs. The `cio_gpio_pull_en_o` and `cio_gpio_pull_select_o` bit
diff --git a/hw/top_matcha/sw/autogen/top_matcha.h b/hw/top_matcha/sw/autogen/top_matcha.h index fa639f3..6b2f7a3 100644 --- a/hw/top_matcha/sw/autogen/top_matcha.h +++ b/hw/top_matcha/sw/autogen/top_matcha.h
@@ -1785,8 +1785,8 @@ // PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} // 0 and 1 are tied to value 0 and 1 -#define NUM_MIO_PADS 53 -#define NUM_DIO_PADS 37 +#define NUM_MIO_PADS 47 +#define NUM_DIO_PADS 43 #define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3 @@ -1844,15 +1844,14 @@ kTopMatchaPinmuxPeripheralInFlashCtrlTck = 47, /**< Peripheral Input 47 */ kTopMatchaPinmuxPeripheralInFlashCtrlTms = 48, /**< Peripheral Input 48 */ kTopMatchaPinmuxPeripheralInFlashCtrlTdi = 49, /**< Peripheral Input 49 */ - kTopMatchaPinmuxPeripheralInI2s0RxSd = 50, /**< Peripheral Input 50 */ - kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent = 51, /**< Peripheral Input 51 */ - kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In = 52, /**< Peripheral Input 52 */ - kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In = 53, /**< Peripheral Input 53 */ - kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey2In = 54, /**< Peripheral Input 54 */ - kTopMatchaPinmuxPeripheralInSysrstCtrlAonPwrbIn = 55, /**< Peripheral Input 55 */ - kTopMatchaPinmuxPeripheralInSysrstCtrlAonLidOpen = 56, /**< Peripheral Input 56 */ - kTopMatchaPinmuxPeripheralInUsbdevSense = 57, /**< Peripheral Input 57 */ - kTopMatchaPinmuxPeripheralInLast = 57, /**< \internal Last valid peripheral input */ + kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent = 50, /**< Peripheral Input 50 */ + kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In = 51, /**< Peripheral Input 51 */ + kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In = 52, /**< Peripheral Input 52 */ + kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey2In = 53, /**< Peripheral Input 53 */ + kTopMatchaPinmuxPeripheralInSysrstCtrlAonPwrbIn = 54, /**< Peripheral Input 54 */ + kTopMatchaPinmuxPeripheralInSysrstCtrlAonLidOpen = 55, /**< Peripheral Input 55 */ + kTopMatchaPinmuxPeripheralInUsbdevSense = 56, /**< Peripheral Input 56 */ + kTopMatchaPinmuxPeripheralInLast = 56, /**< \internal Last valid peripheral input */ } top_matcha_pinmux_peripheral_in_t; /** @@ -1908,13 +1907,7 @@ kTopMatchaPinmuxInselIor11 = 46, /**< MIO Pad 44 */ kTopMatchaPinmuxInselIor12 = 47, /**< MIO Pad 45 */ kTopMatchaPinmuxInselIor13 = 48, /**< MIO Pad 46 */ - kTopMatchaPinmuxInselIod0 = 49, /**< MIO Pad 47 */ - kTopMatchaPinmuxInselIod1 = 50, /**< MIO Pad 48 */ - kTopMatchaPinmuxInselIod2 = 51, /**< MIO Pad 49 */ - kTopMatchaPinmuxInselIod3 = 52, /**< MIO Pad 50 */ - kTopMatchaPinmuxInselIod4 = 53, /**< MIO Pad 51 */ - kTopMatchaPinmuxInselIod5 = 54, /**< MIO Pad 52 */ - kTopMatchaPinmuxInselLast = 54, /**< \internal Last valid insel value */ + kTopMatchaPinmuxInselLast = 48, /**< \internal Last valid insel value */ } top_matcha_pinmux_insel_t; /** @@ -1968,13 +1961,7 @@ kTopMatchaPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */ kTopMatchaPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */ kTopMatchaPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */ - kTopMatchaPinmuxMioOutIod0 = 47, /**< MIO Pad 47 */ - kTopMatchaPinmuxMioOutIod1 = 48, /**< MIO Pad 48 */ - kTopMatchaPinmuxMioOutIod2 = 49, /**< MIO Pad 49 */ - kTopMatchaPinmuxMioOutIod3 = 50, /**< MIO Pad 50 */ - kTopMatchaPinmuxMioOutIod4 = 51, /**< MIO Pad 51 */ - kTopMatchaPinmuxMioOutIod5 = 52, /**< MIO Pad 52 */ - kTopMatchaPinmuxMioOutLast = 52, /**< \internal Last valid mio output */ + kTopMatchaPinmuxMioOutLast = 46, /**< \internal Last valid mio output */ } top_matcha_pinmux_mio_out_t; /** @@ -2053,18 +2040,13 @@ kTopMatchaPinmuxOutselPwmAonPwm4 = 69, /**< Peripheral Output 66 */ kTopMatchaPinmuxOutselPwmAonPwm5 = 70, /**< Peripheral Output 67 */ kTopMatchaPinmuxOutselOtpCtrlTest0 = 71, /**< Peripheral Output 68 */ - kTopMatchaPinmuxOutselI2s0RxSclk = 72, /**< Peripheral Output 69 */ - kTopMatchaPinmuxOutselI2s0RxWs = 73, /**< Peripheral Output 70 */ - kTopMatchaPinmuxOutselI2s0TxSclk = 74, /**< Peripheral Output 71 */ - kTopMatchaPinmuxOutselI2s0TxWs = 75, /**< Peripheral Output 72 */ - kTopMatchaPinmuxOutselI2s0TxSd = 76, /**< Peripheral Output 73 */ - kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable = 77, /**< Peripheral Output 74 */ - kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out = 78, /**< Peripheral Output 75 */ - kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out = 79, /**< Peripheral Output 76 */ - kTopMatchaPinmuxOutselSysrstCtrlAonKey2Out = 80, /**< Peripheral Output 77 */ - kTopMatchaPinmuxOutselSysrstCtrlAonPwrbOut = 81, /**< Peripheral Output 78 */ - kTopMatchaPinmuxOutselSysrstCtrlAonZ3Wakeup = 82, /**< Peripheral Output 79 */ - kTopMatchaPinmuxOutselLast = 82, /**< \internal Last valid outsel value */ + kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable = 72, /**< Peripheral Output 69 */ + kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out = 73, /**< Peripheral Output 70 */ + kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out = 74, /**< Peripheral Output 71 */ + kTopMatchaPinmuxOutselSysrstCtrlAonKey2Out = 75, /**< Peripheral Output 72 */ + kTopMatchaPinmuxOutselSysrstCtrlAonPwrbOut = 76, /**< Peripheral Output 73 */ + kTopMatchaPinmuxOutselSysrstCtrlAonZ3Wakeup = 77, /**< Peripheral Output 74 */ + kTopMatchaPinmuxOutselLast = 77, /**< \internal Last valid outsel value */ } top_matcha_pinmux_outsel_t; /** @@ -2103,12 +2085,18 @@ kTopMatchaDirectPadsIspWrapperSHsync = 29, /**< */ kTopMatchaDirectPadsIspWrapperSVsync = 30, /**< */ kTopMatchaDirectPadsCamCtrlCamInt = 31, /**< */ - kTopMatchaDirectPadsSpiHost0Sck = 32, /**< */ - kTopMatchaDirectPadsSpiHost0Csb = 33, /**< */ - kTopMatchaDirectPadsSpiHost2Sck = 34, /**< */ - kTopMatchaDirectPadsSpiHost2Csb = 35, /**< */ - kTopMatchaDirectPadsCamCtrlCamTrig = 36, /**< */ - kTopMatchaDirectPadsLast = 36, /**< \internal Last valid direct pad */ + kTopMatchaDirectPadsI2s0RxSd = 32, /**< */ + kTopMatchaDirectPadsSpiHost0Sck = 33, /**< */ + kTopMatchaDirectPadsSpiHost0Csb = 34, /**< */ + kTopMatchaDirectPadsSpiHost2Sck = 35, /**< */ + kTopMatchaDirectPadsSpiHost2Csb = 36, /**< */ + kTopMatchaDirectPadsCamCtrlCamTrig = 37, /**< */ + kTopMatchaDirectPadsI2s0RxSclk = 38, /**< */ + kTopMatchaDirectPadsI2s0RxWs = 39, /**< */ + kTopMatchaDirectPadsI2s0TxSclk = 40, /**< */ + kTopMatchaDirectPadsI2s0TxWs = 41, /**< */ + kTopMatchaDirectPadsI2s0TxSd = 42, /**< */ + kTopMatchaDirectPadsLast = 42, /**< \internal Last valid direct pad */ } top_matcha_direct_pads_t; /** @@ -2162,13 +2150,7 @@ kTopMatchaMuxedPadsIor11 = 44, /**< */ kTopMatchaMuxedPadsIor12 = 45, /**< */ kTopMatchaMuxedPadsIor13 = 46, /**< */ - kTopMatchaMuxedPadsIod0 = 47, /**< */ - kTopMatchaMuxedPadsIod1 = 48, /**< */ - kTopMatchaMuxedPadsIod2 = 49, /**< */ - kTopMatchaMuxedPadsIod3 = 50, /**< */ - kTopMatchaMuxedPadsIod4 = 51, /**< */ - kTopMatchaMuxedPadsIod5 = 52, /**< */ - kTopMatchaMuxedPadsLast = 52, /**< \internal Last valid muxed pad */ + kTopMatchaMuxedPadsLast = 46, /**< \internal Last valid muxed pad */ } top_matcha_muxed_pads_t; /**
diff --git a/sw/device/examples/hello_world/BUILD b/sw/device/examples/hello_world/BUILD index 37d6e3f..fa9fce8 100644 --- a/sw/device/examples/hello_world/BUILD +++ b/sw/device/examples/hello_world/BUILD
@@ -25,13 +25,13 @@ target_compatible_with = [OPENTITAN_CPU], deps = [ "//hw/top_matcha/sw/autogen:top_matcha", - "//sw/device/lib/dif:pinmux", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing/test_framework:ottf_start", "@lowrisc_opentitan//sw/device/examples:demos", "@lowrisc_opentitan//sw/device/lib/base:mmio", "@lowrisc_opentitan//sw/device/lib/crt", "@lowrisc_opentitan//sw/device/lib/dif:gpio", + "@lowrisc_opentitan//sw/device/lib/dif:pinmux", "@lowrisc_opentitan//sw/device/lib/dif:spi_device", "@lowrisc_opentitan//sw/device/lib/dif:uart", "@lowrisc_opentitan//sw/device/lib/runtime:hart",
diff --git a/sw/device/examples/i2s_record_playback/i2s_record_playback_sec.c b/sw/device/examples/i2s_record_playback/i2s_record_playback_sec.c index f9aeabc..c406e81 100644 --- a/sw/device/examples/i2s_record_playback/i2s_record_playback_sec.c +++ b/sw/device/examples/i2s_record_playback/i2s_record_playback_sec.c
@@ -83,19 +83,6 @@ } CHECK_DIF_OK(dif_smc_ctrl_set_en(&smc_ctrl)); - // Mux I2S to IOD ports - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod0, - kTopMatchaPinmuxOutselI2s0RxSclk)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod1, - kTopMatchaPinmuxOutselI2s0RxWs)); - CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInI2s0RxSd, - kTopMatchaPinmuxInselIod2)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod3, - kTopMatchaPinmuxOutselI2s0TxSclk)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod4, - kTopMatchaPinmuxOutselI2s0TxWs)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod5, - kTopMatchaPinmuxOutselI2s0TxSd)); // Bind switch on IOR5 to GPIO0 and configure interrupts. CHECK_DIF_OK(dif_rv_plic_init( mmio_region_from_addr(TOP_MATCHA_RV_PLIC_BASE_ADDR), &plic));
diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD index 17b76d8..42c11ff 100644 --- a/sw/device/lib/testing/BUILD +++ b/sw/device/lib/testing/BUILD
@@ -13,10 +13,10 @@ target_compatible_with = [OPENTITAN_CPU], deps = [ "//hw/top_matcha/sw/autogen:top_matcha", - "//sw/device/lib/dif:pinmux", "//sw/device/lib/arch:device", "@lowrisc_opentitan//sw/device/lib/dif:base", "@lowrisc_opentitan//sw/device/lib/dif:gpio", + "@lowrisc_opentitan//sw/device/lib/dif:pinmux", "@lowrisc_opentitan//sw/device/lib/runtime:hart", "@lowrisc_opentitan//sw/device/lib/testing/test_framework:check", ],
diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD index 4045fbb..3f5c619 100644 --- a/sw/device/lib/testing/test_rom/BUILD +++ b/sw/device/lib/testing/test_rom/BUILD
@@ -46,7 +46,6 @@ "//hw/top_matcha/ip/flash_ctrl/data/autogen:flash_ctrl_regs", "//hw/top_matcha/ip/sensor_ctrl/data:sensor_ctrl_regs", "//hw/top_matcha/sw/autogen:top_matcha", - "//sw/device/lib/dif:pinmux", "//sw/device/lib/testing:pinmux_testutils", "@lowrisc_opentitan//hw/ip/csrng/data:csrng_regs", "@lowrisc_opentitan//hw/ip/edn/data:edn_regs", @@ -62,6 +61,7 @@ "@lowrisc_opentitan//sw/device/lib/dif:flash_ctrl", "@lowrisc_opentitan//sw/device/lib/dif:gpio", "@lowrisc_opentitan//sw/device/lib/dif:hmac", + "@lowrisc_opentitan//sw/device/lib/dif:pinmux", "@lowrisc_opentitan//sw/device/lib/dif:rstmgr", "@lowrisc_opentitan//sw/device/lib/dif:rv_core_ibex", "@lowrisc_opentitan//sw/device/lib/dif:spi_device",
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 7d398b3..ebd5f27 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD
@@ -407,11 +407,11 @@ deps = [ "//hw/top_matcha/sw/autogen:top_matcha", "//sw/device/lib/arch:device", - "//sw/device/lib/dif:pinmux", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing/test_framework:test_util", "@lowrisc_opentitan//sw/device/lib/base:mmio", "@lowrisc_opentitan//sw/device/lib/crt", + "@lowrisc_opentitan//sw/device/lib/dif:pinmux", "@lowrisc_opentitan//sw/device/lib/dif:uart", "@lowrisc_opentitan//sw/device/lib/runtime:hart", "@lowrisc_opentitan//sw/device/lib/runtime:irq",
diff --git a/sw/device/tests/simple_sec.c b/sw/device/tests/simple_sec.c index 2e05928..85ce450 100644 --- a/sw/device/tests/simple_sec.c +++ b/sw/device/tests/simple_sec.c
@@ -7,7 +7,6 @@ #include "hw/top_matcha/sw/autogen/top_matcha.h" #include "sw/device/lib/arch/device.h" -#include "sw/device/lib/dif/dif_pinmux.h" #include "sw/device/lib/dif/dif_smc_ctrl.h" #include "sw/device/lib/dif/dif_uart.h" #include "sw/device/lib/runtime/hart.h" @@ -39,7 +38,6 @@ OTTF_DEFINE_TEST_CONFIG(); -static dif_pinmux_t pinmux; static dif_smc_ctrl_t smc_ctrl; static dif_uart_t uart; @@ -48,27 +46,6 @@ if (kDeviceType != kDeviceSimDV) { init_uart(TOP_MATCHA_UART0_BASE_ADDR, &uart); } - - CHECK_DIF_OK(dif_pinmux_init( - mmio_region_from_addr(TOP_MATCHA_PINMUX_AON_BASE_ADDR), &pinmux)); -#if defined(I2S_TX_TEST) - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod3, - kTopMatchaPinmuxOutselI2s0TxSclk)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod4, - kTopMatchaPinmuxOutselI2s0TxWs)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod5, - kTopMatchaPinmuxOutselI2s0TxSd)); -#endif - -#if defined(I2S_RX_TEST) - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod0, - kTopMatchaPinmuxOutselI2s0RxSclk)); - CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIod1, - kTopMatchaPinmuxOutselI2s0RxWs)); - CHECK_DIF_OK(dif_pinmux_input_select(&pinmux, kTopMatchaPinmuxPeripheralInI2s0RxSd, - kTopMatchaPinmuxInselIod2)); -#endif - #if defined(HAS_SMC_BIN) if (kDeviceType == kDeviceFpgaNexus) { memcpy((void*)TOP_MATCHA_RAM_SMC_BASE_ADDR, smc_bin, smc_bin_len);
diff --git a/sw/device/tests/smc/smc_i2s_tx_test.c b/sw/device/tests/smc/smc_i2s_tx_test.c index 7f14988..34b202b 100644 --- a/sw/device/tests/smc/smc_i2s_tx_test.c +++ b/sw/device/tests/smc/smc_i2s_tx_test.c
@@ -81,7 +81,6 @@ void _ottf_main(void) { uint32_t reg_val; test_status_set(kTestStatusInTest); - LOG_INFO("Start i2s tx test"); // Initialize the SMC UART to enable logging for non-DV simulation platforms. if (kDeviceType != kDeviceSimDV) {