[smc/hw] Check PTW misalignment on half-words

- Also ensure misaligned dPTW isn't altered by iPTW

Change-Id: I6ca16f2bccd242dcc841af8aeb12c7e5a72d5319

hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv

diff --git a/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv b/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv
index cac7e89..d9ef184 100644
--- a/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv
+++ b/hw/top_matcha/ip/smc/rtl/smc_load_store_unit.sv
@@ -370,9 +370,12 @@
   /////////////
 
   // check for misaligned accesses that need to be split into two word-aligned accesses
-  assign split_misaligned_access = ~ptw_spec_walk_i &
-      ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
-      ((lsu_type_i == 2'b01) && (data_offset == 2'b11));   // misaligned half-word access
+
+  // Because PTEs are aligned in memory, we squelch this signal to prevent the
+  // state machine from entering a bad state during a dPTW.
+  assign split_misaligned_access = ~(ptw_spec_walk_i && ~ptw_spec_iwalk_i) &&
+      (((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
+      ((lsu_type_i == 2'b01) && (data_offset == 2'b11)));   // misaligned half-word access
 
   // FSM
   always_comb begin
@@ -392,8 +395,6 @@
     perf_store_o        = 1'b0;
 
     unique case (ls_fsm_cs)
-    // TODO(hoangm): write more tests for increased coverage when we enter
-    // a PTW / exception while in an non-idle state
 
       IDLE: begin
         pmp_err_d = 1'b0;