blob: 504f2900b3b4c005512e6a635baf7eb4108b8d8a [file] [log] [blame]
/*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/examples/spi_to_host/spi_to_host_smc_fpga_nexus_bin_c.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_gpio.h"
#include "sw/device/lib/dif/dif_pinmux.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_smc_ctrl.h"
#include "sw/device/lib/dif/dif_spi_device.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/spi_to_host/spi_to_host.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/test_util.h"
OTTF_DEFINE_TEST_CONFIG();
static dif_smc_ctrl_t smc_ctrl;
static dif_pinmux_t pinmux;
static dif_uart_t uart;
static dif_rv_plic_t plic_sec;
static dif_gpio_t gpio;
static dif_spi_device_handle_t spi_device;
static spi_to_host_t spi_to_host;
#define kSwStrap0Pin (22)
void ottf_external_isr(void) {
dif_rv_plic_irq_id_t plic_irq_id;
CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_sec, kTopMatchaPlicTargetIbex0,
&plic_irq_id));
top_matcha_plic_peripheral_t peripheral_id =
top_matcha_plic_interrupt_for_peripheral[plic_irq_id];
switch (peripheral_id) {
case kTopMatchaPlicPeripheralSpiDevice: {
CHECK_DIF_OK(spi_to_host_irq_handler(&spi_to_host, plic_irq_id));
break;
}
default:
LOG_FATAL("Unhandled interrupt");
break;
}
CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_sec, kTopMatchaPlicTargetIbex0,
plic_irq_id));
}
void _ottf_main(void) {
test_status_set(kTestStatusInTest);
init_uart(TOP_MATCHA_UART0_BASE_ADDR, &uart);
LOG_INFO("Start spi_to_host");
CHECK_DIF_OK(
dif_gpio_init(mmio_region_from_addr(TOP_MATCHA_GPIO_BASE_ADDR), &gpio));
CHECK_DIF_OK(dif_spi_device_init_handle(
mmio_region_from_addr(TOP_MATCHA_SPI_DEVICE_BASE_ADDR), &spi_device));
CHECK_DIF_OK(
spi_to_host_init(&spi_to_host, &spi_device, &gpio, kSwStrap0Pin));
// Configure pinmux
CHECK_DIF_OK(dif_pinmux_init(
mmio_region_from_addr(TOP_MATCHA_PINMUX_AON_BASE_ADDR), &pinmux));
CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIoc0,
kTopMatchaPinmuxOutselGpioGpio22));
CHECK_DIF_OK(dif_pinmux_input_select(&pinmux,
kTopMatchaPinmuxPeripheralInGpioGpio22,
kTopMatchaPinmuxInselConstantZero));
CHECK_DIF_OK(dif_rv_plic_init(
mmio_region_from_addr(TOP_MATCHA_RV_PLIC_BASE_ADDR), &plic_sec));
CHECK_DIF_OK(
spi_to_host_irq_init(&spi_to_host, &plic_sec, kTopMatchaPlicTargetIbex0));
irq_global_ctrl(true);
irq_external_ctrl(true);
// Copy embedded binary to SMC RAM.
memcpy((void *)TOP_MATCHA_RAM_SMC_BASE_ADDR, smc_bin, smc_bin_len);
CHECK_DIF_OK(dif_smc_ctrl_init(
mmio_region_from_addr(TOP_MATCHA_SMC_CTRL_BASE_ADDR), &smc_ctrl));
CHECK_DIF_OK(dif_smc_ctrl_set_en(&smc_ctrl));
while (true) {
asm volatile("wfi");
}
}