sw/device/examples/spi_display/spi_display_sc.c

/*
 * Copyright 2023 Google LLC
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */


#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/examples/spi_display/spi_display_smc_fpga_nexus_bin_c.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_gpio.h"
#include "sw/device/lib/dif/dif_pinmux.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_smc_ctrl.h"
#include "sw/device/lib/dif/dif_tlul_mailbox.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/test_util.h"
#include "sw/device/lib/util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_smc_ctrl_t smc_ctrl;
static dif_tlul_mailbox_t tlul_mailbox;
static dif_pinmux_t pinmux;
static dif_uart_t uart;
static dif_rv_plic_t plic_sec;
static dif_gpio_t gpio;

void ottf_external_isr(void) {
  uint32_t rx;
  dif_rv_plic_irq_id_t plic_irq_id;

  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_sec, kTopMatchaPlicTargetIbex0,
                                     &plic_irq_id));
  top_matcha_plic_peripheral_t peripheral_id =
      top_matcha_plic_interrupt_for_peripheral[plic_irq_id];

  switch (peripheral_id) {
    case kTopMatchaPlicPeripheralTlulMailboxSec: {
      CHECK_DIF_OK(dif_tlul_mailbox_irq_acknowledge(&tlul_mailbox,
                                                    kDifTlulMailboxIrqRtirq));
      CHECK_DIF_OK(dif_tlul_mailbox_read_message(&tlul_mailbox, &rx));
      uint32_t pin = rx >> 16;
      uint32_t value = rx & 0xFFFF;
      CHECK_DIF_OK(dif_gpio_write(&gpio, pin, value));
      CHECK_DIF_OK(dif_tlul_mailbox_send_message(&tlul_mailbox, &rx));
      break;
    }
    default:
      LOG_FATAL("Unhandled interrupt");
      break;
  }

  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_sec, kTopMatchaPlicTargetIbex0,
                                        plic_irq_id));
}

void _ottf_main(void) {
  test_status_set(kTestStatusInTest);
  init_uart(TOP_MATCHA_UART0_BASE_ADDR, &uart);
  LOG_INFO("Start spi_display");

  // Add GPIO mux / init
  CHECK_DIF_OK(dif_pinmux_init(
      mmio_region_from_addr(TOP_MATCHA_PINMUX_AON_BASE_ADDR), &pinmux));

  CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIob7,
                                        kTopMatchaPinmuxOutselGpioGpio16));
  CHECK_DIF_OK(dif_pinmux_output_select(&pinmux, kTopMatchaPinmuxMioOutIob8,
                                        kTopMatchaPinmuxOutselGpioGpio17));

  CHECK_DIF_OK(
      dif_gpio_init(mmio_region_from_addr(TOP_MATCHA_GPIO_BASE_ADDR), &gpio));
  CHECK_DIF_OK(dif_gpio_output_set_enabled(&gpio, 16, kDifToggleEnabled));
  CHECK_DIF_OK(dif_gpio_output_set_enabled(&gpio, 17, kDifToggleEnabled));

  CHECK_DIF_OK(dif_tlul_mailbox_init(
      mmio_region_from_addr(TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR),
      &tlul_mailbox));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqRtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqWtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqEirq, kDifToggleEnabled));

  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_BASE_ADDR), &plic_sec));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      &plic_sec, kTopMatchaPlicIrqIdTlulMailboxSecRtirq,
      kTopMatchaPlicTargetIbex0, kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      &plic_sec, kTopMatchaPlicIrqIdTlulMailboxSecRtirq, 1));
  irq_global_ctrl(true);
  irq_external_ctrl(true);

  // Copy embedded binary to SMC RAM.
  memcpy((void *)TOP_MATCHA_RAM_SMC_BASE_ADDR, smc_bin, smc_bin_len);
  CHECK_DIF_OK(dif_smc_ctrl_init(
      mmio_region_from_addr(TOP_MATCHA_SMC_CTRL_BASE_ADDR), &smc_ctrl));
  CHECK_DIF_OK(dif_smc_ctrl_set_en(&smc_ctrl));

  while (true) {
    asm volatile("wfi");
  }
}