[ml_top/hw] Remove unused signals Change-Id: I800a90e2d2e80966ffc0f7675557612244eb9104
diff --git a/hw/top_matcha/ip/ml_top/data/ml_top.hjson b/hw/top_matcha/ip/ml_top/data/ml_top.hjson index 4192348..8061135 100644 --- a/hw/top_matcha/ip/ml_top/data/ml_top.hjson +++ b/hw/top_matcha/ip/ml_top/data/ml_top.hjson
@@ -37,7 +37,6 @@ } ], -//Add inter-signal lists for isp inter_signal_list: [ { name: "isp_cvalid", package: "", @@ -84,18 +83,6 @@ ], - // To-do: add parameter defintions here. - param_list: [ - { name: "ml_test_param", - type: "bit", - default: "0", - desc: "Test Param for ml_top" - local: "false", - expose: "true" - }, - ], - - regwidth: "32", registers: {
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv index 6d21c2b..ac1a588 100644 --- a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv +++ b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
@@ -12,20 +12,15 @@ import ml_top_reg_pkg::*; import prim_ram_1p_pkg::ram_1p_cfg_t; ( - input logic rst_ni, - input logic clk_i, + input logic rst_ni, + input logic clk_i, // CSR for memory voltage control - input logic volt_sel_i, - - // CSR Interface to initialize the memory -- placeholder - input ml_top_reg2hw_init_start_reg_t start_reg, - input ml_top_reg2hw_init_end_reg_t end_reg, - output ml_top_hw2reg_init_status_reg_t status_reg, + input logic volt_sel_i, // TLUL Interfaces - input tlul_pkg::tl_h2d_t tl_mem_i, - output tlul_pkg::tl_d2h_t tl_mem_o, + input tlul_pkg::tl_h2d_t tl_mem_i, + output tlul_pkg::tl_d2h_t tl_mem_o, // ISP Memory Interfaces input isp_cvalid_i, @@ -62,17 +57,10 @@ input [31:0] core1_wmask_i, output logic [255:0] core1_rdata_o, output logic core1_rvalid_o, - output logic [7:0] core1_rid_o, + output logic [7:0] core1_rid_o - // CSR Signals -- placeholder - input logic [DMemRows-1:0] bank_enable, - output logic [DMemRows-1:0] access_error ); - // TO-DO (pbf): Placeholder for now, add logic late - assign access_error = 1'b0; - assign status_reg = 4'b0; - // outgoing integrity generation tlul_pkg::tl_d2h_t tl_o_pre; tlul_rsp_intg_gen #( @@ -94,7 +82,7 @@ logic [1:0] dmem_rerror, xbar_rerror; ram_1p_cfg_t ram_cfg; - // cfg_en is unused in memory module and does not qualify volt_sel + // cfg_en (LSB) is unused in memory module and does not qualify volt_sel assign ram_cfg.ram_cfg = { 3'b0, volt_sel_i, 1'b0 }; // xbar_sram only support Byte-Mask for now. i.e 8 data bits per mask bit.
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv index 9f284f9..70e3b89 100644 --- a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv +++ b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
@@ -14,7 +14,6 @@ // definitions // module ml_top #( - parameter bit ml_test_param = 1'b0 // Place holder ) ( input logic rst_ni, input logic clk_i, @@ -66,8 +65,6 @@ ml_top_reg_pkg::ml_top_core_reg2hw_t reg2hw; ml_top_reg_pkg::ml_top_core_hw2reg_t hw2reg; ml_top_reg_pkg::ml_top_reg2hw_ctrl_reg_t ctrl; - ml_top_reg_pkg::ml_top_reg2hw_memory_bank_ctrl_reg_t memory_bank_ctrl; - ml_top_reg_pkg::ml_top_hw2reg_init_status_reg_t dmem_init_status; // Interrupt event, to be wired to correct source logic event_host_req; @@ -75,18 +72,14 @@ logic event_fault; logic event_data_fault; - logic [DMemRows-1:0] dmem_access_error; // Placeholder for now. assign ctrl = reg2hw.ctrl; - assign memory_bank_ctrl = reg2hw.memory_bank_ctrl; always_comb begin hw2reg.error_status.d_mem_out_of_range.d = 1'b0; hw2reg.error_status.d_mem_out_of_range.de = 1'b0; - hw2reg.error_status.d_mem_disable_access.d = reg2hw.error_status.d_mem_disable_access | dmem_access_error; - hw2reg.error_status.d_mem_disable_access.de = |dmem_access_error; - - hw2reg.init_status = dmem_init_status; + hw2reg.error_status.d_mem_disable_access.d = reg2hw.error_status.d_mem_disable_access; + hw2reg.error_status.d_mem_disable_access.de = 1'b0; end // ML_top Control @@ -103,7 +96,6 @@ ); // Kelvin core - Kelvin u_kelvin ( .clk_i, .rst_ni, @@ -111,10 +103,11 @@ // CSR control .clk_freeze (ctrl.freeze), // Default 0, writing 1 will freeze the kelvin's clock. (Clock gate inside) .ml_reset (ctrl.ml_reset), // default 1, writing 1 will reset the ml core. - // Writing 0 to will take it out of reset. + // Writing 0 will take it out of reset. + // Kelvin core execution start address {PC[21:0]}, 4MB address space. See register definition for bitfield lsb. .pc_start (ctrl.pc_start), - .volt_sel (ctrl.volt_sel), // Default 0 for 0.8V memory macros, writing 1 for 0.65V. + .volt_sel (ctrl.volt_sel), // Default 0 for 0.8V memory macros, write 1 for 0.65V. // SRAM Interface .cvalid (core0_cvalid), @@ -138,16 +131,12 @@ .finish (core0_finish) // raised if the kelvin finish the task ); - // Insert Malamult here - // Memory Block (inlcude xbar_sram and SRAM banks) ml_dmem u_ml_dmem ( .rst_ni ( rst_ni ), .clk_i ( clk_i ), - .bank_enable ( memory_bank_ctrl.d_mem_enable ), - .access_error ( dmem_access_error ), .volt_sel_i ( ctrl.volt_sel ), // TLUL Interface @@ -155,16 +144,16 @@ .tl_mem_o ( dmem_tl_o ), // In Port 1 -- ISP - .isp_cvalid_i (isp_cvalid_i), //isp_cvalid_i - .isp_cready_o (isp_cready_o), //isp_cready_o - .isp_cwrite_i (isp_cwrite_i), //isp_cwrite_i - .isp_caddr_i (isp_caddr_i), //isp_caddr_i - .isp_cid_i (8'b0), //isp_cid_i - .isp_wdata_i (isp_wdata_i), //isp_wdata_i - .isp_wmask_i (isp_wmask_i), //isp_wmask_i - .isp_rvalid_o (), //isp_rvalid_o - .isp_rid_o (), //isp_rid_o - .isp_rdata_o (), //isp_rdata_o + .isp_cvalid_i (isp_cvalid_i), + .isp_cready_o (isp_cready_o), + .isp_cwrite_i (isp_cwrite_i), + .isp_caddr_i (isp_caddr_i), + .isp_cid_i (8'b0), + .isp_wdata_i (isp_wdata_i), + .isp_wmask_i (isp_wmask_i), + .isp_rvalid_o (), + .isp_rid_o (), + .isp_rdata_o (), // In Port 2 -- Kelvin .core0_cvalid_i (core0_cvalid), .core0_cready_o (core0_cready), @@ -176,22 +165,17 @@ .core0_rvalid_o (core0_rvalid), .core0_rid_o (core0_rid), .core0_rdata_o (core0_rdata), - // In Port 3 -- Malamute -- Add when ready - .core1_cvalid_i (1'b0), //core1_cvalid_i), - .core1_cready_o (), //core1_cready_o), - .core1_cwrite_i (1'b0), //core1_cwrite_i), - .core1_caddr_i (22'b0), //core1_caddr_i), - .core1_cid_i (8'b0), //core1_cid_i), - .core1_wdata_i (256'b0), //core1_wdata_i), - .core1_wmask_i (32'b0), //core1_wmask_i), - .core1_rvalid_o (), //core1_rvalid_o), - .core1_rid_o (), //core1_rid_o), - .core1_rdata_o (), //core1_rdata_o), - - // CSR Signals for memory bank initializeation use.-- Placeholder for now. - .start_reg ( reg2hw.init_start ), - .end_reg ( reg2hw.init_end ), - .status_reg ( dmem_init_status ) + // In Port 3 -- Unused + .core1_cvalid_i (1'b0), + .core1_cready_o (), + .core1_cwrite_i (1'b0), + .core1_caddr_i (22'b0), + .core1_cid_i (8'b0), + .core1_wdata_i (256'b0), + .core1_wmask_i (32'b0), + .core1_rvalid_o (), + .core1_rid_o (), + .core1_rdata_o () ); @@ -205,7 +189,7 @@ assign event_fault = core0_fault; // TODO: Reserved for WinMMU faults. Hardwired to low as placeholder for now. - assign event_data_fault = 1'b0; + assign intr_data_fault_o = 1'b0; // Host Request interrupt prim_intr_hw #(.Width(1)) intr_host_req ( @@ -250,19 +234,5 @@ .intr_o (intr_fault_o) ); - // Data fault interrupt - prim_intr_hw #(.Width(1)) intr_data_fault ( - .clk_i, - .rst_ni, - .event_intr_i (event_data_fault), - .reg2hw_intr_enable_q_i (reg2hw.intr_enable.data_fault.q), - .reg2hw_intr_test_q_i (reg2hw.intr_test.data_fault.q), - .reg2hw_intr_test_qe_i (reg2hw.intr_test.data_fault.qe), - .reg2hw_intr_state_q_i (reg2hw.intr_state.data_fault.q), - .hw2reg_intr_state_de_o (hw2reg.intr_state.data_fault.de), - .hw2reg_intr_state_d_o (hw2reg.intr_state.data_fault.d), - .intr_o (intr_data_fault_o) - ); - endmodule
diff --git a/hw/top_matcha/rtl/autogen/top_matcha.sv b/hw/top_matcha/rtl/autogen/top_matcha.sv index 3f969cf..4447ec8 100644 --- a/hw/top_matcha/rtl/autogen/top_matcha.sv +++ b/hw/top_matcha/rtl/autogen/top_matcha.sv
@@ -128,7 +128,6 @@ // parameters for tlul_mailbox_smc parameter int TlulMailboxSmcMailboxDepth = 8, // parameters for ml_top - parameter bit MlTopml_test_param = 0, // parameters for spi_host2 // parameters for rv_timer_smc2 // parameters for i2s0 @@ -3242,9 +3241,7 @@ .clk_i (clkmgr_aon_clocks.clk_main_infra), .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); - ml_top #( - .ml_test_param(MlTopml_test_param) - ) u_ml_top ( + ml_top u_ml_top ( // Interrupt .intr_host_req_o (intr_ml_top_host_req),