fpga/ip/rv_core_ibex/README.md

# Ibex RISC-V Core Wrapper Technical Specification

[`rv_core_ibex`](https://ibex.reports.lowrisc.org/opentitan/latest/report.html):
![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/test.svg)
![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/passing.svg)
![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/functional.svg)
![](https://dashboards.lowrisc.org/badges/dv/ibex/opentitan/code.svg)

# Overview

This document specifies Ibex CPU core wrapper functionality.

## Features

* Instantiation of a [Ibex RV32 CPU Core](https://github.com/lowRISC/ibex).
* TileLink Uncached Light (TL-UL) host interfaces for the instruction and data ports.
* Simple address translation.
* NMI support for security alert events for watchdog bark.
* General error status collection and alert generation.
* Crash dump collection for software debug.

## Description

The Ibex RISC-V Core Wrapper instantiates an [Ibex RV32 CPU Core](https://github.com/lowRISC/ibex), and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL).
All configuration parameters of Ibex are passed through.
The pipelining of the bus adapters is configurable.

## Compatibility

Ibex is a compliant RV32 RISC-V CPU core, as [documented in the Ibex documentation](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html).

The TL-UL bus interfaces exposed by this wrapper block are compliant to the [TileLink Uncached Lite Specification version 1.7.1](https://sifive.cdn.prismic.io/sifive%2F57f93ecf-2c42-46f7-9818-bcdd7d39400a_tilelink-spec-1.7.1.pdf).