| tag | 0f036923a576e29151c3e89558c417a85708276b | |
|---|---|---|
| tagger | Cindy Liu <hcindyl@google.com> | Wed Aug 30 16:30:48 2023 -0700 |
| object | 7c1ccd51884a09e0a61b55b1680498f001ba2013 |
RTL v1.0 freeze with branch fix
| commit | 7c1ccd51884a09e0a61b55b1680498f001ba2013 | [log] [tgz] |
|---|---|---|
| author | Michael Hoang <hoangm@google.com> | Tue Aug 29 19:36:28 2023 +0000 |
| committer | Michael Hoang <hoangm@google.com> | Wed Aug 30 15:59:05 2023 +0000 |
| tree | 8c80c7a4cf98d3cf20390e0e329888bfdef5eaf5 | |
| parent | 9e2fc99ed7e6cd4400b2c8f134245a811bc94f22 [diff] |
Disable mlu decoding on taken branches - Use this approach instead of masking, to account for branch prediction and serialization Fix: 295921340 Change-Id: Ia703e5a79f7768cc5ab9b24edf3197b6f848d9fe
Kelvin is a RISC-V32IM core with a custom instruction set.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog