Clean up uses of OneHot and some reduction patterns.
Change-Id: Ice72db1957b501165128922937046362f0deae3a
diff --git a/hdl/chisel/src/kelvin/Library.scala b/hdl/chisel/src/kelvin/Library.scala
index 26b92a3..0919bff 100644
--- a/hdl/chisel/src/kelvin/Library.scala
+++ b/hdl/chisel/src/kelvin/Library.scala
@@ -215,21 +215,6 @@
}
}
-object OneHot {
- def apply(bits: UInt, count: Int): UInt = {
- // // UIntToOH(bits, count)
- // val bools = Wire(Vec(count, Bool()))
- // for (i <- 0 until count) {
- // bools(i) := bits === i.U
- // }
- // val r = bools.asUInt
- // assert(r.getWidth == count)
- // r
-
- UIntToOH(bits, count)
- }
-}
-
// Page mask for two address ranges, factoring unaligned address overflow.
object PageMaskShift {
def apply(address: UInt, length: UInt): UInt = {
diff --git a/hdl/chisel/src/kelvin/scalar/Decode.scala b/hdl/chisel/src/kelvin/scalar/Decode.scala
index 9c7abf4..75ace28 100644
--- a/hdl/chisel/src/kelvin/scalar/Decode.scala
+++ b/hdl/chisel/src/kelvin/scalar/Decode.scala
@@ -353,8 +353,8 @@
d.io.getvl || d.io.getmaxvl || vldst_wb ||
bruValid && (bruOp(bru.JAL) || bruOp(bru.JALR)) && rdAddr =/= 0.U
- // val scoreboard_spec = Mux(rdMark_valid || d.io.vst, OneHot(rdAddr, 32), 0.U) // TODO: why was d.io.vst included?
- val scoreboard_spec = Mux(rdMark_valid, OneHot(rdAddr, 32), 0.U)
+ // val scoreboard_spec = Mux(rdMark_valid || d.io.vst, UIntToOH(rdAddr, 32), 0.U) // TODO: why was d.io.vst included?
+ val scoreboard_spec = Mux(rdMark_valid, UIntToOH(rdAddr, 32), 0.U)
io.scoreboard.spec := Cat(scoreboard_spec(31,1), 0.U(1.W))
io.rdMark.valid := decodeEn && rdMark_valid
diff --git a/hdl/chisel/src/kelvin/scalar/Fetch.scala b/hdl/chisel/src/kelvin/scalar/Fetch.scala
index e265dab..073f62a 100644
--- a/hdl/chisel/src/kelvin/scalar/Fetch.scala
+++ b/hdl/chisel/src/kelvin/scalar/Fetch.scala
@@ -225,7 +225,7 @@
}
when (readDataEn) {
- val bits = OneHot(readIdx, indices)
+ val bits = UIntToOH(readIdx, indices)
l0validSet := bits
l0reqClr := bits
}
@@ -237,7 +237,7 @@
}
when (aslice.io.in.valid && aslice.io.in.ready) {
- l0reqSet := OneHot(aslice.io.in.bits(indexMsb, indexLsb), indices)
+ l0reqSet := UIntToOH(aslice.io.in.bits(indexMsb, indexLsb), indices)
}
when (l0validClr =/= 0.U || l0validSet =/= 0.U) {
diff --git a/hdl/chisel/src/kelvin/scalar/Regfile.scala b/hdl/chisel/src/kelvin/scalar/Regfile.scala
index 5dd884a..4179602 100644
--- a/hdl/chisel/src/kelvin/scalar/Regfile.scala
+++ b/hdl/chisel/src/kelvin/scalar/Regfile.scala
@@ -109,19 +109,11 @@
// The write Addr:Data contract is against speculated opcodes. If an opcode
// is in the shadow of a taken branch it will still Set:Clr the scoreboard,
// but the actual write will be Masked.
- val scoreboard_set =
- MuxOR(io.writeAddr(0).valid, OneHot(io.writeAddr(0).addr, 32)) |
- MuxOR(io.writeAddr(1).valid, OneHot(io.writeAddr(1).addr, 32)) |
- MuxOR(io.writeAddr(2).valid, OneHot(io.writeAddr(2).addr, 32)) |
- MuxOR(io.writeAddr(3).valid, OneHot(io.writeAddr(3).addr, 32))
+ val scoreboard_set = io.writeAddr
+ .map(x => MuxOR(x.valid, UIntToOH(x.addr, 32))).reduce(_|_)
- val scoreboard_clr0 =
- MuxOR(io.writeData(0).valid, OneHot(io.writeData(0).addr, 32)) |
- MuxOR(io.writeData(1).valid, OneHot(io.writeData(1).addr, 32)) |
- MuxOR(io.writeData(2).valid, OneHot(io.writeData(2).addr, 32)) |
- MuxOR(io.writeData(3).valid, OneHot(io.writeData(3).addr, 32)) |
- MuxOR(io.writeData(4).valid, OneHot(io.writeData(4).addr, 32)) |
- MuxOR(io.writeData(5).valid, OneHot(io.writeData(5).addr, 32))
+ val scoreboard_clr0 = io.writeData
+ .map(x => MuxOR(x.valid, UIntToOH(x.addr, 32))).reduce(_|_)
val scoreboard_clr = Cat(scoreboard_clr0(31,1), 0.U(1.W))
diff --git a/hdl/chisel/src/kelvin/vector/VCommon.scala b/hdl/chisel/src/kelvin/vector/VCommon.scala
index 76edbd5..e600259 100644
--- a/hdl/chisel/src/kelvin/vector/VCommon.scala
+++ b/hdl/chisel/src/kelvin/vector/VCommon.scala
@@ -26,7 +26,7 @@
assert(regnum.getWidth == 6)
assert(step <= 4.U)
- val oh = OneHot(regnum(5,2), 16)
+ val oh = UIntToOH(regnum(5,2), 16)
val oh0 = Cat(0.U(3.W), oh(15),
0.U(3.W), oh(14),
diff --git a/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala b/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala
index ebe85f9..f7a294d 100644
--- a/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala
+++ b/hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala
@@ -77,19 +77,19 @@
def RActiveVsVt(i: Int): UInt = {
assert(i == 2 || i == 3)
- val vs = OneHot(vsbits, 64)
- val vsm = MuxOR(m, ToM(OneHot(vsbits(5,2), 16)))
+ val vs = UIntToOH(vsbits, 64)
+ val vsm = MuxOR(m, ToM(UIntToOH(vsbits(5,2), 16)))
val vt =
if (i == 2) {
- MuxOR(!x, OneHot(vtbits, 64))
+ MuxOR(!x, UIntToOH(vtbits, 64))
} else {
- MuxOR(!x3, OneHot(vtbits, 64))
+ MuxOR(!x3, UIntToOH(vtbits, 64))
}
val vtm =
if (i == 2) {
- MuxOR(m && !x, ToM(OneHot(vtbits(5,2), 16)))
+ MuxOR(m && !x, ToM(UIntToOH(vtbits(5,2), 16)))
} else {
- MuxOR(m && !x3, ToM(OneHot(vtbits(5,2), 16)))
+ MuxOR(m && !x3, ToM(UIntToOH(vtbits(5,2), 16)))
}
assert(vs.getWidth == 64)
assert(vt.getWidth == 64)
@@ -100,8 +100,8 @@
def RActiveVs1(): UInt = {
// {vs+1} or {vsm+4}
- val vs = Cat(OneHot(vsbits, 64), 0.U(1.W))(63,0)
- val vsm = MuxOR(m, Cat(ToM(OneHot(vsbits(5,2), 16)), 0.U(4.W))(63,0))
+ val vs = Cat(UIntToOH(vsbits, 64), 0.U(1.W))(63,0)
+ val vsm = MuxOR(m, Cat(ToM(UIntToOH(vsbits(5,2), 16)), 0.U(4.W))(63,0))
assert(vs.getWidth == 64)
assert(vsm.getWidth == 64)
vs | vsm
@@ -109,8 +109,8 @@
def RActiveVs2(): UInt = {
// {vs+2} or {vsm+8}
- val vs = Cat(OneHot(vsbits, 64), 0.U(2.W))(63,0)
- val vsm = MuxOR(m, Cat(ToM(OneHot(vsbits(5,2), 16)), 0.U(8.W))(63,0))
+ val vs = Cat(UIntToOH(vsbits, 64), 0.U(2.W))(63,0)
+ val vsm = MuxOR(m, Cat(ToM(UIntToOH(vsbits(5,2), 16)), 0.U(8.W))(63,0))
assert(vs.getWidth == 64)
assert(vsm.getWidth == 64)
vs | vsm
@@ -118,32 +118,32 @@
def RActiveVs3(): UInt = {
// {vs+3} or {vsm+12}
- val vs = Cat(OneHot(vsbits, 64), 0.U(3.W))(63,0)
- val vsm = MuxOR(m, Cat(ToM(OneHot(vsbits(5,2), 16)), 0.U(12.W))(63,0))
+ val vs = Cat(UIntToOH(vsbits, 64), 0.U(3.W))(63,0)
+ val vsm = MuxOR(m, Cat(ToM(UIntToOH(vsbits(5,2), 16)), 0.U(12.W))(63,0))
assert(vs.getWidth == 64)
assert(vsm.getWidth == 64)
vs | vsm
}
def RActiveVd(): UInt = {
- val vd = OneHot(vdbits, 64)
- val vdm = MuxOR(m, ToM(OneHot(vdbits(5,2), 16)))
+ val vd = UIntToOH(vdbits, 64)
+ val vdm = MuxOR(m, ToM(UIntToOH(vdbits(5,2), 16)))
assert(vd.getWidth == 64)
assert(vdm.getWidth == 64)
vd | vdm
}
def RActiveVu(): UInt = {
- val vu = OneHot(vubits, 64)
- val vum = MuxOR(m, ToM(OneHot(vubits(5,2), 16)))
+ val vu = UIntToOH(vubits, 64)
+ val vum = MuxOR(m, ToM(UIntToOH(vubits(5,2), 16)))
assert(vu.getWidth == 64)
assert(vum.getWidth == 64)
vu | vum
}
def WActiveVd(): UInt = {
- val vd = OneHot(vdbits, 64)
- val vdm = MuxOR(m, ToM(OneHot(vdbits(5,2), 16)))
+ val vd = UIntToOH(vdbits, 64)
+ val vdm = MuxOR(m, ToM(UIntToOH(vdbits(5,2), 16)))
assert(vd.getWidth == 64)
assert(vdm.getWidth == 64)
vd | vdm
@@ -151,8 +151,8 @@
def WActiveVd1(): UInt = {
// {vd+1} or {vdm+4}
- val vd = Cat(OneHot(vdbits, 64), 0.U(1.W))(63,0)
- val vdm = MuxOR(m, Cat(ToM(OneHot(vdbits(5,2), 16)), 0.U(4.W))(63,0))
+ val vd = Cat(UIntToOH(vdbits, 64), 0.U(1.W))(63,0)
+ val vdm = MuxOR(m, Cat(ToM(UIntToOH(vdbits(5,2), 16)), 0.U(4.W))(63,0))
assert(vd.getWidth == 64)
assert(vdm.getWidth == 64)
vd | vdm
@@ -179,15 +179,15 @@
assert(vy.getWidth == 6)
assert(vz.getWidth == 6)
- val ra_vs = OneHot(vs, 64)
- val ra_vt = OneHot(vt, 64)
- val ra_vu = OneHot(vu, 64)
- val ra_vx = OneHot(vx, 64)
- val ra_vy = OneHot(vy, 64)
- val ra_vz = OneHot(vz, 64)
- val ra_vxm = MuxOR(m, ToM(OneHot(vx(5,2), 16)))
- val ra_vym = MuxOR(m, ToM(OneHot(vy(5,2), 16)))
- val ra_vzm = MuxOR(m, ToM(OneHot(vz(5,2), 16)))
+ val ra_vs = UIntToOH(vs, 64)
+ val ra_vt = UIntToOH(vt, 64)
+ val ra_vu = UIntToOH(vu, 64)
+ val ra_vx = UIntToOH(vx, 64)
+ val ra_vy = UIntToOH(vy, 64)
+ val ra_vz = UIntToOH(vz, 64)
+ val ra_vxm = MuxOR(m, ToM(UIntToOH(vx(5,2), 16)))
+ val ra_vym = MuxOR(m, ToM(UIntToOH(vy(5,2), 16)))
+ val ra_vzm = MuxOR(m, ToM(UIntToOH(vz(5,2), 16)))
assert(ra_vs.getWidth == 64)
assert(ra_vt.getWidth == 64)
assert(ra_vu.getWidth == 64)
@@ -219,12 +219,12 @@
assert(vy.getWidth == 6)
assert(vz.getWidth == 6)
- val ra_vs = OneHot(vs, 64)
- val ra_vt = MuxOR(!x || !s, OneHot(vt, 64))
- val ra_vu = MuxOR(!x || !s, OneHot(vu, 64))
- val ra_vx = MuxOR(!x || !s, OneHot(vx, 64))
- val ra_vy = MuxOR(!x || !s, OneHot(vy, 64))
- val ra_vz = MuxOR(!x, OneHot(vz, 64))
+ val ra_vs = UIntToOH(vs, 64)
+ val ra_vt = MuxOR(!x || !s, UIntToOH(vt, 64))
+ val ra_vu = MuxOR(!x || !s, UIntToOH(vu, 64))
+ val ra_vx = MuxOR(!x || !s, UIntToOH(vx, 64))
+ val ra_vy = MuxOR(!x || !s, UIntToOH(vy, 64))
+ val ra_vz = MuxOR(!x, UIntToOH(vz, 64))
assert(ra_vs.getWidth == 64)
assert(ra_vt.getWidth == 64)
assert(ra_vu.getWidth == 64)
@@ -493,8 +493,8 @@
// Depthwise read.
val (vsdw, vtdw, vudw, vxdw, vydw, vzdw, ractivedw) = DepthwiseRead()
- val ractivedi = ToM(OneHot(vsbits(5,2), 16))
- val wactivedw = ToM(OneHot(vdbits(5,2), 16))
+ val ractivedi = ToM(UIntToOH(vsbits(5,2), 16))
+ val wactivedw = ToM(UIntToOH(vdbits(5,2), 16))
// Slide composite read.
val (vssl, vtsl, vusl, vxsl, vysl, vzsl, ractivesl) = SlideRead()
diff --git a/hdl/chisel/src/kelvin/vector/VRegfile.scala b/hdl/chisel/src/kelvin/vector/VRegfile.scala
index 523c7a0..e9f74a5 100644
--- a/hdl/chisel/src/kelvin/vector/VRegfile.scala
+++ b/hdl/chisel/src/kelvin/vector/VRegfile.scala
@@ -410,8 +410,8 @@
if (i < writePorts) {
val wvalid = io.write(i).valid
val hvalid = if (i < whintPorts) io.whint(i).valid else false.B
- val woh = MuxOR(io.write(i).valid, OneHot(io.write(i).addr, 64))
- val hoh = if (i < whintPorts) MuxOR(io.whint(i).valid, OneHot(io.whint(i).addr, 64)) else 0.U
+ val woh = MuxOR(io.write(i).valid, UIntToOH(io.write(i).addr, 64))
+ val hoh = if (i < whintPorts) MuxOR(io.whint(i).valid, UIntToOH(io.whint(i).addr, 64)) else 0.U
val whoh = woh | hoh
val whdata = Cat(whoh, whoh)
assert(whdata.getWidth == 128)
