commit f1f7ea210ef41063e597f1f07f8fa8e4747e1b15
author Cindy Liu <hcindyl@google.com> Fri Aug 18 20:43:27 2023 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> Fri Aug 18 20:43:27 2023 +0000
tree e9e878a8f36d6a5a640eefadf948104d395ba6fe
parent a2c167c175cdb50dc76ef656d586b50ea2ddda0f
parent 50085e15f519a0ca9e46106405b6b74a336438bc

Merge "Add matcha_kelvin_verilog target"

hdl/chisel/BUILD

diff --git a/hdl/chisel/BUILD b/hdl/chisel/BUILD
index 48e7360..3b958a8 100644
--- a/hdl/chisel/BUILD
+++ b/hdl/chisel/BUILD
@@ -77,6 +77,13 @@
 )
 
 chisel_cc_library(
+    name = "valuint_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVAluInt",
+    module_name = "VAluInt",
+)
+
+chisel_cc_library(
     name = "vcmdq_cc_library",
     chisel_lib = ":kelvin",
     emit_class = "kelvin.EmitVCmdq",

hdl/verilog/Sram_1rwm_256x288.v

diff --git a/hdl/verilog/Sram_1rwm_256x288.v b/hdl/verilog/Sram_1rwm_256x288.v
index 011c7cc..425b662 100644
--- a/hdl/verilog/Sram_1rwm_256x288.v
+++ b/hdl/verilog/Sram_1rwm_256x288.v
@@ -11,13 +11,12 @@
   input          volt_sel
 );
 
+`ifdef FPGA
 reg [287:0] mem [0:255];
 reg [7:0] raddr;
 
 assign rdata = mem[raddr];
 
-`ifdef FPGA
-
 always @(posedge clock) begin
   for (int i = 0; i < 32; i++) begin
     if (valid & write & wmask[i]) begin

tests/verilator_sim/BUILD

diff --git a/tests/verilator_sim/BUILD b/tests/verilator_sim/BUILD
index 216b7a7..452c11f 100644
--- a/tests/verilator_sim/BUILD
+++ b/tests/verilator_sim/BUILD
@@ -88,22 +88,44 @@
     ],
 )
 
+cc_library(
+    name = "valu",
+    hdrs = [
+        "kelvin/alu_ref.h",
+        "kelvin/valu.h",
+    ],
+    deps = [
+        ":vencodeop",
+    ],
+)
+
 cc_test(
     name = "valu_tb",
     size = "large",
     srcs = [
-        "kelvin/alu_ref.h",
-        "kelvin/valu.h",
         "kelvin/valu_tb.cc",
     ],
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        ":vencodeop",
+        ":valu",
         "//hdl/chisel:valu_cc_library",
     ],
 )
 
+cc_test(
+    name = "valuint_tb",
+    srcs = [
+        "kelvin/valuint_tb.cc",
+    ],
+    deps = [
+        ":kelvin_if",
+        ":sim_libs",
+        ":valu",
+        "//hdl/chisel:valuint_cc_library",
+    ],
+)
+
 cc_library(
     name = "vdecode",
     hdrs = [

tests/verilator_sim/kelvin/valuint_tb.cc

diff --git a/tests/verilator_sim/kelvin/valuint_tb.cc b/tests/verilator_sim/kelvin/valuint_tb.cc
index f86ad37..05999be 100644
--- a/tests/verilator_sim/kelvin/valuint_tb.cc
+++ b/tests/verilator_sim/kelvin/valuint_tb.cc
@@ -1,12 +1,12 @@
 // Copyright 2023 Google LLC
 
-#include "VVAluInt.h"
-#include "sysc_tb.h"
-#include "valu.h"
+#include "VVAluInt.h"  // Generated.
+#include "tests/verilator_sim/kelvin/valu.h"
+#include "tests/verilator_sim/sysc_tb.h"
 
 struct VAluInt_tb : Sysc_tb {
   sc_out<bool> io_in_valid;
-  sc_out<sc_bv<kOpBits> > io_in_op;
+  sc_out<sc_bv<encode::kOpBits> > io_in_op;
   sc_out<sc_bv<3> > io_in_f2;
   sc_out<sc_bv<3> > io_in_sz;
   sc_out<sc_bv<6> > io_in_vd_addr;
@@ -41,15 +41,15 @@
     const uint8_t ve_addr = rand_int(0, 63);
     uint32_t sv_data = 0;
 
-    uint8_t op = rand_int(0, kOpEntries - 1);
+    uint8_t op = rand_int(0, encode::kOpEntries - 1);
 
     // Inputs.
     valu_t r = {0};
     r_.read(r);
 
-    if (op == vdwconv) {
+    if (op == encode::vdwconv) {
       // Disallow DW in CRT.
-      op = 0;  // TODO
+      op = 0;
     }
 
     io_in_valid = valid;
@@ -142,7 +142,7 @@
 
 static void VAluInt_test(char* name, int loops, bool trace) {
   sc_signal<bool> io_in_valid;
-  sc_signal<sc_bv<kOpBits> > io_in_op;
+  sc_signal<sc_bv<encode::kOpBits> > io_in_op;
   sc_signal<sc_bv<3> > io_in_f2;
   sc_signal<sc_bv<3> > io_in_sz;
   sc_signal<sc_bv<6> > io_in_vd_addr;