commit ee09cb611c1027c0d44c4beaac985ed62e67f035
author Derek Chow <derekjchow@google.com> Thu Jul 31 15:35:56 2025 -0700
committer Derek Chow <derekjchow@google.com> Thu Jul 31 15:55:52 2025 -0700
tree 0dae67be15e0ca71449e04ef3ece6462a8b31891
parent 6681f8ffeea44f9325d7dfb92f332a1efa0da827

Expose VL through Csr.

Change-Id: I21b74e9b68c6617c5d70ebd54e0901e693ac8a21

hdl/chisel/src/kelvin/scalar/Csr.scala

diff --git a/hdl/chisel/src/kelvin/scalar/Csr.scala b/hdl/chisel/src/kelvin/scalar/Csr.scala
index 80a4f26..f702a97 100644
--- a/hdl/chisel/src/kelvin/scalar/Csr.scala
+++ b/hdl/chisel/src/kelvin/scalar/Csr.scala
@@ -21,6 +21,7 @@
 class CsrRvvIO(p: Parameters) extends Bundle {
   // To Csr from RvvCore
   val vstart = Input(UInt(log2Ceil(p.rvvVlen).W))
+  val vl = Input(UInt(log2Ceil(p.rvvVlen).W))
   val vxrm = Input(UInt(2.W))
   val vxsat = Input(Bool())
   // From Csr to RvvCore
@@ -72,6 +73,7 @@
   val MINSTRET  = Value(0xB02.U(12.W))
   val MCYCLEH   = Value(0xB80.U(12.W))
   val MINSTRETH = Value(0xB82.U(12.W))
+  val VL        = Value(0xC20.U(12.W))
   val VLENB     = Value(0xC22.U(12.W))
   val MVENDORID = Value(0xF11.U(12.W))
   val MARCHID   = Value(0xF12.U(12.W))
@@ -299,6 +301,7 @@
   val frmEn       = csr_address === CsrAddress.FRM
   val fcsrEn      = csr_address === CsrAddress.FCSR
   val vstartEn    = Option.when(p.enableRvv) { csr_address === CsrAddress.VSTART }
+  val vlEn        = Option.when(p.enableRvv) { csr_address === CsrAddress.VL }
   val vxrmEn      = Option.when(p.enableRvv) { csr_address === CsrAddress.VXRM }
   val vxsatEn     = Option.when(p.enableRvv) { csr_address === CsrAddress.VXSAT }
   val mstatusEn   = csr_address === CsrAddress.MSTATUS
@@ -409,6 +412,7 @@
       Option.when(p.enableRvv) {
         Seq(
           vstartEn.get -> io.rvv.get.vstart,
+          vlEn.get     -> io.rvv.get.vl,
           vxrmEn.get   -> io.rvv.get.vxrm,
           vxsatEn.get  -> io.rvv.get.vxsat,
           vlenbEn.get -> 16.U(32.W),  // Vector length in Bytes

hdl/chisel/src/kelvin/scalar/SCore.scala

diff --git a/hdl/chisel/src/kelvin/scalar/SCore.scala b/hdl/chisel/src/kelvin/scalar/SCore.scala
index 7a46f36..86c6299 100644
--- a/hdl/chisel/src/kelvin/scalar/SCore.scala
+++ b/hdl/chisel/src/kelvin/scalar/SCore.scala
@@ -432,6 +432,7 @@
     io.rvvcore.get.csr.vxrm_write <> csr.io.rvv.get.vxrm_write
     io.rvvcore.get.csr.vxsat_write <> csr.io.rvv.get.vxsat_write
     csr.io.rvv.get.vstart := io.rvvcore.get.csr.vstart
+    csr.io.rvv.get.vl := io.rvvcore.get.configState.bits.vl
     csr.io.rvv.get.vxrm := io.rvvcore.get.csr.vxrm
     csr.io.rvv.get.vxsat := io.rvvcore.get.csr.vxsat
   }