add lint flow for RVV
Change-Id: Iaac964557f3e830418b68bf40a2c3ed33565b81b
diff --git a/hdl/verilog/rvv/sve/Makefile b/hdl/verilog/rvv/sve/Makefile
new file mode 100755
index 0000000..2177dc3
--- /dev/null
+++ b/hdl/verilog/rvv/sve/Makefile
@@ -0,0 +1,65 @@
+#!/usr/bin/make -f
+
+TOPMODULE = rvv
+KELVIN_PATH =
+TBBUILD = build
+
+DESIGN_PATH = $(PWD)/design/
+STD_PATH = $(PWD)/../common/
+
+TESTBENCH_PATH = $(PWD)/sve/
+
+# ------------------------------------------------------------------
+# Tools used by script
+# ------------------------------------------------------------------
+
+SIMULATOR = vcs
+LINTTOOL = spyglass
+MKDIR = mkdir -p
+MV = mv
+
+
+# generate design filelist
+DESIGNLST = rvv.f
+STDLIST = common.f
+TESTBENCHLST = rvv_tb.f
+
+design_list:
+ @find $(DESIGN_PATH) -name '*.sv' -o -name '*.svh' > $(TBBUILD)/$(DESIGNLST)
+
+std_list:
+ @find $(STD_PATH) -name '*.sv' -o -name '*.svh' > $(TBBUILD)/$(STDLIST)
+
+testbench_list:
+ @find $(TESTBENCH_PATH) -name '*.sv' -o -name '*.svh' > $(TBBUILD)/$(TESTBENCHLST)
+
+filelist: std_list design_list testbench_list
+ @cat $(TBBUILD)/$(STDLIST) > $(TBBUILD)/sim.f
+ #@cat $(TBBUILD)/$(DESIGNLST) >> $(TBBUILD)/sim.f
+ #@cat $(TBBUILD)/$(TESTBENCHLST) >> $(TBBUILD)/sim.f
+
+# lint check for RTL code
+GOALS = lint/lint_rtl
+SGPRJ = $(PWD)/sve/spyglass.prj
+WORKPRJ = $(TBBUILD)/$(LINTTOOL)/work.prj
+
+lint: filelist
+ -@test -d $(TBBUILD)/$(LINTTOOL). || ($(MKDIR) $(TBBUILD)/$(LINTTOOL); echo "$(MKDIR) $(TBBUILD)/$(LINTTOOL)")
+ @echo " ------------------------------ "
+ @echo " Running Lint checker on the RTL "
+ @echo " ------------------------------ "
+ @cp $(SGPRJ) $(WORKPRJ)
+ @sed -i 's/filelist/$(TBBUILD)\/sim.f/g' $(WORKPRJ)
+ @sed -i 's/builddir/$(TBBUILD)\/$(LINTTOOL)/g' $(WORKPRJ)
+ @sed -i 's/topmodule/$(TOPMODULE)/g' $(WORKPRJ)
+ -$(LINTTOOL) -goals $(GOALS) -project $(WORKPRJ) -batch
+ -@$(MV) spyglass.out $(TBBUILD)/$(LINTTOOL)
+ -@$(MV) dashboard.log $(TBBUILD)/$(LINTTOOL)
+ -@$(MV) datasheet.log $(TBBUILD)/$(LINTTOOL)
+ -@$(MV) goals_summary.log $(TBBUILD)/$(LINTTOOL)
+
+lint_vcs: filelist
+ -@test -d $(TBBUILD)/$(SIMULATOR). || ($(MKDIR) $(TBBUILD)/$(SIMULATOR); echo "$(MKDIR) $(TBBUILD)/$(SIMULATOR)")
+ $(SIMULATOR) -c -full64 -sverilog -f $(TBBUILD)/sim.f -top $(TOPMODULE) -l $(TBBUILD)/$(SIMULATOR)/vcs.log
+
+# Synthesis
diff --git a/hdl/verilog/rvv/sve/spyglass.prj b/hdl/verilog/rvv/sve/spyglass.prj
new file mode 100755
index 0000000..0e3fcfe
--- /dev/null
+++ b/hdl/verilog/rvv/sve/spyglass.prj
@@ -0,0 +1,30 @@
+#!SPYGLASS_PROJECT_FILE
+
+##Data Import Section
+read_file -type sourcelist filelist
+
+##Common Options Section
+set_option projectwdir builddir
+set_option language_mode mixed
+set_option designread_enable_synthesis no
+set_option designread_disable_flatten no
+set_option dw no
+set_option enableSV yes
+set_option enableSV09 yes
+set_option libext { .sv .svh }
+set_option mthresh 16384
+set_option sgsyn_loop_limit 8000
+set_option abstract_file_name_style short
+set_option auto_save no
+#set_option ignoredu {}
+set_option top topmodule
+set_option sdc2sgdc no
+set_option active_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
+
+##Goal Setup Section
+current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
+set_parameter check_lrm_and_natural_width yes
+set_parameter use_lrm_width yes
+
+current_goal lint/lint_rtl -top topmodule
+
