commit d79c4a7b1535787d4b002fc8b8a2412b7744da39
author Alex Van Damme <atv@google.com> Tue Sep 09 10:51:22 2025 -0700
committer Alex Van Damme <atv@google.com> Tue Sep 09 11:15:52 2025 -0700
tree 3ba55abcfe6ea374ad611049453834188c466e9a
parent 63cdfa9f188cd6fc52b917ef8ccbc41a253dfe42

Minor BUILD fixups for vcs_sim

Change-Id: I3e5a8dd692fd57db2420a9231b45a1db7334459a

tests/vcs_sim/BUILD

diff --git a/tests/vcs_sim/BUILD b/tests/vcs_sim/BUILD
index 7aee2e0..760b4fe 100644
--- a/tests/vcs_sim/BUILD
+++ b/tests/vcs_sim/BUILD
@@ -34,9 +34,9 @@
         "//hdl/chisel/src/kelvin:core_mini_axi_cc_library_verilog",
     ],
     verilog_srcs = [
-        "//internal/syn:libs/tsmc12ffc/ts1n12ffcllsblvtd512x128m4swbsho_130b/VERILOG/ts1n12ffcllsblvtd512x128m4swbsho_130b.v",
-        "//internal/syn:libs/tsmc12ffc/ts1n12ffcllmblvtd2048x128m4swbsho_130d/VERILOG/ts1n12ffcllmblvtd2048x128m4swbsho_130d.v",
-        "//internal/syn:libs/tsmc12ffc/tcbn12ffcllbwp6t20p96cpdlvt.v",
+        "//internal/syn/libs/tsmc12ffc:ts1n12ffcllsblvtd512x128m4swbsho_130b/VERILOG/ts1n12ffcllsblvtd512x128m4swbsho_130b.v",
+        "//internal/syn/libs/tsmc12ffc:ts1n12ffcllmblvtd2048x128m4swbsho_130d/VERILOG/ts1n12ffcllmblvtd2048x128m4swbsho_130d.v",
+        "//internal/syn/libs/tsmc12ffc:tcbn12ffcllbwp6t20p96cpdlvt.v",
     ],
     build_args = [
         "+define+TSMC_INITIALIZE_MEM_USING_DEFAULT_TASKS",

tests/vcs_sim/top.cc

diff --git a/tests/vcs_sim/top.cc b/tests/vcs_sim/top.cc
index 113088e..1429c27 100644
--- a/tests/vcs_sim/top.cc
+++ b/tests/vcs_sim/top.cc
@@ -77,6 +77,7 @@
   core.io_debug_float_writeData_0_bits_data(debug.float_writeData_0_bits_data);
   core.io_debug_float_writeData_1_bits_data(debug.float_writeData_1_bits_data);
 #endif
+#if (KP_useDebugModule == true)
   core.io_dm_req_valid(dm.req_valid);
   core.io_dm_req_ready(dm.req_valid);
   core.io_dm_req_bits_address(dm.req_bits_address);
@@ -86,6 +87,7 @@
   core.io_dm_rsp_ready(dm.rsp_valid);
   core.io_dm_rsp_bits_data(dm.rsp_bits_data);
   core.io_dm_rsp_bits_op(dm.rsp_bits_op);
+#endif
   // AR
   core.io_axi_master_read_addr_ready(master_arready_4);
   core.io_axi_master_read_addr_valid(master_arvalid_4);