| commit | d1a684d2e74855654d8d7add401fc27880240601 | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Mon Jul 14 02:15:54 2025 -0700 |
| committer | Derek Chow <derekjchow@google.com> | Mon Jul 14 10:35:29 2025 -0700 |
| tree | 87e42787a2465ce4da316c076223be05b1edd912 | |
| parent | aa3f712202a308d0a3ef40c54a4d17770122f682 [diff] |
Adjust coding style to assign sub-fields of the same struct signal in a single always-block for tool-friendly. Change-Id: I0587c25d95b0075387691b285198bc3eb035409c
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog