Fix wrong results for mixed prec indexed loads Adding a bunch of indexed load tests too. The fix is tested on data8 index16 loads below m1 and index32 below mf2. Pending another fix for larger lmul. TODO: test store TODO: test load data16/32 Change-Id: I83b986339ff0900449fa4b57fa2eb895ca4e26f8
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog