| commit | cb8e46ec24d9255f0945c084d6538302c58306d6 | [log] [tgz] |
|---|---|---|
| author | Pu Wang <pu.wang@verisilicon.com> | Mon Dec 23 19:24:04 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Tue Jan 14 17:36:42 2025 -0800 |
| tree | 5567af0abf9bba29823a0fbfd098dbc51f0473b9 | |
| parent | f8ff2223859ec2d134a4b6f61c67f08ca7a08654 [diff] |
Fix typo in for-loop. Add async_rstn param to multi_fifo Change-Id: I106138be909373c12fffffc679d4006163ea5ccd
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog