commit | c4fccd7fff7b4828ef06f6977f5247866756192e | [log] [tgz] |
---|---|---|
author | Cindy Liu <hcindyl@google.com> | Wed Oct 25 14:53:47 2023 -0700 |
committer | Cindy Liu <hcindyl@google.com> | Mon Oct 30 12:02:24 2023 -0700 |
tree | 04afb87c92eaf250ca131ddc9aeb6491c33961bf | |
parent | 0bfa37b1127ff915bbec0ce2f938845f5948e7b2 [diff] |
Fix vsransu padding error Unsigned input upcasting should always padd the MSBs with 0s, whereas signed input upcasting padds the MSBs with the sign bit. Bug: 307590638 Change-Id: If424adceaa78590f0b60ce2e1cde4c83c5d6e1ed
Kelvin is a RISC-V32IM core with a custom instruction set.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog