commit | 150b1ae6e6718e363331ea498e45bd7b1f529231 | [log] [tgz] |
---|---|---|
author | pu.wang <pu.wang@verisilicon.com> | Wed Jul 09 10:52:33 2025 +0800 |
committer | Derek Chow <derekjchow@google.com> | Tue Aug 05 10:48:24 2025 -0700 |
tree | c66ea6fa43d92ff4f5b5ebc58a34cc93110bfa54 | |
parent | 9bb0dd9d19e7b9d78ac4e4bc1c9c9f7663cc63e2 [diff] |
Fix constraint reserve inst Change-Id: I3ced524e4c918f50290537349078dacef67a0622
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog