| commit | eb9e134c9a40600bf2a9d37d73814d6a2c92b481 | [log] [tgz] |
|---|---|---|
| author | pu.wang <pu.wang@verisilicon.com> | Mon Jan 20 21:46:58 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Mar 06 14:56:41 2025 -0800 |
| tree | fcf43f431da110e5524d2e5bc1f95174236e2aa5 | |
| parent | 933c06fe5007486f703f0ddb819637a4dc9c5b7f [diff] |
Update add mask instruction test & model Change-Id: Id8fde511124a25fd606f763d57731944289f3af7
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog