| commit | be3bd7f4ea8911dc90c47fce99566ee01eb5f6fc | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Thu Dec 19 00:51:42 2024 +0000 |
| committer | Yenkai Wang <ykwang@google.com> | Tue Mar 04 13:03:52 2025 -0800 |
| tree | a1f17231df87631f7d1ef4c1c9964080fd256508 | |
| parent | 50e0325ab78f2f0c93c6b655ee0fb5898c0243cc [diff] |
Add rule to run lint on a Verilog module. And lint CoreMiniAxi. Bug: 385003893 Bug: 400475972 Change-Id: Ic3cc714b4e83c090d35a795b82bd57677da7be74
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog