| commit | bad4bf4990b3fe0fe9d711fdc8b9111ec3403f89 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Thu Jul 24 16:44:55 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Fri Jul 25 15:05:55 2025 -0700 |
| tree | 6417b388a2cb4b22f7a29868906e6129a4334573 | |
| parent | 21d428a75bf775d9bf81967cc4a04af3dbc29114 [diff] |
feat(debug): Transition debug module to CSR-based interface
This commit refactors the debug module's external interface, moving from direct pin-level connections to a memory-mapped CSR (Control and Status Register) interface accessible via the AXI bus. This change provides a more structured and extensible mechanism for controlling and interacting with the debug module.
Key changes include:
- **Hardware:**
- The `CoreAxi` top-level module is updated to connect the debug module to the new CSR interface, removing the direct `dm` port.
- `CoreAxiCSR` is enhanced with a set of registers for debug requests and responses, including registers for address, data, operation, and status.
- The debug module's request and response signals are now driven by these CSRs, enabling control via AXI writes and reads.
- **Testbench:**
- The `CoreMiniAxiInterface` is significantly updated to use the new CSR-based communication protocol.
- The `dm_req_agent` and `dm_rsp_agent`, which previously managed the pin-level protocol, have been removed.
- The `dm_read` and `dm_write` functions are rewritten to perform the multi-step process of writing to the request CSRs, polling the status CSR, and reading the response CSRs.
- All debug-related tests are updated to use the new `dm_read` and `dm_write` functions.
- **Documentation:**
- The debug module documentation is updated to describe the new CSR-based command protocol.
- A table of the new AXI CSRs is added, including their addresses and descriptions.
- The command examples are updated to reflect the new multi-step process for reading and writing GPRs via the CSR interface.
This refactoring simplifies the hardware interface, improves the robustness of the testbench, and provides a clearer and more comprehensive programming model for external debuggers.
Change-Id: I39be61d805d0e1236550a33a40dbb20f91da0d67
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog