| commit | ba4f84a0421f1b84d7cd23cf26c48442df79d13c | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Thu Jan 02 17:09:02 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Jan 15 10:17:44 2025 -0800 |
| tree | 729de19f1b4f8a266319a09fc69a88f12a9f503b | |
| parent | af32a474550b47eed1a00db523588f8a0787e54a [diff] |
Add assertion for the situation when an instruction is decoded to 0 uop. Change-Id: Ide02d78bc06052c8290669f5ec2d0b26cd5d9fb3
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog