| commit | b9b0d55ba96b549756bb207a33dae793a9495859 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Aug 19 13:16:46 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Wed Aug 20 11:04:51 2025 -0700 |
| tree | 51f5f9da62f5b35fc9aac3d69a5309035ab27ca8 | |
| parent | 131a9c544c539e32488bc30284b7ef3f2604b5d2 [diff] |
feat(bus): Add SECDED integrity for TileLink-UL This commit implements SECDED (Single Error Correction, Double Error Detection) for the TileLink-UL bus to ensure data integrity. The implementation is compatible with OpenTitan's `prim_secded_inv` logic. Key changes include: - A parameterized `SecdedEncoder` Chisel module that supports 32-bit, 57-bit, and 128-bit data widths. The 128-bit implementation uses a folded ECC scheme. - `RequestIntegrityGen/Check` and `ResponseIntegrityGen/Check` modules to generate and verify integrity codes for the TileLink A and D channels. - A Python-based golden model (`secded_golden.py`) for the SECDED logic to ensure correctness. - A new `TileLinkULInterface` cocotb utility for simplified, transaction-based testing of the TileLink bus. - Comprehensive cocotb tests that verify the `SecdedEncoder` against the golden model and test the full `TlulIntegrity` functionality, including fault injection. Change-Id: I20a059b78a47699f145ae397b0e037d8c56dab69
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog